Resistive random-access memory (RRAM) element that requires no molding process

Abstract

The present disclosure relates to a method of manufacturing a resistive change type random access memory (RRAM) device that does not require a forming process. The method includes a step of manufacturing an RRAM cell and a step of annealing the RRAM cell. The RRAM cell includes a bottom electrode, an oxide switching layer including at least one transition metal oxide, an upper electrode, and an interface layer between the oxide switching layer and the upper electrode. In some embodiments, the at least one transition metal oxide includes at least one of HfO x and TaO y where x ≦ 2.0 and y ≦ 2.5. The interface layer includes at least one layer of Al2O3, MgO, Y2O3, and La2O3. The RRAM device that does not require a forming process can be switched to a plurality of resistance levels without a forming process. 【Representative drawing】FIG. 1A

Description

[Technical Field]

[0001] Embodiments of this disclosure generally relate to resistive random-access memory (RRAM) devices, and more specifically to RRAM devices that do not require a molding process, as well as to a method for manufacturing the same and a method for operating the same. [Background technology]

[0002] Resistive random-access memory (RRAM) elements are two-terminal passive elements with adjustable, non-volatile resistance. The resistance of an RRAM element can be electrically switched between a high-resistance state (HRS) and a low-resistance state (LRS) by applying an appropriate programming signal to the RRAM element. RRAM elements can be used to form crossbar arrays used for implementing in-memory arithmetic applications, non-volatile solid-state memory, image processing applications, neural networks, and the like. [Overview of the project]

[0003] A simplified overview of some aspects of this disclosure is provided below. This overview is not a comprehensive overview of the disclosure, nor is it intended to identify the main features or key elements of the disclosure, nor to define any specific embodiments or claims of the disclosure. Its purpose is to present some of the concepts of the disclosure in a simplified form as an introduction to the more detailed description provided later.

[0004] According to one or more aspects of this disclosure, a method is provided for manufacturing a resistive random-access memory (RRAM) element that does not require a formation step. This method includes the steps of manufacturing an RRAM cell having a designed interface layer and annealing the RRAM cell.

[0005] In some embodiments, the manufacturing of an RRAM cell includes the steps of: manufacturing an oxide switching layer containing at least one transition metal oxide on a bottom electrode; manufacturing an interface layer containing a material more chemically stable than at least one transition metal oxide on the oxide switching layer; and manufacturing an upper electrode on the interface layer.

[0006] In some embodiments, the RRAM cell is annealed in a forming gas environment containing N2 and H2.

[0007] In some embodiments, the RRAM cell is annealed at an annealing temperature between approximately 350°C and 450°C.

[0008] In some embodiments, the method further includes the step of manufacturing one or more interconnection layers on the RRAM cell, and the RRAM cell is annealed together with the one or more interconnection layers.

[0009] In some embodiments, the fabrication of one or more interconnection layers includes the step of fabricating metal pads or metal vias for one or more interconnection layers on the upper electrodes of the RRAM cell.

[0010] In some embodiments, the RRAM and one or more interconnect layers are annealed in multiple annealing processes. In each of the multiple annealing processes, the RRAM cells and one or more interconnect layers are annealed in a forming gas at a temperature of approximately 350°C to 450°C.

[0011] In some embodiments, the thickness of the interface layer is determined based on the device size of the RRAM cell and the thermal budget related to annealing. The interface layer is configured to reduce diffusion and reaction between the upper electrode and the oxide switching layer.

[0012] According to one or more aspects of this disclosure, a resistive random-access memory (RRAM) element that does not require a forming step is provided. The RRAM element does not require a forming step includes a bottom electrode, an oxide switching layer containing at least one transition metal oxide, a top electrode, and an interface layer fabricated between the top electrode and the oxide switching layer. The interface layer contains a material that is chemically more stable than at least one transition metal oxide. The RRAM element does not require a forming step to create conductive filaments in the oxide switching layer and is configured to switch between multiple resistors.

[0013] In some embodiments, at least one transition metal oxide is HfO x and TaO y It includes at least one of the following, where x ≤ 2.0 and y ≤ 2.5.

[0014] In some embodiments, the interface layer includes at least one layer of Al2O3, MgO, Y2O3, and La2O3.

[0015] In some embodiments, the thickness of the interface layer is between 0.2 nm and 1 nm.

[0016] In some embodiments, the thickness of the interface layer is greater than 1 nm.

[0017] In some embodiments, the initial resistance of the RRAM element that does not require a formation process is between 1 kΩ and 1 MΩ.

[0018] According to one or more aspects of the present disclosure, a method for operating a RRAM device that does not require a forming process is provided. This method includes performing a first read operation on a first RRAM device in an initial state that does not require a forming process to determine the first initial resistance of the first RRAM device, and performing a first reset operation on the first RRAM device in an initial state that does not require a forming process to switch the first RRAM device from the first initial resistance to a first target resistance. The first target resistance is greater than the first initial resistance. The first read operation and the first reset operation are performed without pre-forming a conductive filament in the first RRAM device that does not require a forming process in a forming process.

[0019] In some embodiments, the first reset current passing through the first RRAM device that does not require a forming process during the first reset operation is not greater than 500 μA.

[0020] In some embodiments, the method for operating a RRAM device that does not require a forming process further includes performing a first set operation on the first RRAM device that does not require a forming process to switch the first RRAM device from the first target resistance to a second target resistance. In some embodiments, performing the first set operation includes applying a first set voltage to the first RRAM device that does not require a forming process, and the first set voltage is not greater than 1.0 V.

[0021] In some embodiments, performing the first reset operation on the first RRAM device that does not require a forming process includes applying a first reset voltage to the first RRAM device that does not require a forming process, and the first set voltage and the first reset voltage have opposite polarities.

[0022] In some embodiments, a method for operating a pre-formed RRAM element further includes the steps of: performing a second read operation on a second pre-formed RRAM element to determine a second initial resistance of the second pre-formed RRAM element; and performing a second set operation on the second pre-formed RRAM element to switch the second pre-formed RRAM element from a second initial resistance to a third target resistance, the third target resistance being smaller than the second initial resistance. The second read operation and the second set operation are performed without pre-forming conductive filaments in the second pre-formed RRAM element during the formation process.

[0023] In some embodiments, a method for operating a pre-formed RRAM element further includes the step of applying a second reset voltage to a second pre-formed RRAM element to switch the second pre-formed RRAM element from a third target resistance to a fourth target resistance. In some embodiments, performing a second set operation on the second pre-formed RRAM element includes the step of applying a second set voltage to the second pre-formed RRAM element, wherein the second reset voltage and the second set voltage have opposite polarities.

[0024] In some embodiments, the second reset current passing through the second no-formation-step RRAM element in response to the second reset voltage is not greater than 500 μA. The second reset voltage is not greater than 1.0 V. [Brief explanation of the drawing]

[0025] The Disclosure will be better understood from the detailed descriptions of various embodiments shown below. However, the drawings are for illustrative and illustrative purposes only and do not limit the Disclosure to any particular embodiment. [Figure 1A] Figure 1A is a schematic diagram of an example of a crossbar circuit according to some embodiments of the present disclosure. [Figure 1B] Figure 1B is a schematic diagram of an example of a crosspoint element according to some embodiments of the present disclosure. [Figure 2A]Figure 2A is a schematic diagram showing a cross-sectional view of a conventional RRAM element that requires a formation process to operate. [Figure 2B] Figure 2B is a schematic diagram showing a cross-section of a conventional RRAM element that requires a formation process to operate. [Figure 2C] Figure 2C is a schematic diagram showing a cross-section of a conventional RRAM element that requires a formation process to operate. [Figure 2D] Figure 2D shows the current-voltage (IV) characteristics of a conventional RRAM element, as described in relation to Figures 2A, 2B, and 2C. [Figure 2E] Figure 2E shows the current-voltage (IV) characteristics of a conventional RRAM element, as described in relation to Figures 2A, 2B, and 2C. [Figure 2F] Figure 2F shows the current-voltage (IV) characteristics of a conventional RRAM element, as described in relation to Figures 2A, 2B, and 2C. [Figure 3] Figure 3 is a schematic diagram showing a cross-sectional view of an example of a manufacturing-free RRAM element according to some embodiments of this disclosure. [Figure 4] Figure 4 is a schematic diagram showing a cross-sectional view of a semiconductor device, including an example of a manufacturing-free RRAM device according to some embodiments of the present disclosure. [Figure 5A] Figure 5A shows the IV characteristics of a first exemplary fabrication-free RRAM element according to some embodiments of the present disclosure. [Figure 5B] Figure 5B shows the IV characteristics of a first exemplary fabrication-free RRAM element according to some embodiments of the present disclosure. [Figure 5C] Figure 5C shows the IV characteristics of a first exemplary fabrication-free RRAM element according to some embodiments of the present disclosure. [Figure 5D] Figure 5D shows the IV characteristics of a first exemplary fabrication-free RRAM element according to some embodiments of the present disclosure. [Figure 6A] Figure 6A shows the IV characteristics of a second exemplary fabrication-free RRAM element according to some embodiments of the present disclosure. [Figure 6B] Figure 6B shows the IV characteristics of a second exemplary fabrication-free RRAM element according to some embodiments of the present disclosure. [Figure 6C] Figure 6C shows the IV characteristics of a second exemplary fabrication-free RRAM element according to some embodiments of the present disclosure. [Figure 6D] Figure 6D shows the IV characteristics of a second exemplary fabrication-free RRAM element according to some embodiments of the present disclosure. [Figure 7A] Figure 7A is a flowchart illustrating an exemplary process for operating a molding-free RRAM element according to some embodiments of the present disclosure. [Figure 7B] Figure 7B is a flowchart illustrating an exemplary process for operating a molding-free RRAM element according to some embodiments of the present disclosure. [Figure 7C] Figure 7C is a flowchart illustrating an exemplary process for operating a molding-free RRAM element according to some embodiments of the present disclosure. [Figure 8] Figure 8 is a flowchart illustrating an exemplary process for manufacturing a molding-free RRAM element according to some embodiments of this disclosure. [Figure 9A] Figure 9A shows the IV characteristics of exemplary RRAM elements with different device sizes, manufactured under the same annealing conditions. [Figure 9B] Figure 9B shows the IV characteristics of exemplary RRAM elements with different device sizes, manufactured under the same annealing conditions. [Figure 9C] Figure 9C shows the IV characteristics of exemplary RRAM elements with different device sizes, manufactured under the same annealing conditions. [Figure 9D] Figure 9D shows the IV characteristics of exemplary RRAM elements with different device sizes, manufactured under the same annealing conditions. [Figure 9E] Figure 9E shows the IV characteristics of exemplary RRAM elements with different device sizes, manufactured under the same annealing conditions. [Figure 9F] Figure 9F shows the IV characteristics of exemplary RRAM elements manufactured to the same device size but under different annealing conditions. [Figure 9G] Figure 9G shows the IV characteristics of exemplary RRAM elements manufactured to the same device size but under different annealing conditions. [Figure 9H] Figure 9H shows the IV characteristics of exemplary RRAM elements manufactured to the same device size but under different annealing conditions. [Figure 9I] Figure 9I shows the IV characteristics of exemplary RRAM elements manufactured to the same device size but under different annealing conditions. [Figure 9J] Figure 9J shows the IV characteristics of exemplary RRAM elements manufactured to the same device size but under different annealing conditions. [Figure 10] Figure 10 shows an IV curve illustrating the analog operation of an exemplary, fabrication-free RRAM element according to some embodiments of this disclosure. [Figure 11] Figure 11 shows the element readout current characteristics against time of an exemplary fabrication-free RRAM element according to some embodiments of the present disclosure. [Modes for carrying out the invention]

[0026] Aspects of this disclosure provide a resistive random-access memory (RRAM) element that does not require a molding process, and a method for manufacturing and operating the RRAM element that does not require a molding process.

[0027] An RRAM element is a two-terminal passive element with programmable resistance. The RRAM element may include a bottom electrode, an upper electrode, and an oxide switching layer positioned between the bottom and upper electrodes. The bottom electrode may contain a non-reactive metal such as platinum (Pt) or palladium (Pd). The upper electrode may contain a reactive metal such as tantalum (Ta) or titanium (Ti). The oxide switching layer is made of hafnium oxide (HfO x ) or tantalum oxide (TaOx It may also contain transition metal oxides such as )

[0028] Conventional RRAM elements behave as insulators in their initial state (i.e., before receiving appropriate stimulation after manufacturing). Conventional RRAM elements can transition to a conductive state through a formation process in which a high formation voltage (e.g., a voltage of 1.7V) is applied to the conventional RRAM element. During the formation process, conductive filaments are formed within the conventional RRAM element. Subsequently, the RRAM element can switch between two resistive states, namely high resistance (HRS) and low resistance (LRS), in response to an appropriate programming signal (e.g., a voltage signal or a current signal). The switching event that programs the RRAM element from HRS is called the set process. The switching event that programs an RRAM element from the LRS is called a reset process. In a crossbar array circuit that includes an RRAM array, the programming signal can be supplied to a designated RRAM element via a selector such as a transistor.

[0029] The formation process involves the initial decomposition of the metal oxide in the oxide switching layer, making the formation of the initial conductive filaments a rapid process requiring a high formation voltage (e.g., 1.7V). In some embodiments, the formation voltage may be higher than 2V-3V to form RRAM elements with thicker oxide switching layers. Because it is difficult to control the dimensions of the filaments formed in the formation process, the formation process usually does not result in the desired element resistance. Conventional RRAM elements may need to be adjusted in a subsequent reset process (also called the "initial reset process") to achieve the desired element resistance. The initial reset process requires a high reset current to break the conductive filaments. As a result, conventional RRAM elements operate at high currents (e.g., currents exceeding 1mA), leading to high power consumption and requiring relatively large transistors capable of supplying such high operating currents. The formation process is also time-consuming. For example, forming a 256×256 RRAM array can take several minutes, making it a time-consuming process for forming a crossbar circuit containing multiple 256×256 RRAM arrays. Furthermore, the formation of the initial filaments during the molding process and the rupture of the initial filaments during the initial reset process are abrupt, which can cause performance variations between elements.

[0030] Accordingly, this disclosure provides a no-formation-step RRAM and a method for marking and operating them. Unlike conventional RRAMs that require a formation step to operate, the no-formation-step RRAM elements described herein are conductive in their initial state and do not require the formation of filaments to operate. The no-formation-step RRAM elements have a moderate to low resistance in their initial state, which can be read out to determine appropriate programming parameters for subsequent operations (e.g., set operations, reset operations, etc.).

[0031] In some embodiments, a manufacturing-free RRAM element may include an RRAM cell comprising a bottom electrode, an upper electrode, an oxide switching layer fabricated between the bottom electrode and the upper electrode, and an interface layer fabricated between the oxide switching layer and the upper electrode. The oxide switching layer may include one or more transition metal oxides such as hafnium oxide and tantalum oxide. The interface layer may include one or more layers of metal oxides that are chemically more stable than transition metal oxides, such as aluminum oxide. The metal oxides in the interface layer do not react with the upper electrode or the oxide switching layer. Therefore, the interface layer may control the reaction and diffusion between the upper electrode and the oxide switching layer. The interface layer may include one or more continuous or discontinuous layers of aluminum oxide.

[0032] RRAM cells may be annealed to achieve formation-free operation. For example, an RRAM cell may be annealed in one or more annealing processes, each of which involves annealing the RRAM cell in a forming gas environment (e.g., a mixture of N2 and H2) at an annealing temperature of 350-450°C for a suitable time (e.g., 15-30 minutes). The annealing may promote diffusion and reaction between the top electrode and the oxide switching layer, while the interface layer may reduce diffusion and reaction between the top electrode and the oxide switching layer. The interface layer and annealing conditions (e.g., temperature, annealing time, etc.) may be optimized in view of the device size (e.g., critical dimensions) of the RRAM element to achieve the desired initial resistance of the RRAM element.

[0033] The resistance of a pre-formed RRAM element may be programmed to multiple levels without a formation process. For example, a read operation may be performed on the pre-formed RRAM element to determine its initial resistance in order to program it to a target resistance. In some embodiments where the initial resistance is greater than the target resistance, the pre-formed RRAM element may be programmed to the target resistance by applying a set voltage (e.g., 0.6V) to the pre-formed RRAM element without any prior formation process. In some embodiments where the target resistance is greater than the initial resistance of the pre-formed RRAM element, the pre-formed RRAM element may be programmed to the target resistance by applying a reset voltage to the pre-formed RRAM element. The reset current through the RRAM element may be less than 200μA. The reset is performed without any prior formation process or initial setting process on the RRAM element. The set voltage and reset voltage may have opposite polarities (e.g., positive and negative polarities). RRAM elements that do not require a molding process may be switched between a high-resistance state and a low-resistance state in response to an ultra-low set voltage (e.g., a voltage lower than 1V) and a reset current (e.g., a reset peak current lower than 200μA).

[0034] Therefore, this disclosure provides a mechanism for manufacturing and operating RRAM elements without a formation process. By balancing material factors (e.g., interface layer thickness) and annealing factors (e.g., annealing conditions), the mechanism described herein achieves low energy switching, low inter-element performance variation, ultra-low operating current and voltage, and large I on / I off The present invention provides a no-formation-process RRAM element having desirable characteristics such as bipolar switching with a ratio and multi-level analog resistor switching. The no-formation-process RRAM element disclosed herein can enhance the scalability of the RRAM element crossbar array and enable high-density memory and / or computing applications with low power consumption.

[0035] Figure 1A is a schematic diagram of an example 100 of a crossbar circuit according to some embodiments of the present disclosure. As shown, the crossbar circuit 100 may include one or more row wires 111a, 111b, ..., 111i, ..., 111n and a plurality of interconnected electrically conductive wires such as 113a, 113b, ..., 113j, ..., 113m for an n x m crossbar array. The crossbar circuit 100 may further include crosspoint elements 120a, 120b, ..., 120z, etc. Each crosspoint element may connect a row wire to a column wire. For example, crosspoint element 120ij may connect a row wire 111i to a column wire 113j. In some embodiments, the crossbar circuit 100 may further include a digital-to-analog converter (DAC, not shown), an analog-to-digital converter (ADC, not shown), a switch (not shown), and / or other suitable circuit components for implementing a crossbar-based device. The number of column wires 113a-m and row wires 111a-n may be the same or different.

[0036] The row wires 111 may include a first row wire 111a, a second row wire 111b, ..., 111i, ..., and an nth row wire 111n. Each of the row wires 111a, ..., 111n is and / or contains a suitable electrically conductive material. In some embodiments, each row wire 111a-n may be a metal wire.

[0037] The row wires 113 may include a first row wire 113a, a second row wire 113b, ..., and an mth row wire 113m. Each of the row wires 113a-m is and / or contains a suitable electrically conductive material. In some embodiments, each row wire 113a-m may be a metal wire.

[0038] Each crosspoint element 120 may be any suitable element having adjustable resistance, such as a memristor, a phase-change memory (PCM) element, a floating gate, a spintronic element, a resistive random-access memory (RRAM), or a static random-access memory (SRAM), and / or may include such elements. In some embodiments, one or more crosspoint elements 120 may include an RRAM element, as described in relation to Figure 3-11.

[0039] The crossbar circuit 100 may perform parallel weighted voltage multiplication and current summation. For example, an input voltage signal may be applied to one or more rows (e.g., one or more selected rows) of the crossbar circuit 100. The input signal can flow through the crosspoint elements of the rows of the crossbar circuit 100. The conductance of the crosspoint elements can be adjusted to a specific value (also called a "weight"). According to Ohm's law, the input voltage multiplies the crosspoint conductance, generating a current from the crosspoint elements. According to Kirchhoff's laws, the sum of the currents passing through the elements in each column generates a current as an output signal (e.g., the output of an ADC) that can be read from the column. According to Ohm's law and Kirchhoff's current law, the input-output relationship of the crossbar array can be expressed as I=VG, where I represents the output signal matrix as current, V represents the input signal matrix as voltage, and G represents the conductance matrix of the crosspoint elements. Thus, the input signal is weighted by the conductance of each crosspoint element according to Ohm's law. The weighted current is output through each column wire and can be accumulated according to Kirchhoff's current law. This enables in-memory arithmetic (IMC) by parallel multiplication and addition performed on the crossbar array.

[0040] Figure 1B is a schematic diagram of an example 1200 of a crosspoint element according to some embodiments of the present disclosure. As shown, the crosspoint element 1200 may connect a bit line (BL) 1211, a selection line (SEL) 1213, and a word line (WL) 1215. The bit line 1211 and the word line 1215 may be the column wire and row wire described in relation to Figure 1A, respectively.

[0041] The crosspoint element 1200 may include an RRAM element 1201 and a transistor 1203. The transistor is a three-terminal element and may be labeled as gate (G), source (S), and drain (D). Transistor 1203 may be connected in series with RRAM element 1201. As shown in Figure 1B, the bottom electrode of RRAM element 1201 may be connected to the drain of transistor 1203. The top electrode of RRAM element 1201 may be connected to the bit line 1211. The source of transistor 1203 may be connected to the word line 1215. The gate of transistor 1203 may be connected to the selection line 1213. The RRAM element 1201 may include one or more RRAM elements as described in relation to Figures 2A to 5D below. The crosspoint element 1200 may also be referred to as a one-transistor-one-resistor (1T1R) configuration. Transistor 1203 can function as a selector and as a current controller to set the current compliance of the RRAM element 1201 during programming. The gate voltage of transistor 1203 can set the current compliance of the crosspoint element 1200 during programming, thereby controlling the conductance and analog operation of the crosspoint element 1200. For example, when the crosspoint element 1200 is set from a high-resistance state to a low-resistance state, a set signal (e.g., a voltage signal, a current signal) may be supplied via the bit line (BL) 1211. While the word line (WL) 1215 is grounded, another voltage, also referred to as a select voltage or gate voltage, can be applied to the transistor gate via the select line (SEL) 1213 to open the gate and set the current compliance. When the cross-point element 1200 is reset from the low-resistance state to the high-resistance state, a gate voltage can be applied to the gate of the transistor 1203 via the selection line 1213 to open the transistor gate. On the other hand, while the bit line 1211 is grounded, a reset signal can be sent to the RRAM element 1201 via the word line 1215.

[0042] FIGS. 2A, 2B, and 2C are schematic diagrams showing cross-sectional views of conventional RRAM elements that require a forming process to operate. The RRAM elements 200a, 200b, and 200c may correspond to RRAM elements in the initial state, low-resistance state, and high-resistance state, respectively.

[0043] As shown in FIG. 2A, the RRAM element 200a may include a bottom electrode 210, an oxide switching layer 220, and a top electrode 230. The bottom electrode 210 may include a suitable material that is electrically conductive and non-reactive to oxide switching, such as Pt, Pd, etc. The oxide switching layer 220 may include one or more transition metal oxides of binary oxides, ternary oxides, and higher-order oxides such as TaO x 、HfO x 、TiO x 、NbOx, ZrOx, etc. In some embodiments, the chemical stability of the non-reactive material of the bottom electrode 210 may be higher than that of the transition metal oxide of the oxide switching layer 220. The top electrode 230 may include any suitable metal material that is electrically conductive and reactive to oxide switching. For example, the metal material of the top electrode 230 may include Ta, Hf, Ti, etc.

[0044] The RRAM element 200a has a high initial resistance (e.g., several gigaohms) and can be considered an insulator in its initial state. The initial resistance of the RRAM element 200a can be changed through a formation process, switching the RRAM element 200a to a low-resistance state. For example, a formation voltage can be applied to the RRAM element 200a. Applying a voltage to the RRAM element 200a can cause the metallic material of the upper electrode to absorb oxygen from the oxide switching layer 220, creating oxygen vacancies in the oxide switching layer 220. As a result, oxygen-vacancy-rich conductive paths (e.g., filaments) can be formed in the oxide switching layer 220. For example, a conductive filament 225a can be formed in the oxide switching layer 220, as shown in Figure 2B. As shown, the conductive filament 225a can be formed from the upper electrode 230 to the bottom electrode 210 via the oxide switching layer 220. The RRAM element 200b can be reset to a high-resistance state. For example, a reset signal (e.g., a voltage signal or a current signal) may be applied to the RRAM element 200b during the reset process. In some embodiments, the set signal and the reset signal may have opposite polarities, i.e., a positive signal and a negative signal, respectively. The application of the reset signal can cause oxygen to flow back into the oxide switching layer 220 and recombine with one or more oxygen vacancies. For example, as shown in Figure 2C, a suspended conductive filament 225b may be formed in the oxide switching layer 220 during the reset process. As shown, the conductive filament may be suspended with an oxide gap between the suspended conductive filament 225b and the bottom electrode 210. The lateral dimensions of the conductive filament 225b may be smaller than those of the conductive filament 225a. The conductive filament 225b does not continuously connect the bottom electrode 210 and the top electrode 230. The RRAM elements 200b-c can be electrically switched between a high-resistance state and a low-resistance state by applying an appropriate programming signal (e.g., a voltage signal, a current signal, etc.) to the RRAM element.

[0045] Figures 2D, 2E, and 2F are graphs 200d, 200e, and 200f showing the current-voltage (IV) characteristics of a conventional RRAM element, as described in relation to Figures 2A-2C. Figure 2D shows the IV curve 200d of a conventional RRAM element in its initial state. As shown, the initial resistance of the conventional element is approximately 1.3 GΩ at 0.2 V. Therefore, the conventional RRAM element can be considered an insulator in its initial state. As shown in Figure 2E, the voltage V formed on the RRAM element... form The formation process may be carried out by applying a voltage. The formation voltage may be approximately 1.7V. After the formation process, the RRAM element can be reset to a high-resistance state by applying a reset voltage within the voltage range 261 in a reset process (also referred to as "initial reset process"). The reset peak current passing through the RRAM element during the initial reset process is approximately 1 mA. As shown in Figure 2F, the RRAM element can be switched between a high-resistance state and a low-resistance state by applying an appropriate set voltage within voltage range 263 and a reset voltage within voltage range 261, respectively. The set voltage may be approximately 0.7 V. The reset peak current may be approximately 100 μA. Therefore, the formation of conventional RRAM elements requires the application of a high formation voltage. The reset peak current during the initial reset process is high. Conventional RRAM elements operate at high operating currents. The resistance of conventional RRAM elements cannot be switched without a formation process.

[0046] Figure 3 is a schematic cross-sectional view showing an example of a molding-free RRAM cell 300 according to some embodiments of this disclosure. The RRAM cell 300 is also referred to herein as an RRAM element.

[0047] As shown in the figure, the RRAM cell 300 may include a substrate 310, a bottom electrode 320, an oxide switching layer 330, an interface layer 340, and an upper electrode 350. The interface layer 340 is fabricated between the upper electrode 350 and the oxide switching layer 330.

[0048] The substrate 310 may include one or more layers of suitable materials that can function as a substrate for RRAM elements, such as silicon (Si), silicon dioxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3), and aluminum nitride (AlN). In some embodiments, the substrate 310 may include diodes, transistors, interconnects, integrated circuits, etc. In some embodiments, the substrate may include a drive circuit comprising one or more individually controllable electrical circuits (e.g., an array of electrical circuits). In some embodiments, the drive circuit may include one or more complementary metal-oxide-semiconductor (CMOS) drivers.

[0049] The bottom electrode 320 may be any suitable material that is electrically conductive and non-reactive to oxide switching, such as platinum (Pt), palladium (Pd), iridium (Ir), titanium nitride (TiN), or tantalum nitride (TaN), and / or may contain such material.

[0050] The oxide switching layer 330 is TaO x , HfO x , TiO x NbO x ZrO x This may include one or more transition metal oxides of binary oxides, ternary oxides, and higher-order oxides, such as HfO. Here, x may be used to indicate an oxide that is oxygen-deficient compared to the perfect oxide in its stoichiometry, and the value of x may vary from the atomic ratio of oxygen to metal in the perfect oxide. For example, HfO x (If HfO2 is a perfect oxide) then x ≤ 2.0, and TaO x (When Ta2O5 is a perfect oxide) x ≤ 2.5. As an example, the oxide switching layer 330 may contain Ta2O5 and / or HfO2.

[0051] The upper electrode 350 may contain any suitable metallic material that is electrically conductive and reactive to oxide switching. For example, the metallic material of the upper electrode 350 may include Ta, Hf, Ti, TiN, TaN, etc. The upper electrode 350 may also be reactive to oxide switching and may have suitable oxygen solubility to absorb oxygen from the oxide switching layer 330 and create oxygen vacancies in the oxide switching layer 330. That is, the reactive metallic material of the upper electrode 350 may have suitable oxygen solubility and / or oxygen mobility. In some embodiments, the upper electrode 350 can not only create oxygen vacancies in the oxide switching layer 330 (e.g., by collecting oxygen) but can also function as an oxygen reservoir or source to the oxide switching layer 330 during cell programming.

[0052] In some embodiments, the upper electrode 350 may comprise one or more alloys. Each alloy may comprise two or more metallic elements. Each alloy may comprise a binary alloy (e.g., an alloy comprising two metallic elements), a ternary alloy (e.g., an alloy comprising three metallic elements), a quaternary alloy (e.g., an alloy comprising four metallic elements), a pentary alloy (e.g., an alloy comprising five metallic elements), a hexary alloy (e.g., an alloy comprising six metallic elements), and / or a higher-order alloy (e.g., an alloy comprising more than six metallic elements). In some embodiments, the upper electrode 350 may comprise one or more alloys comprising a first metallic element and one or more second metallic elements. Each second metallic element may be less or more reactive than the first metallic element with respect to the transition metal oxide in the oxide switching layer. In some embodiments, the first metallic element may be Ta. The second metallic elements may comprise one or more such as W, Hf, Mo, Nb, Zr, etc.

[0053] The interface layer 340 is in thermochemical equilibrium with the upper electrode 350 and the oxide switching layer 330, and does not react with either the upper electrode 350 or the oxide switching layer 330. Therefore, the interface layer 340 may reduce diffusion and reaction between the upper electrode 350 and the oxide switching layer 330. The interface layer 340 may be a film of a material that is more chemically stable than the transition metal oxide of the oxide switching layer 330, and / or may contain such a material. As a result, the material may not react with the transition metal oxide of the oxide switching layer 330. For example, the transition metal oxide of the oxide switching layer may be HfO x and / or TaO y This may be the case, provided that x ≤ 2.0 and y ≤ 2.5, and the interface layer 340 may include one or more layers such as Al2O3, MgO, Y2O3, and La2O3. In some embodiments, the interface layer 340 may include a continuous film of a material that is more chemically stable than a transition metal oxide (e.g., a film with a thickness of 1 nm or more). In some embodiments, the interface layer 340 may be discontinuous (e.g., a film with a thickness of 0.2 nm to 0.6 nm).

[0054] The RRAM cell 300 may be annealed in one or more annealing processes to achieve desired fabrication-free operation. Each annealing process may include annealing the RRAM element in a forming gas atmosphere for an appropriate period (e.g., 15-30 minutes) and at an appropriate temperature (e.g., 350-450°C). The forming gas may include a mixture of nitrogen (N2) and hydrogen (H2) in an appropriate ratio (e.g., 95:5, 90:10, etc.). The thickness of the interface layer 340 may be determined based on the device size (critical size, device area, etc.) and annealing conditions of the RRAM cell 300. Smaller device sizes may require longer annealing times and / or thinner interface layers 340 to reduce the initial resistance of the fabrication-free RRAM.

[0055] Annealing may reduce diffusion and reaction between the upper electrode 350 and the oxide switching layer 330, while promoting diffusion and reaction between the upper electrode 350 and the oxide switching layer 330. In view of the device size of the RRAM cell 300, balancing and / or optimizing the thermal budget (e.g., annealing temperature, annealing time, etc.) associated with the interface layer 340 and annealing can control the initial resistance of the RRAM cell 300 within a desired target range, thereby achieving desirable device operation such as no formation step required, low energy switching, and low inter-device performance variation. As will be described in more detail with reference to Figures 9A-9J, the thickness of the interface layer 340 may be determined based on the device size and thermal budget of the RRAM cell 300. In some embodiments, the initial resistance of the no-formation-step-free RRAM cell 300 may be between approximately 1 kΩ and approximately 1 MΩ. In some embodiments, the initial resistance of the RRAM cell 300 may be between several hundred ohms and several kilohms (e.g., 500 Ω to 5 kΩ).

[0056] In some embodiments, the RRAM cell 300 may be manufactured during the CMOS process. The thermal budget for annealing the RRAM cell 300 may be determined based on the annealing conditions associated with the CMOS process. For example, as shown in Figure 4, the semiconductor device 400 may include a transistor 403 manufactured on a substrate 401. The transistor 403 may include a source region 403a, a gate region 403b, and a drain region 403c. The interconnection layer 410 may be fabricated on the transistor 403 and the substrate 401.

[0057] Each interconnection layer 410 may provide electrical connections between transistor 403 and / or one or more other elements (e.g., one or more other transistors, RRAM cell 300, one or more other RRAM elements, etc.). The interconnection layer 410 may include, for example, via layers 411, 412, 413, 414, and 415 and metal layers (or pad layers) 421, 423, 424, and 425. Each via layer may include one or more metal vias. Each metal via may contain a suitable metallic material such as Al, Cu, or W. Each metal layer may include one or more metal pads and / or one or more metal wires. Each metal pad may contain a suitable metallic material such as Al, Cu, or W. For example, via layer 411 may include metal vias 411a, 411b, and 411c that can be connected to the source region 403a, gate region 403b, and drain region 403c of transistor 403, respectively. In some embodiments, the via layer 411 may include tungsten (W) vias and doped polycrystalline silicon (poly-Si) terminals, the poly-Si terminals may be in direct contact with the gate 403b, source region 403a, and drain region 403c of transistor 403. The tungsten vias may be in direct contact with the poly-Si terminals. Other via layers and metal layers above the via layer 411 may be made of Cu, W, Al, etc. The metal layer 421 may include metal pads 421a, 421b, and 421c. The metal pads 421a, 421b, and 421c may be connected to the metal vias 411a, 411b, and 411c, respectively. The metal layer 422 may include metal pads 422a, 422b, and 422c. The metal pads 422a, 422b, and 422c may be connected to the metal vias 412a, 412b, and 412c, respectively. As shown in the figure, pairs of adjacent metal layers may be connected via layers fabricated between adjacent metal layers.

[0058] Manufacturing the interconnection layer 410 may involve manufacturing a layer of dielectric material using a suitable deposition technique such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plasma-enhanced chemical vapor deposition (PECVD), or sputtering. The dielectric layer may be patterned to form one or more vias. One or more suitable metallic materials may be deposited within the vias and patterned to manufacture one or more metallic vias and / or metallic pads. The metallic vias and / or metallic pads may then be annealed in a forming gas environment. In some embodiments, the via layer and the metallic layer may be manufactured in a dual damascene manufacturing process in which the metallic vias and metallic pads are manufactured during the same metal deposition and patterning process and then annealed together.

[0059] For example, a dielectric layer 451 may be fabricated on the substrate 401 and transistor 403 in order to produce the first via layer 411. The dielectric layer 451 may contain any suitable dielectric material such as silicon nitride (Si3N4) or silicon dioxide (SiO2). The dielectric layer 451 may be processed using any suitable deposition technique. For example, the dielectric layer 451 may be patterned and filled by metal deposition in order to produce metal vias 411a, 411b, and 411c within the dielectric layer 451.

[0060] The RRAM cell 300 may be manufactured during the manufacturing of the interconnect layer 410 and may therefore be referred to as a CMOS-compatible RRAM element. For example, the RRAM cell 300 may be manufactured on the top interconnect layer metal pad or metal via of the first interconnect layer 410a. Thereafter, one or more second interconnect layers 410b may be manufactured on the RRAM cell 300 and the first interconnect layer 410a. More specifically, for example, the bottom interconnect layer metal pad or metal via of the second interconnect layer 410b may be manufactured on the RRAM cell 300 and in direct contact with the RRAM cell 300.

[0061] Manufacturing each second interconnection layer 410b may include annealing the second interconnection layer in relation to the RRAM cell 300. In some embodiments, the via layer and metal layer may be manufactured in a dual damascene manufacturing process in which the metal vias and metal pads are manufactured during the same metal deposition and patterning process and annealed together. The interface layer 340 may have an appropriate thickness to achieve the desired forming gas annealing (FGA) resistance. For example, a relatively thick interface layer may have higher FGA resistance than a relatively thin interface layer. Therefore, the thermal budget for annealing the RRAM cell 300 may be determined based on the location of the RRAM cell 300, the number of second interconnection layers manufactured on the RRAM cell 300, and / or the annealing conditions used to anneal the second interconnection layers. The thickness of the interface layer 340 may then be optimized based on the annealing conditions and the device size of the RRAM cell 300.

[0062] The specific interconnection layers shown in Figure 4 (e.g., metal layer and via layer) are merely illustrative. The first interconnection layer 410a and the second interconnection layer 410b may include any appropriate number of interconnection layers. For example, in some embodiments, the RRAM cell 300 may be manufactured on a metal layer 413. In some embodiments, the semiconductor element 400 and / or interconnection layer 410 may be manufactured using the technology described in U.S. Patent Application No. 17 / 848,238 (filed June 23, 2022), which is incorporated herein by reference.

[0063] Figures 5A-5D show IV curves 500A, 500B, 500C, and 500D of a first exemplary mold-free RRAM according to some embodiments of the present disclosure.

[0064] Figure 5A shows the IV curve 500A for an RRAM in its initial state. The horizontal axis of the IV curve 500A represents the read voltage applied to the RRAM element in its initial state. The vertical axis of the IV curve 500A represents the current flowing through the RRAM element while the read voltage is applied. As shown in the figure, the initial resistance of the RRAM element is approximately 4.5kΩ at 0.2V.

[0065] As shown in Figure 5B, a reset voltage within the voltage range 511 may be applied to the RRAM element to switch it from its initial resistance to a target resistance greater than the initial resistance (also referred to as the "first target resistance"). The initial resistance of the RRAM element is reset without any prior formation process or initial setting process on the RRAM element. For example, the resistance of the RRAM element may be reset to approximately 127 kΩ. As shown in Figure 5B, the reset peak current through the RRAM element is lower than 200 μA, which is significantly lower than the reset current required to reset a conventional RRAM element after formation.

[0066] After the reset process, the resistance of the RRAM element may be set to a second target resistance that is greater than the first target resistance. For example, as shown in Figure 5C, a set voltage within the voltage range 513 may be applied to the RRAM element during the set process. In some embodiments, the set voltage is approximately 0.6V. The set voltage and reset voltage have opposite polarity. In some embodiments, the resistance of the RRAM element after the set process is approximately 5.2kΩ at 0.2V.

[0067] As shown in Figure 5D, the resistance of the RRAM element can be switched between a high-resistance state 521 and a low-resistance state 523 under a set voltage within the voltage range 513 or a reset voltage within the voltage range 511. The set voltage may be approximately 0.6V. The reset peak current is approximately 200μA or not greater. In some embodiments, the reset peak current is about 500 μA or less. As shown in Figures 5A-5D, the RRAM element can be reset to a desired target resistance with a low initial reset peak current without pre-forming steps and initial reset processing. The RRAM element has a large I at low voltage. on / I off It switches ratio-based and operates with ultra-low current.

[0068] Figures 6A-6D show current-to-voltage curves (IV curves) 600A, 600B, 600C, and 600D of a second exemplary molding-free RRAM according to some embodiments of the present disclosure.

[0069] Figure 6A shows the IV curve 600A for an RRAM in its initial state. The horizontal axis of the IV curve 600A represents the read voltage applied to the RRAM element in its initial state. The vertical axis of the IV curve 600A represents the current flowing through the RRAM element while the read voltage is applied. The initial resistance of the RRAM element is approximately 19kΩ at 0.2V.

[0070] As shown in Figure 6B, the RRAM element can be switched from its initial state 621 to a low-resistance state 623 by applying a set voltage within the voltage range 611. For example, the set voltage may be as low as 0.6V, which is much lower than the formation voltage required to electrically form a conventional RRAM element. After the setting process, the resistance of the RRAM element is approximately 8kΩ at 0.2V.

[0071] After the setup process, the RRAM element can be reset to a higher resistance by applying a reset voltage within the voltage range 613 to the RRAM element. The reset peak current may be less than 200 μA, which is significantly lower than the reset peak current required to reset conventional elements after formation. The resistance of the RRAM element after reset may be approximately 100 kΩ.

[0072] As shown in Figures 6C and 6D, the RRAM element can be repeatedly switched on and off under a set voltage within the voltage range 611 or a reset voltage within the voltage range 613. As an example, the resistance of the RRAM element can be set to about 5 kΩ by applying a set voltage of 0.7 V to the RRAM element. In some embodiments, the set voltage may be about 1 V or lower. As another example, the resistance of the RRAM element can be reset to about 100 kΩ under a reset peak current of about 200 μA or lower. As shown in Figures 6A-6D, the RRAM element can be reset to a desired target resistance at a set voltage significantly lower than the formation voltage required in the formation process, and operate at low voltage and low current in subsequent switching events.

[0073] Figure 7A is a flowchart illustrating an exemplary process 700a for operating a no-formation RRAM element according to some embodiments of the present disclosure. The resistance of the no-formation RRAM element can be switched to one of several resistance levels without a formation process.

[0074] In step 710, a read operation may be performed to determine the initial resistance of the RRAM element. For example, one or more read voltages may be applied to the RRAM element in its initial state to determine the initial resistance of the RRAM element. The read voltage may be, for example, a voltage between 0.05 and 0.5V. Note that a read operation cannot be performed on a conventional RRAM without prior formation. This is because conventional RRAMs are not conductive in their initial state.

[0075] In step 720, the initial resistance may be compared with the target resistance to determine whether the target resistance is greater than or equal to the initial resistance. The target resistance may be a desired resistance or a weight on which an RRAM element is programmed.

[0076] In some embodiments, the target resistance may be greater than the initial resistance of the RRAM element. In such embodiments, process 700a may proceed to 730, where a reset operation may be performed to program the RRAM element to the target resistance. For example, a reset voltage may be applied to the RRAM element. The reset current may be several hundred microamperes (μA). Unlike conventional RRAM elements described in relation to Figure 2A-2F, the formation-free RRAM element can be programmed to a target resistance without a formation process and subsequent initial reset process.

[0077] In some embodiments, the initial resistance of the RRAM element may be greater than the target resistance. In such embodiments, process 700a proceeds to 735, where a set operation may be performed on the RRAM element to program it to the target resistance. For example, a set voltage may be applied to the RRAM element. In some embodiments, the set voltage may be about 0.3 to 0.7V. In some embodiments, the set voltage may be about 0.5 to 1V. Thus, a formation-free RRAM element can be set to a target resistance without a formation process that generates conductive filaments in the RRAM element.

[0078] Figure 7B is a flowchart illustrating an exemplary process 700b for operating a molding-free RRAM element (also referred to as the "first molding-free RRAM element") according to some embodiments of the present disclosure.

[0079] In step 740, a first read operation may be performed on the first pre-formed RRAM element in its initial state, and a first initial resistance of the first pre-formed RRAM element may be determined. The first initial resistance represents the resistance of the first pre-formed RRAM element in its initial state without undergoing a formation process. Performing the first read operation on the first pre-formed RRAM element in its initial state includes applying one or more read voltages (for example, a voltage of about 0.2V) to the first pre-formed RRAM element.

[0080] In step 750, a first reset operation may be performed to program the first pre-formed RRAM element to a first target resistance greater than the first initial resistance. Performing the first reset operation may include applying a reset signal (e.g., a voltage signal, a current signal, etc.) to the first pre-formed RRAM element. The reset peak current (also referred to as the "first reset current") passing through the first pre-formed RRAM element during the first reset operation may be about 200 μA or less. In some embodiments, the first reset current may be about 500 μA or less. The reset operation is performed without pre-forming the first pre-formed RRAM element in a formation process.

[0081] In 760, a first set operation may be performed on the first non-forming RRAM element, and the first non-forming RRAM element may be switched from a first target resistance to a second target resistance. The first target resistance is greater than the second target resistance. Performing the first set operation may include applying a first set voltage to the first non-forming RRAM element. In some embodiments, the first set voltage is not greater than 0.7V. In some embodiments, the first set voltage is not greater than 1V.

[0082] Referring to Figure 7C, a flowchart is shown illustrating an exemplary process 700c for operating a mold-free RRAM element having moderate resistance ("second mold-free RRAM element") according to some embodiments of the present disclosure.

[0083] In step 770, a second read operation may be performed on the initial state of the second non-forming RAM element, and the initial resistance of the second non-forming RRAM element ("second initial resistance") may be determined. The second initial resistance represents the resistance of the second pre-formed RRAM element in its initial state without undergoing the formation process. Performing a second read operation on the second pre-formed RRAM element includes applying one or more read voltages to the second pre-formed RRAM element in its initial state.

[0084] In step 780, a second set operation may be performed to switch the second RRAM element from a second initial resistance to a third target resistance. The second initial resistance is greater than the third target resistance. The second set operation is performed on the second RRAM element that does not require a formation process without performing the formation process beforehand. The execution of the second set operation may include applying a second set voltage to the second formation-free RRAM element. In some embodiments, the second set voltage is not greater than 0.7V. In some embodiments, the second set voltage is not greater than 1V.

[0085] In step 790, a second reset operation may be performed to switch the second RRAM element that does not require a second formation process from the third resistor to the fourth target resistor. The fourth target resistor may be smaller than the third target resistor. The reset operation is performed on the second RRAM element that does not require a second formation process without performing a formation process beforehand.

[0086] Figure 8 is a flowchart illustrating an exemplary process 800 for manufacturing a molding-free RRAM element according to some embodiments of the present disclosure.

[0087] In block 810, an RRAM cell may be manufactured. The RRAM cell may include a bottom electrode, an oxide switching layer, an upper electrode, and an interface layer manufactured between the oxide switching layer and the upper electrode. The RRAM cell may be the RRAM cell 300 in Figure 3. In particular, the bottom electrode may be manufactured on the substrate in 811. Manufacturing the bottom electrode may involve depositing one or more layers of one or more inert metals such as Pt, Pd, Ir using physical vapor deposition (PVD) technology, chemical vapor deposition (CVD) technology, sputter deposition technology, atomic layer deposition (ALD) technology, and / or any other suitable deposition technology. In some embodiments, manufacturing the bottom electrode may involve depositing one or more layers of metal nitrides such as TiN or TaN. The bottom electrode may be and / or include the bottom electrode 320 described above in relation to Figure 3.

[0088] In block 813, an oxide switching layer may be fabricated on the bottom electrode. The oxide switching layer may contain one or more transition metal oxides. The transition metal oxide is, for example, TaO x , HfO x , TiO x NbO x ZrO x The oxide switching layer may include the following: The oxide switching layer may be deposited using PVD, CVD, ALD, and / or any other suitable deposition technique.

[0089] In block 815, the interface layer may be fabricated on the oxide switching layer. Fabrication of the interface layer may involve depositing a material that is more chemically stable than the transition metal oxide of the oxide switching layer, such as Al2O3, MgO, Y2O3, or La2O3. In one embodiment, fabrication of the interface layer may involve depositing a continuous layer of Al2O3, MgO, Y2O3, or La2O3. In another embodiment, fabrication of the interface layer may involve depositing a layer of material of a suitable thickness (e.g., about 0.2 nm to about 0.6 nm) for forming a discontinuous film of Al2O3, MgO, Y2O3, or La2O3. The interface layer may be fabricated using PVD, CVD, ALD, and / or any other suitable deposition technique.

[0090] In block 817, the upper electrode may be fabricated on the interface layer. Fabrication of the upper electrode may involve depositing one or more suitable metallic materials that are electrically conductive and reactive to the oxide switching of the oxide switching layer, such as Ta, Hf, Ti, TiN, and TaN. The upper electrode may comprise one or more alloys. The upper electrode may be fabricated using PVD, CVD, ALD, and / or any other suitable deposition technique.

[0091] In block 830, the RRAM cell may be annealed. For example, the RRAM cell may be annealed in one or more annealing processes, each of which may include annealing the RRAM cell in a forming gas environment (e.g., a mixture of N2 and H2) at a suitable annealing temperature (e.g., 350-450°C) for a suitable time (e.g., 15-30 minutes) for each annealing process.

[0092] In some embodiments, process 800 may further include block 820, in which one or more interconnection layers are fabricated on the upper electrode. In such embodiments, the RRAM cell may be annealed together with the interconnection layers in block 830. The fabrication of each interconnection layer may include fabricating a layer of dielectric material such as Si3N4, SiO2, using a suitable deposition technique such as chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced chemical vapor deposition (PECVD), or sputtering. The dielectric layer may be patterned to form one or more vias. One or more suitable metallic materials may be deposited within the vias and patterned to produce one or more metallic vias and / or metallic pads.

[0093] Figures 9A-9E show the IV characteristics of exemplary RRAM elements of different device sizes manufactured under the same annealing conditions.

[0094] IV curves 911, 913, and 915 show the IV characteristics of an RRAM element with a critical dimension of 0.18 μm. IV curves 921, 923, and 925 show the IV characteristics of an RRAM element with a critical dimension of 0.24 μm. IV curves 931, 933, and 935 show the IV characteristics of an RRAM element with a critical dimension of 0.28 μm. The RRAM elements corresponding to IV curves 911, 921, and 931 do not include an interface layer. Each RRAM element corresponding to IV curves 913, 923, and 933 includes a thin interface layer (e.g., a layer of 0.2 nm to 0.6 nm). In some embodiments, the thin interface layer may be a discontinuous layer and / or may include one. Each RRAM element corresponding to IV curves 915, 925, and 935 includes a thick interface layer (e.g., a layer of about 1 nm or larger). The RRAM elements exhibit various resistances, as shown in Figure 9A. The RRAM elements corresponding to IV curves 921, 931, 913, 923, and 933 are pre-formed RRAM elements with initial resistances of approximately 549Ω, 543Ω, 7.5kΩ, 465Ω, and 460Ω, respectively.

[0095] Figures 9F-9J show the IV characteristics of exemplary RRAM elements fabricated under various annealing conditions for the same device size (e.g., critical dimension of 0.24 μm).

[0096] RRAM elements corresponding to IV curves 941, 943, and 945 are manufactured without annealing. RRAM elements corresponding to IV curves 951, 953, and 955 are manufactured under short-time annealing. RRAM elements corresponding to IV curves 961, 963, and 965 are manufactured under long-time annealing. Each RRAM element corresponding to IV curves 941, 951, and 961 does not include an interface layer. Each RRAM element corresponding to IV curves 943, 953, and 963 includes a thin interface layer (e.g., a layer of 0.2 nm to 0.6 nm). In some embodiments, the thin interface layer may be a discontinuous layer and / or may include one. Each RRAM element corresponding to IV curves 945, 955, and 965 includes a thick interface layer (e.g., a layer of about 1 nm or larger). The RRAM elements corresponding to IV curves 951, 953, 961, and 963 are the fabrication-free RRAM elements described herein, having initial resistances of approximately 549Ω, 460Ω, 389Ω, and 239Ω, respectively. As shown in Figures 9A-9B, the annealing conditions and interface layer thickness may be optimized in view of the device size to achieve the desired initial resistance.

[0097] Figure 10 shows an IV curve 1000 illustrating the analog operation of an exemplary fabrication-free RRAM element according to some embodiments of the present disclosure. As shown, the fabrication-free RRAM element can be adjusted to multiple levels (or analog operation) without a fabrication process by controlling the current compliance, exhibiting a desirable analog operation in which the current is linearly proportional to the voltage (or linear operation) in each resistance state.

[0098] Figure 11 is a graph 1100 showing the element read current characteristics of an exemplary fabrication-free RRAM element against time according to some embodiments of the present disclosure. Graph 1100 shows the element read current characteristics of an exemplary RRAM element at 135°C. Graph 1100 may also represent the results of an element retention test regarding the ability of a fabrication-free RRAM element to maintain its resistance level over time. Graph 1100 may also represent the results of a read stability test regarding the ability of an RRAM element to maintain its resistance level over time, since it is under constant readout conditions (at a readout voltage of 0.2V).

[0099] For the sake of simplicity, the methods of this disclosure are described and explained as a series of actions. However, the actions of this disclosure may be performed in various orders and / or simultaneously, and in conjunction with other actions not presented and explained herein. Furthermore, not all illustrated actions are required to implement the methods of this disclosure. In addition, as those skilled in the art will understand and recognize, the methods may be alternatively represented as a series of interrelated states via state diagrams or events.

[0100] As used herein, “about,” “approximately,” and “substantially” may mean within the range of normal tolerances in the industry, such as within ±20% of the target dimension in some embodiments, within ±10% of the target dimension in some embodiments, within ±5% of the target dimension in some embodiments, within ±2% of the target dimension in some embodiments, within ±1% of the target dimension in some embodiments, and within ±0.1% of the target dimension in some embodiments, for example, within two standard deviations of the mean. “About” and “approximately” may include the target dimension. Unless otherwise specified or evident from the context, all numerical values ​​described herein are modified by “about.”

[0101] As used herein, a range includes all values ​​within that range. For example, the range from 1 to 10 may include any number, any combination of numbers, any subrange, and fractions thereof from the digits 1, 2, 3, 4, 5, 6, 7, 8, 9, and 10.

[0102] The above description contains numerous details. However, it is clear that this disclosure can be implemented without these specific details. In some examples, well-known structures and elements are shown in block diagram form to avoid obscuring this disclosure.

[0103] The terms "first," "second," "third," and "fourth" used herein are intended as labels to distinguish different elements and do not necessarily have an ordinal meaning according to their numerical designations.

[0104] As used herein, the terms “example” or “exemplary” are used to mean that they serve as examples, cases, or illustrations. Any aspect or design described herein as “example” or “exemplary” should not necessarily be construed as being preferable or advantageous to other aspects or designs. Rather, the use of the terms “example” or “exemplary” is intended to present a concept in a concrete form. As used in this application, “or” is intended to mean an inclusive “or” unless otherwise specified or it is clear from the context. That is, unless otherwise specified or it is clear from the context, “X includes A or B” is intended to be satisfied under any of the following cases: X includes A, X includes B, or X includes both A and B. In addition, as used in this application and the appended claims, the articles “a” and “an” should generally be construed as meaning “one or more” unless otherwise specified or it is clear from the context that they refer to a singular form. Throughout this specification, any reference to “embodiment” or “one embodiment” means that a particular feature, structure, or characteristic described in relation to an embodiment is included in at least one embodiment. Therefore, the appearance of the phrase “embodiment” or “one embodiment” in various places throughout this specification does not necessarily refer to the same embodiment.

[0105] As used herein, when an element or layer is referred to as being "on top of" another element or layer, that element or layer may be directly on the other element or layer, or there may be an intervening element or layer. In contrast, when an element or layer is referred to as being "directly on top of" another element or layer, there is no intervening element or layer.

[0106] Many variations and modifications of this disclosure will become apparent to those skilled in the art after reading the foregoing description. These are shown and illustrated by drawing specific embodiments, but it is not intended in any way that any particular embodiment should be considered restrictive. Accordingly, references to the details of various embodiments are not intended to limit the claims to those features alone.

[0107] [Cross-reference of related applications] This application claims the benefits of U.S. Patent Application No. 17 / 812,866, “FORMING-FREE RANDOM-ACCESS MEMORY (RRAM) DEVICES,” filed on 15 July 2022, which is incorporated herein by reference in its entirety.

Claims

1. A method for manufacturing a resistive random access memory (RRAM) element that does not require a molding process, A process for manufacturing an RRAM cell, comprising: a step of manufacturing an oxide switching layer containing at least one transition metal oxide on a bottom electrode; a step of manufacturing an interface layer containing a material more chemically stable than the at least one transition metal oxide on the oxide switching layer; and a step of manufacturing an upper electrode on the interface layer. The process of annealing the RRAM cell, Includes, The RRAM cell is annealed in a forming gas environment containing N2 and H2.

2. The method according to claim 1, wherein the RRAM cell is annealed at an annealing temperature between 350°C and 450°C.

3. The process further includes the step of manufacturing one or more interconnection layers on the RRAM cell, The method according to claim 1, wherein the RRAM cell is annealed together with the one or more interconnection layers.

4. The method according to claim 3, wherein the step of manufacturing the one or more interconnection layers includes the step of manufacturing metal pads or metal vias of the one or more interconnection layers on the upper electrodes of the RRAM cell.

5. The RRAM cell and the one or more interconnection layers are annealed by a plurality of annealing processes. The method according to claim 3, wherein the RRAM cell and the one or more interconnection layers are annealed in a forming gas at a temperature of 350°C to 450°C in each of the plurality of annealing processes.

6. The thickness of the interface layer is determined based on the device size of the RRAM cell and the thermal budget related to the annealing process of the annealing step. The method according to claim 1, wherein the interface layer is configured to reduce diffusion and reaction between the upper electrode and the oxide switching layer.

7. A resistive random-access memory (RRAM) element that does not require a molding process, Bottom electrode and An oxide switching layer comprising at least one transition metal oxide, Upper electrode and The upper electrode and the oxide switching layer are provided together, and an interface layer is manufactured between them. The interface layer comprises a material that is chemically more stable than the at least one transition metal oxide. The aforementioned RRAM element that does not require a formation step is configured to switch between multiple resistors without performing a formation step to generate conductive filaments in the oxide switching layer. The thickness of the interface layer is determined based on the device size of the RRAM cell and the thermal budget related to the annealing process performed during the manufacturing of the RRAM element. The interface layer is configured to reduce diffusion and reaction between the upper electrode and the oxide switching layer, making it a manufacturing-free RRAM element.

8. The at least one transition metal oxide is HfO ｘ and TaO ｙ A molding-free RRAM element according to claim 7, comprising at least one of the following, wherein x ≤ 2.0 and y ≤ 2.

5.

9. The aforementioned interface layer is Al ２ O ３ , MgO, Y ２ O ３ , and La ２ O ３ A RRAM element that does not require a formation step, according to claim 8, comprising at least one layer.

10. The RRAM element that does not require a formation step, according to claim 9, wherein the thickness of the interface layer is between 0.2 nm and 1 nm.

11. The initial resistance of the RRAM element is between 1 kΩ and 1 MΩ, as described in claim 7, for an RRAM element that does not require a forming step.

Images