A method, system and FPGA device for implementing a DMA read operation

By using a node manager on the host side to store the complete packet header and having the FPGA device continuously initiate DMA read requests, the problems of large memory consumption and low efficiency in DMA read operations are solved, achieving efficient data transmission.

CN117033273BActive Publication Date: 2026-07-21ZHENGZHOU XINDA JIEAN INFORMATION TECH
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Patent Information

Application Number
CN202311081556.3
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2023-08-25
Publication Date
2026-07-21
Estimated Expiration
2043-08-25

AI Technical Summary

Technical Problem

In existing DMA read operations, the host randomly allocates memory addresses to store data, resulting in large memory space consumption, heavy host burden, and low transmission efficiency when transferring large amounts of data, thus affecting data transmission performance.

Method used

By allocating a contiguous physical memory space on the host to form a node manager, storing the complete packet header of the data to be transmitted, and having the FPGA device send two consecutive DMA read requests to the host to obtain the data and the complete packet header, the host operation is simplified and the transmission efficiency is improved.

Benefits of technology

It reduces the amount of host memory used, simplifies host operation procedures, improves DMA transfer efficiency, and ensures the correspondence between data and complete packet headers.

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Abstract

The application provides a DMA read operation implementation method, system and FPGA device, and relates to the technical field of DMA transmission. The method comprises the following steps: a host applies for a continuous physical memory space, a node manager is formed, a complete packet header of to-be-transmitted data is written into a node of the node manager, and only the complete packet header of the to-be-transmitted data is stored in the node manager, so that the occupied host memory space is small, and the host operation is simplified; transmission parameters and a command word of the node manager are written into an FPGA device, when it is found that the command word FIFO is not empty, the FPGA device initiates a DMA read request twice to the host according to the transmission parameters and the command word of the node manager; and the FPGA device takes out corresponding data and a complete packet header from a TLP completion packet returned by the host, stores the data and the complete packet header after splicing, and thus the DMA read operation is completed, and the DMA transmission efficiency is improved.
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Citation Information

Patent Citations

  • Multi-node multi-channel high-speed parallel processing method and system

    CN112035898A

  • DMA read operation implementation method based on FPGA, FPGA equipment and communication system

    CN113485951A