Interrupt control method, interrupt controller, computer device and storage medium

Abstract

The application relates to the technical field of interrupt control, and discloses an interrupt control method, an interrupt controller, computer equipment and a storage medium, the method is applied to an interrupt controller, the method comprises the following steps: receiving a plurality of interrupt requests; determining the current priority of each interrupt request in the plurality of interrupt requests according to the N-time historical processing time length of each interrupt request in the plurality of interrupt requests, wherein N is a positive integer; and sending the plurality of interrupt requests to a processor according to the sequence of the current priorities of the plurality of interrupt requests. The application can flexibly adjust the priorities of the plurality of interrupt requests according to actual application scenes, and improves the performance of a system.

Description

Technical Field

[0001] This invention relates to the field of interrupt control technology, specifically to interrupt control methods, interrupt controllers, computer devices, and storage media. Background Technology

[0002] The interrupt controller is a crucial component of computer systems, primarily responsible for coordinating and managing interrupt requests between various peripherals and the Central Processing Unit (CPU). Specifically, the interrupt controller monitors various interrupt requests in the system, prioritizes multiple received interrupt requests, and distributes them to the CPU for processing according to priority. By coordinating interrupt requests through the interrupt controller, the efficiency of CPU interrupt handling can be improved.

[0003] However, current interrupt controllers typically use fixed priorities, controlling the priorities of various interrupts through register configuration. Once the configuration is determined, the priorities of each interrupt are also fixed. Such interrupt controllers introduce many limitations in system applications. For example, the priorities of multiple interrupts cannot be adjusted according to actual conditions, impacting system performance. Summary of the Invention

[0004] In view of this, the present invention provides an interrupt control method, an interrupt controller, a computer device, and a storage medium to solve the problem of low system performance caused by a fixed priority order of multiple interrupt requests.

[0005] In a first aspect, the present invention provides an interrupt control method applied to an interrupt controller, the method comprising: receiving a plurality of interrupt requests; determining the current priority of each interrupt request among the plurality of interrupt requests based on N historical processing times of each interrupt request, where N is a positive integer; and sending the plurality of interrupt requests to a processor in order of their current priorities.

[0006] The interrupt control method provided in this embodiment, after receiving multiple interrupt requests, determines the current priority of each interrupt request based on the N historical processing times of each interrupt request. Then, it sends multiple interrupt requests to the processor according to the order of their current priorities. Through the above steps, the priority order of multiple interrupt requests can be dynamically adjusted based on the N historical processing times. This ensures that the processing needs of high-priority interrupt requests are met while also accommodating the processing needs of low-priority interrupt requests with shorter processing times, avoiding excessively long waiting times for short-processing interrupt requests. In other words, it optimizes the priority order of multiple interrupt requests, enabling the CPU to process interrupt requests more flexibly and efficiently, thereby improving system performance.

[0007] In one optional implementation, determining the current priority of each interrupt request based on the N historical processing times of each interrupt request includes: determining the current priority of each interrupt request based on the N historical processing times of each interrupt request and the previous priority of each interrupt request, wherein the previous priority is the priority of the interrupt request obtained when the corresponding interrupt request was processed last time.

[0008] The interrupt control method provided in this embodiment determines the current priority of an interrupt request based on the preset priority and the previous priority of the interrupt request, according to the processing time of the previous N historical interrupt requests, which can more quickly adjust the priority order of multiple interrupt requests.

[0009] In an optional implementation, determining the current priority of each interrupt request based on the N historical processing times of each interrupt request and the previous priority of each interrupt request includes: determining a preset priority for each interrupt request; determining a first processing time for each interrupt request, where the first processing time is the average of the N historical processing times of the corresponding interrupt request; determining a second processing time for each interrupt request, where the second processing time is the average of the processing times required for the M interrupt requests prior to processing the corresponding interrupt request, where M is a positive integer; and determining the current priority of each interrupt request using the following formula based on the first processing time, the second processing time, and the previous priority:

[0010]

[0011] Where P is the current priority of the corresponding interrupt request, α is the weighting coefficient, and P f The preset priority corresponding to the interrupt request, T is the first processing duration corresponding to the interrupt request, T E P is the second processing duration corresponding to the interruption request. n-1 The previous priority corresponding to the interrupt request.

[0012] In this embodiment, after determining the preset priority, previous priority, first processing time and second processing time corresponding to the interrupt request, the current priority of each interrupt request among multiple interrupt requests is determined according to a specific formula. This allows for a more reasonable adjustment of the current priority of the interrupt requests based on the preset priority, thereby optimizing the current priority order of multiple interrupt requests.

[0013] In an optional implementation, the method further includes: when processing the plurality of interrupt requests for the first time, the current priority of each interrupt request among the plurality of interrupt requests is a corresponding preset priority.

[0014] In one optional implementation, determining the first processing duration of each interrupt request among the plurality of interrupt requests includes: determining the first processing duration based on a third processing duration and a fourth processing duration, wherein the third processing duration is the Nth historical processing duration, and the fourth processing duration is the average of the previous N-1 historical processing durations, where N≥2.

[0015] In this embodiment, determining the first processing time by using the third processing time and the fourth processing time allows for a faster determination of the first processing time, and thus a faster determination of the current priority of the interruption request.

[0016] In an optional implementation, the method further includes storing the first processing duration of each of the plurality of interrupt requests in the interrupt controller.

[0017] In one optional implementation, when a preset priority is given priority, the weighting coefficient takes any value from 0.5 to 1.

[0018] Secondly, the present invention provides an interrupt controller, the interrupt controller comprising: an interrupt receiving unit for receiving a plurality of interrupt requests; an interrupt processing unit for determining the current priority of each interrupt request among the plurality of interrupt requests based on the N historical processing durations of each interrupt request among the plurality of interrupt requests, where N is a positive integer; and an interrupt redistribution unit for sending the plurality of interrupt requests to a processor according to the order of the current priorities of the plurality of interrupt requests.

[0019] In one optional implementation, the interrupt handling unit includes: a first processing unit, configured to determine the current priority of each interrupt request among the plurality of interrupt requests based on the N historical processing durations of each interrupt request among the plurality of interrupt requests and the previous priority of each interrupt request among the plurality of interrupt requests, wherein the previous priority is the priority of the interrupt request obtained when the corresponding interrupt request was processed last time.

[0020] In an optional implementation, the first processing unit includes: a first processing subunit, configured to determine a preset priority for each interrupt request among the plurality of interrupt requests; a second processing subunit, configured to determine a first processing duration for each interrupt request among the plurality of interrupt requests, wherein the first processing duration is the average of the N historical processing durations of the corresponding interrupt request; a third processing subunit, configured to determine a second processing duration for each interrupt request among the plurality of interrupt requests, wherein the second processing duration is the average of the processing durations required for the M interrupt requests prior to processing the corresponding interrupt request, where M is a positive integer; and a fourth processing subunit, configured to determine the current priority of each interrupt request among the plurality of interrupt requests based on the first processing duration, the second processing duration, and the previous priority, using the following formula:

[0021]

[0022] Where P is the current priority of the corresponding interrupt request, α is the weighting coefficient, and P f The preset priority corresponding to the interrupt request, T is the first processing duration corresponding to the interrupt request, T E P is the second processing duration corresponding to the interruption request. n-1 The previous priority corresponding to the interrupt request.

[0023] In an optional implementation, the interrupt handling unit further includes a second processing unit, configured to, when processing the plurality of interrupt requests for the first time, assign a current priority to a corresponding preset priority to each of the plurality of interrupt requests.

[0024] In one optional implementation, the second processing subunit includes: a determining unit, configured to determine the first processing duration based on a third processing duration and a fourth processing duration, wherein the third processing duration is the Nth historical processing duration, and the fourth processing duration is the average of the previous N-1 historical processing durations, where N≥2.

[0025] In one optional implementation, the interrupt controller further includes a control register for storing the first processing duration of each of the plurality of interrupt requests in the interrupt controller.

[0026] In one optional implementation, when a preset priority is given priority, the weighting coefficient takes any value from 0.5 to 1.

[0027] Thirdly, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the computer instructions to perform the method described in the first aspect or any corresponding embodiment thereof.

[0028] Fourthly, the present invention provides a computer-readable storage medium storing computer instructions for causing a computer to perform the method described in the first aspect or any corresponding embodiment thereof. Attached Figure Description

[0029] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0030] Figure 1 This is a flowchart illustrating an interrupt control method according to an embodiment of the present invention;

[0031] Figure 2 This is a schematic diagram illustrating the variation of the mean error rate with N according to an embodiment of the present invention;

[0032] Figure 3 This is a flowchart illustrating another interrupt control method according to an embodiment of the present invention;

[0033] Figure 4 This is a schematic diagram of the architecture of an application scenario of the interrupt control method according to an embodiment of the present invention;

[0034] Figure 5 This is a structural block diagram of an interrupt controller according to an embodiment of the present invention;

[0035] Figure 6 This is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0037] An interrupt request is a signal sent by an external device or program, notifying the computer system that the current task needs to be stopped immediately and a new event needs to be handled. Interrupt requests can come from external devices such as the keyboard, mouse, timer, and network, or from software programs.

[0038] An interrupt controller is an electronic device or chip that sends interrupt requests from external devices to the CPU to improve the efficiency of CPU processing interrupt requests. The interrupt controller typically determines the priority order of multiple received interrupt requests based on a user-configured fixed priority list, and then sends the interrupt requests to the CPU sequentially according to their priority. Using a fixed priority order to send interrupt requests to the CPU may result in some interrupt requests occupying the CPU for a long time, causing other interrupt requests to wait for an extended period before being processed, thus impacting system performance.

[0039] For example, the interrupt controller receives three interrupt requests: Interrupt Request 11, Interrupt Request 12, and Interrupt Request 13. Specifically, Interrupt Request 11 could be for a 1-bit correctable error in the Tag Random Access Memory (TRAM) of the core's L2 cache; Interrupt Request 12 could be for a 1-bit correctable error in the Dirty RAM of the core's L2 cache; and Interrupt Request 13 could be for an overflow in the Performance Monitor Unit (PMU) counter. For the same system, all three interrupt requests are non-fatal errors. Interrupt Request 13 may require the CPU to initiate a read / write operation, resulting in a longer processing time, while Interrupt Requests 11 and 12 only need to alert the CPU that an event has occurred, requiring no further action and thus having very short processing times. If the interrupt controller sends the interrupt requests to the CPU sequentially in the order of Interrupt Request 13, Interrupt Request 12, and Interrupt Request 11, Interrupt Request 12 and 11 may require a longer waiting time to be processed, affecting the operation of corresponding peripherals in the system and consequently impacting system performance.

[0040] In view of this, embodiments of the present invention provide an interrupt control method that can flexibly adjust the priority of multiple interrupt requests according to actual application scenarios, thereby improving system performance.

[0041] According to an embodiment of the present invention, an interrupt control method embodiment is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0042] This embodiment provides an interrupt control method that can be used in the aforementioned interrupt controller. Figure 1 This is a flowchart illustrating an interrupt controller method according to an embodiment of the present invention, as shown below. Figure 1 As shown, the method includes the following steps:

[0043] Step S101: Receive multiple interrupt requests.

[0044] Specifically, the interrupt controller may receive multiple interrupt requests from various peripherals.

[0045] Step S102: Determine the current priority of each interrupt request among the multiple interrupt requests based on the N historical processing times of each interrupt request among the multiple interrupt requests.

[0046] Where N is a positive integer, representing the current priority of each interrupt request determined by the historical processing time of one or multiple historical processing times among the multiple interrupt requests. The N historical processing times of an interrupt request represent the processing time required by the interrupt controller to process the interrupt request in the previous N attempts.

[0047] For example, when N is 1, the current priority of the interrupt request can be determined based on the processing time of the last time the interrupt request was processed, in addition to the preset priority corresponding to the interrupt request. When N is greater than 1, the current priority of the interrupt request can be determined based on the average processing time of the previous N times the interrupt request was processed (average processing time), in addition to the preset priority corresponding to the interrupt request. For example, the shorter the average processing time, the higher the current priority of the interrupt request.

[0048] N can be a preset value, and its size can be set by the user. Specifically, the larger N is, the more accurate the average processing time and the more accurate the current priority are. However, the larger N is, the more hardware resources the interrupt processor needs to consume, while the improvement in accuracy is smaller. For example, Figure 2 The graph shows the change in the mean error rate as N increases from 1 to 2000, with the horizontal axis representing the number of historical processing times (N) and the vertical axis representing the mean error rate. From... Figure 2It can be seen that when N≤1000, the difference in the mean error rate is still quite significant. However, when N>1000, the vertical axis hardly changes as N increases. This means that a larger value for N is not necessarily better; accuracy and resource consumption need to be considered comprehensively. Therefore, the value of N can be determined based on both accuracy and resource consumption.

[0049] Specifically, based on the preset priority corresponding to each interrupt request, the current priority of each interrupt request is determined according to the processing time of N historical data. When multiple interrupt requests have similar preset priorities (the absolute value of the difference between the preset priorities of two interrupt requests is less than the preset value) or the same, interrupt requests with shorter processing times can be processed first to avoid interrupt requests with shorter processing times waiting for longer periods.

[0050] Step S103: Send multiple interrupt requests to the processor according to their current priority order.

[0051] Specifically, after the interrupt controller obtains the current priorities of the multiple interrupt requests after adjustment, it can arrange the current priorities of the multiple interrupt requests in descending order, and send the corresponding interrupt requests to the CPU in descending order.

[0052] For example, if the interrupt controller receives three interrupt requests, interrupt request 11, interrupt request 12 and interrupt request 13, and determines that the priority of interrupt request 11 is 1.3, the priority of interrupt request 12 is 1.2 and the priority of interrupt request 13 is 1.1, then interrupt request 11 can be sent to the CPU first, then interrupt request 12 can be sent to the CPU, and then interrupt request 13 can be sent to the CPU.

[0053] The interrupt control method provided in this embodiment, after receiving multiple interrupt requests, determines the current priority of each interrupt request based on the N historical processing times of each interrupt request. Then, it sends multiple interrupt requests to the processor according to the order of their current priorities. Through the above steps, the priority order of multiple interrupt requests can be dynamically adjusted based on the N historical processing times. This ensures that the processing needs of high-priority interrupt requests are met while also accommodating the processing needs of low-priority interrupt requests with shorter processing times, avoiding excessively long waiting times for short-processing interrupt requests. In other words, it optimizes the priority order of multiple interrupt requests, enabling the CPU to process interrupt requests more flexibly and efficiently, thereby improving system performance.

[0054] Furthermore, in the above embodiments, when multiple interrupt requests are processed for the first time, the current priority of each interrupt request among the multiple interrupt requests is the corresponding preset priority.

[0055] For example, if the interrupt controller receives three interrupt requests: interrupt request 21, interrupt request 22, and interrupt request 23, with interrupt request 21 having a preset priority of 2.1, interrupt request 22 having a preset priority of 2.2, and interrupt request 23 having a preset priority of 2.3, then if interrupt request 21 is processed for the first time, its current priority is 2.1. If interrupt request 21 is processed for the fifth time, its current priority can be adjusted based on the processing times of the four previous attempts. These four processing times can be the time consumed by the CPU when processing interrupt request 21 for the first, second, third, and fourth times.

[0056] This embodiment provides an interrupt control method that can be used in the aforementioned interrupt controller. Figure 3 This is a flowchart illustrating another interrupt control method according to an embodiment of the present invention, such as... Figure 3 As shown, the method includes the following steps:

[0057] Step S301: Receive multiple interrupt requests.

[0058] Please see details Figure 1 Step S101 of the illustrated embodiment will not be described again here.

[0059] Step S302: Determine the current priority of each interrupt request based on the N historical processing times of each interrupt request and the previous priority of each interrupt request.

[0060] Specifically, step S302 above is Figure 1 One specific implementation of step S102 in the illustrated embodiment.

[0061] The previous priority of an interrupt request is the priority of the interrupt request obtained when it was last processed.

[0062] Specifically, based on the preset priority corresponding to each interrupt request, the current priority of each interrupt request can be determined according to the N historical processing times and the previous priority, thereby obtaining the current priorities of multiple interrupt requests.

[0063] In some optional implementations, step S302 above includes:

[0064] Step S3021: Determine the preset priority of each interrupt request among multiple interrupt requests.

[0065] Specifically, multiple preset priorities corresponding to multiple interrupt requests can be configured by the user in advance.

[0066] Step S3022: Determine the first processing time for each interrupt request among the multiple interrupt requests.

[0067] The first processing time is the average of the N historical processing times.

[0068] For example, when determining the priority (current priority) of processing each interrupt request for the (N+1)th time, if the processing time (historical processing time) of the interrupt request for the first time is 10 seconds (Second, s), the historical processing time for the second time is 15 seconds, the historical processing time for the third time is 16 seconds, the historical processing time for the fourth time is 6 seconds, and the historical processing time for the fifth time is 8 seconds, then when N is 5, the first processing time is 11 seconds = (10 seconds + 15 seconds + 16 seconds + 6 seconds + 8 seconds) / 5; when N is 1, the first processing time is 10 seconds.

[0069] In some optional implementations, to determine the first processing time more quickly, step S3022 includes:

[0070] Step a1: Determine the first processing time based on the third and fourth processing times.

[0071] The third processing time is the Nth historical processing time, and the fourth processing time is the average of the previous N-1 historical processing times, where N is an integer greater than or equal to 2. Furthermore, if N is 1, the fourth processing time is zero.

[0072] In this embodiment, the first processing time can be determined by formula (1).

[0073]

[0074] Where T is the first processing time, T n-1 For the fourth processing time, T n This represents the third processing time, where n indicates the number of times the corresponding interruption request occurs.

[0075] For example, when determining the current priority of each interrupt request in the (N+1)th processing, if the first historical processing time is 8s, the second historical processing time is 7s, and the third historical processing time is 12s, then when N is 3, the third processing time is 12s, the fourth processing time is 7.5s = (8s + 7s) / 2, and the first processing time is 9s = (7.5s * 2 + 12) / 3.

[0076] Step S3023: Determine the second processing time for each interrupt request among the multiple interrupt requests.

[0077] The second processing time is the average of the processing times required for the M interrupt requests prior to processing the corresponding interrupt request.

[0078] In this embodiment, the second processing time of the interruption request can be determined by formula (2).

[0079]

[0080] Among them, T E The second processing time for the corresponding interrupt request is t, where m is the M previous interrupt requests for the corresponding interrupt request, and t is the second processing time for the corresponding interrupt request. i Let m be the processing time required for the i-th interrupt request, where i is an integer and 1 ≤ i ≤ m.

[0081] For example, when determining the current priority of the (M+1)th interrupt request, if the processing time required for the CPU to process the first interrupt request is 20s, the processing time required for the CPU to process the second interrupt request is 25s, the processing time required for the CPU to process the third interrupt request is 15s, and the processing time required for the CPU to process the fourth interrupt request is 20s, then when M is 4 (i.e., m = 4), the second processing time is 20s = (20s + 25s + 15s + 20s) / 4.

[0082] Step S3024: Based on the first processing time, the second processing time and the previous priority, determine the current priority of each interrupt request among multiple interrupt requests using formula (3).

[0083]

[0084] Where P is the current priority of the corresponding interrupt request, α is the weighting coefficient, and α is a preset value. f The preset priority for this interrupt request is T, and the first processing time for this interrupt request is T. E P is the second processing time corresponding to this interruption request. n-1 The previous priority level for this interrupt request.

[0085] α is used to characterize the degree of importance the interrupt controller places on the preset priority. In some optional implementations, when the preset priority takes precedence (in scenarios where the preset priority is valued), that is, when there is a strict processing order among the priorities of multiple received interrupt requests, the value of α can be any value from 0.5 to 1. For example, α can be 0.5, 0.6, 0.8, or 1. That is, the value range of α is [0.5, 1]. For example, the greater the emphasis on the preset priority, the closer α is to 1. When α is 1, the processing time of each interrupt request is no longer considered.

[0086] For example, in use cases where interrupt handling duration and preset priority need to be considered together—that is, when the execution order of multiple received interrupt priorities is not strict or there is no interrupt priority—the interrupt handling duration affects the processing order of interrupt requests. In this case, the value of α is greater than 0 and less than 0.5, that is, the value range of α is [0, 0.5). When the value of α is 0, the preset priority of each interrupt request is no longer considered.

[0087] In this embodiment, after determining the preset priority, previous priority, first processing time and second processing time corresponding to the interrupt request, the current priority of each interrupt request among multiple interrupt requests is determined according to a specific formula. This allows for a more reasonable adjustment of the current priority of the interrupt requests based on the preset priority, thereby optimizing the current priority order of multiple interrupt requests.

[0088] Step S303: Send multiple interrupt requests to the processor according to the current priority order of the multiple interrupt requests.

[0089] Please see details Figure 1 Step S103 of the illustrated embodiment will not be described again here.

[0090] The interrupt control method provided in this embodiment determines the current priority of an interrupt request based on the preset priority and the previous priority of the interrupt request, according to the processing time of the previous N historical interrupt requests, which can more quickly adjust the priority order of multiple interrupt requests.

[0091] Furthermore, in the above Figure 3 In the illustrated embodiment, to facilitate the rapid determination of the first processing time in the process of determining the current priority of each interrupt request, the interrupt control method further includes storing the first processing time of each interrupt request among multiple interrupt requests in the interrupt controller. In the above embodiment, the first processing time is the fourth processing time required when determining the current priority of the interrupt request for the (N+2)th time.

[0092] The following is in conjunction with the appendix Figure 4 The interrupt control method provided in the embodiments of the present invention will be described in detail.

[0093] For example, such as Figure 4 As shown, the interrupt controller 400 may include an interrupt receiving unit 410, an interrupt processing unit 420, an interrupt redistribution unit 430, and a control register 440.

[0094] For example, the interrupt receiving unit 410 can be connected to an external device 500 via a bus. The interrupt receiving unit 410 is also connected to an interrupt handling unit 420, which is further connected to a control register 440 and an interrupt redistribution unit 430. The interrupt redistribution unit can be connected to a CPU 600, and the control register 440 can be connected to a human-machine interface device 700 via a configuration interface. Specifically, upon initial power-on (or reset) of the interrupt controller 400, the user can configure a preset priority for each interrupt request among multiple interrupt requests in the control register 440 according to the human-machine interface device 700 (keyboard, mouse, etc.).

[0095] Specifically, the interrupt receiving unit 410 receives one or more interrupt requests from the external device 500. After receiving an interrupt request, the interrupt receiving unit 410 sends the interrupt request to the interrupt handling unit 420. After receiving multiple interrupt requests, the interrupt handling unit 420 can obtain the preset priority and the previous N historical processing times of each interrupt request from the control register 440. Then, based on the preset priority of each interrupt request, the current priority of each interrupt request is determined according to the previous N historical processing times, that is, the priority order of the multiple interrupt requests is optimized based on the historical processing times. Afterwards, the interrupt handling unit 420 sends the optimized priority order of the multiple interrupt requests (the current priority order of the multiple interrupt requests) and the multiple interrupt requests to the interrupt redistribution unit 430. The interrupt redistribution unit 430 sends the corresponding interrupt requests to the CPU 600 in descending order of the current priority of the multiple interrupt requests.

[0096] This embodiment also provides an interrupt controller for implementing the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that implements a predetermined function. Although the apparatus described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0097] This embodiment provides an interrupt controller, such as Figure 5 As shown, it includes:

[0098] Interrupt receiving unit 501 is used to receive multiple interrupt requests.

[0099] Interrupt handling unit 502 is used to determine the current priority of each interrupt request among multiple interrupt requests based on the N historical processing times of each interrupt request among multiple interrupt requests, where N is a positive integer.

[0100] Interrupt redistribution unit 503 is used to send multiple interrupt requests to the processor according to the current priority order of the multiple interrupt requests.

[0101] Interrupt receiving unit 501 is identical to interrupt receiving unit 410, interrupt processing unit 502 is identical to interrupt processing unit 420, and interrupt redistribution unit 503 is identical to interrupt redistribution unit 430.

[0102] In some optional implementations, the interrupt handling unit 502 includes:

[0103] The first processing unit is used to determine the current priority of each interrupt request among the multiple interrupt requests based on the N historical processing times of each interrupt request among the multiple interrupt requests and the previous priority of each interrupt request among the multiple interrupt requests. The previous priority is the priority of the interrupt request obtained when the corresponding interrupt request was processed last time.

[0104] In some optional implementations, the first processing unit includes:

[0105] The first processing subunit is used to determine the preset priority of each interrupt request among multiple interrupt requests.

[0106] The second processing subunit is used to determine the first processing duration of each interrupt request among multiple interrupt requests. The first processing duration is the average of the N historical processing durations of the corresponding interrupt request.

[0107] The third processing subunit is used to determine the second processing duration for each interrupt request among multiple interrupt requests. The second processing duration is the average of the processing durations required for the M interrupt requests before processing the corresponding interrupt request, where M is a positive integer.

[0108] The fourth processing subunit is used to determine the current priority of each interrupt request among multiple interrupt requests based on the first processing duration, the second processing duration, and the previous priority using the following formula:

[0109]

[0110] Where P is the current priority of the corresponding interrupt request, α is the weighting coefficient, and P f The preset priority for the interrupt request is T, where T is the first processing time for the interrupt request. E P is the second processing time corresponding to the interruption request. n-1 The previous priority level for the interrupt request.

[0111] In some optional implementations, the interrupt handling unit 502 further includes:

[0112] The second processing unit is used to determine the current priority of each interrupt request among the multiple interrupt requests as the corresponding preset priority when processing multiple interrupt requests for the first time.

[0113] In some alternative implementations, the second processing subunit includes:

[0114] The determining unit is used to determine the first processing duration based on the third processing duration and the fourth processing duration. The third processing duration is the Nth historical processing duration, and the fourth processing duration is the average of the previous N-1 historical processing durations, where N≥2.

[0115] In some alternative implementations, the interrupt controller further includes:

[0116] The control register is used to store the first processing duration of each of the multiple interrupt requests in the interrupt controller.

[0117] In some alternative implementations, when a preset priority is given priority, the weighting coefficient can take any value from 0.5 to 1.

[0118] Further functional descriptions of the above modules and units are the same as those in the corresponding embodiments described above, and will not be repeated here.

[0119] In this embodiment, the interrupt controller is presented in the form of a functional unit. Here, a unit refers to an application-specific integrated circuit (ASIC), a processor and memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0120] This invention also provides a computer device having the above-described features. Figure 5 The interrupt controller shown.

[0121] Please see Figure 6 , Figure 6 This is a schematic diagram of the structure of a computer device provided in an optional embodiment of the present invention, such as... Figure 6As shown, the computer device includes one or more processors 610, memory 620, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a GUI on external input / output devices (such as display devices coupled to the interfaces). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 6 Take the 610 processor as an example.

[0122] The processor 610 may be a central processing unit, a network processor, or a combination thereof. The processor 610 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GDA), or any combination thereof.

[0123] The memory 620 stores instructions executable by at least one processor 610 to cause the at least one processor 610 to perform the method shown in the above embodiments.

[0124] The memory 620 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the computer device. Furthermore, the memory 620 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 620 may optionally include memory remotely located relative to the processor 610, and these remote memories may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0125] The memory 620 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 620 may also include a combination of the above types of memory.

[0126] The computer device also includes a communication interface 630 for communicating with other devices or communication networks.

[0127] This invention also provides a computer-readable storage medium. The methods described above according to embodiments of the invention can be implemented in hardware or firmware, or implemented as computer code that can be recorded on a storage medium, or implemented as computer code downloaded via a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and then stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the methods shown in the above embodiments.

[0128] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. An interrupt control method, characterized in that, Applied to an interrupt controller, the method includes: Receive multiple interrupt requests; Based on the N historical processing times of each interrupt request among the plurality of interrupt requests, the current priority of each interrupt request among the plurality of interrupt requests is determined, where N is a positive integer; The multiple interrupt requests are sent to the processor in the order of their current priorities. The step of determining the current priority of each interrupt request based on the N historical processing times of each interrupt request among the plurality of interrupt requests includes: Determine the preset priority of each interrupt request among the plurality of interrupt requests; Determine a first processing time for each of the plurality of interrupt requests, wherein the first processing time is the average of the N historical processing times of the corresponding interrupt request; Determine a second processing time for each of the plurality of interrupt requests, wherein the second processing time is the average of the processing times required for the M interrupt requests prior to processing the corresponding interrupt request, where M is a positive integer; Based on the first processing time, the second processing time, and the previous priority, the current priority of each interrupt request among the plurality of interrupt requests is determined by the following formula: in, P This represents the current priority of the corresponding interrupt request. These are the weighting coefficients. The preset priority corresponding to the interruption request. The first processing time corresponding to the interruption request. The second processing time corresponding to the interruption request. The previous priority corresponding to the interrupt request is the priority of the interrupt request obtained when the corresponding interrupt request was processed last time.

2. The method according to claim 1, characterized in that, The method further includes: In the case of processing the multiple interrupt requests for the first time, the current priority of each interrupt request is the corresponding preset priority.

3. The method according to claim 1, characterized in that, Determining the first processing duration for each of the plurality of interruption requests includes: The first processing duration is determined based on the third processing duration and the fourth processing duration. The third processing duration is the Nth historical processing duration, and the fourth processing duration is the average of the previous N-1 historical processing durations, where N≥2.

4. The method according to any one of claims 1 to 3, characterized in that, The method further includes: The interrupt controller stores the first processing duration of each of the plurality of interrupt requests.

5. The method according to any one of claims 1 to 3, characterized in that, Under the premise of preset priority, the weight coefficient can take any value from 0.5 to 1.

6. An interrupt controller, characterized in that, The interrupt controller includes: The interrupt receiving unit is used to receive multiple interrupt requests; An interrupt handling unit is configured to determine the current priority of each interrupt request among the plurality of interrupt requests based on the N historical processing times of each interrupt request among the plurality of interrupt requests, where N is a positive integer; specifically, the interrupt handling unit is configured to: determine a preset priority of each interrupt request among the plurality of interrupt requests; determine a first processing time for each interrupt request among the plurality of interrupt requests, the first processing time being the average of the N historical processing times of the corresponding interrupt request; determine a second processing time for each interrupt request among the plurality of interrupt requests, the second processing time being the average of the processing times required for the M interrupt requests preceding the corresponding interrupt request, where M is a positive integer; and determine the current priority of each interrupt request among the plurality of interrupt requests according to the first processing time, the second processing time, and the previous priority using the following formula: Where P is the current priority of the corresponding interrupt request. These are the weighting coefficients. The preset priority corresponding to the interruption request. The first processing time corresponding to the interruption request. The second processing time corresponding to the interruption request. The previous priority corresponding to the interrupt request is the priority of the interrupt request obtained when the corresponding interrupt request was processed last time; An interrupt redistribution unit is used to send the multiple interrupt requests to the processor in the order of their current priorities.

7. A computer device, characterized in that, include: A memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, the processor executing the computer instructions to perform the method of any one of claims 1 to 5.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing a computer to perform the method of any one of claims 1 to 5.

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