Chip and terminal

Abstract

The application provides a chip and a terminal, and can make a chip based on magnetic domain wall logic have a timing function. The chip comprises a magnetic material layer and a conductive layer which are arranged in a stack, the magnetic material layer comprises a first trunk, a second trunk, a first branch and a second branch, and the first branch and the second branch constitute a closed loop. The first branch comprises a first transmission branch, a logic operation branch and a second transmission branch which are connected in sequence, and the second branch comprises a third transmission branch, a feedback branch and a fourth transmission branch which are connected in sequence; the first transmission branch and the third transmission branch are connected with the first trunk, and the second transmission branch and the fourth transmission branch are connected with the second trunk. The line width of the first transmission branch is smaller than that of the third transmission branch, and the line width of the second transmission branch is larger than that of the fourth transmission branch. The conductive layer is used for transmitting current, so that the magnetic domains of the magnetic material layer are alternately moved from the first trunk to the second trunk and from the second trunk to the first trunk.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of electromagnetic technology, in particular to a chip and a terminal. BACKGROUND

[0002] The minimum unit of integrated circuit is transistor, and the existing technology usually controls the flow of electrons through the transistor to realize various functions of the integrated circuit. With the development of integrated circuits following Moore's Law, the integrated circuits are constantly developing towards high density and low power consumption, and the process nodes of the integrated circuits have been reduced to single-digit nanometer level. The feature size of the transistor is getting closer to the quantum size (5nm or less), and many physical effects, such as short channel effect and quantum tunneling, will cause the leakage current of the integrated circuit to increase, and even the integrated circuit to fail. In order to ensure the normal switching function of the transistor, the traditional integrated circuit will become more and more difficult in the process of size miniaturization.

[0003] In order to solve the above problems, electromagnetism based on the spin characteristics of electrons can work at lower power consumption and can realize non-volatile storage, and has been widely studied in recent years to replace transistors. Among them, the domain wall logic (DWL) is considered to be a strong candidate in the post-Moore era due to its ultimate miniaturization, fast speed, simple structure and less heat generation during operation.

[0004] However, the scale of the magnetic domain wall logic circuit that can be realized at present is limited to combinational logic circuits, and the circuit functions that can be realized by the combinational logic circuits are relatively simple and have no timing, which has great limitations in the application of large-scale circuits. SUMMARY

[0005] The present application provides a chip and a terminal, which can enable the chip based on the magnetic domain wall logic to have timing functions.

[0006] In a first aspect, the present application provides a chip, which comprises a magnetic material layer and a conductive layer stacked, the magnetic material layer comprises a first trunk, a second trunk, a first branch and a second branch, and the first branch and the second branch constitute a closed loop. The first branch comprises a first transmission branch, a logic operation branch and a second transmission branch connected in sequence, and the second branch comprises a third transmission branch, a feedback branch and a fourth transmission branch connected in sequence; the first transmission branch and the third transmission branch are connected with the first trunk, and the second transmission branch and the fourth transmission branch are connected with the second trunk.

[0007] The line width of the first transmission branch is less than the line width of the third transmission branch, and the line width of the second transmission branch is greater than the line width of the fourth transmission branch. The first trunk includes a first part and a second part between the first part and the first branch and the second branch, and the second trunk includes a third part and a fourth part between the third part and the first branch and the second branch. The magnetization direction of the first part, the third part, the first transmission branch, the third transmission branch and the second branch is perpendicular to the interface between the magnetic material layer and the conductive layer, and the magnetization direction of the second part and the fourth part is parallel to the interface.

[0008] The conductive layer is used to transmit current to make the magnetic domains of the magnetic material layer alternately move from the first trunk to the second trunk, and from the second trunk to the first trunk. Wherein, the direction of the first trunk to the second trunk can be the first direction, and the direction of the second trunk to the first trunk can be the second direction.

[0009] In the present application, in the case that the magnetic domain of the magnetic material layer moves from the first trunk to the second trunk, because the line width of the second transmission branch in the first branch is greater than the line width of the fourth transmission branch in the second branch, the energy of the electromagnetic signal transmitted by the second transmission branch is greater than the energy of the electromagnetic signal transmitted by the fourth transmission branch. Compared with the fourth transmission branch, the second transmission branch can play a majority voting role, so that the read electromagnetic signal read from the second trunk is the electromagnetic signal transmitted by the second transmission branch.

[0010] In the case that the magnetic domain of the magnetic material layer moves from the first trunk to the second trunk, because the line width of the first transmission branch in the first branch is less than the line width of the third transmission branch, the energy of the electromagnetic signal transmitted by the third transmission branch is greater than the energy of the electromagnetic signal transmitted by the first transmission branch. Compared with the first transmission branch, the third transmission branch can play a majority voting role, so that the read electromagnetic signal read from the first trunk is the electromagnetic signal transmitted by the third transmission branch.

[0011] By changing the magnetic domain logic composed of the first transmission branch and the logical operation branch, the magnetization direction of the magnetic domain transmitted to the second transmission branch and the magnetization direction of the magnetic domain transmitted to the third transmission branch are changed, so as to change the read electromagnetic signal read by the first trunk and the second trunk. And a continuous current pulse is applied to the conductive layer to make the magnetic material layer periodically output 0 and 1, so as to realize the timing of the chip based on the magnetic domain wall logic in the present application.

[0012] In addition, the simulation experiment shows that the reliability of the magnetic material layer in normally outputting the read electromagnetic signal can be improved by making the first part, the second part, the first transmission branch and the second transmission branch constitute an inverter, and making the third part, the fourth part, the third transmission branch and the fourth transmission branch constitute an inverter. If the first part, the second part, the first transmission branch and the second transmission branch do not constitute an inverter, and the third part, the fourth part, the third transmission branch and the fourth transmission branch do not constitute an inverter, but the magnetization directions of the first trunk, the second trunk, the first transmission branch, the second transmission branch, the third transmission branch and the fourth transmission branch are all OOP, the magnetic material layer will not be able to normally output data.

[0013] In some possible implementations, the conductive layer includes a first conductive layer, which is arranged on one side of the magnetic material layer. When the current flows along the first trunk in a direction pointing to the second trunk, the magnetic domains move from the first trunk to the second trunk. When the current flows along the second trunk in a direction pointing to the first trunk, the magnetic domains move from the second trunk to the first trunk.

[0014] When the chip is in operation, the current flows in the first direction, and the write electromagnetic signal can be input to the first trunk. Under the driving of the current in the first direction, the write electromagnetic signal is transmitted to the second trunk along the first branch and the second branch respectively, and the read electromagnetic signal is read out from the second trunk.

[0015] Since the line width of the second transmission branch in the first branch is greater than the line width of the fourth transmission branch in the second branch, the energy of the electromagnetic signal transmitted by the second transmission branch is greater than the energy of the electromagnetic signal transmitted by the fourth transmission branch. Compared with the fourth transmission branch, the second transmission branch can play a majority voting role, so that the read electromagnetic signal read out from the second trunk is the electromagnetic signal transmitted by the second transmission branch.

[0016] Then, the current flows in the second direction, and the write electromagnetic signal can be input to the second trunk. Under the driving of the current in the first direction, the write electromagnetic signal is transmitted to the first trunk along the second trunk and the first branch respectively, and is transmitted to the first trunk along the second trunk and the second branch, and the read electromagnetic signal is read out from the first trunk.

[0017] Since the line width of the first transmission branch in the first branch is less than the line width of the third transmission branch, the energy of the electromagnetic signal transmitted by the third transmission branch is greater than the energy of the electromagnetic signal transmitted by the first transmission branch. Compared with the first transmission branch, the third transmission branch can play a majority voting role, so that the read electromagnetic signal read out from the first trunk is the electromagnetic signal transmitted by the third transmission branch.

[0018] In this case, the chip further comprises a first current generating circuit, a second current generating circuit, a first switch and a second switch. The first conductive layer comprises a first current terminal and a second current terminal, the first current terminal coincides with the first trunk, and the second current terminal coincides with the second trunk. The first current generating circuit is electrically connected to the first current terminal through the first switch, and the second current generating circuit is electrically connected to the second current terminal through the second switch.

[0019] In this way, when the first switch is closed and the second switch is opened, the first current generating circuit can provide the first conductive layer with a current in the first direction through the first switch to drive the magnetic domains of the magnetic material layer to move in the first direction. When the second switch is closed and the first switch is opened, the second current generating circuit can provide the first conductive layer with a current in the second direction through the second switch to drive the magnetic domains of the magnetic material layer to move in the second direction.

[0020] In some possible implementations, the conductive layer comprises a first conductive layer and a second conductive layer, and the first conductive layer and the second conductive layer are arranged on opposite sides of the magnetic material layer. The current flows in the direction from the first trunk to the second trunk through the first conductive layer and the second conductive layer alternately, so that the magnetic domains of the magnetic material layer move alternately from the first trunk to the second trunk and from the second trunk to the first trunk. The material of the magnetic material layer is a magnetic insulating material.

[0021] When the chip works, a unidirectional current is applied to one end of the first conductive layer coinciding with the first trunk, a write electromagnetic signal is input to the first trunk, and under the drive of the current in the first direction, the write electromagnetic signal is transmitted along the first branch and the second branch to the second trunk respectively, and a read electromagnetic signal is read out from the second trunk.

[0022] Since the line width of the second transmission branch is greater than that of the fourth transmission branch, the energy of the electromagnetic signal transmitted by the second transmission branch in the first branch is greater than that of the electromagnetic signal transmitted by the fourth transmission branch in the second branch. Compared with the fourth transmission branch, the second transmission branch can play a majority voting role, so that the read electromagnetic signal read out from the second trunk is the electromagnetic signal transmitted by the second transmission branch.

[0023] Then, a unidirectional current is applied to one end of the second conductive layer coinciding with the first trunk, a write electromagnetic signal is input to the second trunk, and under the drive of the current in the first direction, the write electromagnetic signal is transmitted along the first branch and the second branch to the first trunk respectively, and a read electromagnetic signal is read out from the first trunk.

[0024] Since the line width of the first transmission branch in the first branch is smaller than the line width of the third transmission branch in the second branch, the energy of the electromagnetic signal transmitted by the third transmission branch is greater than the energy of the electromagnetic signal transmitted by the first transmission branch, and the third transmission branch can play a majority role compared with the first transmission branch, so that the read electromagnetic signal read from the first trunk is the electromagnetic signal transmitted by the third transmission branch.

[0025] Although the direction of the current when writing the write electromagnetic signal from the first trunk and writing the write electromagnetic signal from the second trunk is the first direction, according to the spin Hall effect, since the first conductive layer and the second conductive layer are respectively located on the opposite sides of the magnetic material layer, the directions of the magnetic domain movement driven by the current are opposite.

[0026] In this case, the chip further includes a current generation circuit and a multiplexing gating circuit. The first conductive layer includes a third current terminal and a fourth current terminal, and the second conductive layer includes a fifth current terminal and a sixth current terminal. The third current terminal and the fifth current terminal coincide with the first trunk, and the fourth current terminal and the sixth current terminal coincide with the second trunk. The current generation circuit is electrically connected to the third current terminal and the fifth current terminal through the multiplexing gating circuit, and the fourth current terminal and the sixth current terminal are grounded.

[0027] In this way, the current generation circuit inputs the current in the first direction to the first conductive layer through the multiplexing gating circuit to drive the magnetic domain of the magnetic material layer to move in the first direction. The current generation circuit inputs the current in the first direction to the second conductive layer through the multiplexing gating circuit to drive the magnetic domain of the magnetic material layer to move in the second direction.

[0028] In some possible implementations, the logic operation branch is used as an inverter. The logic operation branch includes a first sub-logic operation branch, a second sub-logic operation branch and a third sub-logic operation branch connected in sequence. The magnetization directions of the first sub-logic operation branch and the third sub-logic operation branch are perpendicular to the interface, and the magnetization direction of the second sub-logic operation branch is parallel to the interface.

[0029] Taking the initial state as inputting 1 to the first trunk, the initial flow direction of the current is the first direction, and the initial movement direction of the magnetic domain is the first direction as an example, the electromagnetic signals read from the magnetic material layer in one period are digital signals 0, 0, 1 and 1 respectively. After that, the current can be continuously applied, that is, the magnetic material layer can be periodically output 0 and 1, so that the chip based on the magnetic domain wall logic realizes timing.

[0030] In some possible implementation manners, the logic operation branch includes the second sub-logic operation branch and the third sub-logic operation branch connected in sequence. The magnetic material layer further includes a first bias voltage end and a second bias voltage end, the magnetization directions of the first bias voltage end, the second bias voltage end, and the third sub-logic operation branch are perpendicular to the interface, and the magnetization direction of the second sub-logic operation branch is parallel to the interface. Under the driving of the current, when the magnetic domain of the magnetic material layer moves from the first trunk to the second trunk, the first bias voltage end inputs the first digital signal or the second digital signal to the second sub-logic operation branch, the first digital signal is opposite to the second digital signal, and the second bias voltage end inputs the digital signal to the second sub-logic branch, which is the same as the digital signal input by the first transmission branch to the second sub-logic branch.

[0031] In a case where the first bias voltage end inputs the first digital signal to the first sub-logic operation branch, and the first digital signal is 0, the first bias voltage end, the second bias voltage end, the first transmission branch, and the logic operation branch can constitute an NAND gate.

[0032] Taking an initial state of inputting 1 to the first trunk, an initial flow direction of the current being the first direction, and an initial moving direction of the magnetic domain being the first direction as an example, in one period, the electromagnetic signals read from the magnetic material layer are digital signals 0, 0, 1, and 1. Then, the current can be continuously applied, so that the magnetic material layer periodically outputs 0 and 1, thereby realizing the timing of the chip based on the magnetic domain wall logic.

[0033] In a case where the first bias voltage end inputs the second digital signal to the first sub-logic operation branch, and the first digital signal is 1, the first bias voltage end, the second bias voltage end, the first transmission branch, and the logic operation branch can constitute an NOR gate.

[0034] Taking an initial state of inputting 1 to the first trunk, an initial flow direction of the current being the first direction, and an initial moving direction of the magnetic domain being the first direction as an example, in one period, the electromagnetic signals read from the magnetic material layer are digital signals 0, 0, 1, and 1. Then, the current can be continuously applied, so that the magnetic material layer periodically outputs 0 and 1, thereby realizing the timing of the chip based on the magnetic domain wall logic.

[0035] In some possible implementation manners, under the driving of the current, the magnetic material layer is used as a Fibonacci linear feedback shift register. The first transmission branch includes N register units connected in sequence, and the N register units are arranged from the first register unit to the Nth register unit in a direction from the first trunk to the second trunk; N is a positive integer.

[0036] The logic operation branch includes a plurality of exclusive-OR operation branches, and the plurality of taps in the N-bit register unit are connected with the exclusive-OR operation branches; and the line width of the first transmission branch is greater than the line width of each exclusive-OR operation branch. The plurality of exclusive-OR operation branches include exclusive-OR gates, which are used to feed back the exclusive-OR result of the plurality of taps in the exclusive-OR operation branches to the first trunk through the second branch.

[0037] The structure of the application can not only realize the shift function, but also feed back the exclusive-OR result of the logic operation branch to the first register unit. Moreover, by making the line width of the first transmission branch greater than the line width of the exclusive-OR operation branch connected with the tap, the moving speed of the magnetic domain of the N-bit register unit can be made less than the moving speed of the magnetic domain in the exclusive-OR operation branch connected with the first register unit. In this way, it can be ensured that the exclusive-OR operation branch connected with the tap has completed the exclusive-OR calculation before the magnetic domain of the register unit moves to the adjacent register unit, thereby avoiding the change of the magnetization direction of the magnetic domain of the tap due to the movement of the magnetic domains of the plurality of register units during the exclusive-OR calculation, and further avoiding the change of the exclusive-OR result calculated by the exclusive-OR operation branch connected with the tap.

[0038] In some possible implementation manners, the chip further includes a second magnetic domain diode, which is connected with the adjacent register units and is used to move the magnetic domain along the direction from the first trunk to the second trunk.

[0039] Compared with the first mode, the second mode can apply the current in the first direction once less in one period. Moreover, since the exclusive-OR calculation and the shift are realized under the driving of the current in the first direction, and the feedback is realized under the driving of the current in the second direction, the second magnetic domain diode can be arranged between the adjacent register units to avoid the magnetic domain that has been shifted from moving back under the driving of the current in the second direction.

[0040] In some possible implementation manners, for the case that the magnetic material layer is used as the Fibonacci linear feedback shift register, the chip further includes a first magnetic domain diode, which is arranged at the input side of the exclusive-OR gate and is used to move the magnetic domain in the tap along the direction from the first trunk to the second trunk. In this way, the magnetic domain of each exclusive-OR operation branch will not move back to each tap even under the driving of the current in the second direction.

[0041] In a second aspect, a terminal is provided, which includes a circuit board and the chip of the first aspect, and the chip is arranged on the circuit board.

[0042] The second aspect and any kind of implementation form of the second aspect correspond to the first aspect and any kind of implementation form of the first aspect respectively. The technical effects corresponding to the second aspect and any kind of implementation form of the second aspect can refer to the technical effects corresponding to the first aspect and any kind of implementation form of the first aspect, which will not be described herein again. BRIEF DESCRIPTION OF DRAWINGS

[0043] Figure 1 A structure schematic diagram of a chip provided by an embodiment of the present application;

[0044] Figure 2 Another structure schematic diagram of a chip provided by an embodiment of the present application;

[0045] Figure 3 A top view of a magnetic material layer provided by an embodiment of the present application;

[0046] Figure 4a A working process diagram of a magnetic material layer provided by an embodiment of the present application when used as an inverter;

[0047] Figure 4b A working process diagram of a magnetic material layer provided by an embodiment of the present application when used as an inverter;

[0048] Figure 4c A working process diagram of a magnetic material layer provided by an embodiment of the present application when used as an inverter;

[0049] Figure 5a A working process diagram of a magnetic material layer provided by an embodiment of the present application;

[0050] Figure 5b A working process diagram of a magnetic material layer provided by an embodiment of the present application;

[0051] Figure 5c A working process diagram of a magnetic material layer provided by an embodiment of the present application;

[0052] Figure 5d A working process diagram of a magnetic material layer provided by an embodiment of the present application;

[0053] Figure 6 A structure schematic diagram of a NAND gate provided by an embodiment of the present application;

[0054] Figure 7a Another working process diagram of a magnetic material layer provided by an embodiment of the present application;

[0055] Figure 7b Another working process diagram of a magnetic material layer provided by an embodiment of the present application;

[0056] Figure 7cAnother working process diagram of the magnetic material layer provided by the embodiment of the present application;

[0057] Figure 7d Another working process diagram of the magnetic material layer provided by the embodiment of the present application;

[0058] Figure 8 A structure schematic diagram of the NOR gate provided by the embodiment of the present application;

[0059] Figure 9a Another working process diagram of the magnetic material layer provided by the embodiment of the present application;

[0060] Figure 9b Another working process diagram of the magnetic material layer provided by the embodiment of the present application;

[0061] Figure 9c Another working process diagram of the magnetic material layer provided by the embodiment of the present application;

[0062] Figure 9d Another working process diagram of the magnetic material layer provided by the embodiment of the present application;

[0063] Figure 10 A circuit connection diagram of the Fibonacci linear feedback shift register provided by the embodiment of the present application;

[0064] Figure 11a Another working process diagram of the magnetic material layer provided by the embodiment of the present application;

[0065] Figure 11b Another working process diagram of the magnetic material layer provided by the embodiment of the present application;

[0066] Figure 12a Another working process diagram of the magnetic material layer provided by the embodiment of the present application;

[0067] Figure 12b Another working process diagram of the magnetic material layer provided by the embodiment of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0069] 10 - conductive layer; 11 - first conductive layer; 12 - second conductive layer; 21 - first main path; 211 - first part; 212 - second part; 22 - second main path; 221 - third part; 222 - fourth part; 23 - first branch; 231 - first transmission branch; 232 - logical operation branch; 2321 - first sub-logical operation branch; 2322 - second sub-logical operation branch; 2323 - third sub-logical operation branch; 233 - second transmission branch; 24 - second branch; 241 - third transmission branch; 242 - feedback branch; 243 - fourth transmission branch; 25 - first bias voltage terminal; 26 - second bias voltage terminal; 31 - first current generating circuit; 32 - second current generating circuit; 33 - current generating circuit; 34 - multiplexing gating circuit; 41 - register unit; 42 - XOR operation branch; 43 - first magnetic domain diode; 44 - second magnetic domain diode; DETAILED DESCRIPTION

[0070] In order to make the purpose, technical scheme and advantages of the present application clearer, the technical scheme of the present application will be described clearly and completely below in conjunction with the drawings in the present application. Obviously, the described embodiments are some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by those of ordinary skill in the art without any creative work fall within the scope of protection of the present application.

[0071] The terms "first", "second", etc. in the description embodiments of the present application and claims and drawings are only used for distinguishing purposes and should not be understood as indicating or implying relative importance. They should also not be understood as indicating or implying an order. "And / or" is used to describe the association relationship of the associated objects, which means that there can be three relationships, for example, "A and / or B" can mean that there are three cases of only A, only B and A and B at the same time, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after it. "Installation", "connection", "connection" and the like should be broadly understood, for example, it can be fixed connection, or detachable connection, or integrally connected; it can be direct connection, or indirect through intermediate medium, or internal communication of two elements. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a series of steps or units. The method, system, product or device is not necessarily limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices. "Up", "down", "left", "right" and the like are only used for the orientation of the components in the drawings, and these directional terms are relative concepts, which are used for relative description and clarification, which can change accordingly according to the change of the orientation of the components in the drawings.

[0072] The terminal provided by the embodiments of the present application can also be a mobile phone, a computer, a tablet computer, a personal digital assistant (PDA), a smart wearable device, a smart home device, a traffic light, and the like, which includes a time sequence circuit, and the embodiments of the present application are not limited thereto. The terminal can include a circuit board and a chip, the chip can be arranged on the circuit board, the chip can be integrated with an integrated circuit, and the time sequence circuit can be integrated on the chip as at least part of the integrated circuit.

[0073] Compared with the output of the combinational logic circuit at any time, only the input at the current time is dependent on the original state of the combinational logic circuit. The time sequence circuit contains a memory element to determine the current state according to the original state. The basic unit of the time sequence circuit can include a latch and a flip-flop. The flip-flop can include a reset-set (RS) type flip-flop, a JK (jump-key) type flip-flop, a D (data) type flip-flop, and a T (trigger) type flip-flop, etc.

[0074] Taking a D flip-flop as an example, the D flip-flop has the function of keeping the input state at the clock rising moment and is a clock synchronous sequential circuit. The D flip-flop is a basic element of a sequential circuit and has a very wide range of uses. For example, a multi-stage combination of the D flip-flop can be applied to a shift register, a frequency division circuit, etc., and can also be used for a register in a central processing unit (CPU) and the like. Therefore, in order to better solve a series of problems caused by size miniaturization of a traditional integrated circuit, implementation of a sequential logic circuit based on magnetic domain wall logic is imminent.

[0075] Based on this, an embodiment of the present application provides a chip which can be used as the above-mentioned sequential circuit, so that the circuit based on magnetic domain wall logic has a sequential function. The specific structure of the chip will be described in detail below in combination with the drawings.

[0076] As shown in FIG. 1, Figure 1 the chip includes a magnetic material layer and a conductive layer 10 which are arranged in a stack, the magnetic material layer includes a first trunk 21, a second trunk 22, a first branch 23 and a second branch 24, and the first branch 23 and the second branch 24 form a closed loop.

[0077] The first branch 23 includes a first transmission branch 231, a logic operation branch 232 and a second transmission branch 233 which are connected in sequence, and the second branch 24 includes a third transmission branch 241, a feedback branch 242 and a fourth transmission branch 243 which are connected in sequence. The first transmission branch 231 and the third transmission branch 241 are connected with the first trunk 21, and the second transmission branch 233 and the fourth transmission branch 243 are connected with the second trunk 22. The line width of the first transmission branch 231 is smaller than the line width of the third transmission branch 241, and the line width of the second transmission branch 233 is larger than the line width of the fourth transmission branch 243.

[0078] As shown in FIG. 1, Figure 3 the first trunk 21 includes a first part 201 and a second part 212 which is located between the first part 211 and the first branch 23 and the second branch 24. The second trunk 22 includes a third part 221 and a fourth part 222 which is located between the third part 221 and the first branch 23 and the second branch 24; the magnetization direction of the first part 211, the third part 221, the first branch 23 and the second branch 24 is perpendicular to the interface between the magnetic material layer and the conductive layer 10, and the magnetization direction of the second part 212 and the fourth part 222 is parallel to the interface.

[0079] The conductive layer 10 is used for transmitting current, so as to make the magnetic domains of the magnetic material layer alternately move from the first trunk 21 to the second trunk 22 and from the second trunk 22 to the first trunk 21. For the convenience of description, the direction from the first trunk 21 to the second trunk 22 can be a first direction, and the direction from the second trunk 22 to the first trunk 21 can be a second direction.

[0080] The first branch 23 and the second branch 24 constitute a closed loop, which means that the closed loop has a starting point and an ending point adjacent to each other. The starting point can be the intersection of the first transmission branch 231 and the third transmission branch 241 with the first trunk 21, and the ending point can be the intersection of the second transmission branch 232 and the fourth transmission branch 242 with the second trunk 22.

[0081] In one embodiment, the conductive layer 10 includes a first conductive layer 11, and the first conductive layer 11 is arranged on one side of the magnetic material layer. Since the first conductive layer 11 is arranged in a stack with the magnetic material layer, based on the above-mentioned closed loop, when a unidirectional current is applied to the first conductive layer 11 along the first direction and the second direction in time, the magnetic domains in the magnetic material layer can move along the direction of the current flow in time.

[0082] For example, the current flows along the first direction, and the write electromagnetic signal can be input to the first trunk 21. Under the driving of the current along the first direction, the write electromagnetic signal is transmitted along the first branch 23 and the second branch 24 with the magnetic domains, respectively, to the second trunk 22, and the read electromagnetic signal is read from the second trunk 22.

[0083] Since the line width of the second transmission branch 233 in the first branch 23 is greater than the line width of the fourth transmission branch 243 in the second branch 24, the energy of the electromagnetic signal transmitted by the second transmission branch 233 is greater than the energy of the electromagnetic signal transmitted by the fourth transmission branch 243. Compared with the fourth transmission branch 243, the second transmission branch 233 can play a majority voting role, so that the read electromagnetic signal read from the second trunk 22 is the electromagnetic signal transmitted by the second transmission branch 233.

[0084] For another example, the current flows along the second direction, and the write electromagnetic signal can be input to the second trunk 22. Under the driving of the current along the first direction, the write electromagnetic signal is transmitted along the second trunk 22 and the first branch 23 with the magnetic domains, respectively, to the first trunk 21, and is transmitted along the second trunk 22 and the second branch 24 to the first trunk 21, and the read electromagnetic signal is read from the first trunk 22.

[0085] Since the line width of the first transmission branch 231 in the first branch 23 is less than the line width of the third transmission branch 241, the energy of the electromagnetic signal transmitted by the third transmission branch 241 is greater than the energy of the electromagnetic signal transmitted by the first transmission branch 231. Compared with the first transmission branch 231, the third transmission branch 241 can play a majority voting role, so that the read electromagnetic signal read from the first trunk 21 is the electromagnetic signal transmitted by the third transmission branch 241.

[0086] In some possible implementations, as Figure 1As shown, the current for driving the magnetic domain movement can be provided by the first current generating circuit 31 and the second current generating circuit 32. That is, the chip can further include the first current generating circuit 31 and the second current generating circuit 32. On this basis, the chip further includes the first switch K1 and the second switch K2. The first conductive layer 11 includes a first current terminal and a second current terminal, the first current terminal coincides with the first trunk 21, and the second current terminal coincides with the second trunk 22. The first current generating circuit 31 can be electrically connected to the first current terminal through the first switch K1, and the second current generating circuit 32 can be electrically connected to the second current terminal through the second switch K2.

[0087] In this way, when the first switch K1 is closed and the second switch K2 is opened, the first current generating circuit 31 can provide the first conductive layer 11 with a current in the first direction through the first switch K1 to drive the magnetic domain of the magnetic material layer to move in the first direction. When the second switch K2 is closed and the first switch K1 is opened, the second current generating circuit 32 can provide the first conductive layer 11 with a current in the second direction through the second switch K2 to drive the magnetic domain of the magnetic material layer to move in the second direction.

[0088] Here, if the chip further includes a substrate, the first current terminal and the magnetic material layer can be stacked on the substrate. The first current terminal coincides with the first trunk 21, that is, the orthographic projection of the first current terminal on the substrate coincides with the orthographic projection of the first trunk 21 on the substrate. The second current terminal coincides with the second trunk 22, that is, the orthographic projection of the second current terminal on the substrate coincides with the orthographic projection of the second trunk 22 on the substrate. The orthographic projection of the first current terminal on the substrate is the projection of the first current terminal on the substrate in the direction in which the first current terminal points to the substrate. The orthographic projection of other structures on the substrate can be explained with reference to the orthographic projection of the first current terminal on the substrate, which will not be described here.

[0089] In some possible implementation manners, the application does not limit the way of writing the write electromagnetic signal and reading the read electromagnetic signal.

[0090] Optionally, the write electromagnetic signal can be input by applying an external magnetic field, and the signal can be read by a magnetic imaging technology such as a magnetic force microscope (MFM), a magneto-optical kerr effect (MOKE), or a schematics of the scanning transmission x-ray microscope (STXM).

[0091] Optionally, a magnetoresistive random access memory (MRAM) can also be used to read / write electromagnetic signals. Using a magnetoresistive random access memory to read / write electromagnetic signals can realize fast movement of magnetic domains and magnetic domain walls and fast reading and writing of electromagnetic signals, which is conducive to large-scale integration of magnetic material layers in chips and industrial production.

[0092] For example, using a magnetoresistive random access memory to read / write electromagnetic signals, the read electromagnetic signal can be identified as 1 or 0 in the following manner: the information carrier of the magnetoresistive random access memory is a magnetic tunnel junction (MTJ), each magnetic tunnel junction includes a fixed layer and a free layer. The magnetization direction of the fixed layer is fixed, and the magnetization direction of the free layer can be changed by a spin torque. When the magnetization directions of the fixed layer and the free layer are the same, the resistance value of the magnetic tunnel junction is the lowest, indicating that the read electromagnetic signal is 0; otherwise, when the magnetization directions of the fixed layer and the free layer are opposite, the resistance value of the magnetic tunnel junction is the highest, indicating that the read electromagnetic signal is 1.

[0093] Of course, other ways of writing a write electromagnetic signal, reading a read electromagnetic signal, and identifying a read electromagnetic signal as 1 or 0 can also be used, which are not limited in the embodiments of the present application.

[0094] In addition, in the embodiments of the present application, the material of the magnetic material layer can include a magnetic insulating material and / or a magnetic metal material, which are not limited in the embodiments of the present application. For example, in the direction of the magnetic material layer pointing to the conductive layer 10, the magnetic material layer can include cobalt (Co) or an alloy of cobalt, iron, and boron.

[0095] In another embodiment, the conductive layer 10 includes a first conductive layer 11 and a second conductive layer 12, and the first conductive layer 11 and the second conductive layer 12 are respectively arranged on opposite sides of the magnetic material layer. The current alternately flows through the first conductive layer 11 and the second conductive layer 12 in the direction of the first trunk 21 pointing to the second trunk 22, so that the magnetic domains of the magnetic material layer alternately move from the first trunk 21 to the second trunk 22 and from the second trunk 22 to the first trunk 21. The material of the magnetic material layer is a magnetic insulating material to avoid short circuit of the first conductive layer 11 and the second conductive layer 12 through the magnetic material layer. For example, the material of the magnetic material layer can include yttrium iron garnet.

[0096] Since the first conductive layer 11 and the second conductive layer 12 are respectively located on opposite sides of the magnetic material layer, based on the closed loop formed by the first branch 23 and the second branch 24, unidirectional current is applied to one end of the first conductive layer 11 coinciding with the first trunk 21 and one end of the second conductive layer 12 coinciding with the first trunk 21 in time, the magnetic domain in the magnetic material layer can be moved in the first direction and the second direction in time. Although the write electromagnetic signal is written from the first trunk 21, and the write electromagnetic signal is written from the second trunk 22, the direction of the current is the first direction, but according to the spin Hall effect, since the first conductive layer 11 and the second conductive layer 12 are respectively located on opposite sides of the magnetic material layer, the direction of the magnetic domain driven by the current is opposite.

[0097] Of course, unidirectional current can also be applied to one end of the first conductive layer 11 coinciding with the second trunk 22 and one end of the second conductive layer 12 coinciding with the second trunk 22 in time, and the embodiment of the application does not limit this. In order to facilitate understanding, the following is described by applying current to one end of the first conductive layer 11 and one end of the second conductive layer 12 coinciding with the first trunk 21.

[0098] For example, unidirectional current is applied to one end of the first conductive layer 11 coinciding with the first trunk 21, and the write electromagnetic signal is input to the first trunk 21, and under the drive of the current in the first direction, the write electromagnetic signal is transmitted along the first branch 23 and the second branch 24 with the magnetic domain respectively to the second trunk 22, and the read electromagnetic signal is read from the second trunk 22.

[0099] Since the line width of the second transmission branch 233 is greater than the line width of the fourth transmission branch 243, the energy of the electromagnetic signal transmitted by the second transmission branch 233 in the first branch 23 is greater than the energy of the electromagnetic signal transmitted by the fourth transmission branch 243 in the second branch 24. Compared with the fourth transmission branch 243, the second transmission branch 233 can play a majority voting role, so that the read electromagnetic signal read from the second trunk 22 is the electromagnetic signal transmitted by the second transmission branch 233.

[0100] For example, unidirectional current is applied to one end of the second conductive layer 12 coinciding with the first trunk 21, and the write electromagnetic signal is input to the second trunk 22, and under the drive of the current in the first direction, the write electromagnetic signal is transmitted along the first branch 23 and the second branch 24 with the magnetic domain respectively to the first trunk 21, and the read electromagnetic signal is read from the first trunk 21.

[0101] Since the line width of the first transmission branch 231 in the first branch 23 is smaller than the line width of the third transmission branch 241 in the second branch 24, the energy of the electromagnetic signal transmitted by the third transmission branch 241 is greater than the energy of the electromagnetic signal transmitted by the first transmission branch 231, and compared with the first transmission branch 231, the third transmission branch 241 can play a majority voting role, so that the read electromagnetic signal read from the first trunk 21 is the electromagnetic signal transmitted by the third transmission branch 241.

[0102] One end (hereinafter referred to as the third current end) of the first conductive layer 11 coincides with the first trunk 21, that is, the orthogonal projection of the one end of the first conductive layer 11 on the substrate coincides with the orthogonal projection of the first trunk 21 on the substrate. One end (hereinafter referred to as the fourth current end) of the first conductive layer 11 coincides with the second trunk 22, that is, the orthogonal projection of the one end of the first conductive layer 11 on the substrate coincides with the orthogonal projection of the second trunk 22 on the substrate. One end (hereinafter referred to as the fifth current end) of the second conductive layer 12 coincides with the first trunk 21, that is, the orthogonal projection of the one end of the second conductive layer 12 on the substrate coincides with the orthogonal projection of the first trunk 21 on the substrate. One end (hereinafter referred to as the sixth current end) of the second conductive layer 12 coincides with the second trunk 22, that is, the orthogonal projection of the one end of the second conductive layer 12 on the substrate coincides with the orthogonal projection of the second trunk 22 on the substrate.

[0103] In some possible implementation manners, as shown in Figure 2 The current for driving the movement of the magnetic domain can be provided by the current generation circuit 33. That is, the chip can further include the current generation circuit 33. On this basis, the chip further includes a multiplexing gating circuit 34. The first conductive layer 11 includes a third current end and a fourth current end, and the second conductive layer 12 includes a fifth current end and a sixth current end. The third current end and the fifth current end coincide with the first trunk 21, and the fourth current end and the sixth current end coincide with the second trunk 22. The current generation circuit 33 is electrically connected to the third current end and the fifth current end through the multiplexing gating circuit 34, and the fourth current end and the sixth current end are grounded.

[0104] In this way, the current generation circuit 33 inputs a current in the first direction to the first conductive layer 11 through the a path of the multiplexing gating circuit 34, so as to drive the magnetic domain of the magnetic material layer to move in the first direction. The current generation circuit 33 inputs a current in the first direction to the second conductive layer 12 through the b path of the multiplexing gating circuit 34, so as to drive the magnetic domain of the magnetic material layer to move in the second direction.

[0105] In some possible implementation manners, the manner in which the present application embodiment inputs a write electromagnetic signal, reads a read electromagnetic signal, and identifies whether the read electromagnetic signal is 1 or 0 is the same as that in the manner in which the aforementioned conductive layer 10 does not include the second conductive layer 12, which will not be described herein again.

[0106] Both of the above embodiments are exemplified by the magnetic domain moving first in the first direction and then in the second direction. In other possible implementations, the magnetic domain can first move in the second direction and then move in the first direction.

[0107] In addition, in some possible implementations, the material and the pattern of the conductive layer 10 are not limited. Optionally, the material of the conductive layer 10 can include heavy metals, for example, the material of the conductive layer 10 can include platinum (Pt) or tungsten (W). The shape of the conductive layer 10 can be flat; or the pattern of the conductive layer 10 can be the same as the pattern of the magnetic material layer, that is, the shape of the orthographic projection of the conductive layer 10 on the substrate is the same as the shape of the orthographic projection of the magnetic material layer on the substrate.

[0108] When the current is applied to the flat conductive layer 10, the current can flow irregularly in the first direction or the second direction. When the current is applied to the conductive layer 10 with the same pattern as the magnetic material layer, the current can flow in the first direction or the second direction along the pattern of the conductive layer 10, which is more conducive to driving the magnetic domain to move.

[0109] In some possible implementations, the first part 211 and the second part 212 of the first bus 21, and the first transmission branch 231 of the first branch 23 and the third transmission branch 241 of the second branch 24 can constitute an inverter. The third part and the fourth part of the second bus 22, and the second transmission branch 233 of the first branch 23 and the fourth transmission branch 243 of the second branch 24 can constitute an inverter.

[0110] Specifically, as shown in Figures 4a-4c The chip further includes an oxide layer covering the magnetic material layer, and the oxide layer can be used to change the magnetization direction of the magnetic material layer.

[0111] For example, the oxide layer can be aluminum oxide (AlOx) obtained by oxidizing aluminum (Al). Before the aluminum is oxidized, the magnetization direction of the magnetic material layer is parallel to the interface, which can also be said to be in-plane (IP). After the aluminum is oxidized to obtain the aluminum oxide, the magnetization direction of the part of the magnetic material layer coinciding with the aluminum oxide changes from IP to perpendicular to the interface, which can also be said to be out-of-plane (OOP). The shape is that an IP region is embedded on a nanowire with an OOP magnetization direction.

[0112] As shown in Figure 4a Taking the inverter constituted by the third part 221, the fourth part 222, the second transmission branch 233, and the fourth transmission branch 243 as an example, it is assumed that the current flows in the first direction and the magnetic domain moves in the first direction. As shown in Figure 4aAs shown, the initial magnetization direction of the magnetic domains on the second transmission branch 233 and the fourth transmission branch 243 is vertically downward, and the initial magnetization direction of the magnetic domains on the third portion is vertically upward. As shown in FIG. 2B, under the drive of the current in the first direction, the magnetic domains also move in the first direction, and after passing through the fourth portion 222, the third portion 221 outputs magnetic domains with a magnetization direction of vertically downward (i.e., the magnetic domains in the third portion 221 close to the fourth portion 222). Figure 4b As shown, magnetic domains with a magnetization direction of vertically upward are input to the second transmission branch 233 and the fourth transmission branch 243. Under the drive of the current in the first direction, the magnetic domains also move in the first direction, and after passing through the fourth portion 222, the third portion 221 outputs magnetic domains with a magnetization direction of vertically downward (i.e., the magnetic domains in the third portion 221 close to the fourth portion 222).

[0113] If the magnetic domains with a magnetization direction of vertically downward represent the digital signal 1, and the magnetic domains with a magnetization direction of vertically upward represent the digital signal 0, then the magnetic domains output by the third portion 221 are 1. For the convenience of description, the following description takes the magnetic domains with a magnetization direction of vertically downward to represent the digital signal 1, and the magnetic domains with a magnetization direction of vertically upward to represent the digital signal 0 as an example.

[0114] Through simulation experiments, it is found that by making the first portion 211, the second portion 212, the first transmission branch 231, and the second transmission branch 241 constitute an inverter, and making the third portion 221, the fourth portion 222, the third transmission branch 233, and the fourth transmission branch 243 constitute an inverter, the reliability of the magnetic material layer to normally output the read electromagnetic signal can be improved.

[0115] If the first portion 211, the second portion 212, the first transmission branch 231, and the second transmission branch 241 do not constitute an inverter, and the third portion 221, the fourth portion 222, the third transmission branch 233, and the fourth transmission branch 243 do not constitute an inverter, but the magnetization directions of the first trunk 21, the second trunk 22, the first transmission branch 231, the second transmission branch 241, the third transmission branch 233, and the fourth transmission branch 243 are all OOP, then the magnetic material layer will not be able to normally output data.

[0116] By using the conductive layer 10 and the magnetic material layer mentioned in the above two embodiments, by changing the magnetic domain logic constituted by the first transmission branch 231 and the logic operation branch 232, the magnetization direction of the magnetic domains transmitted to the second transmission branch and the magnetization direction of the magnetic domains transmitted to the third transmission branch can be changed, so as to change the read electromagnetic signal read by the first trunk and the second trunk. By applying a continuous current pulse, the magnetic material layer can periodically output 0 and 1, so as to realize the timing of the chip based on the magnetic domain wall logic in the present application.

[0117] It should be noted that the embodiments of this application do not limit the magnetic domain logic constituted by the first transmission branch 231 and the logic operation branch 232. For example, it can be used as an inverter, AND gate, NAND gate, NOR gate, etc. The following lists the cases in which the magnetic material layer periodically outputs 0 and 1 when the logic operation branch 232 is used as an inverter, NAND gate, or NOR gate. For ease of description, the following cases are all described with the structure of the aforementioned conductive layer 10 including the first conductive layer 11 but excluding the second conductive layer 12.

[0118] The first case, such as Figures 5a-5d As shown, logic operation branch 232 is used as an inverter. Logic operation branch 232 includes a first sub-logic operation branch 2321, a second sub-logic operation branch 2322, and a third sub-logic operation branch 2323 connected in sequence. The magnetization directions of the first sub-logic operation branch 2321 and the third sub-logic operation branch 2323 are perpendicular to the interface, while the magnetization direction of the second sub-logic operation branch 2322 is parallel to the interface.

[0119] Taking the initial state as inputting 1 to the first main circuit 21, the initial flow direction of current J as the first direction, and the initial movement direction of the magnetic domains as the first direction as an example, as follows: Figure 5a As shown, the first part 211 of the first trunk 21 receives digital signal 1. After passing through an inverter formed by the first part 211, the second part 212, and the first transmission branch 231, the digital signal 1 transmitted by the first part 211 is input to the first transmission branch 231 as digital signal 0. After passing through an inverter formed by the first part 211, the second part 212, and the third transmission branch 241, the digital signal 1 transmitted by the first part 211 is input to the third transmission branch 241 as digital signal 0.

[0120] The digital signal 0 transmitted by the first transmission branch 231 is inverted by the first sub-logic branch 2321, the second sub-logic branch 2322, and the third sub-logic branch 2323, and then inputs the digital signal 1 into the second transmission branch 233; the digital signal 0 transmitted by the third transmission branch 241 is inverted by the feedback branch 242 and then inputs the digital signal 0 into the fourth transmission branch 243.

[0121] Since the line width of the second transmission branch 233 is greater than that of the fourth transmission branch 243, the second transmission branch 233 has the majority voting right and can input the digital signal 1 to the second trunk 22.

[0122] The digital signal 1 transmitted by the second transmission branch 233 passes through the inverter composed of the second transmission branch 233, the fourth part 222, and the third part 221. The electromagnetic signal output by the third part 222 is the digital signal 0.

[0123] Next, as Figure 5bAs shown, the direction of current J is changed so that current J flows in the second direction. The digital signal 0 output by the third part 222 in the previous stage can be used as the input digital signal. The digital signal 0 transmitted by the third part 222 passes through the inverter formed by the third part 221, the fourth part 222, and the second transmission branch 233, and then inputs the digital signal 1 into the second transmission branch 233; the digital signal 0 transmitted by the third part 222 passes through the inverter formed by the third part 221, the fourth part 222, and the fourth transmission branch 243, and then inputs the digital signal 1 into the fourth transmission branch 243.

[0124] The digital signal 1 transmitted by the second transmission branch 233 is input to the first transmission branch 231 after passing through the inverter formed by the first sub-logic branch 2321, the second sub-logic branch 2322, and the third sub-logic branch 2323; the digital signal 1 transmitted by the fourth transmission branch 243 is input to the third transmission branch 241 after passing through the feedback branch 242.

[0125] Since the line width of the third transmission branch 241 is greater than that of the first transmission branch 231, the third transmission branch 241 has the majority voting right and can input the digital signal 1 to the first trunk 21.

[0126] The digital signal 1 transmitted by the third transmission branch 241 is converted into a digital signal 0 after passing through the inverter composed of the third transmission branch 241, the second part 212, and the first part 211.

[0127] Next, as Figure 5c As shown, the direction of current J is changed again, causing current J to flow in the first direction. The digital signal 0 output by the first part 212 in the previous stage can be used as the input digital signal. The digital signal 0 transmitted by the first part 211 passes through the inverter formed by the first part 211, the second part 212, and the first transmission branch 231, and then inputs the digital signal 1 into the first transmission branch 231; the digital signal 0 transmitted by the first part 211 passes through the inverter formed by the first part 211, the second part 212, and the third transmission branch 241, and then inputs the digital signal 1 into the third transmission branch 241.

[0128] The digital signal 1 transmitted by the first transmission branch 231 is inverted by the first sub-logic branch 2321, the second sub-logic branch 2322, and the third sub-logic branch 2323, and then inputs the digital signal 0 into the second transmission branch 233; the digital signal 0 transmitted by the third transmission branch 241 is inverted by the feedback branch 242 and then inputs the digital signal 1 into the fourth transmission branch 243.

[0129] Since the line width of the second transmission branch 233 is greater than that of the fourth transmission branch 243, the second transmission branch 233 has the majority voting right and can input the digital signal 0 to the second trunk 22.

[0130] The digital signal 0 transmitted by the second transmission branch 233 passes through the inverter composed of the second transmission branch 233, the fourth part 222, and the third part 221. The electromagnetic signal output by the third part 222 is the digital signal 1.

[0131] Next, as Figure 5d As shown, the direction of current J is changed so that current J flows in the second direction. The digital signal 1 output by the third part 222 in the previous stage can be used as the input digital signal. After the digital signal 1 transmitted by the third part 222 passes through the inverter composed of the third part 221, the fourth part 222, and the second transmission branch 233, the digital signal 0 is input to the second transmission branch 233; after the digital signal 1 transmitted by the third part 222 passes through the inverter composed of the third part 221, the fourth part 222, and the fourth transmission branch 243, the digital signal 0 is input to the fourth transmission branch 243.

[0132] The digital signal 0 transmitted by the second transmission branch 233 is input to the first transmission branch 231 after passing through the inverter formed by the first sub-logic branch 2321, the second sub-logic branch 2322, and the third sub-logic branch 2323; the digital signal 0 transmitted by the fourth transmission branch 243 is input to the third transmission branch 241 after passing through the feedback branch 242.

[0133] Since the line width of the third transmission branch 241 is greater than that of the first transmission branch 231, the third transmission branch 241 has the majority voting right and can input the digital signal 0 to the first trunk 21.

[0134] The digital signal 0 transmitted by the third transmission branch 241 is converted into a digital signal 1 by an inverter composed of the third transmission branch 241, the second part 212, and the first part 211.

[0135] The electromagnetic signals output from the above four steps are digital signals 0, 0, 1, and 1, respectively. Afterward, a current can be continuously applied, repeating the above four steps, to periodically cause the magnetic material layer to output 0 and 1, thereby enabling the chip based on magnetic domain wall logic to achieve timing.

[0136] The second scenario, such as Figure 6 As shown, logic operation branch 232 is used as a NAND gate. Logic operation branch 232 includes a second sub-logic operation branch 2322 and a third sub-logic operation branch 2323 connected in sequence.

[0137] The magnetic material layer further comprises a first bias voltage terminal 25 and a second bias voltage terminal 26, the magnetization directions of the first bias voltage terminal 25 and the second bias voltage terminal 26 and the third sub-logic operation branch 2323 are perpendicular to the interface, and the magnetization direction of the second sub-logic operation branch 2322 is parallel to the interface.

[0138] Under the driving of the current J, when the magnetic domain of the magnetic material layer moves from the first trunk 21 to the second trunk 22, the first bias voltage terminal 25 inputs a first digital signal to the second sub-logic operation branch 2322, and the first digital signal is 0; the digital signal inputted by the second bias voltage terminal 26 to the second sub-logic branch 2322 is the same as the digital signal inputted by the first transmission branch 231 to the second sub-logic branch 2322.

[0139] As shown in Figure 6 , in the case that the first digital signal inputted by the first bias voltage terminal 25 to the second sub-logic operation branch 2322 is 0, the first bias voltage terminal 25, the second bias voltage terminal 26, the first transmission branch 231 and the logic operation branch 232 can constitute an NAND gate.

[0140] For example, the first transmission branch 231 receives the digital signal 1 inputted by the first trunk 21, and the second bias voltage terminal 26 also inputs the digital signal 1 to the second sub-logic operation branch 2322, the three digital signals inputted to the second sub-logic operation branch 2322 are 1, 1 and 0 respectively, and the three digital signals 1, 1 and 0 output 0 after passing through the NAND gate.

[0141] For another example, the first transmission branch 231 receives the digital signal 0 inputted by the first trunk 21, and the second bias voltage terminal 26 also inputs the digital signal 0 to the second sub-logic operation branch 2322, the three digital signals inputted to the second sub-logic operation branch 2322 are 0, 0 and 0 respectively, and the three digital signals 0, 0 and 0 output 1 after passing through the NAND gate.

[0142] Taking the initial state that the input to the first trunk 21 is 1 and the initial flow direction of the current J is the first direction as an example, as shown in Figure 7a , the first part 211 of the first trunk 21 receives the digital signal 1. The digital signal 1 transmitted by the first part 211 inputs the digital signal 0 to the first sub-transmission branch 2311 and the second sub-transmission branch 2312 of the first transmission branch 231 after passing through the inverter composed of the first part 211, the second part 212 and the first transmission branch 231; the digital signal 1 transmitted by the first part 211 inputs the digital signal 0 to the third transmission branch 241 after passing through the inverter composed of the first part 211, the second part 212 and the third transmission branch 241.

[0143] The digital signal 0 transmitted from the first bias voltage terminal 25 and the second bias voltage terminal 26, and the digital signal 0 transmitted from the first transmission branch 231, are fed into the second transmission branch 233 after passing through a NAND gate; the digital signal 0 transmitted from the third transmission branch 241 is fed into the fourth transmission branch 243 after passing through the feedback branch 242.

[0144] Since the line width of the second transmission branch 233 is greater than that of the fourth transmission branch 243, the second transmission branch 233 has the majority voting right. The read electromagnetic signal read by the second trunk 22 is a digital signal transmitted from the second transmission branch 233 to the second trunk 22.

[0145] The digital signal 1 transmitted by the second transmission branch 233 passes through the inverter composed of the second transmission branch 233, the fourth part 222, and the third part 221. The electromagnetic signal output by the third part 222 is the digital signal 0.

[0146] Next, as Figure 7b As shown, the direction of current J is changed so that current J flows in the second direction. The digital signal 0 output by the third part 222 in the previous stage can be used as the input digital signal. The digital signal 0 transmitted by the third part 222 passes through the inverter formed by the third part 221, the fourth part 222, and the second transmission branch 233, and then inputs the digital signal 1 into the second transmission branch 233; the digital signal 0 transmitted by the third part 222 passes through the inverter formed by the third part 221, the fourth part 222, and the fourth transmission branch 243, and then inputs the digital signal 1 into the fourth transmission branch 243.

[0147] Because the linewidth of the third transmission branch 241 is greater than that of the first transmission branch 231, the third transmission branch 241 has majority voting rights. That is, the read electromagnetic signal read from the first trunk 21 is a digital signal transmitted to the first trunk 21 after passing through the feedback branch 242 and the third transmission branch 241 from the fourth transmission branch 243.

[0148] The digital signal 1 transmitted by the third transmission branch 241 is converted into a digital signal 0 after passing through the inverter composed of the third transmission branch 241, the second part 212, and the first part 211.

[0149] Next, as Figure 7cAs shown, the direction of current J is changed so that current J flows in the first direction. The digital signal 0 output by the third part 222 in the previous stage can be used as the input digital signal. The digital signal 0 transmitted by the first part 211 passes through the inverter formed by the first part 211, the second part 212, and the first transmission branch 231, and then inputs the digital signal 1 to the first sub-transmission branch 2311 and the second sub-transmission branch 2312 of the first transmission branch 231; the digital signal 1 transmitted by the first part 211 passes through the inverter formed by the first part 211, the second part 212, and the third transmission branch 241, and then inputs the digital signal 1 to the third transmission branch 241.

[0150] The digital signal 0 transmitted from the first bias voltage terminal 25 and the second bias voltage terminal 26, and the digital signal 1 transmitted from the first transmission branch 231, are fed into the second transmission branch 233 after passing through a NAND gate; the digital signal 1 transmitted from the third transmission branch 241 is fed into the fourth transmission branch 243 after passing through the feedback branch 242.

[0151] Since the line width of the second transmission branch 233 is greater than that of the fourth transmission branch 243, the second transmission branch 233 has the majority voting right. The read electromagnetic signal read by the second trunk 22 is a digital signal transmitted from the second transmission branch 233 to the second trunk 22.

[0152] The digital signal 0 transmitted by the second transmission branch 233 passes through the inverter composed of the second transmission branch 233, the fourth part 222, and the third part 221. The electromagnetic signal output by the third part 222 is the digital signal 1.

[0153] Next, as Figure 7d As shown, the direction of current J is changed so that current J flows in the second direction. The digital signal 1 output by the third part 222 in the previous stage can be used as the input digital signal. The digital signal 1 transmitted by the third part 222 passes through the inverter formed by the third part 221, the fourth part 222, and the second transmission branch 233, and then inputs the digital signal 0 into the second transmission branch 233; the digital signal 0 transmitted by the third part 222 passes through the inverter formed by the third part 221, the fourth part 222, and the fourth transmission branch 243, and then inputs the digital signal 0 into the fourth transmission branch 243.

[0154] Because the linewidth of the third transmission branch 241 is greater than that of the first transmission branch 231, the third transmission branch 241 has majority voting rights. That is, the read electromagnetic signal read from the first trunk 21 is a digital signal transmitted to the first trunk 21 after passing through the feedback branch 242 and the third transmission branch 241 from the fourth transmission branch 243.

[0155] The digital signal 0 transmitted by the third transmission branch 241 is converted into a digital signal 1 by an inverter composed of the third transmission branch 241, the second part 212, and the first part 211.

[0156] The electromagnetic signals output from the above four steps are digital signals 0, 0, 1, and 1, respectively. Afterward, a current can be continuously applied, repeating the above four steps, to periodically cause the magnetic material layer to output 0 and 1, thereby enabling the chip based on magnetic domain wall logic to achieve timing.

[0157] The third scenario, such as Figure 8 As shown, logic operation branch 232 is used as a NAND gate. Logic operation branch 232 includes a second sub-logic operation branch 2322 and a third sub-logic operation branch 2323 connected in sequence.

[0158] The magnetic material layer also includes a first bias voltage terminal 25 and a second bias voltage terminal 26. The magnetization direction of the first bias voltage terminal 25, the second bias voltage terminal 26, and the third sub-logic operation branch 2323 is perpendicular to the interface, and the magnetization direction of the second sub-logic operation branch 2322 is parallel to the interface.

[0159] Driven by current J, when the magnetic domains of the magnetic material layer move from the first trunk 21 to the second trunk 22, the first bias voltage terminal 25 inputs a second digital signal to the second sub-logic operation branch 2322, and the second digital signal is 1; the digital signal input by the second bias voltage terminal 26 to the second sub-logic branch 2322 is the same as the digital signal input by the first transmission branch 231 to the second sub-logic branch 2322.

[0160] like Figure 8 As shown, when the first digital signal input from the first bias voltage terminal 25 to the second sub-logic operation branch 2322 is 1, the first bias voltage terminal 25, the second bias voltage terminal 26, the first transmission branch 231, and the logic operation branch 232 can form a NOR gate.

[0161] For example, the first transmission branch 231 receives the digital signal 1 input from the first trunk 21, and the second bias voltage terminal 26 also inputs the digital signal 1 to the second sub-logic operation branch 2322. The three digital signals input to the second sub-logic operation branch 232 are 1, 1, and 1, respectively. After the three digital signals 1, 1, and 1 pass through the NOR gate, the output is 0.

[0162] For example, the first transmission branch 2311 receives the digital signal 0 input from the first trunk 21, and the second bias voltage terminal 26 also inputs the digital signal 0 to the second sub-logic operation branch 2322. The three digital signals input to the second sub-logic operation branch 2322 are 0, 0, and 1, respectively. After the three digital signals 0, 0, and 1 pass through the NOR gate, the output is 1.

[0163] Taking the initial state as inputting 1 to the first main circuit 21, the initial flow direction of current J as the first direction, and the initial movement direction of the magnetic domains as the first direction as an example, as follows: Figure 9a As shown, the first part 211 of the first trunk 21 receives digital signal 1. After passing through the inverter formed by the first part 211, the second part 212, and the first transmission branch 231, the digital signal 1 transmitted by the first part 211 is input to the first sub-transmission branch 2311 and the second sub-transmission branch 2312 of the first transmission branch 231; after passing through the inverter formed by the first part 211, the second part 212, and the third transmission branch 241, the digital signal 1 transmitted by the first part 211 is input to the third transmission branch 241.

[0164] The digital signal 1 transmitted from the first bias voltage terminal 25 and the second bias voltage terminal 26, and the digital signal 0 transmitted from the first transmission branch 231, are fed into the second transmission branch 233 after passing through an NOR gate; the digital signal 0 transmitted from the third transmission branch 241 is fed into the fourth transmission branch 243 after passing through the feedback branch 242.

[0165] Since the line width of the second transmission branch 233 is greater than that of the fourth transmission branch 243, the second transmission branch 233 has the majority voting right. The read electromagnetic signal read by the second trunk 22 is a digital signal transmitted from the second transmission branch 233 to the second trunk 22.

[0166] The digital signal 1 transmitted by the second transmission branch 233 passes through the inverter composed of the second transmission branch 233, the fourth part 222, and the third part 221. The electromagnetic signal output by the third part 222 is the digital signal 0.

[0167] Next, as Figure 9b As shown, the direction of current J is changed so that current J flows in the second direction. The digital signal 0 output by the third part 222 in the previous stage can be used as the input digital signal. The digital signal 0 transmitted by the third part 222 passes through the inverter formed by the third part 221, the fourth part 222, and the second transmission branch 233, and then inputs the digital signal 1 into the second transmission branch 233; the digital signal 0 transmitted by the third part 222 passes through the inverter formed by the third part 221, the fourth part 222, and the fourth transmission branch 243, and then inputs the digital signal 1 into the fourth transmission branch 243.

[0168] Because the linewidth of the third transmission branch 241 is greater than that of the first transmission branch 231, the third transmission branch 241 has majority voting rights. That is, the read electromagnetic signal read from the first trunk 21 is a digital signal transmitted to the first trunk 21 after passing through the feedback branch 242 and the third transmission branch 241 from the fourth transmission branch 243.

[0169] The digital signal 1 transmitted by the third transmission branch 241 is converted into a digital signal 0 after passing through the inverter composed of the third transmission branch 241, the second part 212, and the first part 211.

[0170] Next, as Figure 9c As shown, the direction of current J is changed so that current J flows in the first direction. The digital signal 0 output by the third part 222 in the previous stage can be used as the input digital signal. The digital signal 0 transmitted by the first part 211 passes through the inverter formed by the first part 211, the second part 212, and the first transmission branch 231, and then inputs the digital signal 1 to the first sub-transmission branch 2311 and the second sub-transmission branch 2312 of the first transmission branch 231; the digital signal 1 transmitted by the first part 211 passes through the inverter formed by the first part 211, the second part 212, and the third transmission branch 241, and then inputs the digital signal 1 to the third transmission branch 241.

[0171] The digital signal 1 transmitted by the first bias voltage terminal 25, the second bias voltage terminal 26 and the first transmission branch 231 is fed into the second transmission branch 233 after passing through the NOR gate; the digital signal 1 transmitted by the third transmission branch 241 is fed into the fourth transmission branch 243 after passing through the feedback branch 242.

[0172] Since the line width of the second transmission branch 233 is greater than that of the fourth transmission branch 243, the second transmission branch 233 has the majority voting right. The read electromagnetic signal read by the second trunk 22 is a digital signal transmitted from the second transmission branch 233 to the second trunk 22.

[0173] The digital signal 0 transmitted by the second transmission branch 233 passes through the inverter composed of the second transmission branch 233, the fourth part 222, and the third part 221. The electromagnetic signal output by the third part 222 is the digital signal 1.

[0174] Next, as Figure 9dAs shown, the direction of current J is changed so that current J flows in the second direction. The digital signal 1 output by the third part 222 in the previous stage can be used as the input digital signal. After the digital signal 1 output by the third part 222 passes through the inverter composed of the third part 221, the fourth part 222 and the second transmission branch 233, the digital signal 0 is input to the second transmission branch 233; after the digital signal 0 output by the third part 222 passes through the inverter composed of the third part 221, the fourth part 222 and the fourth transmission branch 243, the digital signal 0 is input to the fourth transmission branch 243.

[0175] Since the line width of the third transmission branch 241 is greater than that of the first transmission branch 231, the third transmission branch 241 has the majority voting right. That is, the read electromagnetic signal read by the first trunk 21 is the digital signal transmitted to the first trunk 21 by the fourth transmission branch 243 after passing through the feedback branch 242 and the third transmission branch 241.

[0176] After the digital signal 0 transmitted by the third transmission branch 241 passes through the inverter composed of the third transmission branch 241, the second part 212 and the first part 211, the read electromagnetic signal output by the first part 211 is the digital signal 1.

[0177] The read electromagnetic signals output by the above four steps are digital signals 0, 0, 1 and 1 respectively. After that, the current can be continuously applied to circulate the above four steps, so that the magnetic material layer outputs 0 and 1 periodically, thereby realizing the timing of the chip based on the magnetic domain wall logic.

[0178] In addition, in some possible implementations, under the driving of the current J, the magnetic material layer can also be used as a Fibonacci linear feedback shift register.

[0179] Those skilled in the art should know that, for example, Figure 10 As shown, the working process of the Fibonacci linear feedback shift register is to perform an exclusive OR operation on multiple taps in the register unit, and then use the exclusive OR result as input and perform overall shift on each bit in the register unit.

[0180] For example, as shown in FIG. 6, the Fibonacci linear feedback shift register is composed of a plurality of register units 61, 62, 63, 64 and 65. Figure 10As shown, the Fibonacci linear feedback shift register includes 16 register units, among which the 11th bit, the 13th bit, the 14th bit and the 16th bit are taps, the tap at the rightmost side can be called output bit, and the taps other than the output bit are sequentially XORed with the output bit in the direction from right to left, and the XOR result is fed back to the leftmost bit. That is, the 14th bit register unit is first XORed with the 16th bit register unit to output the first XOR result; then, the 13th bit register unit is XORed with the first XOR result to output the second XOR result; then, the 11th bit register unit is XORed with the second XOR result to output the third XOR result, and the third XOR result is input to the 1st bit register unit at the leftmost side.

[0181] Here, the direction from right to left is the second direction, and the direction from left to right is the first direction.

[0182] In the present application, the magnetic material layer can be used as a Fibonacci linear feedback shift register in two ways.

[0183] The first way is as shown in FIG. 1. Figure 11a As shown, the first transmission branch 231 includes N-bit register units 41 connected in sequence, and the N-bit register units 41 are arranged from the 1st bit register unit to the Nth bit register unit in the direction of the first trunk 21 pointing to the second trunk 22. Wherein, N is a positive integer.

[0184] The logic operation branch 232 includes a plurality of XOR operation branches 42, and the plurality of taps in the N-bit register units 41 are connected with the XOR operation branches 42. The line width of the first transmission branch 231 is greater than the line width of each XOR operation branch 42. The XOR operation branch 42 includes an XOR gate, which is used to feed back the XOR result of the plurality of taps connected therewith in the XOR operation branch 42 to the first trunk 21 through the second branch 24.

[0185] In this way, the working process of the magnetic material layer used as a Fibonacci linear feedback shift register can be as follows:

[0186] As shown in FIG. 2, Figure 11aAs shown, still taking the tap of the 11th, 13th, 14th and 16th register units 41 as an example, the magnetization directions of the domains of the 11th and 16th register units are vertically downward, corresponding to the digital signal 1; the magnetization directions of the domains of the 13th and 14th register units are vertically upward, corresponding to the digital signal 0. The first direction current J is applied to the first conductive layer 11, and under the driving of the first direction current J, the domains of the plurality of register units 41 also move in the first direction, for example, the domain of the 1st register unit moves to the 2nd register unit. At the same time, under the driving of the first direction current J, the XOR operation branch 42 connected with the tap also receives the domains connected therewith and performs XOR calculation to obtain the XOR result (i.e., the third XOR result described above).

[0187] As shown, still taking the tap of the 11th, 13th, 14th and 16th register units 41 as an example, the magnetization directions of the domains of the 11th and 16th register units are vertically downward, corresponding to the digital signal 1; the magnetization directions of the domains of the 13th and 14th register units are vertically upward, corresponding to the digital signal 0. The first direction current J is applied to the first conductive layer 11, and under the driving of the first direction current J, the domains of the plurality of register units 41 also move in the first direction, for example, the domain of the 1st register unit moves to the 2nd register unit. At the same time, under the driving of the first direction current J, the XOR operation branch 42 connected with the tap also receives the domains connected therewith and performs XOR calculation to obtain the XOR result (i.e., the third XOR result described above).

[0188] As shown, still taking the tap of the 11th, 13th, 14th and 16th register units 41 as an example, the magnetization directions of the domains of the 11th and 16th register units are vertically downward, corresponding to the digital signal 1; the magnetization directions of the domains of the 13th and 14th register units are vertically upward, corresponding to the digital signal 0. The first direction current J is applied to the first conductive layer 11, and under the driving of the first direction current J, the domains of the plurality of register units 41 also move in the first direction, for example, the domain of the 1st register unit moves to the 2nd register unit. At the same time, under the driving of the first direction current J, the XOR operation branch 42 connected with the tap also receives the domains connected therewith and performs XOR calculation to obtain the XOR result (i.e., the third XOR result described above).

[0189] In order to avoid the change of the magnetization direction of the domain of the tap due to the movement of the domains of the plurality of register units 41 during the XOR calculation, and further avoid the change of the XOR result calculated by the XOR operation branch 42 connected with the tap, the line width of the first transmission branch 231 can be greater than the line width of each XOR operation branch 42. In this way, the movement speed of the domains in each register unit 41 can be less than the movement speed of the domains in the XOR operation branch 42, so that the domain of the register unit 41 located on the left side of the tap does not move into the tap and the domain of the tap does not move into the register unit 41 located on the right side of the tap before the XOR calculation of the XOR operation branch 42 connected with the tap is completed.

[0190] For example, the magnetization direction of the domain of the 16th register unit represents the digital signal 1, and the magnetization direction of the domain of the 15th register unit located at the left side thereof represents the digital signal 0. If the XOR operation branch 42 connected with the tap moves the domain of the 15th register unit to the 16th register unit in the process of XOR calculation, it will cause the magnetization direction of the domains of the 16th register unit and the XOR operation branch 42 connected with the 16th register unit to change from the digital signal 1 to the digital signal 0, thereby affecting the XOR result.

[0191] By making the line width of the first transmission branch 231 greater than the line width of the XOR operation branch 42 connected with the tap, the moving speed of the domains in the 15th register unit and the 16th register unit can be made less than the moving speed of the domain in the XOR operation branch 42 connected with the 16th register unit. In this way, it can be ensured that the XOR operation branch 42 connected with the tap has completed the XOR calculation before the domain of the 15th register unit moves to the 16th register unit.

[0192] Then, the XOR operation branch 42 can send the calculated third XOR result 0 to the second trunk 22, and after passing through the inverter composed of the XOR operation branch 42, the fourth part 222 and the third part 221, the third part 221 receives the digital signal 1.

[0193] Then, the current J of the second direction can be applied to the first conductive layer 11, and the third part 221 feeds back the digital signal 1 to the first trunk 21 through the second branch 24. After passing through the inverter composed of the second branch 24, the second part 212 and the first part 211, the first part 211 receives the digital signal 0.

[0194] At the same time, under the driving of the current of the second direction, the domains in each register unit 41 can also move back a distance in the second direction, which offsets the distance of the domains in each register unit 41 moving in the first direction under the driving of the current of the first direction.

[0195] On this basis, as shown in Figure 11b The chip can further include a first magnetic domain diode 43 arranged at the input side of the XOR gate of the XOR operation branch 42, for moving the domains in the taps in the direction of the second trunk from the first trunk 21. In this way, even under the driving of the current of the second direction, the domains of each XOR operation branch 42 will not move back to each tap.

[0196] Then, the current J of the first direction can be continuously applied to the first conductive layer 11, the magnetic domains of the register units 41 are moved along the first direction by increasing the current value of the current J of the first direction, and / or increasing the time of applying the current J of the first direction, and the magnetic domains of any register unit 41 are moved into the register unit 41 on the right side of the register unit 41, so as to complete the shift of the magnetic domains of the register units 41.

[0197] For example, the magnetic domain of the second register unit is moved into the third register unit, the magnetic domain of the first register unit is moved into the second register unit, the magnetic domain of the first part 211 is moved into the first register unit, and so on.

[0198] By periodically and continuously applying the current of the first direction, the second direction, and the second direction to the first conductive layer 11, multiple shifts of the register units 41 can be realized, so as to realize the function of the Fibonacci linear feedback shift register.

[0199] The second mode is shown in Figure 12a The first transmission branch 231 includes N register units 41 connected in sequence, and the N register units 41 are arranged from the first register unit to the Nth register unit in the direction of the first trunk 21 pointing to the second trunk 22. The chip further includes a second magnetic domain diode 44 connected between adjacent register units 41, for moving the magnetic domains in the direction of the first trunk 21 pointing to the second trunk 22.

[0200] The logic operation branch 232 includes a plurality of exclusive OR operation branches 42, and a plurality of taps in the N register units 41 are connected to the exclusive OR operation branches 42. The line width of the first transmission branch 231 is greater than the line width of each exclusive OR operation branch 42. The exclusive OR operation branch 42 includes an exclusive OR gate, for feeding back the exclusive OR result of the plurality of taps connected thereto in the exclusive OR operation branch 42 to the first trunk 21 through the second branch 24.

[0201] In this mode, the working process of the magnetic material layer as the Fibonacci linear feedback shift register can be as follows:

[0202] As Figure 12aAs shown, still taking the tap of the 11th, 13th, 14th and 16th register units 41 as an example, the magnetization directions of the domains of the 11th and 16th register units are vertically downward, corresponding to the digital signal 1; the magnetization directions of the domains of the 13th and 14th register units are vertically upward, corresponding to the digital signal 0. A current J of the first direction is applied to the first conductive layer 11, under the drive of the current J of the first direction, the domains of the plurality of register units 41 also move along the first direction, for example, the domain of the 1st register unit moves to the 2nd register unit. Meanwhile, under the drive of the current J of the first direction, the XOR operation branch 42 connected with the tap also receives the domains connected therewith and performs XOR calculation to obtain an XOR result (i.e., the third XOR result mentioned above).

[0203] As an example, the magnetization direction of the domain transmitted by the XOR operation branch 42 connected with the 16th register unit and the 11th register unit represents the digital signal 1, and the magnetization direction of the domain transmitted by the XOR operation branch 42 connected with the 14th register unit and the 13th register unit both represent the digital signal 0.

[0204] The digital signal 1 transmitted by the XOR operation branch 42 connected with the 16th register unit is first subjected to XOR calculation with the digital signal 0 transmitted by the XOR operation branch 42 connected with the 14th register unit to obtain a first XOR result 1. Then, the digital signal 0 transmitted by the XOR operation branch 42 connected with the 13th register unit is subjected to XOR calculation with the first XOR result 1 to obtain a second XOR result 1. Next, the digital signal 1 transmitted by the XOR operation branch 42 connected with the 11th register unit is subjected to XOR calculation with the second XOR result 1 to obtain a third XOR result 0.

[0205] The same as the first mode is that the line width of the first transmission branch 231 and the line width of the XOR operation branch 42 can be controlled to ensure that the domains of the register units 41 located at the left side of the tap do not move into the tap and the domain of the tap does not move into the register units 41 located at the right side of the tap before the XOR calculation of the XOR operation branch 42 connected with the tap is completed. But after the XOR calculation of the XOR operation branch 42 connected with the tap is completed, the domains of the register units 41 can move one bit to the right, for example, the domain of the 2nd register unit moves into the 3rd register unit and the domain of the 1st register unit moves into the 2nd register unit. That is, under the application of the current of the first direction, the XOR calculation is completed and the shift between the register units 41 is also completed.

[0206] Then, the second direction current J is applied to the first conductive layer 11, and the third part 221 feeds back the digital signal 1 to the first trunk 21 through the second branch 24. After passing through the inverter composed of the second branch 24, the second part 212 and the first part 211, the first part 211 receives the digital signal 0.

[0207] Meanwhile, since the chip further comprises the second magnetic domain diode 44 connected to the adjacent register units 41 for moving the magnetic domain of each register unit 41 along the first trunk 21 to the direction of the second trunk 22, the magnetic domain of the register unit 41 will not move along the second direction under the drive of the second direction current J.

[0208] On this basis, as shown in Figure 12b the chip can further comprise the first magnetic domain diode 43 arranged at the input side of the XOR gate of the XOR operation branch 42 for moving the magnetic domain in the tap along the first trunk 21 to the direction of the second trunk. In this way, even under the drive of the second direction current, the magnetic domain of each XOR operation branch 42 will not move back to each tap.

[0209] Afterwards, when the first direction current is applied to the first conductive layer 11 in the next period, the third XOR result 0 of the last period is input into the first bit register unit after being inverted. By continuously applying the first direction and the second direction current to the first conductive layer 11, multiple shifts of the register unit 41 can be realized, thereby realizing the function of the Fibonacci linear feedback shift register.

[0210] Compared with the first mode, the second mode can realize the shift by applying the first direction current once less in one period.

[0211] The above merely describes the specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of the changes or replacements within the technical range disclosed by the present application, which shall be covered within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A chip, characterized by The magnetic material layer includes a first main path, a second main path, a first branch path and a second branch path, and the first branch path and the second branch path form a closed loop; The first branch path includes a first transmission branch path, a logic operation branch path and a second transmission branch path connected in sequence, and the second branch path includes a third transmission branch path, a feedback branch path and a fourth transmission branch path connected in sequence; the first transmission branch path and the third transmission branch path are connected with the first main path, and the second transmission branch path and the fourth transmission branch path are connected with the second main path; The line width of the first transmission branch path is smaller than that of the third transmission branch path, and the line width of the second transmission branch path is larger than that of the fourth transmission branch path; the first main path includes a first part and a second part between the first part and the first branch path and the second branch path, and the second main path includes a third part and a fourth part between the third part and the first branch path and the second branch path; the magnetization direction of the first part, the third part, the first transmission branch path, the third transmission branch path and the second branch path is perpendicular to the interface between the magnetic material layer and the conductive layer, and the magnetization direction of the second part and the fourth part is parallel to the interface; The conductive layer is used for transmitting current to make the magnetic domains of the magnetic material layer alternately move from the first main path to the second main path and from the second main path to the first main path.

2. The chip according to claim 1, characterized in that, The conductive layer includes a first conductive layer arranged on one side of the magnetic material layer; When the current flows in the direction of the first main path pointing to the second main path, the magnetic domains move from the first main path to the second main path; When the current flows in the direction of the second main path pointing to the first main path, the magnetic domains move from the second main path to the first main path.

3. The chip of claim 2, wherein, The chip further includes a first current generating circuit, a second current generating circuit, a first switch and a second switch; The first conductive layer includes a first current terminal and a second current terminal, the first current terminal coincides with the first main path, and the second current terminal coincides with the second main path; The first current generating circuit is electrically connected with the first current terminal through the first switch, and the second current generating circuit is electrically connected with the second current terminal through the second switch.

4. The chip of claim 1, wherein The conductive layer includes a first conductive layer and a second conductive layer arranged on opposite sides of the magnetic material layer; The current alternately flows through the first conductive layer and the second conductive layer in the direction of the first main path pointing to the second main path, so that the magnetic domains of the magnetic material layer alternately move from the first main path to the second main path and from the second main path to the first main path; The material of the magnetic material layer is a magnetic insulating material.

5. The chip of claim 4, wherein, The chip further includes a current generating circuit and a multiplexing gating circuit; The first conductive layer comprises a third current terminal and a fourth current terminal, the second conductive layer comprises a fifth current terminal and a sixth current terminal, the third current terminal and the fifth current terminal coincide with the first trunk, and the fourth current terminal and the sixth current terminal coincide with the second trunk; The current generation circuit is electrically connected with the third current terminal and the fifth current terminal through the multiplexing gating circuit, and the fourth current terminal and the sixth current terminal are grounded.

6. The chip according to any one of claims 1 to 5, characterized in that The logic operation branch serves as an inverter; The logic operation branch comprises a first sub-logic operation branch, a second sub-logic operation branch and a third sub-logic operation branch connected in sequence, the magnetization directions of the first sub-logic operation branch and the third sub-logic operation branch are perpendicular to the interface, and the magnetization direction of the second sub-logic operation branch is parallel to the interface.

7. The chip according to any one of claims 1 to 5, wherein The logic operation branch comprises a second sub-logic operation branch and a third sub-logic operation branch connected in sequence; The magnetic material layer further comprises a first bias voltage terminal and a second bias voltage terminal, the magnetization directions of the first bias voltage terminal, the second bias voltage terminal and the third sub-logic operation branch are perpendicular to the interface, and the magnetization direction of the second sub-logic operation branch is parallel to the interface; Under the driving of the current, when the magnetic domain of the magnetic material layer moves from the first trunk to the second trunk, the first bias voltage terminal inputs a first digital signal or a second digital signal to the second sub-logic operation branch, the first digital signal is opposite to the second digital signal, and the second bias voltage terminal inputs a digital signal to the second sub-logic branch which is the same as the digital signal inputted by the first transmission branch to the second sub-logic branch.

8. The chip of claim 1, wherein, Under the driving of the current, the magnetic material layer serves as a Fibonacci linear feedback shift register; The first transmission branch comprises N-bit register units connected in sequence, and the N-bit register units are arranged from a first bit register unit to an Nth bit register unit in the direction of the first trunk pointing to the second trunk; N is a positive integer; The logic operation branch comprises a plurality of XOR operation branches, a plurality of taps in the N-bit register units are connected with the XOR operation branches; and the line width of the first transmission branch is greater than the line width of each XOR operation branch. The plurality of XOR operation branches comprise an XOR gate for feeding back the XOR result of the plurality of taps connected therewith in the XOR operation branch to the first trunk through the second branch.

9. The chip of claim 8, wherein, The chip further comprises a first magnetic domain diode arranged at the input side of the XOR gate for moving the magnetic domain in the tap in the direction of the first trunk pointing to the second trunk.

10. The chip according to claim 8 or 9, characterized in that The chip further comprises a second magnetic domain diode connected with adjacent register units for moving the magnetic domain in the direction of the first trunk pointing to the second trunk.

11. A terminal, characterized by comprising: The chip according to any one of claims 1-10 is arranged on a circuit board.

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