A phase synchronization processing method and device for cameralink high-speed camera signals

Abstract

The present invention discloses a phase synchronization processing method and device for CameraLink high-speed camera signals. The method analyzes CameraLink high-speed camera frame data, detects the line frequency, field frequency, and resolution based on the camera's output synchronization signal, and performs frequency detection on the input clock frequency. A logical AND operation is performed on the line signal and frame signal of the first input data channel A1 to generate a write enable for the corresponding channel. Address counting is performed when the write enable is detected to be valid. Based on the count result, the currently valid data is temporarily stored in the corresponding area. Corresponding operations are performed on the input data channels A1, A2, ..., An, respectively, to temporarily store the data in the M1, M2, ..., Mn area blocks. The write enable and address are judged. When the write enable is detected to be valid, a read enable for the cache area is generated when the accumulated address count value equals a set first count threshold X. The present invention can adaptively resolve phase differences between different channels and improve signal phase synchronization.

Description

Technical Field

[0001] The present invention relates to the field of high-speed camera signal processing, and in particular discloses a phase synchronization processing method and device for cameralink high-speed camera signals. Background Art

[0002] With the continuous advancement of vision technology, high-performance CameraLink high-speed cameras are core components of vision systems and crucial for detecting the accuracy and speed of fast-moving objects. Capturing more information and features from images requires extremely high real-time image processing, so high-speed cameras are often used to capture the motion characteristics and trajectories of fast-moving objects. CameraLink high-speed camera technology has been widely used in industrial and military fields such as aerospace, shipbuilding, industrial automation, product inspection, particle imaging velocimetry, and biomedicine.

[0003] CameraLink high-speed camera signal technology is used in applications characterized by high frame rates and high bandwidth. While this technology can capture rich motion features and trajectories, it also increases the difficulty and complexity of data acquisition, processing, and transmission. Due to the diverse transmission channels, processing methods, and application scenarios used by CameraLink high-speed camera signals, the back-end acquisition and processing of camera output signals faces challenges such as high data throughput, high frame rates, and physical differences in transmission channels. This results in phase shifts in the pixels of the captured camera output images, affecting calculation and display accuracy.

[0004] Generally, high-speed camera signals are collected using a dedicated image processor. During the operation of the processor, due to differences in camera frame size and frame rate, processor operating temperature, etc., the collected camera image data has nonlinear and periodic uncertain phase differences between different channels, affecting the accuracy and stability of image calculation and display, and thus affecting the observation, analysis, recognition and tracking of object motion trajectories.

[0005] Therefore, the existing CameraLink high-speed camera has nonlinear and periodically uncertain phase differences between different channels, which is a technical problem that needs to be solved urgently. Summary of the Invention

[0006] The present invention provides a method and device for phase synchronization processing of CameraLink high-speed camera signals, aiming to solve the technical problem of nonlinear and periodically uncertain phase differences between different channels of existing CameraLink high-speed cameras.

[0007] One aspect of the present invention relates to a method for phase synchronization processing of a cameralink high-speed camera signal, comprising the following steps:

[0008] Parse the frame data of the CameraLink high-speed camera, detect the line frequency, field frequency and resolution size based on the synchronization signal output by the camera, and perform frequency detection on the input clock frequency;

[0009] Perform logical AND processing on the row signal and frame signal of the first input data channel A1 to generate the write enable of the corresponding channel. At the same time, perform address counting when the write enable is detected to be valid. According to the counting result, the current valid data is temporarily stored in the corresponding area.

[0010] According to the corresponding operations on the input data channels A1, A2...An, the data is temporarily suspended in the M1, M2...Mn area blocks respectively, where A1 is the first input data channel, A2 is the second input data channel, and An is the nth input data channel; M1, M2...Mn are independent cache area blocks; M1 is the first independent cache area block, M2 is the second independent cache area block, and Mn is the nth independent cache area block;

[0011] The write enable and address are judged. When the write enable is detected to be valid and the accumulated address count value is equal to the set first count threshold X, the cache area read enable is generated. At the same time, the read enable is output to the M1, M2...Mn area blocks respectively, and data is read from all cache area blocks simultaneously. If only one area block is used, the others are reserved area blocks. The first count threshold X is the threshold of the cache area address count.

[0012] Synchronously read the block and count the number of data read. When it is detected that the number of data read reaches a second counting threshold T, the read enable is reset to zero, the reading is stopped, and the data number counter is reset to zero. The second counting threshold T is the number of counts of a row of data output by the high-speed camera.

[0013] The synchronized data obtained from the cache area is sorted in pixel format according to the number of channels of each camera, and the sorted output of each port is performed according to the requirements of the CameraLink protocol. Depending on the configuration of the input camera, different bit order output modes are adapted through lookup table mapping.

[0014] Furthermore, the frame data of the CameraLink high-speed camera is parsed, and the line frequency, field frequency and resolution size are detected according to the synchronization signal output by the camera. In the step of frequency detection of the input clock frequency, the frame data of the CameraLink high-speed camera is parsed using a three-channel parallel processing method.

[0015] Furthermore, the cameralink high-speed camera frame data is parsed, and the line frequency, field frequency and resolution size are detected according to the synchronization signal output by the camera. In the step of frequency detection of the input clock frequency, the line frequency, field frequency and resolution size are detected according to the synchronization signal output by the camera through the synchronization signal detection module.

[0016] Furthermore, the cameralink high-speed camera frame data is parsed, and the line frequency, field frequency and resolution size are detected according to the synchronization signal output by the camera. In the step of frequency detection of the input clock frequency, the clock signal detection module is also used to detect the input clock frequency.

[0017] Furthermore, the row signal and frame signal of the first input data channel A1 are logically ANDed to generate a write enable for the corresponding channel. At the same time, address counting is performed when it is detected that the write enable is valid. According to the counting result, the current valid data is temporarily suspended in the step of the corresponding area. The valid data includes the synchronization signal and pixel data. When the write enable is invalid, the counting result is cleared synchronously.

[0018] Furthermore, the steps of performing corresponding operations on the input data channels A1, A2, ...An and temporarily suspending the data to the M1, M2, ...Mn area blocks respectively include:

[0019] Select different areas according to the image size output by the high-speed camera. The camera image size can be detected by the synchronization signal to obtain the image width and height parameters;

[0020] Mapping addressing is performed according to the screen width and height parameters to obtain the corresponding cache area size. The addressing calculation adopts width×height×pixel width and 4-byte alignment.

[0021] Furthermore, the write enable and address are judged. When the write enable is detected to be valid and the accumulated address count value is equal to the set first count threshold X, the read enable of the cache area is generated. At the same time, the read enable is output to the M1, M2...Mn area blocks respectively, and data is read from all the cache area blocks simultaneously. If only one area block is used, the others are used as reserved area blocks. In the step, the first count threshold X needs to be reasonably selected based on the number of data channels output by the camera, the resolution of the image, and the number of channel inputs. The number of data channels is the tap mode of the camera.

[0022] Furthermore, the write enable and address are judged. When the write enable is detected to be valid and the accumulated address count value is equal to the set first count threshold X, the read enable of the cache area is generated. At the same time, the read enable is output to the M1, M2...Mn area blocks respectively, and data is read from all the cache area blocks synchronously. If only one area block is used, the others are used as reserved area blocks. In the step, when the high-speed camera output mode is N tap mode, the count threshold of the first input data channel A1 is L1, and L1 is calculated as follows:

[0023] L1=(first detection screen width W1) / N1

[0024] Wherein, L1 is the counting threshold of the first input data channel A1, W1 is the first detection screen width, and N1 is the tap mode of the camera of the first input data channel;

[0025] By analogy, the counting threshold of the nth data channel An is:

[0026] Ln=(nth detection screen width Wn) / Nn

[0027] Wherein, Ln is the counting threshold of the nth input data channel An, W1 is the width of the nth detection screen, and Nn is the tap mode of the camera of the nth input data channel.

[0028] Furthermore, the write enable and address are judged. When the write enable is detected to be valid and the accumulated address count value is equal to the set first count threshold X, the read enable of the cache area is generated. At the same time, the read enable is output to the M1, M2...Mn area blocks respectively, and data is read from all the cache area blocks synchronously. If only one area block is used, the others are used as reserved area blocks.

[0029] When the camera outputs the same tap mode and image resolution, the first counting threshold X = max(L1, L2…Ln). That is, the maximum channel threshold is used as the unified threshold for the entire synchronous read and write operation. At the same time, the first counting threshold X must be less than or equal to min(M1, M2…Mn-1), that is, the minimum depth value of all area blocks.

[0030] When the tap mode and image resolution of the camera output are different, the threshold of the data channel contained in each camera remains consistent, and the threshold of different cameras needs to be configured according to the camera parameters.

[0031] Another aspect of the present invention relates to a phase synchronization processing device for a CameraLink high-speed camera signal, which is used to implement the above-mentioned phase synchronization processing method for a CameraLink high-speed camera signal. The phase synchronization processing device for a CameraLink high-speed camera signal comprises:

[0032] Data channel A1 is responsible for synchronously correcting the data output by the first data port of the cameralink high-speed camera;

[0033] The synchronization signal detection module is used to detect the line synchronization and frame synchronization signals output by each CameraLink high-speed camera, and obtain the width, height and frame rate information of the image output by the current camera;

[0034] The clock signal detection module is used to detect the clock signal output by each CameraLink high-speed camera to obtain the clock frequency and accuracy information of the current camera output image;

[0035] Phase synchronization processing module, used for synchronous control and processing of camera data;

[0036] The data channel buffer area is used to buffer the camera image data during the processing of the phase synchronization processing module;

[0037] The data synchronization and sorting module is used to obtain camera data after being processed by the phase synchronization processing module. It needs to sort and control the data format according to the CameraLink protocol. According to the different configurations of the input camera, different bit sequence output modes are adapted through lookup table mapping to achieve different camera output modes.

[0038] The beneficial effects achieved by the present invention are:

[0039] The present invention provides a phase synchronization processing method and device for cameralink high-speed camera signals. The method comprises the following steps: parsing cameralink high-speed camera frame data, detecting the line frequency, field frequency and resolution size according to the synchronization signal output by the camera, and frequency detecting the input clock frequency; performing logical phase AND processing on the line signal and frame signal of the first input data channel A1, generating a write enable for the corresponding channel, and performing address counting when the write enable is detected to be valid. According to the counting result, the current valid data is temporarily suspended to the corresponding area; performing corresponding operations on the input data channels A1, A2...An, and temporarily suspending the data to the M1, M2...Mn area blocks respectively; judging the write enable and the address. When the write enable is detected to be valid, the cumulative address count value is equal to the set first counting threshold value X. Generate a read enable for the cache area, and simultaneously output the read enable to the M1, M2, ..., Mn area blocks, respectively, and synchronously read data from all cache area blocks. If only one area block is used, the others are reserved area blocks; synchronously read the area blocks and count the number of read data. When it is detected that the number of read data reaches a second counting threshold T, which is the counted number of a row of data output by the high-speed camera, the read enable is reset to zero, reading is stopped, and the data number counter is reset to zero; the synchronized data obtained from the cache area is synchronously sorted in pixel format according to the number of channels of each camera, and sorted and outputted for each port according to the CameraLink protocol requirements. Different bit order output modes are adapted through a lookup table mapping method according to different input camera configurations. The present invention provides a phase synchronization processing method and device for CameraLink high-speed camera signals, which can adaptively resolve phase differences between different channels and improve signal phase synchronization. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 Schematic diagram of the process of phase synchronization processing method of cameralink high-speed camera signal of the present invention;

[0041] Figure 2 This is a functional block diagram of the phase synchronization processing device for cameralink high-speed camera signals of the present invention. DETAILED DESCRIPTION

[0042] In order to better understand the above technical solution, the above technical solution will be described in detail below with reference to the accompanying drawings and specific implementation methods.

[0043] like Figure 1 As shown, the first embodiment of the present invention provides a phase synchronization processing method for cameralink high-speed camera signals, comprising the following steps:

[0044] Step S100: parse the cameralink high-speed camera frame data, detect the line frequency, field frequency and resolution size according to the synchronization signal output by the camera, and perform frequency detection on the input clock frequency.

[0045] The cameralink high-speed camera frame data is parsed using a three-channel parallel processing method. The synchronization signal output by the camera is then passed through the synchronization signal detection module to detect the line frequency, field frequency, and resolution. The clock signal detection module is also used to detect the input clock frequency.

[0046] Step S200: Perform logical AND processing on the row signal and frame signal of the first input data channel A1 to generate a write enable for the corresponding channel. At the same time, perform address counting when the write enable is detected to be valid. According to the counting result, temporarily store the current valid data in the corresponding area.

[0047] Based on the logical AND processing of the row signal and frame signal of the first input data channel A1, the write enable of the corresponding first channel data cache area module M1 is generated. At the same time, the address is counted when the write enable is valid. According to the counting result, the current valid data is temporarily suspended to the corresponding area. The valid data includes the synchronization signal and pixel data. When the write enable is invalid, the counting result is cleared synchronously.

[0048] Step S300: Perform corresponding operations on input data channels A1, A2...An, and temporarily suspend data to M1, M2...Mn area blocks, respectively, where A1 is the first input data channel, A2 is the second input data channel, and An is the nth input data channel; M1, M2...Mn are independent cache area blocks; M1 is the first independent cache area block, M2 is the second independent cache area block, and Mn is the nth independent cache area block.

[0049] Similarly, based on the input data channels A1, A2, …An, corresponding operations are performed to temporarily buffer the data in the M1, M2, …Mn blocks, respectively. M1, M2, …Mn are independent cache blocks, and the cache size can be dynamically configured based on actual usage. First, different areas are selected based on the image size output by the high-speed camera. The camera image size can be obtained by detecting the width and height parameters of the image using the synchronization signal in step 1. Second, the corresponding cache area size is mapped and addressed based on the image width and height parameters. The addressing calculation uses width x height x pixel width, with 4-byte alignment.

[0050] Step S400: Determine the write enable and address. When the write enable is detected to be valid and the accumulated address count value is equal to a set first count threshold X, a read enable is generated for the cache area. Simultaneously, the read enable is output to the M1, M2, ..., Mn area blocks, and data is read from all cache area blocks simultaneously. If only one area block is used, the others are reserved. The first count threshold X is the threshold for the cache area address count.

[0051] The write enable and address are judged. When the write enable is detected to be valid, the read enable of the cache area is generated when the accumulated address count value is equal to the set first count threshold X. The threshold X is the threshold of the cache area address count. It needs to be reasonably selected based on the number of data channels output by the camera, that is, the camera's tap mode; the resolution of the image and the number of channel inputs.

[0052] At the same time, read enables are output to the M1, M2...Mn area blocks respectively, and data is read from all cache area blocks synchronously. If only one area block is used, the others are used as reserved area blocks.

[0053] Step S500: Synchronously read the regional blocks and count the number of data read. When it is detected that the number of data read reaches a second counting threshold T, the read enable is reset to zero, the reading is stopped, and the data number counter is reset to zero. The second counting threshold T is the number of counts of a row of data output by the high-speed camera.

[0054] The buffer block is read synchronously and the number of read data is counted separately. When the number of read data reaches the second counting threshold T (the second counting threshold T is the number of counts of a row of data output by the high-speed camera), the read enable is reset to zero, reading is stopped, and the data count counter is reset to zero. The data read operation of the buffer block is restarted when the next row valid read enable is valid. To ensure phase synchronization, the clock for synchronous reading of the buffer block is the same, and the clock can be selected based on the clock accuracy of the input channel. To ensure processing compatibility, the clock of input channel A0 is selected as the first option by default.

[0055] Step S600: Sort the pixel format of the synchronized data obtained from the cache area according to the number of channels of each camera, and output the sorted data to each port according to the CameraLink protocol requirements. Based on the different configurations of the input cameras, different bit order output modes are adapted through lookup table mapping.

[0056] The synchronized data obtained from the cache area is sorted in pixel format according to the number of channels of each camera, and the output of the A / B / C / D / E / F / G / H / I / J ports is sorted according to the CameraLink protocol requirements. Depending on the configuration of the input camera, different bit order output modes are adapted through lookup table mapping.

[0057] Further, see Figure 1 In the phase synchronization processing method for cameralink high-speed camera signals proposed in this embodiment, in step S400, when the high-speed camera output mode is N tap mode, the counting threshold of the first input data channel A1 is L1, and L1 is calculated as follows:

[0058] L1=(first detection screen width W1) / N1 (1)

[0059] In formula (1), L1 is the counting threshold of the first input data channel A1, W1 is the first detection screen width, and N1 is the tap mode of the camera of the first input data channel.

[0060] By analogy, the counting threshold of the nth data channel An is:

[0061] Ln=(nth detection screen width Wn) / Nn (2)

[0062] In formula (2), Ln is the counting threshold of the nth input data channel An, W1 is the width of the nth detection screen, and Nn is the tap mode of the camera of the nth input data channel.

[0063] When the camera output tap mode and image resolution are the same, the first counting threshold X = max(L1, L2…Ln). This means the maximum channel threshold is used as the unified threshold for all synchronous read and write operations. Furthermore, the first counting threshold X must be less than or equal to min(M1, M2…Mn-1), which is the minimum depth value for all blocks. L1 is the counting threshold for the first input data channel A1, L2 is the counting threshold for the second input data channel A1, M1 is the first independent cache block, M2 is the second independent cache block, and Mn is the nth independent cache block.

[0064] When the tap mode and image resolution of the camera output are different, the threshold of the data channel contained in each camera remains consistent, and the threshold of different cameras needs to be configured according to the camera parameters.

[0065] See also Figure 2The present invention also provides a phase synchronization processing device for cameralink high-speed camera signals, which is used to implement the above-mentioned phase synchronization processing method for cameralink high-speed camera signals. The phase synchronization processing device for cameralink high-speed camera signals includes a data channel A1, a synchronization signal detection module, a clock signal detection module, a phase synchronization processing module, a data channel buffer area and a data synchronization sorting module. Among them, the data channel A1 is responsible for performing synchronization correction on the first data port data output by the cameralink high-speed camera; the synchronization signal detection module is used to detect the line synchronization and frame synchronization signals output by each cameralink high-speed camera, and detect the current camera. The output image width, height and frame rate information; the clock signal detection module is used to detect the clock signal output by each CameraLink high-speed camera to obtain the clock frequency and accuracy information of the current camera output image; the phase synchronization processing module is used to synchronize and control the camera data; the data channel cache area is used to cache the camera image data processed by the phase synchronization processing module; the data synchronization sorting module is used to obtain the camera data after processing by the phase synchronization processing module. It is necessary to sort and control the data format according to the CameraLink protocol. According to the different configurations of the input camera, different bit sequence output modes are adapted through lookup table mapping to achieve different camera output modes.

[0066] The phase synchronization processing module is the synchronization control and processing module for camera data described in step S100 , step S200 , step S300 , step S400 , and step S500 .

[0067] Compared with the prior art, the phase synchronization processing method and device for cameralink high-speed camera signals provided in this embodiment parse the cameralink high-speed camera frame data, detect the line frequency, field frequency and resolution size based on the synchronization signal output by the camera, and perform frequency detection on the input clock frequency; perform logical phase AND processing on the line signal and frame signal of the first input data channel A1 to generate a write enable for the corresponding channel, and perform address counting when the write enable is detected to be valid. Based on the counting result, the current valid data is temporarily suspended to the corresponding area; perform corresponding operations on the input data channels A1, A2...An, and temporarily suspend the data to the M1, M2...Mn area blocks respectively; judge the write enable and address, and when the write enable is detected to be valid, the accumulated address count value is equal to the set first count value. When the threshold value X is reached, a read enable of the cache area is generated. At the same time, the read enable is output to the M1, M2...Mn area blocks respectively, and data is read from all the cache area blocks synchronously. If only one area block is used, the others are reserved area blocks; the area blocks are read synchronously and the number of read data is counted separately. When it is detected that the number of read data reaches the second counting threshold T, which is the count number of a row of data output by the high-speed camera, the read enable is reset to zero, the reading is stopped, and the data number counter is reset to zero; the synchronized data obtained from the cache area is synchronously sorted in pixel format according to the number of channels of each camera, and the sorting and output of each port are performed separately according to the requirements of the CameraLink protocol. According to the different configurations of the input cameras, different bit order output modes are adapted through a lookup table mapping method. The phase synchronization processing method and device for CameraLink high-speed camera signals provided in this embodiment can adaptively solve the phase difference between different channels and improve signal phase synchronization.

[0068] Although preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they are aware of the basic inventive concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the invention. Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the invention. Thus, the present invention is intended to include such changes and modifications as fall within the scope of the claims and their equivalents.

Claims

1. A phase synchronization processing method for cameralink high-speed camera signals, characterized in that: The following steps are involved: Parse the frame data of the CameraLink high-speed camera, detect the line frequency, field frequency and resolution size based on the synchronization signal output by the camera, and perform frequency detection on the input clock frequency; Performing a logical AND process on the row signal and the frame signal of the first input data channel A1 to generate a write enable for the corresponding channel. At the same time, performing address counting when the write enable is detected to be valid, and temporarily suspending the current valid data to the corresponding area according to the counting result; According to the corresponding operations on the input data channels A1, A2...An, the data is temporarily suspended in the M1, M2...Mn area blocks respectively, where A1 is the first input data channel, A2 is the second input data channel, and An is the nth input data channel; M1, M2...Mn are independent cache area blocks; M1 is the first independent cache area block, M2 is the second independent cache area block, and Mn is the nth independent cache area block; The write enable and address are judged. When the write enable is detected to be valid and the accumulated address count value is equal to the set first count threshold X, a read enable of the cache area is generated. At the same time, the read enable is output to the M1, M2...Mn area blocks respectively, and data is read from all the cache area blocks simultaneously. If only one area block is used, the others are reserved as area blocks. The first count threshold X is the threshold of the cache area address count. Synchronously reading the block and counting the number of data read. When it is detected that the number of data read reaches a second counting threshold T, the read enable is reset to zero, the reading is stopped, and the data number counter is reset to zero. The second counting threshold T is the number of counts of a row of data output by the high-speed camera. The synchronized data obtained from the cache area is sorted in pixel format according to the number of channels of each camera, and the sorted output of each port is performed according to the requirements of the CameraLink protocol. Depending on the configuration of the input camera, different bit order output modes are adapted through lookup table mapping.

2. The method for phase synchronization processing of cameralink high-speed camera signals according to claim 1, wherein: In the steps of parsing the CameraLink high-speed camera frame data, detecting the line frequency, field frequency and resolution size according to the synchronization signal output by the camera, and detecting the input clock frequency, a three-channel parallel processing method is used to parse the CameraLink high-speed camera frame data.

3. The method for phase synchronization processing of cameralink high-speed camera signals according to claim 2, wherein: In the step of parsing the frame data of the CameraLink high-speed camera, detecting the line frequency, field frequency and resolution size according to the synchronization signal output by the camera, and detecting the input clock frequency, the line frequency, field frequency and resolution size are detected according to the synchronization signal output by the camera through the synchronization signal detection module.

4. The method for phase synchronization processing of cameralink high-speed camera signals according to claim 3, wherein: In the steps of parsing the cameralink high-speed camera frame data, detecting the line frequency, field frequency and resolution size according to the synchronization signal output by the camera, and detecting the input clock frequency, a clock signal detection module is used to detect the input clock frequency.

5. The method for phase synchronization processing of cameralink high-speed camera signals according to claim 1, wherein: The row signal and frame signal of the first input data channel A1 are logically ANDed to generate a write enable for the corresponding channel, and address counting is performed when the write enable is detected to be valid. According to the counting result, the current valid data is temporarily suspended to the corresponding area. The valid data includes a synchronization signal and pixel data. When the write enable is invalid, the counting result is synchronously cleared.

6. The method for phase synchronization processing of cameralink high-speed camera signals according to claim 1, wherein: The step of performing corresponding operations on the input data channels A1, A2...An and temporarily suspending the data to the M1, M2...Mn area blocks respectively includes: Select different areas according to the image size output by the high-speed camera. The camera image size can be detected by the synchronization signal to obtain the image width and height parameters; Mapping addressing is performed according to the picture width and height parameters to obtain the corresponding cache area size. The addressing calculation adopts width×height×pixel width and 4-byte alignment.

7. The method for phase synchronization processing of cameralink high-speed camera signals according to claim 1, wherein: The write enable and address are judged. When the write enable is detected to be valid, the cache area read enable is generated when the accumulated address count value is equal to the set first count threshold X. At the same time, the read enable is output to the M1, M2...Mn area blocks respectively, and data is read from all cache area blocks simultaneously. If only one area block is used, the others are used as reserved area blocks. In the step, the first count threshold X needs to be reasonably selected based on the number of data channels output by the camera, the resolution of the image, and the number of channel inputs. The number of data channels is the tap mode of the camera.

8. The method for phase synchronization processing of cameralink high-speed camera signals according to claim 7, wherein: The write enable and address are judged. When the write enable is detected to be valid, the read enable of the cache area is generated when the accumulated address count value is equal to the set first count threshold X. At the same time, the read enable is output to the M1, M2...Mn area blocks respectively, and data is read from all cache area blocks simultaneously. If only one area block is used, the others are used as reserved area blocks. In the step, when the high-speed camera output mode is N tap mode, the count threshold of the first input data channel A1 is L1, and L1 is calculated as follows: L1=(first detection screen width W1) / N1 Wherein, L1 is the counting threshold of the first input data channel A1, W1 is the first detection screen width, and N1 is the tap mode of the camera of the first input data channel; By analogy, the counting threshold of the nth data channel An is: Ln=(nth detection screen width Wn) / Nn Wherein, Ln is the counting threshold of the nth input data channel An, W1 is the width of the nth detection screen, and Nn is the tap mode of the camera of the nth input data channel.

9. The method for phase synchronization processing of cameralink high-speed camera signals according to claim 8, wherein: The write enable and address are judged. When the write enable is detected to be valid, the address count accumulation value is equal to the set first count threshold X, and the read enable of the cache area is generated. At the same time, the read enable is output to the M1, M2...Mn area blocks respectively, and data is read from all the cache area blocks synchronously. If only one area block is used, the others are used as reserved area blocks. When the camera outputs the same tap mode and image resolution, the first counting threshold X = max(L1, L2…Ln). That is, the maximum channel threshold is used as the unified threshold for the entire synchronous read and write operation. At the same time, the first counting threshold X must be less than or equal to min(M1, M2…Mn-1), that is, the minimum depth value of all area blocks. When the tap mode and image resolution of the camera output are different, the threshold of the data channel contained in each camera remains consistent, and the threshold of different cameras needs to be configured according to the camera parameters.

10. A phase synchronization processing device for cameralink high-speed camera signals, used to implement the phase synchronization processing method for cameralink high-speed camera signals according to any one of claims 1 to 9, characterized in that: The phase synchronization processing device of the cameralink high-speed camera signal includes: Data channel A1 is responsible for synchronously correcting the data output by the first data port of the cameralink high-speed camera; The synchronization signal detection module is used to detect the line synchronization and frame synchronization signals output by each CameraLink high-speed camera, and obtain the width, height and frame rate information of the image output by the current camera; The clock signal detection module is used to detect the clock signal output by each CameraLink high-speed camera to obtain the clock frequency and accuracy information of the current camera output image; Phase synchronization processing module, used for synchronous control and processing of camera data; The data channel buffer area is used to buffer the camera image data during the processing of the phase synchronization processing module; The data synchronization and sorting module is used to obtain camera data after being processed by the phase synchronization processing module. It needs to sort and control the data format according to the CameraLink protocol. According to the different configurations of the input camera, different bit sequence output modes are adapted through lookup table mapping to achieve different camera output modes.

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