A pre-regulator circuit based on a bandgap reference core

Abstract

The application relates to a pre-stabilization circuit based on a band gap reference core, which comprises a driving tube, a high-gain feedback, an impulse protection circuit, a multi-path starting and biasing unit, a band gap reference core and a voltage dividing feedback resistor. When the circuit is powered on, the output DC voltage will completely depend on the band gap reference core and the voltage dividing feedback resistor and will not be related to the input voltage. When the output voltage changes, the error voltage will be transmitted to the band gap reference core through the voltage dividing feedback resistor, the state of the high-voltage PMOS driving tube is adjusted through the high-gain feedback path, and stable output is realized. The application solves the problems of low output voltage precision, weak load driving capacity and low circuit reliability existing in the prior art, and can be used as a high-voltage pre-stabilization circuit of a general high-voltage power supply integrated circuit including an LDO and a DC-DC.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, in particular to a pre-regulator circuit based on a bandgap reference core. BACKGROUND

[0002] The pre-regulator circuit is usually applied in general high-voltage power supply integrated circuits including LDO and DC-DC. In addition to the requirement of converting the high-voltage input from an external power supply into a stable and reliable low-voltage output, the circuit should also have a certain current load driving capability. With the higher requirement for the output accuracy of the subsequent LDO and DC-DC circuit, the requirement for the output accuracy of the pre-regulator circuit is also increasing. The traditional pre-regulator circuit usually uses multiple diodes in series or a combination of reverse-connected Zener diodes and MOS tubes to determine the output DC voltage. The former will be directly affected by the change of the on-voltage of the device with process angle, temperature and input voltage conditions, and the latter will be directly affected by the change of the breakdown threshold voltage of the Zener diode and the on-threshold voltage of the MOS tube with process angle, temperature and input voltage conditions, so the voltage conversion accuracy of both is low.

[0003] Xi'an University of Electronic Science and Technology in its applied patent document "High-voltage voltage regulator using PNP-type Brokaw reference core" (application number 202310595301.2, application publication number CN 116610185 A) proposes a high-voltage voltage regulator using a PNP-type Brokaw reference core. The high-voltage voltage regulator described in the circuit uses a PNP-type Brokaw reference core and the voltage division ratio of the feedback resistor network to determine the output DC voltage, and uses a high-voltage NMOS tube to realize high-low voltage isolation and circuit state adjustment, finally realizes a stable voltage output with an accuracy comparable to that of the PNP-type Brokaw reference core. The deficiency of the circuit is that: although the high-voltage NMOS tube in the high-voltage circuit described by it has high current driving capability, it is connected to the circuit negative feedback loop in common source configuration, so it cannot exert its intrinsic gain advantage. When the input voltage VIN of the voltage regulator described in the circuit has ripple or disturbance, the ripple generated at the output end VOUT is also obvious.

[0004] University of Electronic Science and Technology in its applied patent document "High power supply rejection ratio bandgap reference circuit with pre-regulator structure" (application number 201910327106.5, application publication number CN 109947169 A) combines the pre-regulator structure with the bandgap reference to realize high-precision reference voltage output and good input ripple isolation. The deficiency of the circuit is that the bandgap reference circuit described by it does not have current load driving capability, and the pre-regulator structure described by it needs a front-stage circuit to provide current bias to work normally, which does not meet the demand of general pre-regulator circuit application scenarios. SUMMARY

[0005] To solve the technical problems of the prior art, the application provides a pre-stabilized voltage circuit based on a band gap reference core, which is used to solve the problems of poor output voltage precision, weak ripple suppression capability, weak current driving capability and low circuit reliability in the prior art.

[0006] To solve the above technical problems, the application provides the following technical solutions.

[0007] The pre-stabilized voltage circuit based on the band gap reference core comprises a driving tube, a high-gain feedback, an impulse protection circuit, a multi-path starting and biasing unit, a band gap reference core, a voltage dividing feedback resistor, an input end VIN, an output end VOUT and a ground end GND. The input end VIN is connected with the impulse protection circuit, the multi-path starting and biasing unit, the high-gain feedback and the driving tube respectively. The output end VOUT of the pre-stabilized voltage circuit is connected with the driving tube, the high-gain feedback, the voltage dividing feedback resistor, the multi-path starting and biasing unit and the band gap reference core respectively. The multi-path starting and biasing unit is connected with the impulse protection circuit, the high-gain driving and the band gap reference core respectively. The band gap reference core is connected with the voltage dividing feedback resistor and the high-gain feedback. The high-gain feedback is connected with the driving tube. The ground end GND of the pre-stabilized voltage circuit is connected with the impulse protection circuit, the multi-path starting and biasing unit, the band gap reference core and the voltage dividing feedback resistor respectively.

[0008] Further, the driving tube is a high-voltage PMOS tube HP1, the source of the high-voltage PMOS tube HP1 is connected with the input end VIN of the pre-stabilized voltage circuit, the gate of the high-voltage PMOS tube HP1 is connected with the high-gain feedback, and the drain of the high-voltage PMOS tube HP1 is connected with the output end VOUT of the pre-stabilized voltage circuit, the voltage dividing feedback resistor, the band gap reference core and the multi-path starting and biasing unit respectively.

[0009] Further, the high-gain feedback comprises a fifth PMOS tube PM5, a first NMOS tube NM1, a second high-voltage NMOS tube HN2, a third resistor R3, a fourth resistor R4, a fifth resistor R5 and a first capacitor C1. The input end VIN is connected with the gate of the high-voltage PMOS tube HP1 and the drain of the second high-voltage NMOS tube HN2 through the third resistor R3. The source of the second high-voltage NMOS tube HN2 is connected with the drain of the first NMOS tube NM1. The source of the first NMOS tube NM1 is connected with the drain of the fifth PMOS tube PM5, and is connected with the fourth resistor R4 and the fifth resistor R5 in sequence to the ground end GND. The source of the fifth PMOS tube PM5 is connected with the drain of the high-voltage PMOS tube HP1, and the gate of the fifth PMOS tube is connected with the band gap reference core. The first capacitor C1 is connected with the gate and the drain of the fifth PMOS tube PM5 respectively.

[0010] Further, the multi-path starting and biasing unit comprises a first resistor R1, a second resistor R2, a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, a fifth diode D5, a first high-voltage NMOS tube HN1, a third PMOS tube PM3, a fourth PMOS tube PM4, and a third NPN transistor Q3. The input terminal VIN is connected to the first diode D1, the second diode D2, and the third diode D3 in sequence in a forward direction, and the cathode of the third diode D3 is connected to the ground terminal GND. The drain of the first high-voltage NMOS tube HN1 is connected to the input terminal VIN through the second resistor R2, and the gate of the first high-voltage NMOS tube HN1 is connected to the anode of the first diode D1. The source of the first high-voltage NMOS tube HN1 is connected to the fourth diode D4 and the fifth diode D5 in sequence in a forward direction, and the cathode of the fifth diode D5 is connected to the ground terminal GND. The source of the third PMOS tube PM3 is connected to the output terminal VOUT, and the drain of the third PMOS tube PM3 is connected to the gate of the fourth PMOS tube PM4 and the collector of the third NPN transistor Q3. The source of the fourth PMOS tube PM4 is connected to the output terminal VOUT, and the drain of the fourth PMOS tube PM4 is connected to a high-gain feedback. The emitter of the third NPN transistor Q3 is connected to the ground terminal GND.

[0011] Further, the bandgap reference core comprises a first NPN transistor Q1, a second NPN transistor Q2, a first PMOS tube PM1, a second PMOS tube PM2, a sixth resistor R6, and a seventh resistor R7. The output terminal VOUT is connected to the source of the first PMOS tube PM1 and the source of the second PMOS tube PM2. The drain of the first PMOS tube PM1 is connected to the collector of the first NPN transistor Q1. The gate of the second PMOS tube PM2 is connected to the gate of the first PMOS tube PM1 and the drain of the second PMOS tube PM2. The drain of the second PMOS tube PM2 is connected to the collector of the second NPN transistor Q2. The base of the first NPN transistor Q1 is connected to the base of the second NPN transistor Q2. The emitter of the first NPN transistor Q1 is connected to the ground terminal GND through the seventh resistor R7. The emitter of the second NPN transistor Q2 is connected to the sixth resistor R6 and the seventh resistor R7 in sequence to the ground terminal GND.

[0012] Further, the impulse protection circuit comprises a first Zener diode DZ1. The cathode of the first Zener diode DZ1 is connected to the input terminal VIN through the first resistor R1, and the anode of the first Zener diode DZ1 is connected to the ground terminal GND.

[0013] Further, the anode of the first diode D1 is connected with the gate of the second high-voltage NMOS tube HN2, the anode of the fourth diode D4 is connected with the gate of the first NMOS tube NM1, the base of the third NPN triode Q3 is connected with the third resistor R3 and the fourth resistor R4, and the gate of the third PMOS tube PM3 is connected with the gate of the second PMOS tube PM2.

[0014] Compared with the prior art, the present application has the following advantages:

[0015] Firstly, since the present application uses the bandgap reference core and the voltage division ratio of the voltage division feedback resistor to determine the output DC voltage, the output DC voltage of the circuit can have the precision comparable to the bandgap reference core, and the problem of insufficient voltage output precision in the conventional scheme of determining the output DC voltage by using multiple diodes in series or by using the reverse-connection Zener diode and MOS tube combination can be overcome.

[0016] Secondly, since the present application designs the common-source and common-gate amplification branch to guide the high-gain negative feedback to drive the high-voltage PMOS gate, and the high-voltage PMOS is connected to the negative feedback loop in the common-source configuration, the high intrinsic gain characteristic of the high-voltage PMOS is fully utilized, and higher negative feedback loop gain is achieved. Thus, the power supply rejection capability and the load current driving capability of the pre-regulator circuit can be significantly improved.

[0017] Thirdly, since the present application designs the multi-path starting and biasing unit, when the power supply is powered on, the starting current is actively provided for the high-gain feedback, the driving tube and the bandgap reference core, respectively, and after the starting is completed, the corresponding devices in the circuit obtain the required DC bias from the starting path and enter the set device working state. Thus, the reliability of the circuit starting and static working point biasing is improved.

[0018] Fourthly, since the present application connects the resistor series reverse-connection Zener diode branch to the ground at the power supply input end, the corresponding devices can be protected from being broken down by the inrush voltage occurring on the power supply, and the reliability of the circuit working under high voltage is improved. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 The circuit block diagram of the present application;

[0020] Figure 2 The circuit principle diagram of the embodiment of the present application;

[0021] Figure 3 The DC temperature characteristic simulation result diagram of the present application;

[0022] Figure 4 The linear regulation rate characteristic simulation result diagram of the present application;

[0023] Figure 5 The power supply ripple rejection characteristic simulation result diagram of the present application. DETAILED DESCRIPTION

[0024] The following is a specific embodiment of the present application and further describes the technical solutions of the present application in conjunction with the drawings, but the present application is not limited to these embodiments.

[0025] Reference Figure 1 The overall structure of the circuit of the present application is further described in detail.

[0026] The circuit of the present application includes a driving tube, a high-gain feedback, an impulse protection circuit, a multi-path starting and biasing unit, a bandgap reference core, and a voltage dividing feedback resistor.

[0027] The input end VIN of the pre-stabilization circuit is connected to the impulse protection circuit, the multi-path starting and biasing unit, the high-gain feedback, and the driving tube, respectively; the output end VOUT of the pre-stabilization circuit is connected to the driving tube, the high-gain feedback, the voltage dividing feedback resistor, the multi-path starting and biasing unit, and the bandgap reference core, respectively; the multi-path starting and biasing unit is connected to the impulse protection circuit, the high-gain driving, and the bandgap reference core, respectively; the bandgap reference core is connected to the voltage dividing feedback resistor and the high-gain feedback; the high-gain feedback is connected to the driving tube; and the ground end GND of the pre-stabilization circuit is connected to the impulse protection circuit, the multi-path starting and biasing unit, the bandgap reference core, and the voltage dividing feedback resistor, respectively.

[0028] The driving tube uses a high-voltage PMOS tube HP1, the source of which is connected to the input end VIN of the pre-stabilization circuit, the gate of which is connected to the high-gain feedback, and the drain of which is connected to the output end VOUT of the pre-stabilization circuit, the voltage dividing feedback resistor, the bandgap reference core, and the multi-path starting and biasing unit, respectively.

[0029] The maximum voltage resistance value of the source and drain of the high-voltage PMOS tube HP1 used by the driving tube is set to 60V, the maximum voltage resistance value of the gate and source is set to 5.5V, the width-length ratio is set to 40um / 3um, the fork index is set to 2, and the number of parallel connections is 20; in the case of requiring stronger load current driving capability, the number of parallel connections can be increased.

[0030] The feedback resistor network is composed of series voltage dividing resistors, the sum of the resistance values of which is in the order of megaohms, which can ensure the normal output load capacity while reducing the overall power consumption of the circuit.

[0031] The current gain of the NPN-type triode in the bandgap reference core is 30, which is mainly limited by the process platform device library used in the embodiment of the present application. Therefore, the gain in the feedback loop is mainly contributed by the high-gain feedback.

[0032] Reference Figure 2 The principle of the circuit of the embodiment of the present application is further described in detail.

[0033] The driving tube adopts a high-voltage PMOS tube HP1, the source of the high-voltage PMOS tube HP1 is connected with the input end VIN of the pre-stabilized voltage circuit, the gate is connected with the high-gain feedback, and the drain is respectively connected with the output end VOUT of the pre-stabilized voltage circuit, the voltage dividing feedback resistor, the bandgap reference core and the multi-path starting and biasing unit.

[0034] The high-gain feedback is composed of a fifth PMOS tube PM5, a first NMOS tube NM1, a second high-voltage NMOS tube HN2, a third resistor R3, a fourth resistor R4, a fifth resistor R5 and a first capacitor C1; the input end VIN of the pre-stabilized voltage circuit is connected with the gate of the high-voltage PMOS tube HP1 and the drain of the second high-voltage NMOS tube HN2 through the third resistor R3; the source of the second high-voltage NMOS tube HN2 is connected with the drain of the first NMOS tube NM1; the source of the first NMOS tube NM1 is connected with the drain of the fifth PMOS tube PM5, and is connected with the fourth resistor R4 and the fifth resistor R5 in series to the ground GND; the source of the fifth PMOS tube PM5 is connected with the drain of the high-voltage PMOS tube HP1, and the gate of the fifth PMOS tube is connected with the bandgap reference core; the first capacitor is connected with the gate and the drain of the fifth PMOS tube.

[0035] The multi-path starting and biasing unit is composed of a first resistor R1, a second resistor R2, a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, a fifth diode D5, a first high-voltage NMOS tube HN1, a third PMOS tube PM3, a fourth PMOS tube PM4 and a third NPN transistor Q3; the input end VIN of the pre-stabilized voltage circuit is connected with the first diode D1, the second diode D2 and the third diode D3 in series, and the cathode of the third diode D3 is connected with the ground GND; the drain of the first high-voltage NMOS tube HN1 is connected to the input end VIN of the pre-stabilized voltage circuit through the second resistor R2, the gate is connected to the anode of the first diode D1, the source is connected with the fourth diode D4 and the fifth diode D5 in series, and the cathode of the fifth diode D5 is connected with the ground GND; the source of the third PMOS tube is connected with the output end VOUT of the pre-stabilized voltage circuit, and the drain is respectively connected with the gate of the fourth PMOS tube PM4 and the collector of the third NPN transistor Q3; the source of the fourth PMOS tube is connected with the output end VOUT of the pre-stabilized voltage circuit, and the drain is connected with the high-gain feedback; the emitter of the third NPN transistor Q3 is connected with the ground GND.

[0036] The bandgap reference core is composed of a first NPN transistor Q1, a second NPN transistor Q2, a first PMOS PM1, a second PMOS PM2, a sixth resistor R6 and a seventh resistor R7; the pre-stabilized voltage circuit output end VOUT is connected with the first PMOS PM1 source and the second PMOS PM2 source; the first PMOS PM1 drain is connected with the first NPN transistor Q1 collector; the second PMOS PM2 gate is connected with the first PMOS PM1 gate and the second PMOS PM2 drain respectively, and the drain is connected with the second NPN transistor Q2 collector; the first NPN transistor Q1 base is connected with the second NPN transistor Q2 base, and the emitter is connected to the ground through the seventh resistor R7; the fourth NPN transistor Q2 emitter is connected to the ground GND in sequence through the sixth resistor R6 and the seventh resistor R7.

[0037] The impulse protection circuit is composed of a first Zener diode DZ1; the Zener diode DZ1 cathode is connected to the pre-stabilized voltage circuit input end VIN through the multi-path starting and biasing unit first resistor R1, and the anode is connected to the ground GND.

[0038] The first diode D1 anode is connected with the high-gain feedback second high-voltage NMOS HN2 gate, the fourth diode D4 anode is connected with the high-gain feedback first NMOS NM1 gate, the third NPN transistor Q3 base is connected between the high-gain feedback third resistor R3 and the fourth resistor R4, and the third PMOS PM3 gate is connected with the bandgap reference core second PMOS PM2 gate.

[0039] Referring to Figure 2 When the input high voltage is applied between the input end VIN and the ground GND, the power supply high potential is directly transmitted to the first high-voltage PMOS HP1 source, transmitted to the first high-voltage NMOS HN1 gate and the second high-voltage NMOS HN2 gate through the first resistor R1, transmitted to the first high-voltage NMOS HN1 drain through the second resistor R2, and transmitted to the first high-voltage PMOS HP1 gate and the second high-voltage NMOS HN2 drain through the third resistor R3.

[0040] The first high-voltage NMOS HN1 is turned on and applies a pull-up current to the first NMOS NM1 gate, the first NMOS NM1 is turned on and applies a pull-down current to the first high-voltage PMOS HP1 gate, so that the first high-voltage PMOS HP1 is turned on and applies a pull-up current to the output end VOUT.

[0041] The pull-up current guided by the first high-voltage PMOS tube HP1 is applied to the first NPN transistor Q1 and the second NPN transistor Q2 base through the eighth resistor R8. The pull-down current guided by the first NMOS tube flows to the ground GND through the series connection of the fourth resistor R4 and the fifth resistor R5, and a part of the pull-down current is injected into the third NPN transistor Q3 base, so that the third NPN transistor Q3 base potential is raised, the pull-down current is guided to the fourth PMOS tube PM4 gate, and the fourth PMOS tube PM4 guides the pull-up current to the first NPN transistor Q1 collector, so as to start the bandgap reference core.

[0042] The bandgap reference core is composed of the first PMOS tube PM1 and the second PMOS tube PM2 to form a current mirror, and the width-length ratios of the first PMOS tube PM1 and the second PMOS tube PM2 are the same, so as to ensure that the currents flowing through the first NPN transistor Q1 collector and the second NPN transistor Q2 collector are the same. The number of the first NPN transistor Q1 in parallel is 1, and the number of the second NPN transistor Q2 in parallel is 8.

[0043] According to the structure principle of the bandgap reference core, the expression of the voltage across the ninth resistor R9 is:

[0044]

[0045] VBE1 represents the base-emitter voltage of the first NPN transistor Q1, R7 represents the resistance value of the seventh resistor R7, R6 represents the resistance value of the sixth resistor R6, and VBE2 represents the base-emitter voltage of the second NPN transistor Q2. BE1 T VBE1 represents the base-emitter voltage of the first NPN transistor Q1, R7 represents the resistance value of the seventh resistor R7, R6 represents the resistance value of the sixth resistor R6, and VBE2 represents the base-emitter voltage of the second NPN transistor Q2. R9 VBE1 represents the base-emitter voltage of the first NPN transistor Q1, R7 represents the resistance value of the seventh resistor R7, R6 represents the resistance value of the sixth resistor R6, and VBE2 represents the base-emitter voltage of the second NPN transistor Q2.

[0046] According to the voltage division relationship between the eighth resistor R8 and the ninth resistor R9 in the voltage division feedback resistor, the direct current voltage of the output end VOUT is:

[0047]

[0048] VBE1 represents the base-emitter voltage of the first NPN transistor Q1, R7 represents the resistance value of the seventh resistor R7, R6 represents the resistance value of the sixth resistor R6, and VBE2 represents the base-emitter voltage of the second NPN transistor Q2.

[0049] ​The fifth PMOS PM5 and the first NMOS NM1 constitute a folded cascode amplification structure in the high gain feedback, and high gain can be realized.

[0050] With reference to Figure 3 Further beneficial effects of the embodiments of the present application are described in detail.

[0051] In combination with the circuit schematic diagram in Figure 2 , the Linux operating system and the Virtuoso design simulation platform, a simulation test circuit is built by using a 60V BCD process. Under a typical process angle, a 60V high voltage is applied to the input end VIN, and a direct current scan is performed on the output end VOUT voltage in a temperature range of -40℃ to 130℃, to obtain the simulation result shown in Figure 3 . Figure 3 In the simulation result shown in , the horizontal coordinate is temperature, in units of ℃, and the vertical coordinate is the output end VOUT voltage, in units of V. The output end VOUT voltage is kept between 4.742V and 4.747V, and the variation in the simulation temperature range is about 4.85mV, and the temperature coefficient is about 6.02ppm / ℃, so the output end VOUT voltage has very high precision.

[0052] Figure 4 With reference to , further beneficial effects of the embodiments of the present application are described in detail.

[0053] Figure 2 In combination with the circuit schematic diagram in Figure 4 , the Linux operating system and the Virtuoso design simulation platform, a simulation test circuit is built by using a 60V BCD process. Under a typical process angle, a 60V high voltage is applied to the input end VIN, and a direct current scan is performed on the output end VOUT voltage in a temperature range of -40℃ to 130℃, to obtain the simulation result shown in Figure 4 . In the simulation result shown in

[0054] , the horizontal coordinate is the input end VIN voltage, in units of V, and the vertical coordinate is the output end VOUT voltage, in units of V. The output end VOUT voltage is kept around 4.746V, and the variation in the simulation voltage range is 59μV, and the linear adjustment rate is about 12ppm, so the function of high-voltage direct-current voltage stabilization is completed. Figure 5 With reference to

[0055] , further beneficial effects of the embodiments of the present application are described in detail. Figure 2The circuit schematic in the figure is simulated with Linux operating system and Virtuoso design simulation platform, and a simulation test circuit is built with 60V BCD process. Under typical process corner and 27℃ temperature condition, 60V high voltage is applied to the input terminal VIN of the circuit, 1V AC ripple is superimposed, the output terminal VOUT voltage is scanned in the frequency range of 1Hz-100MHz, and the simulation result is shown in the figure Figure 5 . Figure 5 The horizontal coordinate in the figure is the frequency of the AC ripple superimposed on the input terminal VIN, and the unit is Hz; the vertical coordinate is the ripple rejection ratio of the output terminal VOUT, and the unit is dB. The ripple rejection ratio of the output terminal VOUT is greater than 125dB at 1Hz low frequency, greater than 98dB at 1kHz medium-low frequency, greater than 42dB at 100kHz high frequency, the minimum value in the simulation frequency range is 13.9dB, and the circuit has excellent power supply ripple rejection capability as a whole.

[0056] The specific embodiments described herein are merely illustrative of the spirit of the present application. Those skilled in the art of the present application can make various modifications or supplements to the described specific embodiments or replace them with similar ways, without departing from the spirit of the present application or exceeding the scope defined by the appended claims.

Claims

1. A pre-regulator circuit based on a bandgap reference core, characterized in that, The circuit includes a driver transistor, high-gain feedback, impulse protection circuit, multi-path startup and bias unit, bandgap reference core, voltage divider feedback resistor, input terminal VIN, output terminal VOUT, and ground terminal GND. The input terminal VIN is connected to the impulse protection circuit, the multi-path startup and bias unit, the high-gain feedback, and the driver transistor, which is a high-voltage PMOS transistor HP1. The output terminal VOUT is connected to the driver transistor, the high-gain feedback, the voltage divider feedback resistor, the multi-path startup and bias unit, and the bandgap reference core. The multi-path startup and bias unit is connected to the impulse protection circuit, the high-gain driver transistor, and the bandgap reference core. The bandgap reference core is connected to... The voltage divider feedback resistor is connected to the high-gain feedback; the high-gain feedback is connected to the driving transistor; the ground terminal GND is connected to the impulse protection circuit, the multi-path startup and bias unit, the bandgap reference core, and the voltage divider feedback resistor; the high-gain feedback includes a fifth PMOS transistor PM5, a first NMOS transistor NM1, a second high-voltage NMOS transistor HN2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a first capacitor C1; the input terminal VIN is connected to the gate of the high-voltage PMOS transistor HP1 and the drain of the second high-voltage NMOS transistor HN2 through the third resistor R3; the source of the second high-voltage NMOS transistor HN2 is connected to the drain of the first NMOS transistor NM1. The first NMOS transistor NM1 is connected to the drain of the fifth PMOS transistor PM5, and is connected in series with the fourth resistor R4 and the fifth resistor R5 to the ground terminal GND; the source of the fifth PMOS transistor PM5 is connected to the drain of the high-voltage PMOS transistor HP1, and the gate of the fifth PMOS transistor is connected to the bandgap reference core; the first capacitor C1 is connected to the gate and drain of the fifth PMOS transistor PM5 respectively; the multipath startup and bias unit includes a first resistor R1, a second resistor R2, a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, a fifth diode D5, a first high-voltage NMOS transistor HN1, a third... The transistor consists of a PMOS transistor PM3, a fourth PMOS transistor PM4, and a third NPN transistor Q3. The input terminal VIN is connected in forward series with the first diode D1, the second diode D2, and the third diode D3 via a first resistor R1. The cathode of the third diode D3 is connected to the ground terminal GND. The drain of the first high-voltage NMOS transistor HN1 is connected to the input terminal VIN via a second resistor R2. The gate of the first high-voltage NMOS transistor HN1 is connected to the anode of the first diode D1. The source of the first high-voltage NMOS transistor HN1 is connected in forward series with the fourth diode D4 and the fifth diode D5. The cathode of the fifth diode D5 is connected to the ground terminal GND.The source of the third PMOS transistor PM3 is connected to the output terminal VOUT; the drain of the third PMOS transistor PM3 is connected to the gate of the fourth PMOS transistor PM4 and the collector of the third NPN transistor Q3, respectively; the source of the fourth PMOS transistor PM4 is connected to the output terminal VOUT; the drain of the fourth PMOS transistor PM4 is connected to the high-gain feedback; the emitter of the third NPN transistor Q3 is connected to the ground terminal GND.

2. The pre-regulator circuit based on a bandgap reference core according to claim 1, characterized in that, The source of the high-voltage PMOS transistor HP1 is connected to the input terminal VIN, the gate of the high-voltage PMOS transistor HP1 is connected to the high-gain feedback, and the drain of the high-voltage PMOS transistor HP1 is connected to the output terminal VOUT, the voltage divider feedback resistor, the bandgap reference core, and the multipath startup and bias unit.

3. The pre-regulator circuit based on a bandgap reference core according to claim 1, characterized in that, The bandgap reference core includes a first NPN transistor Q1, a second NPN transistor Q2, a first PMOS transistor PM1, a second PMOS transistor PM2, a sixth resistor R6, and a seventh resistor R7. The output terminal VOUT is connected to the source of the first PMOS transistor PM1 and the source of the second PMOS transistor PM2. The drain of the first PMOS transistor PM1 is connected to the collector of the first NPN transistor Q1. The gate of the second PMOS transistor PM2 is connected to the gate of the first PMOS transistor PM1 and the drain of the second PMOS transistor PM2, and the drain of the second PMOS transistor PM2 is connected to the collector of the second NPN transistor Q2. The base of the first NPN transistor Q1 is connected to the base of the second NPN transistor Q2. The emitter of the first NPN transistor Q1 is connected to the ground terminal GND through the seventh resistor R7. The emitter of the second NPN transistor Q2 is connected in series with the sixth resistor R6 and the seventh resistor R7 to the ground terminal GND.

4. The pre-regulator circuit based on a bandgap reference core according to claim 2, characterized in that, The impulse protection circuit includes a first Zener diode DZ1; the cathode of the first Zener diode DZ1 is connected to the input terminal VIN through the first resistor R1, and the anode of the first Zener diode DZ1 is connected to the ground terminal GND.

5. The pre-regulator circuit based on a bandgap reference core according to claim 3, characterized in that, The anode of the first diode D1 is connected to the gate of the second high-voltage NMOS transistor HN2, the anode of the fourth diode D4 is connected to the gate of the first NMOS transistor NM1, the base of the third NPN transistor Q3 is connected to the third resistor R3 and the fourth resistor R4, and the gate of the third PMOS transistor PM3 is connected to the gate of the second PMOS transistor PM2.

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