A multi-channel high-speed dual AD synchronous sampling device and method

Abstract

The present invention discloses a multi-channel high-speed dual AD synchronous sampling device and method, which is applied to data acquisition equipment for new energy vehicle testing. The synchronous sampling device includes a dual AD sampling unit, which includes a first amplifier circuit and a second amplifier circuit for analog input, a first second-order pass filter circuit and a second second-order pass filter circuit, a first high-precision AD sampling circuit and a second high-precision AD sampling circuit, a serial / parallel shift register, and a digital signal processor. The dual AD sampling unit used in this application can fully cover the amplitude of the measured signal, reduce the occurrence of shearing and clipping, avoid the component harmonics above the Nyquist frequency from being aliased into the baseband, resulting in data distortion, ensure signal integrity, and reduce the design difficulty and cost of the anti-aliasing filter.

Description

Technical Field

[0001] The present invention relates to the technical field of signal acquisition and processing, and in particular to a multi-channel high-speed dual AD synchronous sampling device and method. Background Art

[0002] Data acquisition equipment used in new energy vehicle testing typically collects signals such as voltage, current, temperature, pressure, torque, speed, and flow. With the exception of voltage, these other physical quantities are often acquired in analog form. Therefore, an AD converter is required to convert these analog quantities into digital quantities for computation and analysis on a host computer. This collected analog information places high demands on sampling frequency, accuracy, and synchronization.

[0003] With the rapid development of new energy vehicle technology, automakers and testing agencies are placing higher demands on related testing technologies, particularly for high data volumes, high sampling frequencies, and high synchronization. Previous designs have amplified and filtered digital signals, then transmitted to the FPGA circuit using a high-precision AD converter. However, because each board only has one AD converter, high-frequency sampling can lead to low signal acquisition accuracy and synchronization issues. Furthermore, higher-than-expected signal gain can cause signal truncation, compromising measurement integrity and accuracy. Summary of the Invention

[0004] The purpose of the present invention is to address the above problems and provide a multi-channel high-speed dual AD synchronous sampling device and method, which can meet the simultaneous high-speed AD sampling of multiple physical quantity signals in new energy vehicles, and the sampling accuracy of data at high sampling frequency is not affected, thereby reducing aliasing.

[0005] To achieve the purpose of the present invention, a first aspect of an embodiment of the present invention provides a multi-channel high-speed dual AD synchronous sampling device, which is used in data acquisition equipment for new energy vehicle testing. The device includes a dual AD sampling unit, and the dual AD sampling unit includes a first amplifier circuit and a second amplifier circuit for analog input; the signal output ends of the first amplifier circuit and the second amplifier circuit are respectively connected to the signal input ends of the first second-order pass filter circuit and the second second-order pass filter circuit; the signal output ends of the first second-order pass filter circuit and the second second-order pass filter circuit are respectively connected to the signal input ends of the first high-precision AD sampling circuit and the second high-precision AD sampling circuit; the first high-precision AD sampling circuit and the second high-precision AD sampling circuit are both connected to the signal input end of the serial / parallel shift register; the serial / parallel shift register is connected to the signal input end of the digital signal processor via a buffer; there are multiple dual AD sampling units, each corresponding to a channel.

[0006] Corresponding to the first aspect, the second aspect of this embodiment provides a multi-channel high-speed dual AD synchronous sampling method, which is applied to new energy vehicle testing. The method is performed using a multi-channel high-speed dual AD synchronous sampling device as described above, and specifically includes the following: the collected signal is amplified through a first amplifier circuit and a second amplifier circuit to amplify tiny signal fluctuations, and high-frequency noise is filtered out through a first second-order pass filter circuit and a second second-order pass filter circuit; oversampling is performed using a first high-precision AD sampling circuit and a second high-precision AD sampling circuit at a higher analog sampling rate, and the analog quantity is converted into a 1-bit digital quantity and sent to a serial / parallel shift register, and stored in a buffer.

[0007] Compared with the prior art, the present invention has the following beneficial effects:

[0008] (1) The dual AD sampling units used in this application can fully cover the amplitude of the measured signal, reduce the occurrence of shearing and clipping, avoid the harmonics of components above the Nyquist frequency from being aliased into the baseband, causing data distortion, ensure the integrity of the signal, and reduce the difficulty and cost of designing anti-aliasing filters.

[0009] (2) To address the noise problem caused by oversampling, this application suppresses the noise within the Nyquist bandwidth and its 64 times, 128 times, and 256 times through an upstream low-pass filter and a downstream anti-aliasing filter, ensuring that there is almost no attenuation or phase shift within the bandwidth of interest.

[0010] (3) Each channel of the present application obtains the reference clock from the clock synchronization bus and has the same sampling interval, but there is a phase difference between the master and slave cards. The present invention sends the trigger signal of the master card to all slave cards. After the slave cards receive the trigger signal, they simultaneously collect data at the rising edge of the next sampling cycle, thereby improving the phase consistency between channels and playing an important role in multi-channel, high-precision acquisition. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A schematic diagram of the circuit structure of a dual AD sampling unit provided in an embodiment of the present application;

[0012] Figure 2 A schematic diagram of the circuit structure of a multi-channel high-speed dual AD synchronous sampling device provided in an embodiment of the present application;

[0013] In the figure: 1-first amplifier circuit; 2-second amplifier circuit; 3-first second-order low-pass filter circuit; 4-second second-order low-pass filter circuit; 5-first high-precision AD sampling circuit; 6-second high-precision AD sampling circuit; 7-serial / parallel shift register; 8-buffer; 9-digital signal processor; 10-power supply circuit; 11-bus drive circuit; 12-host computer; 13-external clock source; 14-voltage-controlled crystal oscillator; 15-clock synchronization bus; 16-monitoring circuit; 17-first clock divider; 18-second clock divider; 19-third clock divider. DETAILED DESCRIPTION

[0014] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. Example 1

[0015] like Figure 1 As shown, a multi-channel high-speed dual AD synchronous sampling device provided in this embodiment is applied to data acquisition equipment for new energy vehicle testing, which includes a dual AD sampling unit, and the dual AD sampling unit includes a first amplifier circuit 1 and a second amplifier circuit 2 for analog input; the signal output ends of the first amplifier circuit 1 and the second amplifier circuit 2 are respectively connected to the signal input ends of the first second-order pass filter circuit 3 and the second second-order pass filter circuit 4; the signal output ends of the first second-order pass filter circuit 3 and the second second-order pass filter circuit 4 are respectively connected to the signal input ends of the first high-precision AD sampling circuit 5 and the second high-precision AD sampling circuit 6; the first high-precision AD sampling circuit 5 and the second high-precision AD sampling circuit 6 are both connected to the signal input end of the serial / parallel shift register 7; the serial / parallel shift register 7 is connected to the signal input end of the digital signal processor 9 via the buffer 8; there are multiple dual AD sampling units, each corresponding to a channel.

[0016] It should be noted that both the first high-precision AD sampling circuit 5 and the second high-precision AD sampling circuit 6 are integrated with anti-aliasing filters.

[0017] In an embodiment of the present application, signals such as current, pressure, torque, speed, and temperature are collected from new energy vehicles, and the collected signals are processed by an amplification circuit and a low-pass filter circuit, converted into a 1-bit digital quantity through a dual AD conversion circuit, and an anti-aliasing filter is used to suppress the part above the Nyquist frequency. The digital signal processor will resample the data and expand it to 24 bits, thereby achieving higher acquisition and calculation accuracy.

[0018] In addition, in a preferred embodiment, there are multiple dual AD sampling units, each corresponding to a channel. Each channel has two amplifier circuits that cooperate with the dual AD to amplify the signal. The amplifier circuits use differential amplifier circuits to avoid ground loops. The first amplifier circuit 1 and the second amplifier circuit 2 share a common ground line and are isolated from other modules.

[0019] It should be noted that to block signals with frequencies outside the Nyquist bandwidth, the signal passes through the aforementioned second-order low-pass filter before reaching the A / D converter circuit, thereby preventing aliasing. At the same time, the low-pass filter effectively suppresses high-frequency noise generated by the amplifier circuit.

[0020] In addition, in a preferred embodiment, the first high-precision AD sampling circuit 5 and the second high-precision AD sampling circuit 6 are two Σ-Δ type AD converters, which meet the measurement range of 0 to 160 dB, avoiding clipping and shearing caused by excessive amplitude, which in turn leads to filter suppression failure and damage to high-frequency digital data.

[0021] In order to reduce the difficulty of anti-aliasing filter design and improve sampling frequency and sampling accuracy, oversampling is used to sample at 128 times the data rate and output a 1-bit digital signal;

[0022] The digital signal is resampled by the digital signal processor 9 and expanded to 24 bits, and the signal is efficiently filtered and quickly processed by the digital filter.

[0023] In a preferred embodiment, Figure 2 As shown, this embodiment also includes an external clock source 13 and a voltage-controlled crystal oscillator 14, a clock synchronization bus 15 and a monitoring circuit 16. The external clock source 13 and the voltage-controlled crystal oscillator 14 are both connected to the clock synchronization bus 15, and the clock synchronization bus 15 is connected to the monitoring circuit 16; the clock synchronization bus 15 is respectively connected to the dual AD sampling units of the corresponding channels via multiple clock dividers; the digital signal processor 9 has a bidirectional signal connection with the host computer 12 via the bus driving circuit 11, and the digital signal processor 9 is connected to the power supply circuit 10.

[0024] Each channel has a clock divider, using the clock synchronization bus from the baseboard crystal clock as a reference, with the same sampling interval. The trigger signal of the main card is sent to all slave cards to achieve trigger synchronization

[0025] There may be three clock dividers, and the three clock dividers correspond to three dual AD sampling units. Example 2

[0026] This embodiment provides a multi-channel high-speed dual AD synchronous sampling method for use in new energy vehicle testing. The method is performed using a multi-channel high-speed dual AD synchronous sampling device as described above, and specifically includes the following steps: amplifying small signal fluctuations of the collected signal through a first amplifier circuit 1 and a second amplifier circuit 2, filtering out high-frequency noise through a first second-order pass filter circuit 3 and a second second-order pass filter circuit 4 to improve the signal-to-noise ratio; and oversampling at a higher analog sampling rate using a first high-precision AD sampling circuit 5 and a second high-precision AD sampling circuit 6, converting the analog quantity into a 1-bit digital quantity, sending the digital quantity to a serial / parallel shift register 7, and storing the digital quantity in a buffer 8.

[0027] The digital signal processor 9 obtains the conversion result from the buffer 8, resamples it into a 24-bit digital signal, performs filtering operation using the digital anti-aliasing filter IIR, and after relevant compensation and operation, uploads the final result to the host computer 12 via the bus driver circuit 11; when an acquisition cycle is completed, the first high-precision AD sampling circuit 5 and the second high-precision AD sampling circuit 6 both send an external interrupt instruction to the digital signal processor 9, and store the data in the buffer 8 through the serial / parallel shift register 7; the digital signal processor 9 sends a read data instruction to obtain data from the buffer 8, performs anti-aliasing filtering on the part above 0.5465 times the sampling frequency, suppresses mixing signals greater than 72dB, resamples it into a 24-bit digital signal, and transmits it to the host computer 12 via the bus driver circuit 11.

[0028] After all AD conversions are completed, the bus driving circuit 11 receives the interrupt request from the first high-precision AD sampling circuit 5 and the second high-precision AD sampling circuit 6, and sends the interrupt request instruction to the serial / parallel shift register 7, the buffer 8 and the host computer 12 through the digital signal processor 9.

[0029] Among them, the collected signal, before entering the first amplifying circuit 1 and the second amplifying circuit 2, also includes the following steps: after the system is powered on, the digital signal processor 9 initializes the clock synchronization bus 15, connects to the interface of the host computer 12, and sets the serial / parallel shift register 7; sets the sampling frequency, and sets the parameters of the low-pass filter circuit and the anti-aliasing filter according to the sampling frequency and the frequency of the measured signal; selects the external clock source 13 or the onboard voltage-controlled crystal oscillator 14 as the clock source of the clock synchronization bus 15 according to the test environment, test object and test requirements; the external clock source can be GNSS, PTP / IEEE1388, IR The onboard clock source directly generates the AD sampling clock through the internal VCO multiplication and transmits it to the clock synchronization bus 15. The clock dividers on different boards will select the sampling frequency according to the settings of the board. The monitoring circuit 16 is used to monitor the error between the internal time base and the external reference during the data acquisition period. When the error exceeds the pre-programmed restart limit, the time base will be adjusted to resynchronize. Each board obtains the sampling clock from the clock synchronization bus 15. In order to ensure phase consistency, the master card sends a trigger signal at the sampling clock lag position. When the slave card receives the next sampling clock rising edge of the trigger signal, all boards start collecting synchronously.

[0030] The above describes in detail the optional implementation methods of the embodiments of the present invention in conjunction with the accompanying drawings. However, the embodiments of the present invention are not limited to the specific details in the above implementation methods. Within the technical concept of the embodiments of the present invention, various simple modifications can be made to the technical solutions of the embodiments of the present invention, and these simple modifications all fall within the scope of protection of the embodiments of the present invention.

Claims

1. A multi-channel high-speed dual AD synchronous sampling device, characterized in that: A data acquisition device for testing new energy vehicles comprises a dual AD sampling unit, wherein the dual AD sampling unit comprises a first amplifier circuit (1) and a second amplifier circuit (2) for analog quantity input; the signal output ends of the first amplifier circuit (1) and the second amplifier circuit (2) are respectively connected to the signal input ends of a first second-order pass filter circuit (3) and a second second-order pass filter circuit (4); the signal output ends of the first second-order pass filter circuit (3) and the second second-order pass filter circuit (4) are respectively connected to the signal input ends of a first high-precision AD sampling circuit (5) and a second high-precision AD sampling circuit (6); the first high-precision AD sampling circuit (5) and the second high-precision AD sampling circuit (6) are both connected to the signal input end of a serial / parallel shift register (7); the serial / parallel shift register (7) is connected to the signal input end of a digital signal processor (9) via a buffer (8); there are a plurality of dual AD sampling units, each corresponding to a channel; The device collects current, pressure, torque, speed, and temperature signals from a new energy vehicle, processes the collected signals through an amplification circuit and an upstream low-pass filter circuit, converts the signals into a 1-bit digital quantity through a dual AD conversion circuit, and uses a downstream anti-aliasing filter to suppress noise. The digital signal processor resamples the conversion result and expands it to 24 bits. The first high-precision AD sampling circuit (5) and the second high-precision AD sampling circuit (6) are both integrated with anti-aliasing filters. The first amplifier circuit (1) and the second amplifier circuit (2) both adopt differential amplifier circuits; The first amplifying circuit (1) and the second amplifying circuit (2) share a common ground line and are isolated from other modules; The first high-precision AD sampling circuit (5) and the second high-precision AD sampling circuit (6) are two Σ-Δ type AD converters that meet the measurement range of 0 to 160 dB, use oversampling to perform sampling at a data rate of 128 times, and output a 1-bit digital signal; the digital signal is resampled by a digital signal processor (9) and expanded to 24 bits; The invention comprises an external clock source (13), a voltage-controlled crystal oscillator (14), a clock synchronization bus (15), and a monitoring circuit (16), wherein the external clock source (13) and the voltage-controlled crystal oscillator (14) are both connected to the clock synchronization bus (15), and the clock synchronization bus (15) is connected to the monitoring circuit (16); the clock synchronization bus (15) is respectively connected to the dual AD sampling units of the corresponding channels via a plurality of clock frequency dividers; the digital signal processor (9) has a bidirectional signal connection with the host computer (12) via the bus driving circuit (11), and the digital signal processor (9) is connected to the power supply circuit (10); There are three clock frequency dividers, and the three clock frequency dividers correspond to three dual AD sampling units.

2. A multi-channel high-speed dual AD synchronous sampling method, characterized in that: Applied to the testing of new energy vehicles, the method is performed using a multi-channel high-speed dual AD synchronous sampling device as claimed in claim 1, specifically comprising the following steps: the collected signal is amplified by a first amplifying circuit (1) and a second amplifying circuit (2) to amplify tiny signal fluctuations, and high-frequency noise is filtered out by a first second-order pass filter circuit (3) and a second second-order pass filter circuit (4); oversampling is performed at a higher analog sampling rate using a first high-precision AD sampling circuit (5) and a second high-precision AD sampling circuit (6), and the analog quantity is converted into a 1-bit digital quantity and sent to a serial / parallel shift register (7), and stored in a buffer (8); The digital signal processor (9) obtains the conversion result from the buffer (8), resamples it into a 24-bit digital signal, performs filtering operation using a digital anti-aliasing filter IIR, and after relevant compensation and operation, uploads the final result to the host computer (12) via the bus driver circuit (11); when an acquisition cycle ends, the first high-precision AD sampling circuit (5) and the second high-precision AD sampling circuit (6) both send an external interrupt instruction to the digital signal processor (9), and store the data in the buffer (8) through the serial / parallel shift register (7); the digital signal processor (9) sends Send a read data instruction, obtain data from the buffer (8), perform anti-aliasing filtering on the portion above 0.5465 times the sampling frequency, suppress the mixing signal greater than 72dB, resample it into a 24-bit digital signal, and transmit it to the host computer (12) through the bus driving circuit (11); after all AD conversions are completed, the bus driving circuit (11) receives the interrupt request from the first high-precision AD sampling circuit (5) and the second high-precision AD sampling circuit (6), and sends an interrupt request instruction to the serial / parallel shift register (7), the buffer (8) and the host computer (12) through the digital signal processor (9); The collected signal, before entering the first amplifying circuit (1) and the second amplifying circuit (2), further comprises the following steps: after the system is powered on, the digital signal processor (9) initializes the clock synchronization bus (15), connects to the interface of the host computer (12), and sets the serial / parallel shift register (7); sets the sampling frequency, and sets the parameters of the low-pass filter circuit and the anti-aliasing filter according to the sampling frequency and the frequency of the measured signal; selects an external clock source (13) or an onboard voltage-controlled crystal oscillator (14) as the clock source of the clock synchronization bus (15) according to the test environment, the test object and the test requirements; the external clock source can be selected from GNSS, PTP / I The onboard clock source is selected from EEE1388 and IRIG. The AD sampling clock is directly generated by the internal VCO multiplication and transmitted to the clock synchronization bus (15). The clock dividers on different boards will select the sampling frequency according to the settings of the board. The monitoring circuit (16) is used to monitor the error between the internal time base and the external reference during the data acquisition period. When the error is higher than the pre-programmed restart limit, the time base will be adjusted and resynchronized. Each board obtains the sampling clock from the clock synchronization bus (15). The master card sends a trigger signal at the sampling clock lag position. When the slave card receives the next sampling clock rising edge of the trigger signal, all boards start collecting synchronously.

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