Semiconductor light-emitting element and method for manufacturing semiconductor light-emitting element

Abstract

A semiconductor light-emitting element (1) provided with an active layer (30), a P-type cladding layer (40), a contact layer (50), and an insulating film (60), in which a ridge portion (R) is formed in a region including the P-type cladding layer (40) and the contact layer (50), the ridge portion (R) includes a lower ridge portion (Rd) including the P-type cladding layer (40), and an upper ridge portion (Ru) disposed on a top surface (Rdt) of the lower ridge portion (Rd) and including the contact layer (50), the top surface (Rdt) of the lower ridge section (Rd) has a flat section (Rdf) located between the side surface (Rds) of the lower ridge section (Rd) and the bottom surface (Rub) of the upper ridge section (Ru), the width of the bottom surface (Rub) of the upper ridge section (Ru) is smaller than the width of the top surface (Rdt) of the lower ridge section (Rd) and the width of the lower ridge section (Rd) at the center position in the stacking direction, and the insulating film (60) continuously covers a part of the top surface (Rut) of the upper ridge section (Ru) from the side surface (Rds) of the lower ridge section (Rd).

Description

Technical Field

[0001] The present disclosure relates to a semiconductor light emitting element and a method for manufacturing the semiconductor light emitting element. Background Art

[0002] Lasers have been used for processing in the past, and a laser light source with high efficiency and high output is required. As such a laser light source, semiconductor light emitting elements such as semiconductor laser elements are used.

[0003] As a technology for improving the efficiency of a semiconductor light emitting element, there is known a technology of forming a ridge portion so as to confine current in the ridge portion (for example, Patent Document 1).

[0004] (Prior art literature)

[0005] (Patent Document)

[0006] Patent Document 1: Japanese Patent Application Publication No. 2010-67763 Summary of the invention

[0007] Problems to be solved by the invention

[0008] However, a semiconductor light emitting element having a ridge portion has a problem in that current flows into the side surfaces of the ridge portion, which causes heat generation.

[0009] In order to solve such a problem, the present disclosure aims to provide a semiconductor light emitting element or the like which can suppress the flow of current to the side surface of a ridge portion.

[0010] Means for solving problems

[0011] In order to solve the above-mentioned problems, one mode of the semiconductor light-emitting element involved in the present disclosure is a semiconductor light-emitting element that emits light, and the semiconductor light-emitting element comprises: a substrate; an N-type cladding layer arranged above the substrate; an active layer arranged above the N-type cladding layer; a P-type cladding layer arranged above the active layer; a contact layer arranged above the P-type cladding layer; and an insulating film arranged above the P-type cladding layer, wherein a ridge extending in the propagation direction of the light is formed in a region including the P-type cladding layer and the contact layer, The ridge includes a lower ridge and an upper ridge, the lower ridge includes the P-type cladding layer, the upper ridge is arranged on the top surface of the lower ridge and includes the contact layer, the top surface of the lower ridge has a flat portion located between the side surface of the lower ridge and the bottom surface of the upper ridge, and the flat portion extends in the propagation direction of the light, the width of the bottom surface of the upper ridge is smaller than the width of the top surface of the lower ridge and the width of the lower ridge at the central position in the stacking direction, and the insulating film continuously covers from the side surface of the lower ridge to a part of the top surface of the upper ridge.

[0012] In order to solve the above-mentioned problems, another embodiment of the semiconductor light-emitting element involved in the present disclosure is a semiconductor light-emitting element that emits light, wherein the semiconductor light-emitting element comprises: a substrate; an N-type cladding layer arranged above the substrate; an active layer arranged above the N-type cladding layer; a P-type cladding layer arranged above the active layer; and a contact layer arranged above the P-type cladding layer, wherein a ridge extending in the propagation direction of the light is formed in a region including the P-type cladding layer and the contact layer, the ridge comprising a lower ridge and an upper ridge, the lower ridge comprising the P-type cladding layer, the upper ridge being arranged on the top surface of the lower ridge and comprising the contact layer, and the P-type cladding layer is made of Al X Ga 1-X As(0<X<1), and the P-type cladding layer comprises: a lower cladding layer, a first cladding layer arranged above the lower cladding layer, a first etching stop layer arranged above the first cladding layer, a second cladding layer arranged above the first etching stop layer, and a second etching stop layer arranged above the second cladding layer, with respect to the Al component ratio X0 of the lower cladding layer, the Al component ratio X1 of the first cladding layer, and the Al component ratio X2 of the second cladding layer, the relationships X1=X2>0.8 and X1=X2>X0 hold.

[0013] In order to solve the above-mentioned problems, one mode of the manufacturing method of the semiconductor light-emitting element involved in the present disclosure is a manufacturing method of the semiconductor light-emitting element that emits light, and the manufacturing method includes the following steps: a step of forming an N-type cladding layer above a substrate; a step of forming an active layer above the N-type cladding layer; a step of forming a P-type cladding layer above the active layer; a step of forming a contact layer above the P-type cladding layer; a step of forming a ridge portion in a region including the P-type cladding layer and the contact layer; and a step of forming an insulating film on the ridge portion, the ridge portion including a lower ridge portion and an upper ridge portion, the lower ridge including the P-type The upper ridge is arranged on the top surface of the lower ridge and includes the contact layer, and the process of forming the ridge includes: a process of forming the upper ridge; and a process of forming the lower ridge after the process of forming the upper ridge, the top surface of the lower ridge has a flat portion, which is located between the side surface of the lower ridge and the bottom surface of the upper ridge and extends in the propagation direction of the light, the width of the bottom surface of the upper ridge is smaller than the width of the top surface of the lower ridge and the width of the lower ridge at the central position in the stacking direction, and the insulating film continuously covers from the side surface of the lower ridge to a part of the top surface of the upper ridge.

[0014] Effects of the Invention

[0015] According to the present disclosure, it is possible to provide a semiconductor light emitting element or the like which can suppress the flow of current to the side surface of the ridge portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a plan view schematically showing the overall structure of a semiconductor light emitting element according to an embodiment.

[0017] Figure 2 It is a first cross-sectional view schematically showing the overall structure of the semiconductor light emitting element according to the embodiment.

[0018] Figure 3 It is a second cross-sectional view schematically showing the overall structure of the semiconductor light emitting element according to the embodiment.

[0019] Figure 4 It is a third cross-sectional view schematically showing the overall structure of the semiconductor light emitting element according to the embodiment.

[0020] Figure 5 It is a cross-sectional view schematically showing the structure of an active layer according to an embodiment.

[0021] Figure 6 It is a cross-sectional view schematically showing the structure of the second etching stop layer according to the embodiment.

[0022] Figure 7 yes Figure 2 A magnified view of the ridge is shown.

[0023] Figure 8 yes Figure 2 An enlarged view of the wing is shown.

[0024] Fig. 9 It is a cross-sectional view schematically showing a first step of the method for manufacturing a semiconductor light emitting element according to the embodiment.

[0025] Fig.10 It is a cross-sectional view schematically showing a second step of the method for manufacturing a semiconductor light emitting element according to the embodiment.

[0026] Fig.11 It is a first cross-sectional view schematically showing a third step of the method for manufacturing a semiconductor light emitting element according to the embodiment.

[0027] Fig.12 It is a second cross-sectional view schematically showing the third step of the method for manufacturing the semiconductor light emitting element according to the embodiment.

[0028] Fig.13 It is a first cross-sectional view schematically showing a fourth step of the method for manufacturing a semiconductor light emitting element according to the embodiment.

[0029] Fig.14 It is a second cross-sectional view schematically showing the fourth step of the method for manufacturing the semiconductor light emitting element according to the embodiment.

[0030] Fig.15 It is a first cross-sectional view schematically showing the fifth step of the method for manufacturing the semiconductor light emitting element according to the embodiment.

[0031] Fig.16 It is a second cross-sectional view schematically showing the fifth step of the method for manufacturing the semiconductor light emitting element according to the embodiment.

[0032] Fig.17 It is a first cross-sectional view schematically showing a sixth step of the method for manufacturing a semiconductor light emitting element according to the embodiment.

[0033] Fig.18 It is a second cross-sectional view schematically showing the sixth step of the method for manufacturing the semiconductor light emitting element according to the embodiment.

[0034] Fig.19 It is a cross-sectional view schematically showing a seventh step of the method for manufacturing a semiconductor light emitting element according to the embodiment.

[0035] Fig. 20 It is a first cross-sectional view schematically showing an eighth step of the method for manufacturing a semiconductor light emitting element according to the embodiment.

[0036] Fig.21 It is a second cross-sectional view schematically showing the eighth step of the method for manufacturing the semiconductor light emitting element according to the embodiment.

[0037] Fig. 22 It is a cross-sectional view schematically showing a ninth step of the method for manufacturing a semiconductor light emitting element according to the embodiment.

[0038] Fig.23 It is a first cross-sectional view schematically showing the tenth step of the method for manufacturing the semiconductor light emitting element according to the embodiment.

[0039] Fig.24 It is a second cross-sectional view schematically showing the tenth step of the method for manufacturing the semiconductor light emitting element according to the embodiment.

[0040] Fig.25 : is a graph showing the relationship between the output power and the injection current of the semiconductor light emitting element according to the embodiment.

[0041] Fig.26 : is a graph showing the relationship between the remaining thickness of the semiconductor light emitting element according to the embodiment and the horizontal diffusion angle of the emitted light.

[0042] Fig. 27 : is a graph showing the relationship between the horizontal diffusion angle of emitted light and the effective refractive index difference of the semiconductor light emitting element according to the embodiment.

[0043] Fig.28 It is a plan view schematically showing the overall structure of a semiconductor light emitting element according to Modification 1 of the embodiment.

[0044] Fig.29 This is a first cross-sectional view schematically showing the overall structure of a semiconductor light emitting element according to Modification 1 of the embodiment.

[0045] Fig.30 This is a second cross-sectional view schematically showing the overall structure of the semiconductor light emitting element according to Modification 1 of the embodiment.

[0046] Fig.31 It is a third cross-sectional view schematically showing the overall structure of the semiconductor light emitting element according to Modification 1 of the embodiment.

[0047] Fig.32 It is a fourth cross-sectional view schematically showing the overall structure of the semiconductor light emitting element according to Modification 1 of the embodiment.

[0048] Fig.33 It is a plan view schematically showing the overall structure of a semiconductor light emitting element according to Modification 2 of the embodiment.

[0049] Fig.34 It is a first cross-sectional view schematically showing the overall structure of a semiconductor light emitting element according to Modification 2 of the embodiment.

[0050] Fig.35 This is a second cross-sectional view schematically showing the overall structure of the semiconductor light emitting element according to Modification 2 of the embodiment.

[0051] Fig.36 It is a third cross-sectional view schematically showing the overall structure of the semiconductor light emitting element according to Modification 2 of the embodiment. DETAILED DESCRIPTION

[0052] Hereinafter, the embodiments of the present disclosure will be described with reference to the accompanying drawings. In addition, the embodiments to be described below are all specific examples of the present disclosure. Therefore, the numerical values, shapes, materials, constituent elements, and the configuration positions and connection forms of the constituent elements shown in the following embodiments are all examples, and their main purpose is not to limit the present disclosure.

[0053] Furthermore, each figure is a schematic diagram, not a strict illustration. Therefore, the scales in each figure are not necessarily the same. In addition, the same reference numerals are given to substantially the same components in each figure, and repeated descriptions are omitted or simplified.

[0054] Furthermore, in the specification, the terms "above" and "below" do not refer to the upper direction (vertically above) and the lower direction (vertically below) in absolute spatial recognition, but are used as terms defined by relative positional relationships based on the stacking order in the stacking structure. In addition, the terms "above" and "below" can be applied not only to the case where two components are arranged at a distance from each other and there is another component between the two components, but also to the case where two components are arranged in a state of being in contact with each other.

[0055] (Implementation Method)

[0056] A semiconductor light emitting element according to an embodiment will be described.

[0057] [1. Overall composition]

[0058] First, use Figures 1 to 4 The overall structure of the semiconductor light emitting element according to this embodiment will be described. Figure 1 It is a plan view schematically showing the overall structure of the semiconductor light emitting element 1 according to the present embodiment. Figures 2 to 4 Each of them is a cross-sectional view schematically showing the overall structure of the semiconductor light emitting element 1 according to the present embodiment. Figure 2 as well as Figure 3 They are shown respectively Figure 1 The cross section of the semiconductor light emitting element 1 at the II-II line and the III-III line. Figure 4 Only Figure 1 The cross section of the semiconductor light emitting element 1 at the IV-IV line includes a portion of the end face 1F. In addition, each figure shows an X-axis, a Y-axis, and a Z-axis that are orthogonal to each other. The X-axis, the Y-axis, and the Z-axis are orthogonal coordinate systems of a right-handed coordinate system. The stacking direction of the semiconductor light emitting element 1 (i.e., the thickness direction of each layer of the semiconductor light emitting element 1) is parallel to the Z-axis direction, and the main propagation direction of the light (laser beam) is parallel to the Y-axis direction.

[0059] The semiconductor light emitting element 1 is an element that emits light by supplying current. In the present embodiment, the semiconductor light emitting element 1 is a semiconductor laser element that emits a laser beam having a wavelength in the near-infrared region (about 900 nm to about 980 nm). More specifically, the semiconductor light emitting element 1 emits a laser beam having a wavelength of about 976 nm. Figure 1As shown, the semiconductor light emitting element 1 has two end faces 1F and 1R forming a resonator. End face 1F is the front end face that emits the laser beam, and end face 1R is the rear end face having a higher reflectivity than end face 1F. Furthermore, the semiconductor light emitting element 1 has a waveguide formed between end face 1F and end face 1R. There is no special limitation on the resonator length of the semiconductor light emitting element 1, that is, the distance between end faces 1F and 1R in the propagation direction of the laser beam (the Y-axis direction of each figure, that is, the vibration direction), and in this embodiment, it is greater than 2 mm. Furthermore, the resonator length of the semiconductor light emitting element 1 can also be greater than 5 mm. The semiconductor light emitting element 1 has reflective films 2F and 2R arranged at the ends in the propagation direction of the laser beam. The reflective films 2F and 2R are films for adjusting the reflectivity of the end faces 1F and 1R, respectively. In this embodiment, the reflective films 2F and 2R are each a dielectric multilayer film. The reflectivity of the reflective film 2F is lower than that of the reflective film 2R.

[0060] like Figure 2 As shown, the semiconductor light emitting element 1 includes a substrate 10, an N-type cladding layer 20, an active layer 30, a P-type cladding layer 40, a contact layer 50, and an insulating film 60. In this embodiment, the semiconductor light emitting element 1 further includes an N-type buffer layer (not shown), an N-type buffer boundary layer (not shown), a first P-side electrode 71, a pad electrode 73, a second P-side electrode 72, and an N-side electrode 80.

[0061] The substrate 10 is a plate-shaped member serving as a base of the semiconductor light emitting element 1. In the present embodiment, the substrate 10 is an N-type GaAs substrate.

[0062] The N-type buffer layer is an N-type semiconductor layer disposed on the substrate 10. In the present embodiment, the N-type buffer layer is an N-type GaAs layer having a film thickness of 0.5 μm.

[0063] The N-type buffer boundary layer is an N-type semiconductor layer disposed between the N-type buffer layer and the N-type cladding layer 20. In this embodiment, the N-type buffer boundary layer is an N-type Al2O3 layer having a film thickness of 0.05 μm. X22 Ga 1-X22 As layer (0.15≤X22≤0.25). The Al composition ratio X22 of the N-type buffer boundary layer increases as it approaches the N-type cladding layer 20. The Al composition ratio X22 of the N-type buffer boundary layer is 0.15 at the boundary surface with the N-type buffer layer and is 0.25 at the boundary surface with the N-type cladding layer 20.

[0064] The N-type cladding layer 20 is an N-type semiconductor layer disposed on the substrate 10. The average refractive index of the N-type cladding layer 20 is lower than the average refractive index of the active layer 30. In this embodiment, the N-type cladding layer 20 is disposed on the N-type buffer boundary layer. The N-type cladding layer 20 is an N-type Al2O3 layer having a film thickness of 3.1 μm. 0.25 Ga0.75 As layer.

[0065] The active layer 30 is a light emitting layer disposed on the N-type cladding layer 20. In this embodiment, the active layer 30 has a quantum well structure. Figure 5 The structure of the active layer 30 will be described. Figure 5 It is a cross-sectional view schematically showing the structure of the active layer 30 according to the present embodiment. Figure 5 Shows Figure 1 The cross section of the active layer 30 at the II-II line. Figure 5 As shown, the active layer 30 includes an N-side cladding boundary layer 31 , an N-side guide layer 32 , an N-side barrier layer 33 , a well layer 34 , a P-side barrier layer 35 , a P-side guide layer 36 , and a P-side cladding boundary layer 37 .

[0066] like Figure 3 as well as Figure 4 As shown, the active layer 30 has a window region 30w (i.e., a non-luminous region) located near the end face 1F of the semiconductor light-emitting element 1. The window region 30w is a region where a portion of the quantum well structure including the N-side barrier layer 33, the well layer 34, and the P-side barrier layer 35 is disordered, and the band gap energy in the window region 30w is larger than that in the region other than the window region 30w of the active layer 30. Accordingly, the light emission and absorption of light near the end face 1F are suppressed, thereby suppressing the heat generation near the end face 1F. Therefore, the COD (Catastrophic Optical Damage) near the end face 1F of the semiconductor light-emitting element 1 can be suppressed. In the present embodiment, the active layer 30 also has a window region 30w located near the end face 1R. The window region 30w is formed in the active layer 30 from the end on the end face 1F side to a specified length along the propagation direction of light. The length of the window region 30w in the light propagation direction may be equal to the length from the end of the upper ridge Ru on the end face 1F side to the end of the P-type cladding layer 40 on the end face 1F side. The state represented by the description of these equal lengths is not limited to the state that these lengths are completely equal, but also includes a state that they are substantially equal. The state represented by the description of these equal lengths also includes, for example, a state in which the difference between these lengths is less than 10% of each length.

[0067] Figure 5 The N-side cladding boundary layer 31 shown is disposed on the N-type cladding layer 20 (see Figures 2 to 4 ) is a semiconductor layer above the N-type cladding layer 20. In this embodiment, the N-side cladding boundary layer 31 is an N-type Al with a film thickness of 0.83 μm arranged between the N-type cladding layer 20 and the N-side guide layer 32. X31 Ga 1-X31As layer (0.25 ≥ X31 ≥ 0.20). The Al composition ratio X31 of the N-side cladding boundary layer 31 decreases as it approaches the N-side guide layer 32. The Al composition ratio X31 of the N-side cladding boundary layer 31 is 0.25 at the boundary surface with the N-type cladding layer 20 and is 0.20 at the boundary surface with the N-side guide layer 32.

[0068] The N-side guide layer 32 is disposed on the N-type cladding layer 20 (see Figures 2 to 4 ) is a semiconductor layer above the N-side guide layer 32. The average refractive index of the N-side guide layer 32 is higher than the average refractive index of the N-type cladding layer 20. In this embodiment, the N-side guide layer 32 is arranged above the N-side cladding boundary layer 31. The N-side guide layer 32 is an N-type Al2O3 layer with a film thickness of 0.27 μm. 0.20 Ga 0.80 As layer.

[0069] The N-side barrier layer 33 is a semiconductor layer that is disposed above the N-type cladding layer 20 and functions as a barrier for the quantum well structure. In this embodiment, the N-side barrier layer 33 is disposed above the N-side guide layer 32. The N-side barrier layer 33 is an undoped Al layer with a thickness of 0.010 μm. 0.16 Ga 0.84 As layer.

[0070] The well layer 34 is a semiconductor layer that functions as a well of a quantum well structure and is disposed above the N-type cladding layer 20. In the present embodiment, the well layer 34 is disposed above the N-side barrier layer 33. The well layer 34 is an undoped In layer with a film thickness of 0.0090 μm. 0.14 Ga 0.86 As layer.

[0071] The P-side barrier layer 35 is disposed on the N-type cladding layer 20 (see Figures 2 to 4 ) is a semiconductor layer that functions as a barrier of the quantum well structure above the well layer. In this embodiment, the P-side barrier layer 35 is arranged above the well layer 34. The P-side barrier layer 35 is an undoped Al with a film thickness of 0.010 μm. 0.16 Ga 0.84 As layer.

[0072] The P-side guide layer 36 is disposed on the N-type cladding layer 20 (see Figures 2 to 4 ) is a semiconductor layer above the P-side guide layer 36. The average refractive index of the P-type cladding layer 40 (refer to Figures 2 to 4 ) has a high average refractive index. In this embodiment, the P-side guide layer 36 is disposed above the P-side barrier layer 35. The P-side guide layer 36 is a P-type Al with a film thickness of 0.29 μm. X36 Ga 1-X36As layer (0.20≤X36≤0.21). The Al composition ratio X36 of the P-side guide layer 36 is 0.20 in a region where the distance between the boundary surface of the P-side guide layer 36 and the P-side barrier layer 35 is 0.010 μm or less. The Al composition ratio X36 of the P-side guide layer 36 increases as it approaches the P-side cladding boundary layer 37 in a region where the distance between the boundary surface of the P-side guide layer 36 and the P-side barrier layer 35 is greater than 0.010 μm. The Al composition ratio X36 of the P-side guide layer 36 is 0.21 at the boundary surface with the P-side cladding boundary layer 37.

[0073] The P-side cladding boundary layer 37 is disposed on the N-type cladding layer 20 (see Figures 2 to 4 ) is a semiconductor layer above the P-side cladding boundary layer 37. In this embodiment, the P-side guide layer 36 and the P-type cladding layer 40 (see Figures 2 to 4 ) with a film thickness of 0.1 μm X37 Ga 1-X37 As layer (0.21 ≥ X37 ≥ 0.75). The Al composition ratio X37 of the P-side cladding boundary layer 37 increases as it approaches the P-type cladding layer 40. The Al composition ratio X37 of the P-side cladding boundary layer 37 is 0.21 at the boundary surface with the P-side guide layer 36 and is 0.75 at the boundary surface with the P-type cladding layer 40.

[0074] Figures 2 to 4 The P-type cladding layer 40 shown is a P-type semiconductor layer disposed above the active layer 30. The average refractive index of the P-type cladding layer 40 is lower than the average refractive index of the active layer 30. In this embodiment, the P-type cladding layer 40 is made of Al X Ga 1-X It is composed of As (0<X<1), and includes a lower cladding layer 41 , a first cladding layer 42 , a first etching stop layer 43 , a second cladding layer 44 , and a second etching stop layer 45 .

[0075] The lower cladding layer 41 is a P-type semiconductor layer disposed above the active layer 30. In the present embodiment, the lower cladding layer 41 is a P-type Al2O3 layer having a film thickness of 0.050 μm. 0.75 Ga 0.25 As layer.

[0076] The first cladding layer 42 is a P-type semiconductor layer disposed on the active layer 30. In the present embodiment, the first cladding layer 42 is a P-type Al2O3 layer having a film thickness of 0.10 μm disposed on the lower cladding layer 41. 0.85 Ga 0.15 As layer.

[0077] The first etching stop layer 43 is a P-type semiconductor layer disposed above the active layer 30. In this embodiment, the first etching stop layer 43 is disposed above the first cladding layer 42. The Al composition ratio of the first etching stop layer 43 is less than 0.7. The first etching stop layer 43 is a P-type Al with a film thickness of 0.05 μm. 0.70 Ga 0.30 As layer.

[0078] The second cladding layer 44 is a P-type semiconductor layer disposed on the active layer 30. In the present embodiment, the second cladding layer 44 is a P-type Al2O3 layer having a film thickness of 0.20 μm disposed on the first etching stop layer 43. 0.85 Ga 0.15 As layer.

[0079] In the present embodiment, the following relationship holds true regarding the Al composition ratio X0 of the lower cladding layer 41, the Al composition ratio X1 of the first cladding layer 42, and the Al composition ratio X2 of the second cladding layer 44:

[0080] X1=X2>0.8 and X1=X2>X0.

[0081] The second etching stop layer 45 is a P-type semiconductor layer disposed on the active layer 30. In the present embodiment, the second etching stop layer 45 is a P-type Al2O3 layer having a film thickness of 0.050 μm disposed on the second cladding layer 44. X45 Ga 1-X45 As layer (0.70≥X45≥0.15). The second etching stop layer 45 has two or more inclined regions where the Al composition ratio decreases as it approaches the contact layer, and one or more constant regions where the Al composition ratio does not change relative to the stacking direction position. The two or more inclined regions and the one or more constant regions are alternately arranged in the stacking direction. Figure 6 The structure of the second etching stopper layer 45 according to the present embodiment will be described. Figure 6 It is a cross-sectional view schematically showing the structure of the second etching stopper layer 45 according to the present embodiment. Figure 6 Shows Figure 1 The cross section of the second etching stop layer 45 of the ridge R at the II-II line. Figure 6 As shown, the second etch stop layer 45 has two inclined regions 45 b and 45 d and two constant regions 45 a and 45 c .

[0082] The fixed region 45a is a P-type Al layer having a thickness of 0.050 μm and disposed above the second cladding layer 44. 0.70 Ga 0.30 The inclined region 45b is a P-type Al layer having a film thickness of 0.01 μm and arranged above the constant region 45a.X45 Ga 1-X45 As layer. The Al composition ratio X45 of the inclined region 45b decreases as it approaches the contact layer 50. The Al composition ratio X45 of the inclined region 45b is 0.70 at the boundary surface with the constant region 45a and 0.60 at the boundary surface with the constant region 45c. The constant region 45c is a P-type Al film with a thickness of 0.030 μm arranged above the inclined region 45b. 0.60 Ga 0.40 The inclined region 45d is a P-type Al layer having a film thickness of 0.010 μm and arranged above the constant region 45c. X45 Ga 1-X45 The Al composition ratio X45 of the inclined region 45d decreases as it approaches the contact layer 50. The Al composition ratio X45 of the inclined region 45d is 0.60 at the boundary surface with the constant region 45c and is 0.15 at the boundary surface with the contact layer 50.

[0083] The contact layer 50 is a P-type semiconductor layer disposed above the P-type cladding layer 40 and in ohmic contact with the first P-side electrode 71. In the present embodiment, the contact layer 50 is a P-type GaAs layer having a film thickness of 0.25 μm.

[0084] like Figure 1 as well as Figure 2 As shown, a ridge R extending along the propagation direction of light is formed in a region including the P-type cladding layer 40 and the contact layer 50. A waveguide is formed along the ridge R. In addition, Figure 1 The profile of the upper surface of the ridge R is shown. Figures 1 to 4 And use Figure 7 The structure of the ridge portion R will be described. Figure 7 yes Figure 2 The enlarged view of the ridge R is shown. Figure 2As shown, the ridge R includes a lower ridge Rd and an upper ridge Ru, the lower ridge Rd includes a P-type cladding layer 40, and the upper ridge Ru is arranged on the top surface Rdt of the lower ridge Rd and includes a contact layer 50. The top surface Rdt of the lower ridge Rd has a flat portion Rdf located between the side surface Rds of the lower ridge Rd and the bottom surface Rub of the upper ridge Ru and extending in the propagation direction of light. The width Wub of the bottom surface Rub of the upper ridge Ru is smaller than the width Wdt of the top surface Rdt of the lower ridge Rd and the width Wdc of the lower ridge Rd at the central position Rdc in the stacking direction. In addition, the width of the ridge R here refers to the size of the ridge R in the direction perpendicular to the stacking direction (i.e., the Z-axis direction) and the length direction of the ridge R (i.e., the propagation direction of light or the Y-axis direction). The width Wut of the top surface Rut of the upper ridge Ru is smaller than the width Wub of the bottom surface Rub of the upper ridge Ru. That is, the cross section of the upper ridge portion Ru perpendicular to the longitudinal direction of the ridge portion R has a forward mesas shape. The side surface Rus of the upper ridge portion Ru forms an inclined surface of the forward mesas shape.

[0085] The upper ridge portion Ru includes at least a portion of the contact layer 50. In the present embodiment, the upper ridge portion Ru includes at least a portion of each of the second etch stop layer 45 and the contact layer 50.

[0086] like Figure 1 , Figure 3 as well as Figure 4 As shown, the upper ridge Ru is not formed near the end face 1F of the semiconductor light emitting element 1. In other words, the upper surface of the end portion of the ridge R in the light propagation direction, which is close to the end face 1F of the semiconductor light emitting element 1 from which light is emitted, is located on the second etching stop layer 45. That is, the contact layer 50 is not formed at the end portion of the ridge R in the light propagation direction, which is close to the end face 1F of the semiconductor light emitting element 1 from which light is emitted. Accordingly, when the semiconductor light emitting element 1 is mounted on a substrate or the like in a junction-down manner (i.e., flip-chip), stress can be suppressed from being concentratedly applied to the end portion of the ridge R. Therefore, damage near the end face 1F of the semiconductor light emitting element 1 can be suppressed. In addition, in the present embodiment, the upper ridge Ru is also not formed near the end face 1R of the semiconductor light emitting element 1.

[0087] like Figure 4 As shown, in the cross section of the upper ridge Ru in the direction parallel to the light propagation direction (and the stacking direction), the end of the upper ridge Ru on the side close to the light emitting end face 1F of the semiconductor light emitting element 1 has an inverted shape. In other words, the upper end of the upper ridge Ru is located closer to the end face 1F than the lower end.

[0088] like Figure 7As shown, the lower ridge Rd includes at least a portion of each of the second cladding layer 44 and the second etching stop layer 45. In the present embodiment, the lower ridge Rd includes at least a portion of each of the first etching stop layer 43, the second cladding layer 44, and the second etching stop layer 45. The top surface Rdt of the lower ridge Rd is located in the second etching stop layer 45. Therefore, the flat portion Rdf, which is a portion of the top surface Rdt of the lower ridge Rd, is also located in the second etching stop layer 45. The Al composition ratio of the flat portion Rdf is less than 0.7.

[0089] Regarding the width Wdt of the top surface Rdt of the lower ridge Rd, the width Wdc of the lower ridge Rd at the center position Rdc in the stacking direction, and the width Wdb of the bottom surface Rdb of the lower ridge Rd, the following relationship holds, namely:

[0090] Wdt>Wdc and Wdb>Wdc.

[0091] In addition, the width Wdt of the top surface Rdt of the lower ridge Rd may be equal to the width Wdc at the center position Rdc in the stacking direction of the lower ridge Rd. The state represented by the description that the width Wdt is equal to the width Wdc is not limited to the state that the width Wdt and the width Wdc are completely equal, but also includes a state that they are substantially equal. The state represented by the description that the width Wdt and the width Wdc are equal includes, for example, a state in which the difference between the width Wdt and the width Wdc is less than 3% of each width.

[0092] With respect to the bottom surface Rdb of the lower ridge Rd, the upper surface (ie, Figure 7 The bottom portion Tb shown is located at the first etch stop layer 43. In other words, the bottom surface Rdb of the lower ridge Rd is located at the first etch stop layer 43.

[0093] In this embodiment, a wing portion G extending along the ridge portion R is formed in a region including the P-type cladding layer 40 and the contact layer 50. In other words, a groove portion T is formed between the wing portion G and the ridge portion R. Figure 1 The contour of the upper surface of the wing G is shown in FIG. Figure 8 The wing portion G will be described. Figure 8 yes Figure 2 An enlarged view of wing G is shown.

[0094] like Figure 8As shown, the wing G includes a lower wing Gd and an upper wing Gu, the lower wing Gd includes a P-type cladding layer 40, and the upper wing Gu is arranged on the top surface Gdt of the lower wing Gd and includes a contact layer 50. The top surface Gdt of the lower wing Gd has a wing flat portion Gdf, which is a flat area located between the side surface Gds of the lower wing Gd and the bottom surface Gub of the upper wing Gu and extending along the propagation direction of light. In this embodiment, a ridge R is formed between the two wings G. With such a wing G, it is possible to suppress the stress applied to the ridge R when the semiconductor light emitting element 1 is mounted on a mounting substrate or the like.

[0095] A concave portion 3 is formed at the end of the width direction of the semiconductor light emitting element 1 (i.e., the end in the X-axis direction). The concave portion 3 is formed outside the wing portion G in the X-axis direction. The concave portion 3 is a part of the separation groove used when the semiconductor light emitting element 1 is singulated. Figure 8 As shown in the figure, the portion of the side surface of the semiconductor light emitting element 1 corresponding to the recess 3 is retracted inwardly in the X-axis direction. The side surface Gds of the lower wing Gd on the side away from the ridge R is included in the recess 3. The side surface Gds of the lower wing Gd on the side away from the ridge R has a constricted portion 3w, which is located further inwardly in the width direction of the semiconductor light emitting element 1 relative to the upper end of the lower wing Gd (the position of the side surface Gds corresponding to the top surface Gdt).

[0096] The position of the concave portion 3 in the width direction of the semiconductor light emitting element 1 is located at the innermost side in the width direction (i.e., close to the ridge R) in the P-type cladding layer 40. In other words, the concave portion 3 is the most retracted portion in the P-type cladding layer 40. The position of the concave portion 3 in the width direction of the semiconductor light emitting element 1 starts from the upper end of the lower wing portion Gd and gradually approaches the outer side in the width direction of the semiconductor light emitting element 1 (i.e., in the direction away from the ridge R) as it approaches from the active layer 30 to the substrate 10.

[0097] The upper wing portion Gu has a regular conical shape in a cross section perpendicular to the longitudinal direction of the wing portion G. A regular conical shaped inclined surface is formed on a side surface Gus of the upper wing portion Gu.

[0098] The insulating film 60 is an electrical insulating film disposed above the P-type cladding layer 40. Figure 7As shown, the insulating film 60 continuously covers from the side surface Rds of the lower ridge Rd to a part of the top surface Rut of the upper ridge Ru. That is, the insulating film 60 continuously covers the side surface Rds, the flat portion Rdf, the side surface Rus, and the top surface Rut of the lower ridge Rd. In the present embodiment, an opening 60a is formed at a position of the insulating film 60 corresponding to the top surface Rut of the upper ridge Ru. Current is injected from the first P-side electrode 71 to the contact layer 50 through the opening 60a. In other words, the opening 60a is a current injection window area for injecting current into the contact layer 50. The upper surface of the semiconductor stack formed on the substrate 10 is continuously covered by the insulating film 60 except for the opening 60a. Accordingly, it is possible to suppress the current from flowing out to the area outside the ridge R. There is no special limitation on the material of the insulating film 60 as long as it has electrical insulation. In the present embodiment, the insulating film 60 is a silicon nitride film with a film thickness of 100nm.

[0099] The first P-side electrode 71 is a conductive layer disposed above the contact layer 50. Figure 7 As shown, the first P-side electrode 71 is in contact with the contact layer 50 on the upper surface of the ridge R, that is, on the top surface Rut of the upper ridge Ru. Figure 7 as well as Figure 8 As shown in FIG. 1 , the first P-side electrode 71 continuously covers the upper surface of one wing G (i.e., the top surface Gut of the upper wing Gu) except for the opening 60a to the upper surface of the other wing G. The material of the first P-side electrode 71 is not particularly limited as long as it has conductivity. The first P-side electrode 71 includes, for example, a Ti film with a thickness of 50 nm, a Pt film with a thickness of 150 nm, and an Au film with a thickness of 50 nm, which are sequentially stacked from the contact layer 50 side.

[0100] Figure 2 as well as Figure 4 The pad electrode 73 shown is a pad-shaped conductive layer disposed above the first P-side electrode 71. In the present embodiment, the pad electrode 73 has an eaves portion 73a at the end in the X-axis direction. The eaves portion 73a is a portion protruding outward in the X-axis direction at the upper end of the X-axis end of the pad electrode 73. The configuration of the pad electrode 73 is not particularly limited. In the present embodiment, the pad electrode 73 is a gold-plated film with a film thickness of 2.5 μm.

[0101] Figures 2 to 4The second P-side electrode 72 shown is a conductive layer disposed above the pad electrode 73. The second P-side electrode 72 may also be disposed in a region of the first P-side electrode 71 and the upper surface of the insulating film 60 where the pad electrode 73 is not disposed. The configuration of the second P-side electrode 72 is not particularly limited. In the present embodiment, the second P-side electrode 72 is a Ti film with a thickness of 50 nm, a Pt film with a thickness of 150 nm, and an Au film with a thickness of 300 nm stacked in sequence from the pad electrode 73 side.

[0102] Figure 2 , Figure 4 The N-side electrode 80 shown is a conductive layer disposed on the main surface below the substrate 10 (i.e., the main surface on the back of the main surface on which the semiconductor layer is stacked among the main surfaces of the substrate 10). The composition of the N-side electrode 80 is not particularly limited. In the present embodiment, the N-side electrode 80 includes a 90nm thick AuGe film, a 20nm thick Ni film, a 50nm thick Au film, a 100nm thick Ti film, a 50nm thick Pt film, a 50nm thick Ti film, a 100nm thick Pt film, and a 500nm thick Au film, which are stacked in sequence from the substrate 10 side.

[0103] [2. Manufacturing method]

[0104] use Figures 9 to 24 A method for manufacturing the semiconductor light emitting element 1 according to the present embodiment will be described. Figures 9 to 24 2 is a cross-sectional view schematically showing each step of the method for manufacturing the semiconductor light emitting element 1 according to the present embodiment. Fig. 9 , Fig.11 , Fig.13 , Fig.15 , Fig.17 , Fig.19 , Fig. 20 , Fig. 22 ,as well as, Fig.23 Shown with Figure 1 The cross section of the semiconductor light emitting element 1 shown at line II-II. Fig.10 , Fig.12 , Fig.14 , Fig.16 , Fig.18 , Fig.21 ,as well as, Fig.24 It is shown in Figure 1 The cross section corresponding to the III-III line of the semiconductor light emitting element 1 is shown.

[0105] First, Fig. 9As shown, a substrate 10 is prepared to form each semiconductor layer. The process of forming each semiconductor layer includes: a process of forming an N-type cladding layer 20 above the substrate 10, a process of forming an active layer 30 above the N-type cladding layer 20, a process of forming a P-type cladding layer 40 above the active layer 30, and a process of forming a contact layer 50 above the P-type cladding layer 40. In the present embodiment, the process of forming each semiconductor layer also includes: a process of forming an N-type buffer layer above the substrate 10 before the process of forming the N-type cladding layer 20; and a process of forming an N-type buffer boundary layer above the N-type buffer layer. Each semiconductor layer is formed by crystal growth, for example, using MOCVD (Metalorganic Chemical Vapor Deposition).

[0106] Then as Fig.10 As shown, the window region 30w is formed in the region corresponding to the vicinity of the end face 1F in the active layer 30. Specifically, the window region 30w is formed by diffusing impurities such as Zn in the active layer 30. In the present embodiment, the window region 30w is also formed in the region corresponding to the vicinity of the end face 1R.

[0107] Next, a ridge R is formed in a region including the P-type cladding layer 40 and the contact layer 50. The process of forming the ridge R includes: forming an upper ridge Ru, and forming a lower ridge Rd after forming the upper ridge Ru (see Figure 2 ) process. First, Fig.11 as well as Fig.12 As shown, the upper ridge Ru is formed. In this embodiment, the upper wing Gu is also formed at the same time. In this embodiment, wet etching is used in the process of forming the upper ridge Ru. Accordingly, the side Rus can be tilted in such a way that the upper ridge Ru becomes a regular terrace shape. Therefore, the tightness between the side Rus and the insulating film 60 can be improved.

[0108] In this process, specifically, a mask composed of SiO2 or the like is formed in a predetermined pattern by using photolithography technology on the contact layer 50. Thereafter, the portion of the contact layer 50 not covered by the mask is removed by wet etching technology. When performing wet etching, the chemical solution used in etching and the composition of each semiconductor layer are determined in such a way that the etching speed of the second etching stop layer 45 is slower than that of the contact layer 50. Accordingly, it is easy to stop etching at the second etching stop layer 45. In other words, the controllability of the height of the upper ridge Ru and the upper wing Gu can be improved. In this embodiment, the contact layer 50 and a portion of the second etching stop layer 45 are removed by wet etching. That is, the bottom surface Rub of the upper ridge Ru and the bottom surface Gub of the upper wing Gu are located in the second etching stop layer 45.

[0109] In this embodiment, the second etching stop layer 45 has constant regions 45a and 45c (see Figure 6 ), thereby making it possible to more reliably stop etching in the second etching stop layer 45 compared to a case where the entire second etching stop layer 45 is composed of an inclined region.

[0110] As the chemical solution used for etching, for example, a solution containing tartaric acid and hydrogen peroxide can be used. The mixing ratio of tartaric acid to hydrogen peroxide is, for example, 2:1.

[0111] Through the above method, Fig.11 as well as Fig.12 As shown in FIG. 1 , an upper ridge Ru and an upper wing Gu having a regular terrace shape in a cross section perpendicular to the light propagation direction can be formed. Fig.12 As shown in FIG. 1 , no upper ridge Ru is formed near the end face 1F (and the end face 1R) of the semiconductor light emitting element 1. Figure 4 As shown, in a cross section of the upper ridge portion Ru in a direction parallel to the light propagation direction (and the stacking direction), the end portion of the upper ridge portion Ru on the side closer to the end face 1F has a concave shape.

[0112] Then, as described above, after forming the upper ridge Ru and the upper wing Gu, Fig.13 as well as Fig.14 As shown, a lower ridge Rd and a lower wing Gd are formed. In the present embodiment, wet etching is used in the process of forming the lower ridge Rd. Specifically, a mask is formed by photolithography technology in a manner that covers the upper ridge Ru and the upper wing Gu with a mask made of SiO2. Here, a mask is also formed in the region corresponding to the flat portion Rdf and the wing flat portion Gdf. Thereafter, a groove T is formed by etching the region in the P-type cladding layer 40 that is not covered by the mask until the first etching stop layer 43 using wet etching technology. Accordingly, a lower ridge Rd having a flat portion Rdf and a lower wing Gd having a wing flat portion Gdf can be formed. When wet etching is performed, the chemical solution used in etching and the composition of each semiconductor layer are determined in a manner that the etching speed of the first etching stop layer 43 is slower than that of the second cladding layer 44. Accordingly, etching is easily stopped at the first etching stop layer 43. That is, the controllability of the height of the lower ridge Rd and the lower wing Gd can be improved. In this embodiment, the second etching stop layer 45 , the second cladding layer 44 , and a portion of the first etching stop layer 43 are removed by wet etching. That is, the bottom surface Rdb of the lower ridge portion Rd and the bottom surface Gdb of the lower wing portion Gd are located in the first etching stop layer 43 .

[0113] As the chemical solution used for etching, for example, a solution containing sulfuric acid, hydrogen peroxide, and water can be used. The mixing ratio of sulfuric acid, hydrogen peroxide, and water is, for example, 1:1:6.

[0114] Through the above methods, Fig.13 as well as Fig.14 The lower ridge portion Rd and the lower wing portion Gd are formed as shown in FIG. In the present embodiment, the lower ridge portion Rd and the lower wing portion Gd are formed continuously from the end portion on the end surface 1F side of the P-type cladding layer 40 to the end portion on the end surface 1R side.

[0115] In addition, dry etching can also be used in the process of forming the lower ridge Rd. By using dry etching, the controllability of removing the film thickness by etching can be improved. Therefore, the individual differences in the effective refractive index difference ΔN between the inside and outside of the ridge R of the semiconductor light emitting element 1 and the diffusion angle of the emitted light can be reduced. Here, the effective refractive index difference refers to the difference between the effective refractive index n0 of the ridge R and the bottom of the ridge R for light and the effective refractive index n1 on the outside in the width direction of the ridge R. The outside in the width direction of the ridge R refers to the position of the maximum width of the ridge R (in the X-axis direction) further outside. In this embodiment, the maximum width of the ridge R is the width Wdb of the bottom surface Rdb of the lower ridge Rd. The effective refractive index refers to the value obtained by multiplying the distribution of light waveguided in the semiconductor light emitting element 1 (in this embodiment, the light distribution generated during laser oscillation) by the refractive index distribution of the semiconductor light emitting element 1. Dry etching can form the lower ridge Rd and the lower wing Gd having the above-mentioned shape by using (chemical) reactive etching, for example. As a gas for dry etching, SiCl4 can be used, for example. The inclination angle of the side surface Rds of the lower ridge Rd is changed according to the flow rate of SiCl4 during etching. For example, by setting the flow rate of SiCl4 to 10 sccm or more, the side surface Rds of the lower ridge Rd can be formed to have an inclination angle close to a vertical angle with respect to the main surface of the substrate 10.

[0116] Then as Fig.15 as well as Fig.16 As shown in FIG. 1 , a concave portion 3 is formed at the end of the semiconductor light emitting element 1 in the width direction. The concave portion 3 is a part of a separation groove used in singulation of the semiconductor light emitting element 1. Fig.13 as well as Fig.14 In the state shown, a plurality of semiconductor stacks are connected in the X-axis direction, and separation grooves are formed between adjacent semiconductor stacks, and the semiconductor stacks are separated along the separation grooves. Fig.15 as well as Fig.16 Recess 3 shown.

[0117] Then as Fig.17As shown in FIG. 1 , an insulating film 60 is formed on the ridge R. The insulating film 60 continuously covers the side surface Rds of the lower ridge Rd to a portion of the top surface Rut of the upper ridge Ru. Fig.15 as well as Fig.16 An insulating film 60 is formed on the entire upper surface of the semiconductor stack shown. In this embodiment, a silicon nitride film is formed as the insulating film 60 by using a CVD method or the like.

[0118] Then as Fig.19 As shown, an opening 60a is formed in a region corresponding to the top surface Rut of the upper ridge Ru in the insulating film 60. Specifically, a mask is formed in a region other than the region corresponding to the opening 60a of the insulating film 60. For example, the opening 60a is formed by etching the region corresponding to the opening 60a in the insulating film 60.

[0119] Then as Fig. 20 as well as Fig.21 As shown, a first P-side electrode 71 is formed. The first P-side electrode 71 is formed at least in the opening 60a of the insulating film 60. In the present embodiment, the first P-side electrode 71 continuously covers from the top surface Gut of one upper wing portion Gu to the top surface Gut of the other upper wing portion Gu. The first P-side electrode 71 is formed, for example, by photolithography and evaporation.

[0120] Then as Fig. 22 As shown, the pad electrode 73 is formed. The pad electrode 73 is formed at least above the opening 60a of the insulating film 60. In this embodiment, the pad electrode 73 is continuously covered from the top surface Gut of the upper wing portion Gu on one side to the top surface Gut of the upper wing portion Gu on the other side in the region on the first P-side electrode 71. The pad electrode 73 is formed by, for example, electroplating. Fig. 22 As shown, an eaves portion 73a may be provided at the end in the X-axis direction.

[0121] Then as Fig.23 as well as Fig.24 As shown, the second P-side electrode 72 is formed. The second P-side electrode 72 is formed in the area on the pad electrode 73, at least above the opening 60a of the insulating film 60. In the present embodiment, the second P-side electrode 72 covers the entire upper surface of the pad electrode 73. In addition, the second P-side electrode 72 covers at least a portion of the upper surface of the first P-side electrode 71 arranged at the edge of the pad electrode 73. The second P-side electrode 72 may not cover the area below the eaves 73a on the side of the pad electrode 73. The second P-side electrode 72 is formed, for example, by using photolithography technology and evaporation.

[0122] Then as Figure 2 as well as Figure 4As shown, an N-side electrode 80 is formed on the lower surface of the substrate 10 (the main surface of the substrate 10 on the back side of the main surface where each semiconductor layer is stacked). The N-side electrode 80 is formed at least at a position facing the opening 60a of the insulating film 60. The N-side electrode 80 is formed, for example, by using a photolithography technique and a vapor deposition method.

[0123] Through the above steps, the semiconductor light emitting element 1 according to the present embodiment can be formed.

[0124] [3. Effect]

[0125] The effects of the semiconductor light emitting element 1 according to the present embodiment will be described.

[0126] As described above, the semiconductor light emitting element 1 according to the present embodiment includes an upper ridge Ru and a lower ridge Rd. The top surface Rdt of the lower ridge Rd includes a flat portion Rdf extending in the light propagation direction between the side surface Rds of the lower ridge Rd and the bottom surface Rub of the upper ridge Ru. The width Wub of the bottom surface Rub of the upper ridge Ru is smaller than the width Wdt of the top surface Rdt of the lower ridge Rd and the width Wdc of the lower ridge Rd at the center position Rdc in the stacking direction.

[0127] In this way, the width Wub of the bottom surface Rub of the upper ridge Ru is smaller than the width Wdt of the top surface Rdt of the lower ridge Rd and the width Wdc at the central position Rdc in the stacking direction of the lower ridge Rd, so that the current injected from the top surface Rut of the upper ridge Ru will flow into the area of ​​the top surface Rdt of the lower ridge Rd that is closer to the inner side than the side surface Rds. Therefore, it is possible to suppress the current from flowing into the side surface Rds of the lower ridge Rd. Accordingly, the heat generated by the current flowing into the side surface Rds of the lower ridge Rd is suppressed, so that the high output of the semiconductor light emitting element 1 can be achieved. In addition, it is possible to reduce the failure caused by the heat of the semiconductor light emitting element 1.

[0128] Furthermore, since the lower ridge Rd has the flat portion Rdf, the adhesion between the insulating film 60 and the ridge R can be improved. Therefore, the insulation between the first P-side electrode 71 and the side surfaces of the ridge R (side surface Rds and side surface Rus) can be improved.

[0129] Furthermore, the P-type cladding layer 40 is made of Al X Ga 1-X As (0 < X ​​< 1) composition, the relationship X1 = X2 > 0.8 holds for the Al composition ratio X1 of the first cladding layer 42 and the Al composition ratio X2 of the second cladding layer 44, so that the average refractive index of the P-type cladding layer 40 can be reduced compared to the case where the Al composition ratios X1 and X2 are 0.8 or less. Fig.25 To explain. Fig.25: is a graph showing the relationship between the output power and the injection current of the semiconductor light emitting element 1 according to the present embodiment. Fig.25 The relationship when the temperature (Tc) of the measurement stage is 25°C and the Al composition ratio X1 and X2 is 0.85 is represented by a solid line. Fig.25 As a comparative example, the relationship between the output power and the injected current of the semiconductor light emitting element in which the Al composition ratios X1 and X2 are 0.75 is shown by a dotted line.

[0130] In the semiconductor light emitting element 1 according to the present embodiment, since the Al composition ratios X1 and X2 are greater than 0.8, the average refractive index of the P-type cladding layer 40 can be reduced. As a result, the average refractive index difference between the active layer 30 and the P-type cladding layer 40 can be increased, thereby improving the effect of confining light near the active layer 30. Fig.25 As shown, in the semiconductor light emitting element 1 according to the present embodiment, the maximum output power can be improved by about 3.5 W compared with the semiconductor light emitting element of the comparative example.

[0131] Furthermore, in the semiconductor light emitting element 1 according to the present embodiment, the Al composition ratio of the first etching stop layer 43 is less than 0.7. When the Al composition ratio X1 is greater than 0.8, as in the first cladding layer 42, it is easy to be oxidized, and it is easy to be corroded by the chemical solution used in etching, etc. However, by configuring the first etching stop layer 43 having an Al composition ratio of less than 0.7 on the first cladding layer 42, etching can be stopped at the first etching stop layer 43, so that exposure of the first cladding layer 42 can be suppressed. Accordingly, oxidation and corrosion of the first cladding layer 42 can be suppressed.

[0132] In this embodiment, the Al composition ratio of the flat portion Rdf of the lower ridge Rd is less than 0.7. That is, the flat portion Rdf is located in the second etching stop layer 45. Accordingly, etching can be stopped at the flat portion Rdf, so that the exposure of the second cladding layer 44 having an Al composition ratio X2 greater than 0.8 can be reduced. Therefore, oxidation and corrosion of the second cladding layer 44 can be suppressed.

[0133] In the present embodiment, the second etching stop layer 45 includes inclined regions 45b and 45d in which the Al composition ratio decreases as it approaches the contact layer 50. Accordingly, it is possible to suppress the rapid change of the composition in the stacking direction, thereby suppressing the energy barrier generated by the rapid change of the band gap. Therefore, since the resistance in the second etching stop layer 45 can be suppressed, the operating voltage of the semiconductor light emitting element 1 can be suppressed.

[0134] In the present embodiment, the second etching stop layer 45 includes one or more constant regions 45a and 45c whose Al composition ratio is constant relative to the stacking direction position. Accordingly, the performance of stopping etching in the second etching stop layer 45 can be improved. Furthermore, by alternately arranging two or more inclined regions 45b and 45d and one or more constant regions 45a and 45c in the stacking direction, the resistance in the second etching stop layer 45 can be suppressed and the performance of stopping etching can be improved.

[0135] In this embodiment, the width Wdt of the top surface Rdt of the lower ridge Rd, the width Wdc of the lower ridge Rd at the center position Rdc in the stacking direction, and the width Wdb of the bottom surface Rdb of the lower ridge Rd satisfy the relationship of Wdt>Wdc and Wdb>Wdc. Thus, the current can be narrowed in the lower ridge Rd.

[0136] In this embodiment, the width Wut of the top surface Rut of the upper ridge Ru is smaller than the width Wub of the bottom surface Rub of the upper ridge Ru. This can make the side surface Rus of the upper ridge Ru inclined, thereby improving the adhesion between the side surface Rus and the insulating film 60 .

[0137] In the present embodiment, the upper surface of the end portion of the ridge R in the light propagation direction, which is closer to the end face 1F from which light is emitted from the semiconductor light emitting element 1, is located at the second etching stop layer 45. The upper ridge Ru is not formed at the end portion of the ridge R which is closer to the end face 1F from which light is emitted. That is, the contact layer 50 is not formed at the end portion of the ridge R in the light propagation direction, which is closer to the end face 1F from which light is emitted from the semiconductor light emitting element 1. Accordingly, when the semiconductor light emitting element 1 is mounted on a mounting substrate or the like with the junction facing downward, it is possible to suppress the stress from being concentratedly applied to the end portion of the ridge R. Therefore, it is possible to suppress damage near the end face 1F of the semiconductor light emitting element 1.

[0138] In this embodiment, the active layer 30 includes a well layer 34, a P-side barrier layer 35 disposed above the well layer 34, a P-side guide layer 36 disposed above the P-side barrier layer 35, and a P-side cladding boundary layer 37. The remaining thickness dc defined by the sum of the thickness of the P-side guide layer 36 and the P-side cladding boundary layer 37, the thickness tpc0 of the lower cladding layer 41, the thickness tpc1 of the first cladding layer 42, and the thickness ts of the first etching stop layer 43 is greater than 0.5 μm. The effect of this configuration will be described by Fig.26 To explain. Fig.26 1 is a graph showing the relationship between the remaining thickness dc of the semiconductor light emitting element 1 according to the present embodiment and the horizontal diffusion angle of the emitted light. Here, the horizontal diffusion angle refers to the diffusion angle in the X-axis direction of each graph. Fig.26As shown, by making the remaining thickness dc larger than 0.5 μm, the horizontal diffusion angle of the emitted light can be suppressed. In addition, for example, in the case of a light-emitting module with a lens including a semiconductor light-emitting element 1 and a lens disposed near the end face 1F of the semiconductor light-emitting element 1, the horizontal diffusion angle of the emitted light can be suppressed, thereby improving the combination efficiency of the emitted light and the lens.

[0139] In this embodiment, the effective refractive index difference ΔN between the effective refractive index n0 for light at the ridge R and below the ridge R and the effective refractive index n1 outside the ridge R in the width direction is within 4×10 -4 The following will discuss the effect of the above-mentioned effective refractive index difference. Fig. 27 To explain. Fig. 27 : is a graph showing the relationship between the horizontal diffusion angle of the emitted light and the effective refractive index difference ΔN of the semiconductor light emitting element 1 according to the present embodiment. Fig. 27 As shown, by making the effective refractive index difference ΔN 4×10 -4 Therefore, when the above-mentioned light emitting module with a lens is constructed, the coupling efficiency between the emitted light and the lens can be improved by suppressing the horizontal diffusion angle of the emitted light.

[0140] In the present embodiment, the relationship of ts1≤tpc0<tpc1 holds true for the thickness tpc0 of the lower cladding layer 41, the thickness tpc1 of the first cladding layer 42, and the thickness ts1 of the first etching stop layer 43. In this way, by increasing the thickness of the lower cladding layer 41 having a higher refractive index than the first cladding layer 42, it is possible to suppress the leakage of light from the first cladding layer 42 to the first etching stop layer 43 having a higher refractive index than the first cladding layer 42. Furthermore, by reducing the thickness ts1 of the first etching stop layer 43 having a relatively large resistance, it is possible to suppress the operating voltage of the semiconductor light emitting element 1.

[0141] In this embodiment, the relationship of tng>tpg holds true for the thickness tng of the N-side guide layer 32 and the thickness tpg of the P-side guide layer 36. In this way, the peak position of the light intensity distribution can be closer to the N-side guide layer 32 than to the well layer 34. As a result, the waveguide loss in the semiconductor light emitting element 1 can be reduced, thereby improving the slope efficiency.

[0142] In this embodiment, the top surface Gdt of the lower wing Gd has a wing flat portion Gdf, which is a flat region located between the side surface Gds of the lower wing Gd and the bottom surface Gub of the upper wing Gu and extending in the propagation direction of light. This can improve the closeness between the wing G and the insulating film 60.

[0143] [4. Modification 1]

[0144] The semiconductor light emitting element involved in the modification example 1 of the present embodiment is described. The semiconductor light emitting element involved in the modification example is different from the semiconductor light emitting element 1 involved in the embodiment in the structure near the end in the propagation direction of light, and the other structures are the same. The semiconductor light emitting element involved in the modification example is described below, focusing on the differences from the semiconductor light emitting element 1 involved in the embodiment. Figure 28 to Figure 32 To explain. Fig.28 It is a plan view schematically showing the overall structure of a semiconductor light emitting element 1 a according to this modification. Figure 29 to Figure 32 Each of them is a cross-sectional view schematically showing the overall structure of the semiconductor light emitting element 1 a according to the present modification. Fig.29 , Fig.30 as well as Fig.31 They are shown respectively Fig.28 The cross section of the semiconductor light emitting element 1a at the line XXIX-XXIX, the line XXX-XXX, and the line XXXI-XXXI. Fig.32 Only Fig.28 The cross section of the semiconductor light emitting element 1 a taken along the line XXXII-XXXII includes a portion of the end face 1F.

[0145] like Fig.28 as well as Fig.32 As shown, the semiconductor light emitting element 1a according to the present modification is different from the semiconductor light emitting element 1 according to the embodiment in the structure near the end portion in the light propagation direction. Figure 28 to Figure 32 More specifically, the semiconductor light emitting element 1 a according to the present modification example is different from the semiconductor light emitting element 1 according to the embodiment in the structure between the ridge R and the end face 1F and the structure between the ridge R and the end face 1R.

[0146] like Fig.32 As shown, in the semiconductor light emitting element 1a involved in this modification, the region including the P-type cladding layer 40 and the contact layer 50 has an isolation region De disposed between the end face 1F in the light propagation direction of the semiconductor light emitting element 1a and the upper ridge Ru and separated from the upper ridge Ru. In other words, Fig.32 As shown, a groove portion Te is formed between the upper ridge portion Ru and the isolation region De. In this modification, the contact layer 50 and a portion of the P-type cladding layer 40 (a portion of the second etching stop layer 45) are removed in the groove portion Te.

[0147] In this variation, if Fig.28 as well as Fig.31As shown, the isolation region De is disposed between the two wing portions G. Furthermore, the isolation region De is connected to the two wing portions G. In other words, the upper surface of the contact layer 50 at the end portion of the semiconductor light emitting element 1a in the light propagation direction is flat and continuous in the entire width direction of the contact layer 50 (i.e., the X-axis direction).

[0148] Thus, in the end portion of the semiconductor light emitting element 1a according to the present modification in the light propagation direction, since the second cladding layer 44 having a high Al composition ratio is covered by the contact layer 50 and the second etching stop layer 45, it is possible to suppress oxidation and corrosion of the second cladding layer 44 having a high Al composition ratio. By suppressing oxidation and corrosion of the second cladding layer 44 having a high Al composition ratio, the closeness between the semiconductor stack including these layers and the insulating film 60 can be improved.

[0149] Furthermore, since the semiconductor light emitting element 1a is cleaved at the position corresponding to the end in the light propagation direction when being singulated, if the adhesion between the contact layer 50 and the insulating film 60 is low, the insulating film 60 may be peeled off. However, in the semiconductor light emitting element 1a involved in this modification, as described above, since the adhesion between the insulating film 60 and the contact layer 50 at the position corresponding to the end in the light propagation direction can be improved, the peeling of the insulating film 60 can be suppressed.

[0150] And if Fig.32 As shown, the distance D1 from the edge of the contact layer 50 in the light propagation direction to the edge of the pad electrode 73 in the light propagation direction is smaller than the distance D2 between the two ends of the isolation region De in the light propagation direction (i.e., the length of the isolation region De) and greater than zero. For example, the distance D1 is about 10 μm, and the distance D2 is greater than 20 μm and less than 150 μm. The smaller the distance D1 is, the better, as long as it is greater than the control accuracy of the cleavage position when the semiconductor light emitting element 1a is singulated.

[0151] [6. Modification 2]

[0152] The semiconductor light emitting element involved in the modification example 2 of the present embodiment is described. The semiconductor light emitting element involved in this modification example is different from the semiconductor light emitting element 1a involved in the modification example 1 in the structure of the isolation region De, and the other structures are the same. The semiconductor light emitting element involved in this modification example is described below, focusing on the differences from the semiconductor light emitting element 1a involved in the modification example 1. Figure 33 to Figure 36 To explain. Fig.33 It is a plan view schematically showing the overall structure of a semiconductor light emitting element 1 b according to this modification. Figure 34 to Figure 36 Each of them is a cross-sectional view schematically showing the overall structure of the semiconductor light emitting element 1b involved in this modification. Fig.34 , Fig.35as well as Fig.36 The Fig.33 Cross sections of the semiconductor light emitting element 1 b taken along lines XXXIV-XXXIV, XXXV-XXXV, and XXXVI-XXXVI.

[0153] like Fig.33 as well as Fig.36 As shown, the semiconductor light emitting element 1b according to this modification is different from the semiconductor light emitting element 1a according to the modification 1 in the structure of the isolation region De. Figure 34 to Figure 35 The other structures shown are the same.

[0154] In the semiconductor light emitting element 1b according to this modification, Fig.33 as well as Fig.36 As shown, the isolation region De is not connected to the wing G (upper wing Gu). That is, the contact layer 50 is not connected by the isolation region De and the wing G. Fig.33 As shown, the end of the isolation region De in the width direction is located at a position corresponding to the end of the upper ridge Ru in the width direction. In other words, the position of the end of the isolation region De in the width direction in the X-axis direction is equal to the position of the end of the upper ridge Ru in the width direction in the X-axis direction. Here, the state represented by the record that these positions are equal is not limited to the state that these positions are completely equal, but also includes a state that they are substantially equal. The state represented by the record that these positions are equal also includes, for example, a state where the difference between these positions is less than 10% of the width of the ridge R.

[0155] In this modification, as in the modification 1, since the pad electrode 73 is not formed at the end of the semiconductor light emitting element 1b in the light propagation direction, at least a portion of the isolation region De is not covered by the pad electrode 73. Therefore, the position of the end of the isolation region De in the width direction can be confirmed based on the appearance of the semiconductor light emitting element 1b. In addition, in this modification, since the position of the isolation region De in the width direction corresponds to the position of the ridge R in the width direction, the position of the waveguide can be confirmed based on the position of the end of the isolation region De in the width direction, that is, the position of the emitted light on the end face 1F (the position in the X-axis direction) can be confirmed based on the appearance of the semiconductor light emitting element 1b.

[0156] As described above, in the semiconductor light emitting element 1b involved in this modification, although the contact layer 50 is separated by the isolation region De and the wing portion G, the second etching stop layer 45 of the P-type cladding layer 40 and the second cladding layer 44 are not separated. In other words, the upper surface of the second cladding layer 44 at the end portion of the semiconductor light emitting element 1b in the light propagation direction is flat and continuous in the entire width direction of the second cladding layer 44, and is covered by the second etching stop layer 45.

[0157] According to this, since the second etching stop layer 45 covers the second cladding layer 44 and the like having a high Al composition ratio, it is possible to suppress oxidation and corrosion of the second cladding layer 44 and the like. By suppressing oxidation and corrosion of the second cladding layer 44 having a high Al composition ratio, it is possible to improve the closeness between the semiconductor stack including these layers and the insulating film 60. According to this, similarly to the semiconductor light emitting element 1a involved in Modification 1, it is possible to suppress peeling of the insulating film 60 during cleavage.

[0158] (Other modifications, etc.)

[0159] As mentioned above, the semiconductor light emitting element involved in this disclosure has been described based on embodiment and modification example, but this disclosure is not limited to the above-mentioned embodiment and modification example.

[0160] For example, in the above-mentioned embodiment, the semiconductor light emitting element 1 is an example of a semiconductor laser element, but the semiconductor light emitting element 1 is not limited to a semiconductor laser element. For example, the semiconductor light emitting element may be a superluminescent diode.

[0161] Furthermore, in the above-mentioned embodiment, the semiconductor light emitting element 1 has two wing portions G. However, the semiconductor light emitting element 1 may have only one wing portion G.

[0162] Furthermore, in the above-mentioned embodiment, the active layer 30 of the semiconductor light emitting element 1 has a single quantum well structure, but may also have a multi-quantum well structure.

[0163] Furthermore, in the above-described embodiment, the active layer 30 of the semiconductor light emitting element 1 has the window region 30 w near the end face 1F and the end face 1R. However, the semiconductor light emitting element 1 may not have the window region 30 w.

[0164] Furthermore, in the above-described embodiment, although the inclined regions 45 b and 45 d of the second etching stop layer 45 are regions where the Al composition ratio decreases as they approach the contact layer 50 , they may be regions where the Al composition ratio increases as they approach the contact layer 50 .

[0165] Furthermore, the scope of the present disclosure includes forms obtained by performing various modifications that can be thought of by those skilled in the art on the above-mentioned embodiments and modified examples, as well as forms achieved by arbitrarily combining the constituent elements and functions in the above-mentioned embodiments and modified examples without departing from the main purpose of the present disclosure.

[0166] Industrial Applicability

[0167] The semiconductor light emitting element and the like disclosed in the present invention can be used as a light source for laser processing, for example, as a high-output and high-efficiency light source.

[0168] Description of Reference Numerals

[0169] 1.1a, 1b Semiconductor light emitting element

[0170] 1F, 1R end face

[0171] 2F, 2R reflective film

[0172] 3 concave parts

[0173] 3w shrink neck

[0174] 10 substrate

[0175] 20N type coating

[0176] 30 active layers

[0177] 30w window area

[0178] 31N side cladding boundary layer

[0179] 32N side guide layer

[0180] 33N-side barrier layer

[0181] 34-well layer

[0182] 35P side barrier layer

[0183] 36P side guide layer

[0184] 37P side cladding boundary layer

[0185] 40P type coating

[0186] 41 Lower cladding

[0187] 42 first coating layer

[0188] 43 first etching stop layer

[0189] 44 Second coating layer

[0190] 45 second etching stop layer

[0191] 45a, 45c constant region

[0192] 45b, 45d inclined area

[0193] 50 contact layers

[0194] 60 Insulation Film

[0195] 60a opening

[0196] 71 first P-side electrode

[0197] 72 second P-side electrode

[0198] 73 pad electrode

[0199] 73a Eaves

[0200] 80N side electrode

[0201] Isolation area

[0202] G Wing

[0203] Gd lower wing

[0204] Gdb, Gub, Rdb, Rub bottom surface

[0205] Gdf wing flat part

[0206] Gds, Gus, Rds, Rus side

[0207] Gdt, Gut, Rdt, Rut top surface

[0208] Gu upper wing

[0209] R-Spine

[0210] Rd Lower Ridge

[0211] Rdc Center position in stacking direction

[0212] Rdf flat part

[0213] Ru upper ridge

[0214] T, Te groove

[0215] Tb bottom

Claims

1. A semiconductor light emitting element, which is a semiconductor light emitting element that emits light, The semiconductor light emitting element comprises: substrate; An N-type cladding layer disposed above the substrate; an active layer disposed above the N-type cladding layer; A P-type cladding layer disposed above the active layer; A contact layer disposed above the P-type cladding layer; as well as an insulating film disposed above the P-type cladding layer, A ridge extending in the propagation direction of the light is formed in a region including the P-type cladding layer and the contact layer. The ridge portion includes a lower ridge portion and an upper ridge portion, the lower ridge portion includes the P-type cladding layer, and the upper ridge portion is configured on the top surface of the lower ridge portion and includes the contact layer. The top surface of the lower ridge has a flat portion located between the side surface of the lower ridge and the bottom surface of the upper ridge, and the flat portion extends in the propagation direction of the light. The width of the bottom surface of the upper ridge is smaller than the width of the top surface of the lower ridge and the width of the lower ridge at the center position in the stacking direction. The insulating film continuously covers from the side surface of the lower ridge portion to a portion of the top surface of the upper ridge portion.

2. A semiconductor light emitting element, which is a semiconductor light emitting element that emits light, The semiconductor light emitting element comprises: substrate; An N-type cladding layer disposed above the substrate; an active layer disposed above the N-type cladding layer; a P-type cladding layer disposed above the active layer; and a contact layer disposed above the P-type cladding layer, A ridge extending in the propagation direction of the light is formed in a region including the P-type cladding layer and the contact layer. The ridge portion includes a lower ridge portion and an upper ridge portion, the lower ridge portion includes the P-type cladding layer, and the upper ridge portion is configured on the top surface of the lower ridge portion and includes the contact layer. The P-type cladding layer is made of Al X Ga 1-X As, wherein 0<X<1, and the P-type cladding layer comprises: a lower cladding layer, a first cladding layer arranged above the lower cladding layer, a first etch stop layer arranged above the first cladding layer, a second cladding layer arranged above the first etch stop layer, and a second etch stop layer arranged above the second cladding layer, Regarding the Al composition ratio X0 of the lower cladding layer, the Al composition ratio X1 of the first cladding layer, and the Al composition ratio X2 of the second cladding layer, The relations X1=X2>0.8 and X1=X2>X0 hold.

3. The semiconductor light emitting element according to claim 2, The Al composition ratio of the first etching stop layer is less than 0.

7.

4. The semiconductor light emitting element according to claim 2 or 3, The top surface of the lower ridge has a flat portion located between the side surface of the lower ridge and the bottom surface of the upper ridge, and the flat portion extends in the propagation direction of the light. The upper ridge includes at least a portion of the second etch stop layer and at least a portion of the contact layer, The Al composition ratio of the flat portion of the lower ridge portion is 0.7 or less.

5. The semiconductor light emitting element according to any one of claims 2 to 4, The second etch stop layer includes an inclined region in which an Al composition ratio increases or decreases as approaching the contact layer.

6. The semiconductor light emitting element according to any one of claims 2 to 4, The second etching stop layer includes two or more inclined regions and one or more constant regions where the Al composition ratio is constant relative to the stacking direction position. In each of the two or more inclined regions, the Al composition ratio increases or decreases as approaching the contact layer, The two or more inclined regions and the one or more constant regions are alternately arranged in the stacking direction.

7. The semiconductor light emitting element according to claim 5 or 6, The inclined region is a region where the Al composition ratio decreases as approaching the contact layer.

8. The semiconductor light emitting element according to any one of claims 2 to 7, The width of the top surface of the lower ridge is equal to the width of the lower ridge at the center position in the stacking direction. With respect to the bottom surface of the lower ridge portion, an upper surface of the P-type cladding layer at an adjacent position in the width direction of the lower ridge portion is located on the first etching stop layer.

9. The semiconductor light emitting element according to any one of claims 2 to 7, Regarding the width Wdt of the top surface of the lower ridge, the width Wdc of the lower ridge at the center position in the stacking direction, and the width Wdb of the bottom surface of the lower ridge, The relationship of Wdt>Wdc and Wdb>Wdc holds. With respect to the bottom surface of the lower ridge portion, an upper surface of the P-type cladding layer at an adjacent position in the width direction of the lower ridge portion is located on the first etching stop layer.

10. The semiconductor light emitting element according to any one of claims 2 to 9, The active layer includes a well layer, a P-side barrier layer disposed above the well layer, a P-side guide layer disposed above the P-side barrier layer, and a P-side cladding boundary layer disposed above the P-side guide layer. The remaining thickness dc is greater than 0.5 μm and is defined by the sum of the total thickness of the P-side guide layer and the P-side cladding boundary layer, the thickness tpc0 of the lower cladding layer, the thickness tpc1 of the first cladding layer, and the thickness ts of the first etching stop layer.

11. The semiconductor light emitting element according to any one of claims 2 to 10, Regarding the thickness tpc0 of the lower cladding layer, the thickness tpc1 of the first cladding layer, and the thickness ts1 of the first etching stop layer, The relationship of ts1≤tpc0<tpc1 holds.

12. The semiconductor light emitting element according to any one of claims 2 to 11, An upper surface of an end portion of the ridge portion in the light propagation direction, which is closer to an end face of the semiconductor light emitting element from which the light is emitted, is located in the second etching stopper layer.

13. The semiconductor light emitting element according to any one of claims 2 to 12, The upper surface of the second cladding layer at the end of the semiconductor light emitting element in the propagation direction of the light is flat and continuous over the entire width direction of the second cladding layer and is covered by the second etching stop layer, The region including the P-type cladding layer and the contact layer has an isolation region, which is arranged between the end face of the semiconductor light emitting element in the propagation direction of the light and the upper ridge and is separated from the upper ridge. An end portion of the isolation region in the width direction is located at a position corresponding to an end portion of the upper ridge portion in the width direction.

14. The semiconductor light emitting element according to any one of claims 1 to 13, The width of the top surface of the upper ridge is smaller than the width of the bottom surface of the upper ridge.

15. The semiconductor light emitting element according to any one of claims 1 to 14, The difference between the effective refractive index n0 of the ridge and the lower part of the ridge for the light and the effective refractive index n1 of the outer side in the width direction of the ridge is 4×10 -4 the following.

16. The semiconductor light emitting element according to any one of claims 1 to 9 and 11 to 15, The active layer includes an N-side guide layer, an N-side barrier layer disposed above the N-side guide layer, a P-side barrier layer disposed above the N-side barrier layer, and a P-side guide layer disposed above the P-side barrier layer. Regarding the thickness tng of the N-side guide layer and the thickness tpg of the P-side guide layer, The relationship of tng>tpg holds.

17. The semiconductor light emitting element according to any one of claims 1 to 16, A wing portion extending along the ridge portion is formed in a region including the P-type cladding layer and the contact layer. The wing portion includes a lower wing portion and an upper wing portion, the lower wing portion includes the P-type cladding layer, and the upper wing portion is arranged on the top surface of the lower wing portion and includes the contact layer. The top surface of the lower wing portion has a wing flat portion, which is a flat region located between the side surface of the lower wing portion and the bottom surface of the upper wing portion and extending in the propagation direction of the light.

18. The semiconductor light emitting element according to claim 17, A concave portion recessed in the width direction of the semiconductor light emitting element is formed at an end portion in the width direction of the semiconductor light emitting element. The side surface of the lower wing portion which is far from the ridge portion is in the recessed portion, The side surface of the lower wing portion which is far from the ridge portion has a constricted portion, and the constricted portion is located further inward in the width direction of the semiconductor light emitting element than the upper end of the lower wing portion. The position of the recess in the width direction of the semiconductor light emitting element is located at the innermost side in the width direction of the P-type cladding layer and approaches the outer side in the width direction of the semiconductor light emitting element as it approaches the substrate from the active layer.

19. The semiconductor light emitting element according to any one of claims 1 to 18, In a cross section of the upper ridge portion in a direction parallel to the propagation direction of the light, an end portion of the upper ridge portion on a side closer to an end face of the semiconductor light emitting element from which the light is emitted has a concave shape.

20. The semiconductor light emitting element according to any one of claims 1 to 19, An upper surface of the contact layer at an end portion of the semiconductor light emitting element in a propagation direction of the light is flat and continuous over the entire width direction of the contact layer.

21. A method for manufacturing a semiconductor light emitting element, the method comprising: The manufacturing method comprises the following steps: The step of forming an N-type cladding layer on the substrate; A step of forming an active layer on the N-type cladding layer; A step of forming a P-type cladding layer above the active layer; A step of forming a contact layer on the P-type cladding layer; A step of forming a ridge portion in a region including the P-type cladding layer and the contact layer; and a step of forming an insulating film on the ridge portion, The ridge portion includes a lower ridge portion and an upper ridge portion, the lower ridge portion includes the P-type cladding layer, and the upper ridge portion is configured on the top surface of the lower ridge portion and includes the contact layer. The process of forming the ridge portion includes: forming the upper ridge; as well as The step of forming the lower ridge is followed by the step of forming the upper ridge. The top surface of the lower ridge has a flat portion, the flat portion is located between the side surface of the lower ridge and the bottom surface of the upper ridge and extends in the propagation direction of the light, The width of the bottom surface of the upper ridge is smaller than the width of the top surface of the lower ridge and the width of the lower ridge at the center position in the stacking direction. The insulating film continuously covers from the side surface of the lower ridge portion to a portion of the top surface of the upper ridge portion.

22. The method for manufacturing a semiconductor light emitting element according to claim 21, Wet etching is used in the process of forming the upper ridge portion.

23. The method for manufacturing a semiconductor light emitting element according to claim 21 or 22, Dry etching is used in the process of forming the lower ridge portion.

24. The method for manufacturing a semiconductor light emitting element according to claim 21 or 22, Wet etching is used in the process of forming the lower ridge portion.

Images