MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device based on NiO gate modulation and preparation method thereof

Abstract

The invention relates to an MOSFET device based on NiO gate modulation and a preparation method thereof. The device comprises a substrate layer, a first N-type GaN layer, a second N-type GaN layer, a P-type GaN layer and a third N-type GaN layer which are sequentially arranged from bottom to top. The gate step extends into the second N-type GaN layer from the two ends of the upper surface of the third N-type GaN layer; the gate structure extends from the upper surface of the third N-type GaN layer to the bottom of the gate step; a source recess; a source electrode; a drain electrode; and the NiO modulation layer extends from the bottom of the gate step to the upper surface of the first N-type GaN layer. The interface state of the second N-type GaN layer and electrons on the surface of the second N-type GaN layer are depleted through the NiO modulation layer, a depletion region is generated, the electric field distribution range of the device is widened, the peak electric field intensity of the device is reduced, and the voltage withstanding level of the device is improved.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors, and in particular relates to a MOSFET device based on NiO gate modulation and a preparation method thereof. Background Art

[0002] Compared with Si-based materials, GaN has excellent electrical properties such as large bandgap, high critical breakdown electric field, high saturation velocity, and good thermal conductivity, which makes the prepared devices have higher breakdown voltage, and under the same voltage resistance requirements, GaN-based devices have lower on-resistance, thus having great potential in the field of high-voltage and high-power power electronics. For GaN planar devices used in high-voltage environments, in order to increase the breakdown voltage of the device, the source-drain distance and the gate-drain distance must be increased so that the device has a larger voltage resistance space when blocked, but this method increases the size of the device, resulting in reduced wafer utilization and increased cost of a single device.

[0003] GaN trench-gate metal-oxide-semiconductor field-effect transistor (MOSFET) uses a vertical drift layer to block the withstand voltage. Therefore, when the breakdown voltage of the device is increased, there is no need to increase the size of the device. It only needs to increase the thickness of the drift region of the device, which can effectively reduce the cost of a single device and improve the overall wafer utilization.

[0004] However, there is electric field concentration at the bottom corner of the trench of GaN trench gate MOSFET, which affects the voltage resistance performance of the device. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a MOSFET device based on NiO gate modulation and a preparation method thereof. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0006] The present invention provides a MOSFET device based on NiO gate modulation and a preparation method thereof, comprising:

[0007] A substrate layer, a first N-type GaN layer, a second N-type GaN layer, a P-type GaN layer and a third N-type GaN layer are sequentially arranged from bottom to top;

[0008] A gate step extending from two ends of the upper surface of the third N-type GaN layer to the interior of the second N-type GaN layer;

[0009] A gate structure extending from the upper surface of the third N-type GaN layer to the bottom of the gate step;

[0010] A source groove extending from the upper surface of the third N-type GaN layer to the lower surface of the third N-type GaN layer;

[0011] A source electrode, located in the source groove;

[0012] a drain electrode, located on an upper surface of the first N-type GaN layer on both sides of the second N-type GaN layer, and a gap exists between the drain electrode and the second N-type GaN layer;

[0013] The NiO modulation layer extends from the bottom of the gate step to the upper surface of the first N-type GaN layer.

[0014] In one achievable manner, the source electrode extends from the source groove to the upper surface of the third N-type GaN layer, and there is a gap between the source electrode and the gate structure.

[0015] In one achievable manner, the gate structure includes: a gate dielectric layer and a gate electrode, wherein:

[0016] The gate dielectric layer extends from the upper surface of the third N-type GaN layer to the bottom of the gate step;

[0017] The gate electrode is located on the surface of the gate dielectric layer.

[0018] In an achievable manner, the material of the substrate layer includes one or more of Si, SiC, and sapphire;

[0019] The material of the gate dielectric layer includes Al2O3;

[0020] The material of the gate electrode includes Ni / Au;

[0021] The material of the source electrode includes Ti / Al / Ni / Au;

[0022] The material of the drain electrode includes Ti / Al / Ni / Au.

[0023] In an achievable manner, the length of the gate structure located at the bottom of the gate step is 0.1-6 μm.

[0024] In an achievable manner, the length of the NiO modulation layer located at the bottom of the gate step is 2 to 8 μm;

[0025] The length of the NiO modulation layer located on the upper surface of the first N-type GaN layer is 5 to 8 μm.

[0026] The distance between the drain electrode and the second N-type GaN layer is 7-10 μm.

[0027] In an achievable manner, the doping concentration of the first N-type GaN layer is 1.0×10 19 ~1×10 20 cm -3 , thickness is 1 to 2 μm;

[0028] The doping concentration of the second N-type GaN layer is 1.0×10 15 ~2×10 16 cm -3 , thickness is 3-5 μm;

[0029] The doping concentration of the P-type GaN layer is 1.0×10 17 ~1×10 18 cm -3 , thickness is 200~350nm;

[0030] The doping concentration of the third N-type GaN layer is 1.0×10 19 ~1×10 20 cm -3 , with a thickness of 200 to 300 nm.

[0031] In an achievable manner, the doping type of the NiO modulation layer is P-type, and the doping concentration is 1.0×10 15 ~1×10 18 cm -3 , thickness is 100~200nm.

[0032] A second aspect of the present invention provides a method for preparing a MOSFET device based on NiO gate modulation, comprising the following steps:

[0033] S1: obtaining a substrate layer, a first N-type GaN layer, a second N-type GaN layer, a P-type GaN layer and a third N-type GaN layer arranged in sequence from bottom to top;

[0034] S2: etching at both ends of the third N-type GaN layer to form gate steps extending from both ends of the upper surface of the third N-type GaN layer to the inside of the second N-type GaN layer;

[0035] S3: preparing a gate structure on the upper surface of the third N-type GaN layer, the sidewall of the gate step and the bottom of the gate step;

[0036] S4: etching the upper surface of the third N-type GaN layer to form a source groove extending from the upper surface of the third N-type GaN layer to the lower surface of the third N-type GaN layer;

[0037] S5: preparing a source electrode in the source groove, and preparing a drain electrode on the upper surface of the first N-type GaN layer on both sides of the second N-type GaN layer; there is a gap between the drain electrode and the second N-type GaN layer;

[0038] S6: Preparing a NiO modulation layer at the bottom of the gate step, the side surface of the second N-type GaN layer, and the upper surface of the first N-type GaN layer.

[0039] In one achievable manner, the specific steps of step S6 include:

[0040] A magnetron sputtering process is used to sputter P-type NiO with a thickness of 100 to 200 nm at the bottom of the gate step, the side surface of the second N-type GaN layer and the upper surface of the first N-type GaN layer to obtain a NiO modulation layer; wherein the target material of the magnetron sputtering process is nickel oxide, and the working gas is O2 and Ar.

[0041] Compared with the prior art, the present invention has the following beneficial effects:

[0042] The MOSFET device based on NiO gate modulation of the present invention depletes the interface state of the second N-type GaN layer and the electrons on the surface of the second N-type GaN layer through the NiO modulation layer to generate a depletion region, broaden the electric field distribution range of the device, reduce the peak electric field strength of the device, and improve the withstand voltage level of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 It is a structural schematic diagram of a MOSFET device based on NiO gate modulation provided by an embodiment of the present invention;

[0044] Figure 2a to Figure 2i It is a schematic diagram of the steps of a method for preparing a MOSFET device based on NiO gate modulation provided by an embodiment of the present invention.

[0045] Reference numerals:

[0046] 1: substrate layer; 2: first N-type GaN layer; 3: second N-type GaN layer; 4: P-type GaN layer; 5: third N-type GaN layer; 6: gate dielectric layer; 7: gate electrode; 8: source electrode; 9: drain electrode; 10: NiO modulation layer. DETAILED DESCRIPTION

[0047] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0048] Embodiment 1

[0049] See also Figure 1 , Figure 1It is a schematic structural diagram of a MOSFET device based on NiO gate modulation provided by an embodiment of the present invention.

[0050] The present embodiment provides a MOSFET device based on NiO gate modulation, comprising: a substrate layer 1, a first N-type GaN layer 2, a second N-type GaN layer 3, a P-type GaN layer 4, a third N-type GaN layer 5, a gate step, a gate structure, a source groove, a source electrode 8, a drain electrode 9 and a NiO modulation layer 10. Among them, the substrate layer 1, the first N-type GaN layer 2, the second N-type GaN layer 3, the P-type GaN layer 4 and the third N-type GaN layer 5 are arranged in sequence from bottom to top. The gate step extends from both ends of the upper surface of the third N-type GaN layer 5 to the inside of the second N-type GaN layer 3. The gate structure extends from the upper surface of the third N-type GaN layer 5 to the bottom of the gate step. The source groove extends from the upper surface of the third N-type GaN layer 5 to the lower surface of the third N-type GaN layer 5. The source electrode 8 is located in the source groove. The drain electrode 9 is located on the upper surface of the first N-type GaN layer 2 on both sides of the second N-type GaN layer 3, and there is a gap between the drain electrode 9 and the second N-type GaN layer 3. The NiO modulation layer 10 extends from the bottom of the gate step to the upper surface of the first N-type GaN layer 2 .

[0051] Specifically, the gate structure extends from the upper surface of the third N-type GaN layer 5, through the side wall of the gate step to the bottom of the gate step. The depth of the gate step is greater than or equal to the sum of the thicknesses of the P-type GaN layer 4 and the third N-type GaN layer 5. It should be understood that the side wall of the gate step is the side surface of the third N-type GaN layer 5 and the side surface of the P-type GaN layer 4, and the bottom of the gate step is the upper surface of the third N-type GaN layer 5. The NiO modulation layer 10 extends from the bottom of the gate step through the side surface of the second N-type GaN layer 3 to the upper surface of the first N-type GaN layer 2. The gate structure is located at one end of the gate step close to the third N-type GaN layer 5, and the NiO modulation layer 10 extends from one end of the gate step away from the third N-type GaN layer 5 to the upper surface of the first N-type GaN layer 2 between the drain electrode 9 and the second N-type GaN layer 3. The device provided in this embodiment is an axisymmetric layout, the axis of symmetry is the central axis of the device, that is, the central axis of the substrate layer 1, the first N-type GaN layer 2, the second N-type GaN layer 3, the P-type GaN layer 4, and the third N-type GaN layer 5, the source electrode 8 is located in the middle of the top of the device, and the two gate steps are symmetrically arranged on the left and right sides of the device. Correspondingly, there are two gate structures, drain electrodes 9 and NiO modulation layers 10, and they are symmetrically arranged on the left and right sides of the device. In this embodiment, a PN junction is formed between the NiO modulation layer 10 and the second N-type GaN layer 3, and the interface state of the second N-type GaN layer 3 and the electrons near the surface of the second N-type GaN layer 3 are depleted, and a depletion region is generated, so that the electric field distribution is widened from the gate structure of the device to both sides of the device, so that the electric field peak at the gate structure is reduced, and the electric field crowding phenomenon near the gate structure is alleviated, and premature breakdown is prevented, and the withstand voltage level of the device is improved.

[0052] In this embodiment, the source electrode 8 extends from the source groove to the upper surface of the third N-type GaN layer 5, and there is a gap between the source electrode 8 and the gate structure. The length of the gate structure at the bottom of the gate step is 0.1 to 6 μm. The length of the NiO modulation layer 10 at the bottom of the gate step is 2 to 8 μm. The length of the NiO modulation layer 10 located on the upper surface of the first N-type GaN layer 2 is 5 to 8 μm. The distance between the drain electrode 9 and the second N-type GaN layer 3 is 7 to 10 μm.

[0053] Specifically, the length of the gate step is 2 to 10 μm, and the distance between the NiO modulation layer 10 on the gate step and the gate structure is 0 to 2 μm. It should be understood that the device provided in this embodiment is an axisymmetric layout with two gate steps. Correspondingly, there are two gate structures, NiO modulation layers 10 and drain electrodes 9. In this embodiment, the length is the length of a single structure, and the distance is the distance between two structures on a single side of the device. For example, in this embodiment, the length of each gate step is 2 to 10 μm, the total length of the gate steps on the left and right sides of the device is 4 to 20 μm, the length of the NiO modulation layer 10 at the bottom of the gate steps on the left and right sides of the device is 2 to 8 μm, and the length of the NiO modulation layer 10 at the bottom of the gate steps on the left and right sides of the device is 4 to 16 μm in total. The distance between the drain electrode 9 on the left side of the device and the left side wall of the second N-type GaN layer 3 is 7 to 10 μm, and the distance between the drain electrode 9 on the right side of the device and the right side wall of the second N-type GaN layer 3 is 7 to 10 μm.

[0054] In this embodiment, the gate structure includes: a gate dielectric layer 6 and a gate electrode 7 , wherein the gate dielectric layer 6 extends from the upper surface of the third N-type GaN layer 5 to the bottom of the gate step. The gate electrode 7 is located on the surface of the gate dielectric layer 6 .

[0055] In this embodiment, the material of the substrate layer 1 includes one or more of Si, SiC, and sapphire. The doping concentration of the first N-type GaN layer 2 is 1.0×10 19 ~1×10 20 cm -3 , with a thickness of 1 to 2 μm. The doping concentration of the second N-type GaN layer 3 is 1.0×10 15 ~2×10 16 cm -3 , with a thickness of 3 to 5 μm. The doping concentration of the P-type GaN layer 4 is 1.0×10 17 ~1×10 18 cm -3 The thickness is 200-350 nm. The doping concentration of the third N-type GaN layer 5 is 1.0×10 19 ~1×10 20 cm -3 , with a thickness of 200 to 300 nm. The material of the gate dielectric layer 6 includes Al2O3. The material of the gate electrode 7 includes Ni / Au. The material of the source electrode 8 includes Ti / Al / Ni / Au. The material of the drain electrode 9 includes Ti / Al / Ni / Au. The doping type of the NiO modulation layer 10 is P type, and the doping concentration is 1.0×10 15 ~1×10 18 cm -3The thickness is 100-200 nm. The doping ions of the first N-type GaN layer 2, the second N-type GaN layer 3 and the third N-type GaN layer 5 are all Si ions, and the doping ions of the P-type GaN layer 4 are Mg ions.

[0056] Specifically, Ni / Au is Ni and Au stacked from bottom to top, wherein the thickness of Ni is 30-50nm, and the thickness of Au is 300-450nm. Ti / Al / Ni / Au is Ti, Al, Ni, and Au stacked from bottom to top, wherein the thickness of Ti is 20-30nm, the thickness of Al is 140-180nm, the thickness of Ni is 40-60nm, and the thickness of Au is 30-50nm.

[0057] In this embodiment, the MOSFET device further includes a device isolation region, which is located on both sides of the first N-type GaN layer 2 and has a depth of 1-2 μm.

[0058] The MOSFET device provided in this embodiment has two PN junctions, the third N-type GaN layer 5 and the P-type GaN layer 4 form a J1 junction, and the P-type GaN layer 4 and the second N-type GaN layer 3 form a J2 junction. When no bias voltage is applied to the gate electrode 7, the source electrode 8, and the drain electrode 9 of the device, that is, when the gate voltage Vgate, the source voltage Vsource, and the drain voltage Vdrain are all 0, the N-type inversion channel inside the MOSFET is not turned on, the J1 junction and the J2 junction are both in a zero bias state, and no current is generated inside the device.

[0059] When no bias voltage is applied to the source electrode 8 and the gate electrode 7 of the device, and a forward voltage is applied to the drain electrode 9 (Vdrain>0, Vsource=0, Vgate=0), the J2 junction formed by the P-type GaN layer 4 and the second N-type GaN layer 3 is in a reverse bias state. The second N-type GaN layer 3 as the drift region of the device has a low doping concentration, and the P-type GaN layer 4 has a high doping concentration. Therefore, the depletion layer of the J2 junction when reverse biased mainly extends to the low-doped second N-type GaN layer 3. Therefore, the breakdown voltage of the MOSFET depends largely on the structural parameters of the second N-type GaN layer 3, such as the thickness and doping concentration of the drift region. In this embodiment, the doping concentration of the second N-type GaN layer 3 is set to 1.0×10 15 ~2×10 16 cm -3 , with a thickness of 3 to 5 μm, which can ensure that the device has a high breakdown voltage in this state.

[0060] When the source electrode 8 of the device does not apply a bias voltage, and the gate electrode 7 and the drain electrode 9 apply a forward voltage (Vdrain>0, Vsource=0, Vth>Vgate>0), where Vth is the threshold voltage when the device is turned on, when Vgate is greater than 0 but less than Vth, the holes on the surface of the P-type GaN layer 4 are transferred to the inside under the drive of the gate voltage, and some negatively charged acceptor Mg ions appear on the channel surface. At this time, the conduction channel between the source and the drain is still closed, and the device is in a blocking state. As Vgate continues to increase, when Vgate is greater than Vth (Vdrain>0, Vsource=0, Vgate>Vth), as the surface energy band of the P-type GaN layer 4 bends downward, a large number of minority carriers (electrons) appear on the side surface of the P-type GaN layer 4, forming an accumulation layer of electrons, that is, a strong inversion state appears. At this time, the part of the P-type GaN layer 4 close to the gate is equivalent to the N-type, thereby forming a current path between the third N-type GaN layer 5 and the second N-type GaN layer 3. Therefore, under the action of the forward biased drain electrode 9, electrons enter the inversion channel from the third N-type GaN layer 5, and then flow into the second N-type GaN layer 3 below in a direction perpendicular to the substrate layer 1, and are finally collected by the drain electrode 9, forming an output current between the source and the drain.

[0061] The MOSFET device based on NiO gate modulation provided in this embodiment depletes the interface state of the second N-type GaN layer 3 and the electrons on the surface of the second N-type GaN layer 3 through the NiO modulation layer 10, thereby generating a depletion region, widening the electric field distribution range of the device, reducing the peak electric field strength of the device, and improving the withstand voltage level of the device.

[0062] Embodiment 2

[0063] See also Figure 2a to Figure 2i , Figure 2a to Figure 2i It is a schematic diagram of the steps of a method for preparing a MOSFET device based on NiO gate modulation provided by an embodiment of the present invention.

[0064] The present embodiment provides a method for preparing a MOSFET device based on NiO gate modulation, comprising the following steps:

[0065] S1: Obtain a substrate layer 1, a first N-type GaN layer 2, a second N-type GaN layer 3, a P-type GaN layer 4 and a third N-type GaN layer 5 arranged in sequence from bottom to top.

[0066] Specifically, Figure 2a As shown, the material of the substrate layer 1 includes one or more of Si, SiC, and sapphire. The doping concentration of the first N-type GaN layer 2 is 1.0×10 19 ~1×10 20 cm -3, with a thickness of 1 to 2 μm. The doping concentration of the second N-type GaN layer 3 is 1.0×10 15 ~2×10 16 cm -3 , with a thickness of 3 to 5 μm. The doping concentration of the P-type GaN layer 4 is 1.0×10 17 ~1×10 18 cm -3 The thickness is 200-350 nm. The doping concentration of the third N-type GaN layer 5 is 1.0×10 19 ~1×10 20 cm -3 , with a thickness of 200 to 300 nm.

[0067] S2 : etching at both ends of the third N-type GaN layer 5 to form gate steps extending from both ends of the upper surface of the third N-type GaN layer 5 to the inside of the second N-type GaN layer 3 .

[0068] Specifically, Figure 2b As shown, the two ends of the third N-type GaN layer 5 are etched by an inductively coupled plasma ICP process. The etching gas is BCl3 / Cl2, and the etching depth is 600-900nm, so as to completely etch and remove the P-type GaN layer 4 and the two ends of the third N-type GaN layer 5, so that the bottom of the gate step is located inside the second N-type GaN layer 3. In this embodiment, the length of each gate step is 2-10μm.

[0069] S3: preparing a gate structure on the upper surface of the third N-type GaN layer 5 , the sidewall of the gate step and the bottom of the gate step.

[0070] In this embodiment, step S3 includes:

[0071] S301: Figure 2c As shown, by atomic layer deposition ALD process, Al2O3 with a thickness of 45 to 55 nm is grown at the bottom of the gate step, the bottom of the gate step, the sidewall of the gate step and the surface of the third N-type GaN layer 5 to form a gate dielectric layer 6. The length of the gate dielectric layer 6 at the bottom of the gate step is 0.1 to 6 μm.

[0072] S302: Figure 2d As shown, Ni / Au is sputtered on the surface of the gate dielectric layer 6 located at both ends of the upper surface of the third N-type GaN layer 5, and on the surface of the gate dielectric layer 6 located at the bottom of the gate step and the sidewall of the gate step to form a gate electrode 7. The thickness of Ni is 30-50nm, and the thickness of Au is 300-450nm.

[0073] S302: Figure 2eAs shown, the gate dielectric layer 6 not covered by the gate electrode 7 is removed by ICP etching. The etching gas is CF4 gas. The gate dielectric layer 6 and the gate electrode 7 form a gate structure.

[0074] S4 : etching the upper surface of the third N-type GaN layer 5 to form a source groove extending from the upper surface of the third N-type GaN layer 5 to the lower surface of the third N-type GaN layer 5 .

[0075] Specifically, Figure 2f As shown, the ICP process is used to etch the center of the upper surface of the third N-type GaN layer 5 to form a source groove extending from the upper surface of the third N-type GaN layer 5 to the lower surface of the third N-type GaN layer 5. The etching gas is BCl3 / Cl2, and the etching depth is 200-300nm.

[0076] S5: a source electrode 8 is formed in the source groove, and a drain electrode 9 is formed on the upper surface of the first N-type GaN layer 2 on both sides of the second N-type GaN layer 3; there is a gap between the drain electrode 9 and the second N-type GaN layer 3. The distance between the drain electrode 9 and the second N-type GaN layer 3 is 7-10 μm.

[0077] Specifically, Figure 2g As shown, the two ends of the second N-type GaN layer 3 are etched away by the ICP process to form a drain groove, and the two ends of the first N-type GaN layer 2 are etched by the ICP process to form a device isolation region. Figure 2h As shown, Ti / Al / Ni / Au is evaporated in the source groove and the drain groove, wherein the thickness of Ti is 20-30nm, the thickness of Al is 140-180nm, the thickness of Ni is 40-60nm, and the thickness of Au is 30-50nm. In this embodiment, the distance between the drain electrode 9 and the second N-type GaN layer 3 is 7-10μm, the etching depth of the drain groove is 4-6μm, and the etching depth of the device isolation region is 1-2μm.

[0078] S6 : forming a NiO modulation layer 10 on the bottom of the gate step, the side surface of the second N-type GaN layer 3 and the upper surface of the first N-type GaN layer 2 .

[0079] In this embodiment, the specific steps of step S6 include:

[0080] By adopting the magnetron sputtering process, P-type NiO with a thickness of 100 to 200 nm is sputtered on the bottom of the gate step, the side surface of the second N-type GaN layer 3, and the upper surface of the first N-type GaN layer 2 between the second N-type GaN layer 3 and the drain electrode 9 to obtain the NiO modulation layer 10. Among them, the target material of the magnetron sputtering process is nickel oxide, and the working gas is O2 and Ar. Furthermore, the proportion of O2 in the working gas is 0 to 66%. By adjusting the proportion of O2 in the working gas, the doping concentration of the grown P-type NiO is 1.0×10 15 ~1×10 18 cm -3 The length of the NiO modulation layer 10 at the bottom of the gate step is 2-8 μm, the distance between the NiO modulation layer 10 on the gate step and the gate structure is 0-2 μm, and the length of the NiO modulation layer 10 on the upper surface of the first N-type GaN layer 2 is 5-8 μm.

[0081] The present embodiment provides a method for preparing a MOSFET device based on NiO gate modulation, by preparing a NiO modulation layer 10 at the bottom of the gate step, the side surface of the second N-type GaN layer 3 and the upper surface of the first N-type GaN layer 2, so as to deplete the interface state of the second N-type GaN layer 3 and the electrons on the surface of the second N-type GaN layer 3, generate a depletion region, widen the electric field distribution range of the device, reduce the peak electric field strength of the device, and improve the withstand voltage level of the device. In addition, the NiO modulation layer 10 in the present embodiment can be prepared by a magnetron sputtering process, which is simple in process and low in production cost, meeting production needs.

[0082] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A MOSFET device based on NiO gate modulation, It is characterized in that include: A substrate layer (1), a first N-type GaN layer (2), a second N-type GaN layer (3), a P-type GaN layer (4) and a third N-type GaN layer (5) are arranged in sequence from bottom to top; A gate step extending from two ends of the upper surface of the third N-type GaN layer (5) to the interior of the second N-type GaN layer (3); A gate structure extending from the upper surface of the third N-type GaN layer (5) to the bottom of the gate step; A source groove extending from the upper surface of the third N-type GaN layer (5) to the lower surface of the third N-type GaN layer (5); A source electrode (8), located in the source groove; a drain electrode (9) located on the upper surface of the first N-type GaN layer (2) on both sides of the second N-type GaN layer (3), and a gap exists between the drain electrode (9) and the second N-type GaN layer (3); A NiO modulation layer (10) extends from the bottom of the gate step to the upper surface of the first N-type GaN layer (2).

2. A MOSFET device based on NiO gate modulation according to claim 1, It is characterized in that The source electrode (8) extends from the source groove to the upper surface of the third N-type GaN layer (5), and there is a gap between the source electrode (8) and the gate structure.

3. A MOSFET device based on NiO gate modulation according to claim 1, It is characterized in that The gate structure comprises: a gate dielectric layer (6) and a gate electrode (7), wherein: The gate dielectric layer (6) extends from the upper surface of the third N-type GaN layer (5) to the bottom of the gate step; The gate electrode (7) is located on the surface of the gate dielectric layer (6).

4. A MOSFET device based on NiO gate modulation according to claim 3, It is characterized in that The material of the substrate layer (1) includes one or more of Si, SiC, and sapphire; The material of the gate dielectric layer (6) includes Al 2 O 3 ; The material of the gate electrode (7) includes Ni / Au; The material of the source electrode (8) includes Ti / Al / Ni / Au; The material of the drain electrode (9) includes Ti / Al / Ni / Au.

5. A MOSFET device based on NiO gate modulation according to claim 1, It is characterized in that The length of the gate structure located at the bottom of the gate step is 0.1-6 μm.

6. A MOSFET device based on NiO gate modulation according to claim 1, It is characterized in that The length of the NiO modulation layer (10) located at the bottom of the gate step is 2 to 8 μm; The length of the NiO modulation layer (10) located on the upper surface of the first N-type GaN layer (2) is 5 to 8 μm. The distance between the drain electrode (9) and the second N-type GaN layer (3) is 7 to 10 μm.

7. A MOSFET device based on NiO gate modulation according to claim 1, It is characterized in that The doping concentration of the first N-type GaN layer (2) is 1.0×10 19 ~1×10 20 cm -3 , thickness is 1 to 2 μm; The doping concentration of the second N-type GaN layer (3) is 1.0×10 15 ~2×10 16 cm -3 , thickness is 3-5 μm; The doping concentration of the P-type GaN layer (4) is 1.0×10 17 ~1×10 18 cm -3 , thickness is 200~350nm; The doping concentration of the third N-type GaN layer (5) is 1.0×10 19 ~1×10 20 cm -3 , with a thickness of 200 to 300 nm.

8. A MOSFET device based on NiO gate modulation according to claim 1, It is characterized in that The doping type of the NiO modulation layer (10) is P type, and the doping concentration is 1.0×10 15 ~1×10 18 cm -3 , thickness is 100~200nm.

9. A method for preparing a MOSFET device based on NiO gate modulation, It is characterized in that The following steps are involved: S1: obtaining a substrate layer (1), a first N-type GaN layer (2), a second N-type GaN layer (3), a P-type GaN layer (4), and a third N-type GaN layer (5) arranged in sequence from bottom to top; S2: etching at both ends of the third N-type GaN layer (5) to form gate steps extending from both ends of the upper surface of the third N-type GaN layer (5) to the interior of the second N-type GaN layer (3); S3: preparing a gate structure on the upper surface of the third N-type GaN layer (5), the sidewall of the gate step and the bottom of the gate step; S4: etching the upper surface of the third N-type GaN layer (5) to form a source groove extending from the upper surface of the third N-type GaN layer (5) to the lower surface of the third N-type GaN layer (5); S5: preparing a source electrode (8) in the source groove, and preparing a drain electrode (9) on the upper surface of the first N-type GaN layer (2) on both sides of the second N-type GaN layer (3); a gap exists between the drain electrode (9) and the second N-type GaN layer (3); S6: Preparing a NiO modulation layer (10) at the bottom of the gate step, the side surface of the second N-type GaN layer (3), and the upper surface of the first N-type GaN layer (2).

10. The method for preparing a MOSFET device based on NiO gate modulation according to claim 9, It is characterized in that The specific steps of step S6 include: A magnetron sputtering process is used to sputter P-type NiO with a thickness of 100 to 200 nm at the bottom of the gate step, the side surface of the second N-type GaN layer (3) and the upper surface of the first N-type GaN layer (2) to obtain a NiO modulation layer (10); wherein the target material of the magnetron sputtering process is nickel oxide, and the working gas is O 2 and Ar.

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