Data processing method and device of filter, electronic equipment and medium

Abstract

The embodiment of the application provides a data processing method and device of a filter, electronic equipment and medium, the method comprises the following steps: obtaining input data; according to a pre-configured filtering parameter, searching a pre-stored lookup table to find a target output bit width corresponding to the input data; according to the target output bit width, using a cascade integrator to perform integral processing on the input data to obtain integral data; according to the target output bit width, using a decimator to perform decimation sampling on the integral data to obtain sampling data; and according to the target output bit width, using a cascade differentiator to perform differential processing on the sampling data to obtain filtered data corresponding to the input data. In the embodiment of the application, a bit width adaptive control unit is added to realize bit width selection and effective data bit control under different decimation rates and orders, which can effectively avoid the generation of burrs in the filtering process.

Description

Technical Field

[0001] The present application relates to the technical field of digital signal processing, and in particular to a filter data processing method, device, electronic device, and medium. Background Art

[0002] In digital signal processing, the CIC filter is an optimized FIR filter, utilizing a cascaded integration and comb filter approach. A CIC filter consists of one or more pairs of integration-comb filters. During CIC extraction, the input signal undergoes integration, downsampling, and a number of comb filters equal to the number of integration steps. The existing integration, decimation, and differentiation processes utilize a fixed bit width, making it impossible to dynamically adjust the bit width to improve signal filtering accuracy. Summary of the Invention

[0003] Some embodiments of the present application aim to provide a filter data processing method, apparatus, electronic device, and medium. According to the technical solutions of the embodiments of the present application, input data is obtained; a target output bit width corresponding to the input data is searched in a pre-stored lookup table according to pre-configured filtering parameters, wherein the pre-stored lookup table includes at least a correspondence between the input data bit width, decimation rate, filter differential delay, filter order, and data peak value at the output bit width; the filtering parameters include at least the decimation rate and the filter order; the input data is integrated using a cascade integrator according to the target output bit width to obtain integrated data; the integrated data is sampled using a decimator according to the target output bit width to obtain sampled data; and the sampled data is differentiated using a cascade differentiator according to the target output bit width to obtain filtered data corresponding to the input data. In the embodiments of the present application, a bit width adaptive control unit is added to realize bit width selection and control of valid data bits under different decimation rates and orders, which can effectively avoid the generation of burrs during the filtering process.

[0004] In a first aspect, some embodiments of the present application provide a filter data processing method, including:

[0005] Get input data;

[0006] searching, in a pre-stored lookup table, for a target output bit width corresponding to the input data according to pre-configured filtering parameters, wherein the pre-stored lookup table includes at least a correspondence between input data bit width, decimation rate, filter differential delay, filter order, and data peak value at the output bit width; and the filtering parameters include at least the decimation rate and the filter order;

[0007] According to the target output bit width, integrating the input data using a cascade integrator to obtain integrated data;

[0008] According to the target output bit width, a decimator is used to sample the integrated data to obtain sampled data;

[0009] According to the target output bit width, a cascade differentiator is used to perform differentiation processing on the sampled data to obtain filtered data corresponding to the input data.

[0010] Some embodiments of the present application achieve bit width selection and control of valid data bits at different decimation rates and levels by adding a bit width adaptive control unit, which can effectively avoid the generation of glitches during the filtering process.

[0011] Optionally, the pre-stored lookup table is obtained in the following manner:

[0012] Calculate the logarithmic value based on the decimation rate and the filter differential delay;

[0013] Calculating a first product according to the logarithmic value and the filter order;

[0014] Calculating an initial output bit width according to the first product and the input data bit width;

[0015] Rounding up the initial output bit width to obtain an output bit width; the output bit width is used to process the integrator, the decimator, the differentiator and the limiter output unit respectively;

[0016] Determine the correspondence between the input data bit width, the decimation rate, the filter differential delay, the filter order, the output bit width, and the data peak value under the output bit width as the lookup table;

[0017] The first data peak value under the output bit width is calculated based on the decimation rate and the number of filter stages.

[0018] Some embodiments of the present application implement adaptive bit width adjustment at different decimation rates and filtering of data during calculations by means of a lookup table and a shift register.

[0019] Optionally, integrating the input data using a cascade integrator according to the target output bit width to obtain integrated data includes:

[0020] Performing a shift operation on the target output bit width to obtain a second data peak value; wherein the second data peak value is greater than the first data peak value;

[0021] When the input data is valid data, perform first-order integration on the input data to obtain the data after first-order integration;

[0022] Calculating the input data and the data after the first-order integration and performing an addition operation to obtain a first addition result;

[0023] Performing a bitwise AND logic operation on the first addition result and the second data peak value to obtain first-level integration valid data;

[0024] Performing a secondary integration operation on the primary integrated data to obtain secondary integrated data;

[0025] Calculating a second addition result of the data after the secondary integration and the data after the primary integration;

[0026] Performing a bitwise AND logic operation on the second addition result and the second data peak value to obtain secondary integration valid data;

[0027] Performing a third-level integration operation on the data after the second-level integration to obtain third-level integrated data;

[0028] Calculating a third addition result of the data after the third-level integration and the data after the second-level integration;

[0029] Performing a bitwise AND logic operation on the third addition result and the second data peak value to obtain three-level integration valid data;

[0030] Circularly performing N-level integration operations on the data after the N-1-level integration to obtain N-level integrated data;

[0031] Calculating an Nth addition result of the data after the N-level integration and the data after the N-1-level integration;

[0032] Performing a bitwise AND logic operation on the Nth addition result and the second data peak value to obtain N-level integration valid data;

[0033] The N-level integrated valid data is determined as the integrated data, wherein N is the number of filter stages and is a natural number greater than 1.

[0034] Some embodiments of the present application implement integration operations on input bit streams through cascaded integrators, which are implemented internally through adders and can dynamically adjust the bit width of the integrated effective data.

[0035] Optionally, the decimating and sampling the integrated data using a decimator according to the target output bit width to obtain sampled data includes:

[0036] Get the internal counter value;

[0037] When the internal counter value is the same as the preset extraction rate, setting the extraction data valid flag signal to a valid preset value;

[0038] When the valid preset value is detected, a bitwise AND logic process is performed on the N-level integration result and the second data peak value to obtain the sampled data.

[0039] In some embodiments of the present application, the extractor extracts and samples the integrated data and stores the sampling results in a register, and can dynamically adjust the bit width of the extracted valid data.

[0040] Optionally, the step of performing differentiation processing on the sampled data using a cascade differentiator according to the target output bit width to obtain filtered data corresponding to the input data includes:

[0041] Performing a delay process on the sampled data to obtain first sampled data;

[0042] Calculating a difference between the sampled data and the first sampled data to obtain a first difference;

[0043] Performing bitwise AND logic processing on the first difference and the second data peak value to obtain first-level differential data;

[0044] performing a secondary delay process on the first sampled data to obtain second sampled data;

[0045] Calculating a difference between the first-order differential data and the second sampling data to obtain a second difference;

[0046] Performing a bitwise AND logic process on the second difference and the second data peak value to obtain secondary differential data;

[0047] Performing N delay processing on the N-1th sampling data to obtain Nth sampling data;

[0048] Calculating the difference between the N-1 level differential data and the Nth sampling data to obtain an Nth difference;

[0049] Performing bitwise AND logic processing on the Nth difference value and the second data peak value to obtain N-level differential data, where N is the number of filter levels and N is a natural number greater than 1.

[0050] In some embodiments of the present application, a cascade differentiator implements differential operations on the extracted data, which is internally implemented through a subtractor and can dynamically adjust the bit width of the differential effective data.

[0051] Optionally, the method further includes:

[0052] The first data peak value is used to limit the amplitude of the differential data to obtain limited amplitude data.

[0053] The limited amplitude data is determined as the filtered data.

[0054] In some embodiments of the present application, the data in the integral, decimation and differential operation processes is limited in amplitude to obtain differential data, and then the first data peak value is used to limit the amplitude of the differential data to obtain the final filtered target data, so that glitches in the operation process can be effectively avoided.

[0055] In a second aspect, some embodiments of the present application provide a data processing device of a filter, comprising:

[0056] An acquisition module is configured to acquire input data.

[0057] A search module is configured to search a pre-stored search table for a target output bit width corresponding to the input data according to pre-configured filtering parameters, wherein the pre-stored search table at least includes a corresponding relationship among input data bit width, decimation rate, filter differential delay, filter order and data peak value under output bit width; and the filtering parameters at least include the decimation rate and the filter order.

[0058] An integral module is configured to perform integral processing on the input data by using a cascade integrator according to the target output bit width to obtain integral data.

[0059] A decimation module is configured to perform decimation sampling on the integral data by using a decimator according to the target output bit width to obtain sampling data.

[0060] A differential module is configured to perform differential processing on the sampling data by using a cascade differentiator according to the target output bit width to obtain filtered data corresponding to the input data.

[0061] Some embodiments of the present application can effectively avoid the generation of glitches in the filtering process by adding a bit width adaptive control unit to realize bit width selection and effective data bit control under different decimation rates and orders.

[0062] Optionally, the pre-stored search table is obtained by the following method:

[0063] A logarithmic value is calculated according to the decimation rate and the filter differential delay.

[0064] A first product is calculated according to the logarithmic value and the filter order.

[0065] An initial output bit width is calculated according to the first product and the input data bit width.

[0066] Rounding up the initial output bit width to obtain an output bit width; the output bit width is used to process the integrator, the decimator, the differentiator and the limiter output unit respectively;

[0067] Determine the correspondence between the input data bit width, the decimation rate, the filter differential delay, the filter order, the output bit width, and the data peak value under the output bit width as the lookup table;

[0068] The first data peak value under the output bit width is calculated based on the decimation rate and the number of filter stages.

[0069] Some embodiments of the present application implement adaptive bit width adjustment at different decimation rates and filtering of data during calculations by means of a lookup table and a shift register.

[0070] Optionally, the integration module is used to:

[0071] Performing a shift operation on the target output bit width to obtain a bit width peak value and a second data peak value;

[0072] When the input data is valid data, perform first-order integration on the input data to obtain the data after first-order integration;

[0073] Calculating the input data and the data after the first-order integration and performing an addition operation to obtain a first addition result;

[0074] Performing a bitwise AND logic operation on the first addition result and the second data peak value to obtain first-level integration valid data;

[0075] Performing a secondary integration operation on the primary integrated data to obtain secondary integrated data;

[0076] Calculating a second addition result of the data after the secondary integration and the data after the primary integration;

[0077] Performing a bitwise AND logic operation on the second addition result and the second data peak value to obtain secondary integration valid data;

[0078] Performing a third-level integration operation on the data after the second-level integration to obtain third-level integrated data;

[0079] Calculating a third addition result of the data after the third-level integration and the data after the second-level integration;

[0080] Performing a bitwise AND logic operation on the third addition result and the second data peak value to obtain three-level integration valid data;

[0081] Circularly performing N-level integration operations on the data after the N-1-level integration to obtain N-level integrated data;

[0082] Calculating an Nth addition result of the data after the N-level integration and the data after the N-1-level integration;

[0083] Performing a bitwise AND logic operation on the Nth addition result and the second data peak value to obtain N-level integration valid data;

[0084] The N-level integrated valid data is determined as the integrated data, wherein N is the number of filter stages and is a natural number greater than 1.

[0085] Some embodiments of the present application implement integration operations on input bit streams through cascaded integrators, which are implemented internally through adders and can dynamically adjust the bit width of the integrated effective data.

[0086] Optionally, the extraction module is used to:

[0087] Get the internal counter value;

[0088] When the internal counter value is the same as the preset extraction rate, setting the extraction data valid flag signal to a valid preset value;

[0089] When the valid preset value is detected, a bitwise AND logic process is performed on the N-level integration result and the second data peak value to obtain the sampled data.

[0090] In some embodiments of the present application, the extractor extracts and samples the integrated data and stores the sampling results in a register, and can dynamically adjust the bit width of the extracted valid data.

[0091] Optionally, the differentiation module is used to:

[0092] Performing a delay process on the sampled data to obtain first sampled data;

[0093] Calculating a difference between the sampled data and the first sampled data to obtain a first difference;

[0094] Performing bitwise AND logic processing on the first difference and the second data peak value to obtain first-level differential data;

[0095] performing a secondary delay process on the first sampled data to obtain second sampled data;

[0096] Calculating a difference between the first-order differential data and the second sampling data to obtain a second difference;

[0097] Performing a bitwise AND logic process on the second difference and the second data peak value to obtain secondary differential data;

[0098] Performing N delay processing on the N-1th sampling data to obtain Nth sampling data;

[0099] Calculating the difference between the N-1 level differential data and the Nth sampling data to obtain an Nth difference;

[0100] Performing bitwise AND logic processing on the Nth difference value and the second data peak value to obtain N-level differential data, where N is the number of filter levels and N is a natural number greater than 1.

[0101] In some embodiments of the present application, a cascade differentiator implements differential operations on the extracted data, which is internally implemented through a subtractor and can dynamically adjust the bit width of the differential effective data.

[0102] Optionally, the differentiation module is used to:

[0103] performing a limiting process on the differentiated data according to a first data peak value under the bit width to obtain data after the limiting process;

[0104] The data after the clipping process is determined as the filtered data.

[0105] In some embodiments of the present application, after performing limiting processing on the data during the integration, extraction and differentiation operations, the differentiated data is obtained, and then the first data peak value is used to perform limiting processing on the differentiated data to obtain the final filtered target data, which can also effectively avoid glitches in the operation process.

[0106] In a third aspect, some embodiments of the present application provide an electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein when the processor executes the program, the filter data processing method as described in any embodiment of the first aspect can be implemented.

[0107] In a fourth aspect, some embodiments of the present application provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, can implement the filter data processing method as described in any embodiment of the first aspect.

[0108] In a fifth aspect, some embodiments of the present application provide a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, it can implement the filter data processing method as described in any embodiment of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0109] In order to more clearly illustrate the technical solutions of some embodiments of the present application, the following will briefly introduce the drawings needed to be used in some embodiments of the present application. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation on the scope, and for those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0110] Figure 1 A flowchart of a data processing method of a filter provided by an embodiment of the present application is shown in FIG. 2;

[0111] Figure 2 A flowchart of another data processing method of a filter provided by an embodiment of the present application is shown in FIG. 3;

[0112] Figure 3 A simulation diagram of unfiltered data is shown in FIG. 4;

[0113] Figure 4 A simulation diagram of filtered data under a lookup table provided by an embodiment of the present application is shown in FIG. 5;

[0114] Figure 5 A diagram of a peak value of filtered data provided by an embodiment of the present application is shown in FIG. 6;

[0115] Figure 6 A structural diagram of a data processing device of a filter provided by an embodiment of the present application is shown in FIG. 7;

[0116] Figure 7 An electronic device provided by an embodiment of the present application is shown in FIG. 8. DETAILED DESCRIPTION

[0117] The technical solutions of some embodiments of the present application will be described below in combination with the drawings in some embodiments of the present application.

[0118] It should be noted that similar reference numerals and letters indicate similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. Meanwhile, in the description of the present application, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0119] In digital signal processing, the CIC filter is an optimal FIR filter that uses a cascade of integration and comb filters. A CIC filter consists of one or more pairs of integration-comb filters. In decimation CIC, the input signal undergoes integration, downsampling, and comb filtering, the same number of steps as the integration steps. In the existing integration, decimation, and differentiation processes, a fixed bit width is used for processing, and the bit width cannot be dynamically configured according to actual conditions, thereby improving the accuracy of signal filtering. In view of this, some embodiments of the present application provide a filter data processing method, the method comprising obtaining input data; searching a pre-stored lookup table for a target output bit width corresponding to the input data based on pre-configured filtering parameters, wherein the pre-stored lookup table includes at least a correspondence between the input data bit width, decimation rate, filter differential delay, filter order, and output bit width; the filtering parameters include at least the decimation rate and the filter order; according to the target output bit width, a cascade integrator is used to integrate the input data to obtain integrated data; according to the target output bit width, a decimator is used to sample the integrated data to obtain sampled data; according to the target output bit width, a cascade differentiator is used to differentiate the sampled data to obtain filtered data corresponding to the input data. In the embodiments of the present application, a bit width adaptive control unit is added to realize bit width selection and control of valid data bits under different decimation rates and orders, which can effectively avoid the generation of burrs during the filtering process.

[0120] like Figure 1 As shown, an embodiment of the present application provides a filter data processing method, the method comprising:

[0121] S101, obtaining input data;

[0122] Specifically, the input data is bit stream data;

[0123] The terminal device obtains input data to be filtered, that is, bit stream data to be filtered.

[0124] S102. Searching a pre-stored lookup table for a target output bit width corresponding to the input data according to pre-configured filtering parameters, wherein the pre-stored lookup table includes at least a correspondence between the input data bit width, a decimation rate, a filter differential delay, a filter order, and a data peak value at the output bit width; and the filtering parameters include at least the decimation rate and the filter order.

[0125] A lookup table is pre-stored on the terminal device, which includes at least the correspondence between the input data bit width, decimation rate, filter differential delay, filter order, output bit width, and data peak value under the output bit width. After obtaining the bit rate data, the terminal device obtains the bit width of the bit stream data, that is, the input data bit width, where the bit width is the amount of data that can be transmitted at one time by the memory or video memory. Then, based on the pre-configured filtering parameters and the pre-stored lookup table, the target output bit width corresponding to the input data is searched.

[0126] The decimation rate and filter level in the filtering parameters in the embodiment of the present application can be set according to user needs and are not specifically limited here.

[0127] S103, integrating the input data using a cascade integrator according to the target output bit width to obtain integrated data;

[0128] Specifically, the terminal device configures the decimation rate and filter stage of the integrator, decimator and differentiator in the multi-stage CIC filter according to the target output bit width, and then filters the input data. The target output bit width is used to limit the cascaded integrator, decimator and cascaded differentiator, respectively, wherein the cascaded integrator integrates the input data to obtain the integrated data.

[0129] Among them, the multi-stage CIC filter includes at least multiple integrators, one extractor and multiple differentiators, and multiple refers to two or more. In this application, there is no specific limitation on the number of integrators and the number of differentiators.

[0130] S104, using a decimator to sample the integrated data according to the target output bit width to obtain sampled data;

[0131] Specifically, the terminal device uses a decimator to sample the integrated data according to the target output bit width to obtain sampled data.

[0132] S105 , using a cascade differentiator to perform differential processing on the sampled data according to the target output bit width, to obtain filtered data corresponding to the input data.

[0133] The embodiment of the present application is aimed at the input bit stream data, and can realize the dynamic adjustment of the bit width during the filtering process. If the bit width of the input data is changed, the bit width can be further processed by modifying the lookup table, that is, it can be used for optimizing the bit width and limiting the data under the dynamic adjustment of the extraction rate and the number of filter levels.

[0134] Some embodiments of the present application achieve bit width selection and control of valid data bits at different decimation rates and levels by adding a bit width adaptive control unit, which can effectively avoid the generation of glitches during the filtering process.

[0135] Another embodiment of the present application further supplements the data processing method of the filter provided in the above embodiment.

[0136] Optionally, the pre-stored lookup table is obtained by:

[0137] Calculate the logarithmic value based on the decimation rate and the filter differential delay;

[0138] Calculate the first product based on the logarithmic value and the filter order;

[0139] Calculating an initial output bit width based on the first product and the input data bit width;

[0140] The initial output bit width is rounded up to obtain an output bit width; the output bit width is used to process the integrator, the decimator, the differentiator and the limiter output unit respectively;

[0141] Determine the correspondence between the input data bit width, the decimation rate, the filter differential delay, the filter order, the output bit width, and the data peak value under the output bit width as the lookup table;

[0142] The first data peak value under the output bit width is calculated based on the decimation rate and the number of filter stages.

[0143] The lookup table is actually implemented through multiple if conditional statements, and the corresponding bit width value is matched according to the input sampling rate OSR and the number of filter stages N.

[0144] Specifically, the bit width of the intermediate signals of the integration, extraction and differentiation units is:

[0145] Bout = Bin + N * log2DM;

[0146] Where Bin is the input data bit width, D is the decimation rate (OSR), M is the filter differential delay, and N is the number of filter stages.

[0147] The bit width adaptive control unit uses a lookup table and shift register to achieve adaptive bit width adjustment at different decimation rates and filter data during the calculation process. In the design of a multi-stage CIC filter, compared with the system function of rounding up $clog2, it can achieve more accurate bit width calculation and effectively avoid glitches in the filtering process.

[0148] In the embodiment of the present application, the automatic matching of bit width is achieved in the form of a lookup table, specifically:

[0149] In the bit width calculation formula Bout = Bin + N * log2DM, $log2 is a system function that rounds up. When the value of DM is not an integer power of 2, the value calculated by $log2DM is not actually an integer. The traditional method of calculating bit width is to round up and then multiply by N. This method amplifies the difference in the resulting bit width.

[0150] In this embodiment, the calculation process does not perform rounding on $log2DM. Instead, the value of Bout = Bin + N*log2DM is directly calculated, and Bout is then rounded off. After configuring the decimation rate, the bit width value r_width_tmp is directly output through a lookup table. This results in a very small error between the bit width obtained and the actual bit width of the data during filtering. The bit width value is calculated in Excel.

[0151] Some embodiments of the present application implement adaptive bit width adjustment at different decimation rates and filtering of data during calculations by means of a lookup table and a shift register.

[0152] Optionally, according to the target output bit width, a cascade integrator is used to perform integration processing on the input data to obtain integrated data, including:

[0153] A shift operation is performed on the target output bit width to obtain a second data peak value; wherein the second data peak value is obtained by performing a bitwise AND logic on the integral value and the value of the bit width all 1 in each level of integration operation.

[0154] When the input data is valid data, perform first-order integration on the input data to obtain the data after first-order integration;

[0155] Calculating the input data and the data after the first-order integration and performing an addition operation to obtain a first addition result;

[0156] Performing a bitwise AND logic operation on the first addition result and the second data peak value to obtain first-level integration valid data;

[0157] Performing a secondary integration operation on the primary integrated data to obtain secondary integrated data;

[0158] Calculating a second addition result of the data after the secondary integration and the data after the primary integration;

[0159] Performing a bitwise AND logic operation on the second addition result and the second data peak value to obtain secondary integration valid data;

[0160] Performing a third-level integration operation on the data after the second-level integration to obtain third-level integrated data;

[0161] Calculating a third addition result of the data after the third-level integration and the data after the second-level integration;

[0162] Performing a bitwise AND logic operation on the third addition result and the second data peak value to obtain three-level integration valid data;

[0163] Circularly performing N-level integration operations on the data after the N-1-level integration to obtain N-level integrated data;

[0164] Calculating an Nth addition result of the data after the N-level integration and the data after the N-1-level integration;

[0165] Performing a bitwise AND logic operation on the Nth addition result and the second data peak value to obtain N-level integration valid data;

[0166] The N-level integrated valid data is determined as the integrated data, wherein N is the number of filter stages and is a natural number greater than 1.

[0167] Specifically, firstly, the bit width value obtained in the bit width adaptive unit, that is, the target output bit width r_width_tmp, is left-shifted (1 < <r_width_tmp)-1’b1,得到该位宽下的最大值即第二数据峰值w_valid_data。

[0168] Secondly, during the integration operation, the accumulated value of each time, the data r_integ_data after the first-order integration and w_valid_data are logically processed to finally obtain the result after integration.

[0169] For example, in the 3rd level integration operation:

[0170] (1) First-level integration: When the input data valid signal i_sd_valid is detected, the data r_integ_data1 and the original data w_sd_data are added. The result of the addition operation is bitwise ANDed with w_valid_data, and the result is finally stored in the first-level integration result register r_integ_data1. At the same time, the valid signal r_integ_valid1 for the first-level integration result is generated.

[0171] (2) Second-level integration: When the data valid signal r_integ_valid1 is detected, the data r_integ_data2 is added to the first-level integration data r_integ_data1. The result of the addition operation is bitwise ANDed with w_valid_data, and the result is finally stored in the second-level integration result register r_integ_data2. At the same time, the valid signal r_integ_valid2 for the second-level integration result is generated.

[0172] (3) Third-level integration: When the data valid signal r_integ_valid2 is detected, the r_integ_data3 data and the secondary integration data r_integ_data2 are added, and the result of the addition operation is bitwise ANDed with w_valid_data. Finally, the result is saved in the third-level integration result r_integ_data3 register, and the valid signal r_integ_valid3 of the third-level integration result is generated.

[0173] The above is an integration process of 3 integrators, and there can also be N integrators, which is not specifically limited in the embodiments of the present application.

[0174] Some embodiments of the present application implement integration operations on input bit streams through cascaded integrators, which are implemented internally through adders and can dynamically adjust the bit width of the integrated effective data.

[0175] Optionally, according to the target output bit width, using a decimator to sample the integrated data to obtain sampled data includes:

[0176] Get the internal counter value;

[0177] When the internal counter value is the same as the preset extraction rate, setting the extraction data valid flag signal to a valid preset value;

[0178] When the valid preset value is detected, a bitwise AND logic process is performed on the N-level integration result and the second data peak value to obtain the sampled data.

[0179] During each extraction process, the extracted value and the value with a bit width of all 1 are used to perform bitwise AND logic to obtain the final extracted value.

[0180] In some embodiments of the present application, the extractor extracts and samples the integrated data and stores the sampling results in a register, and can dynamically adjust the bit width of the extracted valid data.

[0181] Specifically, during the extraction operation, the internal counter is first counted according to the configured OSR value. When the count value is equal to the OSR configuration value, the flag signal r_osr_valid indicating that the extracted data is valid is set and the counter is cleared at the same time.

[0182] Secondly, when the data valid signal r_osr_valid is detected, the data r_integ_data3 and w_valid_data are bitwise ANDed and the result is stored in the decimation register r_decim_data. At the same time, the valid signal r_decim_valid for the decimation result is generated.

[0183] Optionally, according to the target output bit width, a cascade differentiator is used to perform differentiation processing on the sampled data to obtain filtered data corresponding to the input data, including:

[0184] Performing a delay process on the sampled data to obtain first sampled data;

[0185] Calculating a difference between the sampled data and the first sampled data to obtain a first difference;

[0186] Performing bitwise AND logic processing on the first difference and the second data peak value to obtain first-level differential data;

[0187] performing a secondary delay process on the first sampled data to obtain second sampled data;

[0188] Calculating a difference between the first-order differential data and the second sampling data to obtain a second difference;

[0189] Performing a bitwise AND logic process on the second difference and the second data peak value to obtain secondary differential data;

[0190] Performing N delay processing on the N-1th sampling data to obtain Nth sampling data;

[0191] Calculating the difference between the N-1 level differential data and the Nth sampling data to obtain an Nth difference;

[0192] Performing bitwise AND logic processing on the Nth difference value and the second data peak value to obtain N-level differential data, where N is the number of filter levels and N is a natural number greater than 1.

[0193] Specifically, during the differential operation, each cumulative difference r_diff_data and w_valid_data are subjected to an AND logic process to obtain a differential result.

[0194] For example, in a three-level differential operation: in each level of differential operation, the differential value and the value with a bit width of all 1 are used to perform bitwise AND logic.

[0195] (4) First-order differential: when detecting the data valid signal r_decim_valid, delay processing r_decim_data to obtain r_decim_data_r, and perform subtraction operation on r_decim_data and r_decim_data_r, perform bitwise AND logical processing on the result of the subtraction operation and w_valid_data, and finally save the result in the first-order differential result r_diff_data1 register. At the same time, generate the first-order differential result valid signal r_diff_valid1.

[0196] (5) Second-order differential: when detecting the data valid signal r_diff_valid1, delay processing r_diff_data1 to obtain r_diff_data1_r, and perform subtraction operation on r_diff_data1 and r_diff_data1_r, perform bitwise AND logical processing on the result of the subtraction operation and w_valid_data, and finally save the result in the second-order differential result r_diff_data2 register. At the same time, generate the second-order differential result valid signal r_diff_valid2.

[0197] (6) Third-order differential: when detecting the data valid signal r_diff_valid2, delay processing r_diff_data2 to obtain r_diff_data2_r, and perform subtraction operation on r_diff_data2 and r_diff_data2_r, perform bitwise AND logical processing on the result of the subtraction operation and w_valid_data, and finally save the result in the third-order differential result r_diff_data3 register. At the same time, generate the third-order differential result valid signal r_diff_valid3.

[0198] Some embodiments of the present application, the decimator implements decimation sampling on the integrated data, and saves the sampling result in the register. The bit width of the decimated valid data can be dynamically adjusted. The cascaded differentiator implements differential operation on the decimated data, which is realized by a subtractor inside. The bit width of the differential valid data can be dynamically adjusted.

[0199] Optionally, the method further comprises:

[0200] Amplitude limiting processing the first data peak according to the bit width on the differential data to obtain amplitude limiting processed data;

[0201] Determining the amplitude limiting processed data as the filtered data.

[0202] The maximum value w_valid_data under the corresponding bit width is obtained by shift operation, and its calculation formula is: w_valid_data=(1< <r_width_tmp)-1'b1。

[0203] And use w_valid_data to limit the data during the integration, extraction and differentiation operations, which can effectively avoid glitches during the operation.

[0204] The peak value r_sinc_peak_data is obtained based on the configured decimation rate OSR and the number of filter stages N. If the differentiated result is greater than the peak value, the peak value is output; if the differentiated result is less than the peak value, the current differentiated value is output.

[0205] The peak value of the filtered data is calculated by looking up the table, such as Figure 5 As shown in the figure, the peak data is used for limiting processing to further effectively filter out the burrs.

[0206] In some embodiments of the present application, after performing limiting processing on the data during the integration, extraction and differentiation operations, the differentiated data is obtained, and then the first data peak value is used to perform limiting processing on the differentiated data to obtain the final filtered target data, which can also effectively avoid glitches in the operation process.

[0207] like Figure 2 As shown, an embodiment of the present application provides a multi-stage CIC filter device based on a configurable decimation rate, including a bit width adaptive control unit, a cascaded integrator unit, an extractor unit, a cascaded differentiator unit, and a limiter output unit, wherein:

[0208] Bit width adaptive control realizes bit width selection and control of effective data bits under different extraction rates and levels. It is mainly used to improve data accuracy and is implemented internally through lookup tables and shift registers.

[0209] The cascade integrator implements the integration operation on the input bit stream, which is realized internally by an adder and can dynamically adjust the bit width of the effective data of the integration.

[0210] The decimator extracts and samples the integrated data and stores the sampling results in the register. The bit width of the extracted valid data can be dynamically adjusted.

[0211] The cascade differentiator realizes the differential operation of the extracted data, which is realized internally by a subtractor and can dynamically adjust the bit width of the differential effective data.

[0212] The limiting output realizes the limiting processing of data, which is mainly used to filter out burrs and improve data accuracy.

[0213] For example, for a 3-stage filter N=3, the input unsigned data bit stream Bin=1, the filter differential delay M=1, when configured with OSR=9, the first data peak of the filter is w_sinc_peak_data=16'h03e8.

[0214] During the filtering process, the decimation rate is changed. When OSR=9 is configured, according to the formula Bout=Bin+N*log2DM, if $clog2 is rounded up, Bout=13 can be obtained. The following simulation waveform is obtained, as shown in the following example: Figure 3 As shown: i_osr = 8'h9, the calculated bit width r_width_tmp = 5'hd, the filtered data o_sinc_data is 16'hdeec when it is first extracted after switching the sampling rate OSR, 16'hc0a0 after the second extraction, and 16'h79e8 after the third extraction. It is not until the fourth extraction that the filtered data stabilizes at 16'h03e8. The data of three glitches is generated during the filtering process, as shown in Figure 3 shown.

[0215] Through the bit width adaptive control unit, the bit width r_width_tmp=5'ha can be obtained. The following simulation waveform is obtained, as shown Figure 4 As shown in the figure, after switching the OSR, the filtered data o_sinc_data has a value of 16'h02ec during the first decimation, 16'h00a0 after the second decimation, 16'h01e8 after the third decimation, and stabilizes at 16'h03e8 after the fourth decimation. No glitches are generated during the filtering process, improving the accuracy of the filtered data.

[0216] Compared with the prior art, the embodiment of the present application implements a multi-stage CIC filter with a dynamically configurable decimation rate and realizes automatic adjustment of the bit width at different decimation rates, which can reduce the cumulative error in the data processing process and ensure the accuracy of the filtered data.

[0217] It should be noted that each implementable method in this embodiment can be implemented separately, or can be implemented in combination in any combination without conflict, and this application does not limit it.

[0218] Another embodiment of the present application provides a filter data processing device, which is used to execute the filter data processing method provided by the above embodiment.

[0219] like Figure 6 , which is a schematic diagram of the structure of the data processing device of the filter provided in an embodiment of the present application. The data processing device of the filter includes an acquisition module 601, a search module 602, an integration module 603, an extraction module 604 and a differentiation module 605, wherein:

[0220] The acquisition module 601 is used to obtain input data;

[0221] The search module 602 is configured to search a pre-stored lookup table for a target output bit width corresponding to the input data based on pre-configured filtering parameters, wherein the pre-stored lookup table includes at least a correspondence between the input data bit width, the decimation rate, the filter differential delay, the number of filter stages, and the data peak value at the output bit width; the filtering parameters include at least the decimation rate and the number of filter stages;

[0222] The integration module 603 is used to integrate the input data using a cascade integrator according to the target output bit width to obtain integrated data;

[0223] The extraction module 604 is used to extract and sample the integrated data using a decimator according to the target output bit width to obtain sampled data;

[0224] The differentiation module 605 is used to perform differentiation processing on the sampled data using a cascade differentiator according to the target output bit width to obtain filtered data corresponding to the input data.

[0225] Regarding the device in this embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method and will not be elaborated here.

[0226] Some embodiments of the present application achieve bit width selection and control of valid data bits at different decimation rates and levels by adding a bit width adaptive control unit, which can effectively avoid the generation of glitches during the filtering process.

[0227] Another embodiment of the present application further supplements the data processing device of the filter provided in the above embodiment.

[0228] Optionally, the pre-stored lookup table is obtained by:

[0229] Calculate the logarithmic value based on the decimation rate and the filter differential delay;

[0230] Calculate the first product based on the logarithmic value and the filter order;

[0231] Calculating an initial output bit width based on the first product and the input data bit width;

[0232] The initial output bit width is rounded up to obtain an output bit width; the output bit width is used to process the integrator, the decimator, the differentiator and the limiter output unit respectively;

[0233] Determine the correspondence between the input data bit width, the decimation rate, the filter differential delay, the filter order, the output bit width, and the data peak value under the output bit width as the lookup table;

[0234] The first data peak value under the output bit width is calculated based on the decimation rate and the number of filter stages.

[0235] Some embodiments of the present application implement adaptive bit width adjustment at different decimation rates and filtering of data during calculations by means of a lookup table and a shift register.

[0236] Optionally, the integration module is used to:

[0237] Performing a shift operation on the target output bit width to obtain a second data peak value;

[0238] When the input data is valid data, perform first-order integration on the input data to obtain the data after first-order integration;

[0239] Calculating the input data and the data after the first-order integration and performing an addition operation to obtain a first addition result;

[0240] Performing a bitwise AND logic operation on the first addition result and the second data peak value to obtain first-level integration valid data;

[0241] Performing a secondary integration operation on the primary integrated data to obtain secondary integrated data;

[0242] Calculating a second addition result of the data after the secondary integration and the data after the primary integration;

[0243] Performing a bitwise AND logic operation on the second addition result and the second data peak value to obtain secondary integration valid data;

[0244] Performing a third-level integration operation on the data after the second-level integration to obtain third-level integrated data;

[0245] Calculating a third addition result of the data after the third-level integration and the data after the second-level integration;

[0246] Performing a bitwise AND logic operation on the third addition result and the second data peak value to obtain three-level integration valid data;

[0247] Circularly performing N-level integration operations on the data after the N-1-level integration to obtain N-level integrated data;

[0248] Calculating an Nth addition result of the data after the N-level integration and the data after the N-1-level integration;

[0249] Performing a bitwise AND logic operation on the Nth addition result and the second data peak value to obtain N-level integration valid data;

[0250] The N-level integrated valid data is determined as the integrated data, wherein N is the number of filter stages and is a natural number greater than 1.

[0251] Some embodiments of the present application implement integration operations on input bit streams through cascaded integrators, which are implemented internally through adders and can dynamically adjust the bit width of the integrated effective data.

[0252] Optionally, the extraction module is used to:

[0253] Get the internal counter value;

[0254] When the internal counter value is the same as the preset extraction rate, setting the extraction data valid flag signal to a valid preset value;

[0255] When the valid preset value is detected, a bitwise AND logic process is performed on the N-level integration result and the second data peak value to obtain the sampled data.

[0256] In some embodiments of the present application, the extractor extracts and samples the integrated data and stores the sampling results in a register, and can dynamically adjust the bit width of the extracted valid data.

[0257] Optionally, the differentiation module is used to:

[0258] Performing a delay process on the sampled data to obtain first sampled data;

[0259] Calculating a difference between the sampled data and the first sampled data to obtain a first difference;

[0260] Performing bitwise AND logic processing on the first difference and the second data peak value to obtain first-level differential data;

[0261] performing a secondary delay process on the first sampled data to obtain second sampled data;

[0262] Calculating a difference between the first-order differential data and the second sampling data to obtain a second difference;

[0263] Performing a bitwise AND logic process on the second difference and the second data peak value to obtain secondary differential data;

[0264] Performing N delay processing on the N-1th sampling data to obtain Nth sampling data;

[0265] Calculating the difference between the N-1 level differential data and the Nth sampling data to obtain an Nth difference;

[0266] Performing bitwise AND logic processing on the Nth difference value and the second data peak value to obtain N-level differential data, where N is the number of filter levels and N is a natural number greater than 1.

[0267] In some embodiments of the present application, a cascade differentiator implements differential operations on the extracted data, which is internally implemented through a subtractor and can dynamically adjust the bit width of the differential effective data.

[0268] Optionally, the differentiation module is used to:

[0269] performing a limiting process on the differentiated data according to a first data peak value under the bit width to obtain data after the limiting process;

[0270] The data after the clipping process is determined as the filtered data.

[0271] In some embodiments of the present application, after performing limiting processing on the data during the integration, extraction and differentiation operations, the differentiated data is obtained, and then the first data peak value is used to perform limiting processing on the differentiated data to obtain the final filtered target data, which can also effectively avoid glitches in the operation process.

[0272] Regarding the device in this embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method and will not be elaborated here.

[0273] It should be noted that each implementable method in this embodiment can be implemented separately, or can be implemented in combination in any combination without conflict, and this application does not limit it.

[0274] An embodiment of the present application further provides a computer-readable storage medium having a computer program stored thereon. When the program is executed by a processor, the operation of the method corresponding to any embodiment of the filter data processing method provided in the above embodiments can be implemented.

[0275] An embodiment of the present application further provides a computer program product, which includes a computer program, wherein when the computer program is executed by a processor, it can implement the operations corresponding to any embodiment of the filter data processing method provided in the above embodiments.

[0276] like Figure 7As shown, some embodiments of the present application provide an electronic device 700, which includes: a memory 710, a processor 720, and a computer program stored in the memory 710 and executable on the processor 720, wherein the processor 720 reads the program from the memory 710 through the bus 730 and executes the program to implement a method of any embodiment included in the data processing method of the above-mentioned filter.

[0277] Processor 720 can process digital signals and can include various computing architectures, such as a complex instruction set computer architecture, a reduced instruction set computer architecture, or an architecture that implements a combination of multiple instruction sets. In some examples, processor 720 can be a microprocessor.

[0278] The memory 710 can be used to store instructions executed by the processor 720 or data related to the execution of instructions. These instructions and / or data may include code for implementing some or all functions of one or more modules described in the embodiments of this application. The processor 720 of the embodiment of the present disclosure can be used to execute the instructions in the memory 710 to implement the method shown above. The memory 710 includes dynamic random access memory, static random access memory, flash memory, optical memory, or other memory known to those skilled in the art.

[0279] The above are merely examples of the present application and are not intended to limit the scope of protection of the present application. For those skilled in the art, the present application may have various modifications and variations. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application. It should be noted that similar numbers and letters represent similar items in the following figures. Therefore, once an item is defined in one figure, it does not need to be further defined or explained in subsequent figures.

[0280] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

[0281] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

Claims

1. A filter data processing method, characterized in that: The method comprises: Acquire input data, where the input data is bit stream data; searching, in a pre-stored lookup table, for a target output bit width corresponding to the input data according to pre-configured filtering parameters, wherein the pre-stored lookup table includes at least a correspondence between input data bit width, decimation rate, filter differential delay, filter order, and data peak value at the output bit width; and the filtering parameters include at least the decimation rate and the filter order; According to the target output bit width, the decimation rate and the number of filter stages are configured for the integrator, the decimator, and the differentiator in the multi-stage CIC filter, respectively, and the input data is filtered. The target output bit width is used to perform a limiting process on the cascaded integrator, the decimator, and the cascaded differentiator, respectively, wherein the cascaded integrator integrates the input data to obtain integrated data; the multi-stage CIC filter includes at least a plurality of integrators, a decimator, and a plurality of differentiators; According to the target output bit width, integrating the input data using a cascade integrator to obtain integrated data; According to the target output bit width, a decimator is used to sample the integrated data to obtain sampled data; performing differentiation processing on the sampled data using a cascade differentiator according to the target output bit width to obtain filtered data corresponding to the input data, performing integration, decimation, and differentiation operations on the data, and then performing clipping processing on the differentiated data using a first data peak value to obtain final filtered target data, wherein the first data peak value is calculated based on the decimation rate and the number of filter stages at the output bit width; For the input bit stream data, the bit width can be dynamically adjusted during the filtering process. If the bit width of the input data changes, the bit width can be further processed by modifying the lookup table, that is, it can be used for bit width optimization and data limiting under dynamic adjustment of the decimation rate and filter level. Wherein: the pre-stored lookup table is obtained in the following manner: Calculate the logarithmic value based on the decimation rate and the filter differential delay; Calculating a first product according to the logarithmic value and the filter order; Calculating an initial output bit width according to the first product and the input data bit width; Rounding up the initial output bit width to obtain an output bit width; the output bit width is used to process the integrator, the decimator, the differentiator and the limiter output unit respectively; Determine the correspondence between the input data bit width, the decimation rate, the filter differential delay, the filter order, the output bit width, and the data peak value under the output bit width as the lookup table; The first data peak value under the output bit width is calculated based on the decimation rate and the number of filter stages.

2. The filter data processing method according to claim 1, characterized in that: The step of integrating the input data using a cascade integrator according to the target output bit width to obtain integrated data includes: Performing a shift operation on the target output bit width to obtain a second data peak value under the target output bit width; wherein the second data peak value is greater than the first data peak value; When the input data is valid data, perform first-order integration on the input data to obtain the data after first-order integration; Calculating the input data and the data after the first-order integration and performing an addition operation to obtain a first addition result; Performing a bitwise AND logic operation on the first addition result and the second data peak value to obtain first-level integration valid data; Performing a secondary integration operation on the primary integrated data to obtain secondary integrated data; Calculating a second addition result of the data after the secondary integration and the data after the primary integration; Performing a bitwise AND logic operation on the second addition result and the second data peak value to obtain secondary integration valid data; Performing a third-level integration operation on the data after the second-level integration to obtain third-level integrated data; Calculating a third addition result of the data after the third-level integration and the data after the second-level integration; Performing a bitwise AND logic operation on the third addition result and the second data peak value to obtain three-level integration valid data; Perform N-1 level integration operations on the data after N-1 level integration in a loop to obtain N-level integrated data; Calculating an Nth addition result of the data after the N-level integration and the data after the N-1-level integration; Performing a bitwise AND logic operation on the Nth addition result and the second data peak value to obtain N-level integration valid data; The N-level integrated valid data is determined as the integrated data, wherein N is the number of filter stages and is a natural number greater than 1.

3. The filter data processing method according to claim 2, characterized in that: The method of decimating the integrated data using a decimator according to the target output bit width to obtain sampled data includes: Get the internal counter value; When the internal counter value is the same as the preset extraction rate, setting the extraction data valid flag signal to a valid preset value; When the valid preset value is detected, a bitwise AND logic process is performed on the N-level integration result and the second data peak value to obtain the sampled data.

4. The filter data processing method according to claim 3, characterized in that: The step of performing differential processing on the sampled data using a cascade differentiator according to the target output bit width to obtain filtered data corresponding to the input data includes: Performing a delay process on the sampled data to obtain first sampled data; Calculating a difference between the sampled data and the first sampled data to obtain a first difference; Performing bitwise AND logic processing on the first difference and the second data peak value to obtain first-level differential data; performing a secondary delay process on the first sampled data to obtain second sampled data; Calculating a difference between the first-order differential data and the second sampling data to obtain a second difference; Performing a bitwise AND logic process on the second difference and the second data peak value to obtain secondary differential data; Perform N-1th sampling data delay processing N times to obtain Nth sampling data; Calculating the difference between the N-1 level differential data and the Nth sampling data to obtain an Nth difference; Performing bitwise AND logic processing on the Nth difference value and the second data peak value to obtain N-level differential data, where N is the number of filter levels and N is a natural number greater than 1.

5. The filter data processing method according to claim 4, characterized in that: The method further comprises: performing a limiting process on the differentiated data according to a first data peak value under the bit width to obtain data after the limiting process; The data after the clipping process is determined as the filtered data.

6. A filter data processing device, characterized in that: The device comprises: An acquisition module, configured to acquire input data, wherein the input data is bit stream data; A search module is configured to search a pre-stored lookup table for a target output bit width corresponding to the input data based on pre-configured filtering parameters, wherein the pre-stored lookup table includes at least a correspondence between the input data bit width, a decimation rate, a filter differential delay, a filter order, and a data peak value at the output bit width; the filtering parameters include at least the decimation rate and the filter order; the integrator, decimator, and differentiator in the multi-stage CIC filter are configured with respect to the decimation rate and the filter order based on the target output bit width, thereby filtering the input data; and the cascaded integrator, decimator, and cascaded differentiator are respectively subjected to a limiting process using the target output bit width, wherein the cascaded integrator is integrated on the input data to obtain integrated data; the multi-stage CIC filter includes at least a plurality of integrators, a decimator, and a plurality of differentiators; an integration module, configured to integrate the input data using a cascade integrator according to the target output bit width to obtain integrated data; An extraction module is used to extract samples from the integrated data using a decimator according to the target output bit width to obtain sampled data; a differentiation module, configured to perform differentiation processing on the sampled data using a cascade differentiator according to the target output bit width to obtain filtered data corresponding to the input data; perform amplitude limiting processing on the data during the integration, decimation, and differentiation operations to obtain differentiated data; and further perform amplitude limiting processing on the differentiated data using a first data peak value to obtain final filtered target data, wherein the first data peak value is calculated based on the decimation rate and the number of filter stages at the output bit width; For the input bit stream data, the bit width can be dynamically adjusted during the filtering process. If the bit width of the input data changes, the bit width can be further processed by modifying the lookup table, that is, it can be used for bit width optimization and data limiting under dynamic adjustment of the decimation rate and filter level. Wherein: the pre-stored lookup table is obtained in the following manner: Calculate the logarithmic value based on the decimation rate and the filter differential delay; Calculating a first product according to the logarithmic value and the filter order; Calculating an initial output bit width according to the first product and the input data bit width; Rounding up the initial output bit width to obtain an output bit width; the output bit width is used to process the integrator, the decimator, the differentiator and the limiter output unit respectively; Determine the correspondence between the input data bit width, the decimation rate, the filter differential delay, the filter order, the output bit width, and the data peak value under the output bit width as the lookup table; The first data peak value under the output bit width is calculated based on the decimation rate and the number of filter stages.

7. An electronic device, characterized in that: The invention comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor can implement the filter data processing method according to any one of claims 1 to 5 when executing the program.

8. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein when the program is executed by a processor, the filter data processing method according to any one of claims 1 to 5 can be implemented.

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