Display panel, driving method thereof and display device

Abstract

The invention relates to the technical field of display, in particular to a display panel, a driving method thereof and a display device. The display panel comprises a gate drive circuit, a compensation circuit, a compensation signal line and two power supply signal lines, the gate drive circuit is connected with the two power supply signal lines respectively, and the gate drive circuit is used for outputting gate drive signals according to two power supply signals provided by the two power supply signal lines respectively; the compensation circuit is respectively connected with the compensation signal line and a target power supply signal line, and the compensation circuit is used for selectively conducting a path between the compensation signal line and the target power supply signal line; wherein the target power supply signal line is one of the two power supply signal lines, and the absolute value of a compensation signal provided by the compensation signal line is greater than the absolute value of a target power supply signal provided by the target power supply signal line. According to the invention, flat and burr-free gate driving signals can be output, so that the display effect is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a driving method thereof, and a display device. Background Art

[0002] The display panel is provided with a gate driving circuit for providing a gate driving signal to the pixel circuit to control the pixel circuit in the display panel to drive row by row. In the prior art, the gate driving signal output by the gate driving circuit has an abnormal waveform, which causes the pixel circuit to work abnormally, thereby making the display effect of the display panel poor. Summary of the invention

[0003] Based on this, it is necessary to provide a display panel and a driving method thereof and a display device to address the above technical problems, which can output a flat and burr-free gate driving signal to improve the display effect.

[0004] In a first aspect, an embodiment of the present application provides a display panel, including a gate drive circuit, a compensation circuit, a compensation signal line, and two power signal lines, wherein:

[0005] The gate drive circuit is connected to the two power signal lines respectively, and the gate drive circuit is used to output a gate drive signal according to two power signals respectively provided by the two power signal lines;

[0006] The compensation circuit is connected to the compensation signal line and the target power signal line respectively, and is used to select a path between the compensation signal line and the target power signal line; wherein the target power signal line is one of the two power signal lines, and the absolute value of the compensation signal provided by the compensation signal line is greater than the absolute value of the target power signal provided by the target power signal line.

[0007] In one embodiment, the two power signal lines include a first power signal line and a second power signal line, the first power signal line provides a first power signal that is greater than the second power signal provided by the second power signal line, and the gate drive circuit is used to connect to a target transistor of the pixel circuit, wherein:

[0008] The target transistor is an N-type transistor, and the target power signal line is the first power signal line; or,

[0009] The target transistor is a P-type transistor, and the target power signal line is the second power signal line.

[0010] In one embodiment, the display panel further includes a first control signal line, the compensation circuit includes at least one first compensation module, the first compensation module includes a storage unit, a first gating unit and a second gating unit, wherein:

[0011] In the same first compensation module, the first gating unit is respectively connected to the first control signal line, the compensation signal line, and the first end of the storage unit, the first gating unit receives a first control signal provided by the first control signal line, and the first gating unit is used to select and conduct a path between the compensation signal line and the first end of the storage unit;

[0012] The second end of the storage unit receives a reference signal;

[0013] In the same first compensation module, the second gating unit is respectively connected to the first end of the storage unit, the target power signal line, and the output end of the gate drive circuit, the second gating unit receives the gate drive signal, and the second gating unit is used to select and conduct the path between the first end of the storage unit and the target power signal line.

[0014] In one embodiment, the effective pulse end time of the first control signal is earlier than the effective pulse start time of the gate drive signal.

[0015] In one of the embodiments, the first end of the storage unit is used to store the compensation signal when the first gating unit is in a conducting state;

[0016] The second gating unit applies the compensation signal stored at the first end of the storage unit to the target power signal line in response to an effective pulse of the gate driving signal.

[0017] In one embodiment, the gate drive circuit is used to connect to the pixel circuit, the display panel also includes two pixel power signal lines and an initialization signal line, the pixel circuit is connected to the two pixel power signal lines and the initialization signal line respectively, and the second end of the storage unit is connected to any one of the two pixel power signal lines and the initialization signal line.

[0018] In one of the embodiments, the display panel further includes at least one of a ground signal line and an external power signal line, and the second end of the storage unit is connected to any one of the ground signal line and the external power signal line.

[0019] In one embodiment, the first selection unit includes a first transistor, a first electrode of the first transistor is connected to the compensation signal line, a second electrode of the first transistor is connected to the first end of the storage unit of the same first compensation module, and a gate of the first transistor is connected to the first control signal line.

[0020] In one embodiment, the first transistor includes a P-type transistor or an N-type transistor.

[0021] In one embodiment, the second selection unit includes a second transistor, a first electrode of the second transistor is connected to the first end of the storage unit of the same first compensation module, a second electrode of the second transistor is connected to the target power signal line, and a gate of the second transistor is connected to the output end of the gate drive circuit.

[0022] In one embodiment, the gate driving circuit is used to connect to a target transistor of the pixel circuit, and the second transistor is of the same type as the target transistor.

[0023] In one embodiment, the storage unit includes a capacitor, a first electrode of the capacitor is respectively connected to the first gating unit and the second gating unit of the same first compensation module, and a second electrode of the capacitor is used to receive the reference signal.

[0024] In one embodiment, the gate driving circuit includes a plurality of cascaded gate driving units, and the compensation circuit includes a plurality of the first compensation modules, wherein the output end of the i-th gate driving unit is connected to the second gating unit of the i-th first compensation module, i≥1.

[0025] In one embodiment, the second selection unit of the i-th first compensation module applies the compensation signal stored at the first end of the storage unit of the i-th first compensation module to the target power signal line in response to the valid pulse of the gate driving signal output by the i-th gate driving unit.

[0026] In one embodiment, the gate driving units are arranged in columns, and the first compensation modules are arranged in columns.

[0027] In one embodiment, the i-th first compensation module is arranged in the same row as the i-th stage gate driving unit.

[0028] In one embodiment, the i-th first compensation module is arranged in the same row as the i+1-th gate driving unit.

[0029] In one embodiment, the display panel also includes a second control signal line, the compensation circuit includes at least one second compensation module, the second compensation module includes a third gating unit, the third gating unit is respectively connected to the second control signal line, the compensation signal line, and the target power signal line, the third gating unit receives a second control signal provided by the second control signal line, and the third gating unit is used to select and conduct a path between the compensation signal line and the target power signal line.

[0030] In one embodiment, the third selection unit applies the compensation signal to the target power signal line in response to the valid pulse of the second control signal; wherein the start time of at least one valid pulse of the second control signal is the same as the start time of the valid pulse of the gate drive signal.

[0031] In one embodiment, the gate drive circuit is also configured with a clock signal line, the gate drive circuit is connected to the clock signal line, the gate drive circuit is used to output the gate drive signal according to the two power supply signals and the clock signal provided by the clock signal line, and the frequency of the second control signal is the same as the frequency of the clock signal.

[0032] In one of the embodiments, the gate driving circuit includes a plurality of cascaded gate driving units, and the compensation circuit includes a plurality of second compensation modules, wherein the number of the gate driving units is greater than or equal to the number of the second compensation modules.

[0033] In one embodiment, the gate driving units are arranged in columns, and the second compensation modules are arranged in columns.

[0034] In one embodiment, the second compensation module is disposed in the same row as at least a portion of the gate driving unit.

[0035] In one embodiment, the number of rows of the gate driving units between any two adjacent second compensation modules is the same.

[0036] In one embodiment, at least part of the effective pulses of the second control signal start at the same time as at least part of the effective pulses of the gate driving signal output by the gate driving unit start at the same time.

[0037] In one embodiment, the third selection unit includes a third transistor, a first electrode of the third transistor is connected to the compensation signal line, a second electrode of the third transistor is connected to the target power signal line, and a gate of the third transistor is connected to the second control signal line.

[0038] In one embodiment, the third transistor includes a P-type transistor or an N-type transistor.

[0039] In a second aspect, an embodiment of the present application provides a method for driving a display panel, which is applied to the display panel as described above. The method for driving a display panel includes:

[0040] The compensation module of the control gate driving circuit selects and conducts the path between the compensation signal line and the target power supply signal line.

[0041] In a third aspect, an embodiment of the present application provides a display device, comprising the display panel as described above.

[0042] The display panel and its driving method and display device provided in the embodiments of the present application can open the path between the compensation signal line and the target power signal line through the compensation circuit to apply the compensation signal to the target power signal line, so that the charge requirement of the target power signal line when the gate drive circuit outputs a valid pulse of the gate drive signal can be compensated by the compensation signal, thereby improving the burr problem caused by the target power signal line being unable to meet the charge requirement. In other words, in the related art, the target power signal line generates burrs because it cannot meet the charge requirement when the gate drive circuit outputs a valid pulse of the gate drive signal. In this regard, the display panel provided in the embodiments of the present application applies the compensation signal to the target power signal line when the gate drive circuit outputs a valid pulse of the gate drive signal, which is equivalent to generating burrs in the opposite direction. The two reverse burrs cancel each other out, thereby obtaining a flat and burr-free target power signal waveform, and then obtaining a flat and burr-free gate drive signal waveform, which helps to improve the display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0044] Figure 1 is a waveform diagram of a gate driving signal with glitches;

[0045] Figure 2 One of the structural schematic diagrams of a display panel provided in an embodiment of the present application;

[0046] Figure 3 A second structural schematic diagram of a display panel provided in an embodiment of the present application;

[0047] Figure 4 A third structural schematic diagram of a display panel provided in an embodiment of the present application;

[0048] Figure 5 A fourth structural schematic diagram of a display panel provided in an embodiment of the present application;

[0049] Figure 6 A fifth structural diagram of a display panel provided in an embodiment of the present application;

[0050] Figure 7One of the waveform diagrams of a gate driving signal provided in an embodiment of the present application;

[0051] Figure 8 A second waveform diagram of a gate driving signal provided in an embodiment of the present application;

[0052] Fig. 9 A sixth structural diagram of a display panel provided in an embodiment of the present application;

[0053] Fig.10 A seventh structural diagram of a display panel provided in an embodiment of the present application;

[0054] Fig.11 A third waveform diagram of a gate driving signal provided in an embodiment of the present application;

[0055] Fig.12 A fourth waveform diagram of a gate driving signal provided in an embodiment of the present application;

[0056] Fig.13 A schematic diagram of a flow chart of a method for driving a display panel provided in an embodiment of the present application;

[0057] Fig.14 A schematic diagram of the structure of a display device provided in an embodiment of the present application.

[0058] Description of reference numerals:

[0059] 1-display panel, 10-gate driving circuit, 20-compensation circuit, 210-first compensation module, 220-second compensation module, 1000-display device. DETAILED DESCRIPTION

[0060] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present application more thorough and comprehensive.

[0061] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0062] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.

[0063] In the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity. It is understood that when a layer or element is referred to as being "on" another layer or substrate, the layer or element may be directly on the other layer or substrate, or there may be intervening layers. In addition, it is also understood that when a layer is referred to as being "between" two layers, the layer may be the only layer between the two layers, or there may be one or more intervening layers. In addition, the same reference numerals always represent the same elements.

[0064] In the following embodiments, when a layer, region, or element is "connected", it can be interpreted that the layer, region, or element is not only directly connected but also connected through other constituent elements placed therebetween. For example, when a layer, region, element, etc. is described as being connected or electrically connected, the layer, region, element, etc. can be connected or electrically connected not only directly or directly, but also through another layer, region, element, etc. placed therebetween.

[0065] Hereinafter, although terms such as "first", "second", etc. may be used to describe various components, these components are not necessarily limited to the above terms. The above terms are only used to distinguish one component from another. It will also be understood that expressions used in the singular include plural expressions unless the expression in the singular has an obviously different meaning in the context.

[0066] When a statement such as "at least one (of)..." is located after a list of elements, it modifies the entire list of elements rather than the individual elements in the list. The term "and / or" as used herein includes any and all combinations of one or more related listed items. As used in the application documents, the term "and / or" includes any and all combinations of one or more related listed items. It should also be understood that the terms "include / comprise" or "have" etc. specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof.

[0067] Electronic or electrical devices and / or any other related devices or components according to the embodiments of the concepts of the present application described herein (for example, a display device including a display panel and a display panel driver, wherein the display panel driver also includes a drive controller, a gate driver, a gamma reference voltage generator, a data driver, and an emission driver) can be implemented using any appropriate hardware, firmware (such as a dedicated integrated circuit), software, or a combination of software, firmware, and hardware. For example, the various components of these devices may be formed on an integrated circuit (IC) chip or on separate IC chips. In addition, the various components of these devices may be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on a substrate. In addition, the various components of these devices may be processes or threads that run on one or more processors in one or more computing devices to execute computer program instructions and interact with other system components to perform the various functions described herein. The computer program instructions are stored in a memory that can be implemented in a computing device using standard storage devices (e.g., such as random access memory (RAM). The computer program instructions can also be stored in other non-transitory computer-readable media (e.g., such as CD-ROMs, flash drives, etc.). Moreover, those skilled in the art should recognize that the functions of various computing devices can be combined or integrated into a single computing device, or the functions of a particular computing device can be distributed on one or more other computing devices without departing from the spirit and scope of the exemplary embodiments of the concepts of the present application.

[0068] Although exemplary embodiments of display modules and display devices including display modules have been specifically described herein, many modifications and variations will be apparent to those skilled in the art. Therefore, it will be understood that display modules and display devices including display modules constructed according to the principles of the present application may be implemented in addition to those specifically described herein. The present application is also defined in the claims and their equivalents.

[0069] The display panel is provided with a gate drive circuit or a gate circuit (GIP) for outputting a periodic gate drive signal Gout to drive the pixel circuit in the display panel. The GIP circuit needs at least two power supply signals VGH and VGL to provide support for outputting the gate drive signal. The level of the gate drive signal jumps periodically. At the moment when the level state of the gate drive signal jumps, the GIP circuit will generate an instantaneous charge demand. Since the GIP circuit is not strong enough to resist instantaneous current, the power supply signal VGH or the power supply signal VGL cannot meet the instantaneous charge demand or the charging and discharging demand. Therefore, the power supply signal VGH or the power supply signal VGL will generate periodic glitches, which will cause the gate drive signal Gout output by the GIP circuit based on the power supply signals VGH and VGL to also have periodic glitches. Figure 1 Provides an output waveform of a gate drive signal with periodic glitches. Figure 1 The gate driving signal shown drives the pixel circuit of the display panel, which may affect the display effect of the display panel.

[0070] In order to solve the above technical problems, the present application provides a display panel, a driving method thereof and a display device, which compensates the power supply signal through a compensation signal, thereby offsetting the glitches caused by the instantaneous charge demand generated by the gate drive signal, improving the output waveform of the gate drive signal, and thus improving the display effect.

[0071] Figure 2 A schematic diagram of the structure of a display panel provided in an embodiment of the present application is shown in FIG. Figure 3 A schematic diagram of the structure of another display panel provided in an embodiment of the present application. Figure 2 and Figure 3 As shown, in one embodiment, a display panel is provided, which includes a gate drive circuit 10, a compensation circuit 20, a compensation signal line and two power signal lines. The compensation signal line is used to provide a compensation signal VH or VL. The two power signal lines are used to provide different power signals, respectively. Exemplarily, the two power signal lines include a first power signal line and a second power signal line, wherein the first power signal line is used to provide a first power signal VGH, and the second power signal line is used to provide a second power signal VGL, and the first power signal VGH is different from the second power signal VGL. For ease of description, in the embodiment of the present application, the first power signal VGH is taken as a high-level signal and the second power signal VGL is taken as a low-level signal as an example.

[0072] The gate drive circuit 10 is connected to two power signal lines respectively. The gate drive circuit 10 is used to output a gate drive signal according to two power signals provided by the two power signal lines respectively. The compensation circuit 20 is connected to the compensation signal line and the target power signal line respectively. The compensation circuit 20 is used to select a path between the compensation signal line and the target power signal line. Among them, the target power signal line is one of the two power signal lines, and the absolute value of the compensation signal is greater than the absolute value of the target power signal provided by the target power signal line. Exemplarily, the target power signal line is the first power signal line, then the target power signal VH is greater than the first power signal VGH. In another exemplary embodiment, the target power signal line is the second power signal line, then the target power signal VL is less than the second power signal VGL.

[0073] In applications, the compensation signal line and the target power signal line can be turned on by the compensation circuit 20 to apply the compensation signal VH or VL to the target power signal line, thereby compensating the charge demand of the target power signal line through the compensation signal VH. In applications, when the gate drive circuit 10 outputs a valid pulse of the gate drive signal, an instantaneous charge demand will be generated. In response to this, the compensation circuit 20 can be controlled to turn on the compensation signal line and the target power signal line, and the compensation signal VH or VL can be applied to the target power signal line to offset the glitches generated by the output gate drive signal. The target power signal has the same level state as the effective level of the gate drive signal. The effective level of the gate drive signal includes a high level or a low level. As Figure 2 As shown, when the effective level of the gate drive signal is high, the target power signal is a high level signal, and the target power signal line is the first power signal line. Figure 3 As shown, when the effective level of the gate driving signal is a low level, the target power signal is a low level signal, and the target power signal line is the second power signal line.

[0074] The above-mentioned display panel can conduct the path between the compensation signal line and the target power signal line through the compensation circuit 20 to apply the compensation signal VH or VL to the target power signal line, thereby compensating the charge demand generated by the gate drive circuit 10 outputting the gate drive signal valid pulse on the target power signal line through the compensation signal VH or VL, and can improve the burr problem caused by the target power signal line being unable to meet the charge demand. In other words, in the related art, the target power signal line generates burrs because it cannot meet the instantaneous charge demand of the gate drive circuit 10 outputting the gate drive signal. In this regard, the display panel provided in the embodiment of the present application applies the compensation signal VH or VL to the target power signal line when the gate drive circuit 10 outputs the gate drive signal valid pulse, which is equivalent to generating burrs in the opposite direction. The two reverse burrs cancel each other out, and a flat and burr-free target power signal waveform can be obtained, and then a flat and burr-free gate drive signal waveform can be obtained, which is helpful to improve the display effect of the display panel, especially in application scenarios such as variable frequency direct cutting and partition multi-frequency, the display effect is significantly improved, and the waveform debugging window is also smaller.

[0075] Please continue reading Figure 2 and Figure 3 In one embodiment, the two power signal lines include a first power signal line and a second power signal line, and the first power signal VGH provided by the first power signal line is greater than the second power signal VGL provided by the second power signal line. The gate drive circuit 10 is used to connect to the target transistor of the pixel circuit. Specifically, the output end of the gate drive circuit 10 is used to connect to the gate of the target transistor of the pixel circuit.

[0076] For example, Figure 2 As shown, the target transistor is an N-type transistor, and the gate of the N-type transistor is turned on in response to a high-level signal, that is, the effective level of the gate drive signal is a high level, then the target power signal is a high-level signal, the target power signal line is the first power signal line, and the compensation signal VH is greater than the first power signal VGH.

[0077] In an application, the compensation signal line and the first power signal line can be connected through the compensation circuit 20, and a high-level compensation signal VH can be applied to the first power signal line, and the compensation signal VH is greater than the first power signal VGH, so that the charge demand on the first power signal line generated when the gate drive signal outputs a valid high level is compensated by the compensation signal VH, that is, the high level output of the gate drive signal will cause the first power signal VGH to generate downward burrs, and the compensation signal VH provided in the embodiment of the present application can cause the first power signal VGH to generate upward burrs, and the two reverse glitches cancel each other out, thereby obtaining a flat and glitch-free first power signal VGH waveform and a gate drive signal waveform.

[0078] Another exemplary example is Figure 3 As shown, the target transistor is a P-type transistor, and the gate of the P-type transistor is turned on in response to a low-level signal, that is, the effective level of the gate drive signal is a low level, then the target power signal is a low-level signal, the target power signal line is the second power signal line, and the compensation signal VL is less than the second power signal VGL.

[0079] In application, the compensation signal line and the first power signal line can be compensated by the compensation circuit 20, and a low-level compensation signal VL can be applied to the second power signal line, and the compensation signal VL is smaller than the second power signal VGL, so that the charge demand on the second power signal line when the gate drive signal outputs a valid low level is compensated by the compensation signal VL, that is, the low level output of the gate drive signal will cause the second power signal VGL to generate an upward burr, and the compensation signal VL provided in the embodiment of the present application can cause the second power signal VGL to generate a downward burr, and the two reverse glitches cancel each other out, thereby obtaining a flat and burr-free second power signal VGL waveform and a gate drive signal waveform.

[0080] Figure 4 A schematic diagram of the structure of a display panel provided in an embodiment of the present application is shown in FIG. Figure 5 A schematic diagram of the structure of another display panel provided in an embodiment of the present application, Figure 6 A schematic diagram of the structure of another display panel provided in an embodiment of the present application is shown in FIG. Figure 7 A waveform diagram of a gate drive signal provided in an embodiment of the present application is shown in FIG. Figure 8 A waveform diagram of another gate drive signal provided in an embodiment of the present application. Figures 4 to 8 As shown, in one embodiment, the display panel further includes a first control signal line, and the first control signal line is used to provide a first control signal Reset. The compensation circuit 20 includes at least one first compensation module 210. The first compensation module 210 includes a storage unit, a first gating unit and a second gating unit.

[0081] In the same first compensation module 210, the first gating unit is connected to the first control signal line, the compensation signal line, and the first end of the storage unit respectively. The first gating unit receives the first control signal Reset provided by the first control signal line. The first gating unit is used to select the path between the compensation signal line and the first end of the storage unit.

[0082] The second end of the storage unit is used to receive a reference signal Vx, wherein the reference signal Vx is a DC signal with a fixed level, and the reference signal Vx is used to stabilize the potential of the second end of the storage unit.

[0083] In the same first compensation module 210, the second gating unit is respectively connected to the first end of the storage unit, the target power signal line, and the output end of the gate driving circuit 10. The second gating unit receives the gate driving signal output by the gate driving circuit 10. The second gating unit is used to select a path between the first end of the storage unit and the target power signal line.

[0084] Exemplarily, the first end of the storage unit can be used to store the compensation signal VH or VL when the first gating unit is in a conductive state. The second gating unit is used to conduct the path between the first end of the storage unit and the target power signal line in response to the effective pulse of the gate drive signal to apply the compensation signal VH or VL to the target power signal line.

[0085] The gate drive circuit 10 controls the first selection unit to select and conduct the path between the compensation signal line and the first end of the storage unit through the first control signal Reset, and controls the second selection unit to select and conduct the path between the first end of the storage unit and the target signal line through the gate drive signal, and when the first selection unit conducts the path between the compensation signal line and the first end of the storage unit, the compensation signal VH or VL is stored in the first end of the storage unit, and when the second selection unit responds to the effective level of the gate drive signal, the path between the first end of the storage unit and the target signal line is turned on to apply the compensation signal VH or VL stored in the first end of the storage unit to the target power signal line, thereby compensating the charge demand generated when the gate drive signal output by the gate drive circuit 10 is at an effective level through the compensation signal VH or VL, and a flat and glitch-free gate drive signal waveform can be obtained. Figure 7 and Figure 8 As shown, it helps to improve the display effect.

[0086] Please continue reading Figure 7 and Figure 8 In one embodiment, the effective pulse end time of the first control signal is earlier than the effective pulse start time of the gate drive signal, that is, the effective pulse start time of the first control signal is earlier than the effective pulse start time of the gate drive signal, and the effective pulse of the first control signal does not overlap with the effective pulse of the gate drive signal. In the case where the gate drive circuit 10 includes a plurality of cascaded gate drive units GIPu, the effective pulse end time of the first control signal is earlier than the effective pulse start time of the gate drive signal output by each gate drive unit GIPu.

[0087] In the application, the first gating unit is turned on in response to the effective pulse output by the first control signal, so that the first end of the storage unit of each first compensation module 210 stores the compensation signal. Based on this, the second gating unit is turned on in response to the effective pulse of the gate driving signal output by the gate driving circuit 10, and the compensation signal stored at the first end of the storage unit is applied to the target power signal line, so as to compensate the instantaneous charge demand generated by the output gate driving signal through the compensation signal, so as to obtain a relatively flat gate driving signal, thereby improving the display effect of the display panel.

[0088] Please continue reading Figures 4 to 8 In one embodiment, the gate drive circuit 10 is used to connect to the pixel circuit. Specifically, the output end of the gate drive circuit 10 is used to connect to the gate of the target transistor of the pixel circuit. The display panel also includes two pixel power signal lines and an initialization signal line. The pixel circuit is connected to the two pixel power signal lines and the initialization signal line, respectively. Among them, the two pixel power signal lines are used to provide two power signals ELVDD and ELVSS of different levels to the pixel circuit, respectively. The initialization signal line is used to provide an initialization signal VREF to the pixel circuit. The second end of the storage unit is connected to any one of the two pixel power signal lines and the initialization signal line. That is, any one of the two pixel power signal lines and the initialization signal line can be selected to provide a reference signal Vx to the second end of the storage unit. In this way, the signal lines in the display panel can be reused, which can reduce costs and occupied area.

[0089] Please continue reading Figures 4 to 8 In one embodiment, the display panel further includes at least one of a ground signal line and an external power signal line. The ground signal line is used to provide a ground signal GND. The external power signal line is used to provide an external power signal. The second end of the storage unit is connected to any one of the ground signal line and the external power signal line. That is, any one of the ground signal line and the external power signal line can be selected to provide a reference signal Vx for the second end of the storage unit. In this way, the potential of the second end of the storage unit can be stabilized by additionally designing a ground signal line or an external power signal line.

[0090] Please continue reading Figures 4 to 8In one embodiment, the first selection unit includes a first transistor T1, a first electrode of the first transistor T1 is connected to the compensation signal line, a second electrode of the first transistor T1 is connected to the first end of the storage unit of the same first compensation module 210, and a gate of the first transistor T1 is connected to the first control signal line. The first transistor T1 is used to select and conduct the path between the compensation signal line and the first end of the storage unit in response to the first control signal Reset provided by the first control signal line. Based on this, by controlling the first transistor T1 through the first control signal Reset, the on-off state of the path between the compensation signal line and the first end of the storage unit can be effectively controlled, and when the first transistor T1 is in the on state, the first end of the storage unit can store the compensation signal VH or VL provided by the compensation signal line.

[0091] Please continue reading Figures 4 to 8 In one embodiment, the first transistor T1 includes an N-type transistor or a P-type transistor. Figure 4 and Figure 6 As shown, the first transistor T1 includes an N-type transistor, and the first transistor T1 is turned on in response to a high-level first control signal Reset, and the first transistor T1 is turned off in response to a low-level first control signal Reset. Figure 5 As shown, the first transistor T1 includes a P-type transistor, and the first transistor T1 is turned on in response to a low-level first control signal Reset, and the first transistor T1 is turned off in response to a high-level first control signal Reset. In practical applications, the type of the first transistor T1 can be arbitrarily selected and the corresponding first control signal line can be configured, which is not limited here.

[0092] Please continue reading Figures 4 to 8In one embodiment, the second selection unit includes a second transistor T2, the first electrode of the second transistor T2 is connected to the first end of the storage unit of the same first compensation module 210, the second electrode of the second transistor T2 is connected to the target power signal line, and the gate of the second transistor T2 is connected to the output end of the gate driving circuit 10. The second transistor T2 is used to select and conduct the path between the first end of the storage unit and the target power signal line in response to the gate driving signal output by the gate driving circuit 10. Specifically, the second transistor T2 is used to conduct the path between the first end of the storage unit and the target power signal line in response to the effective pulse of the gate driving signal. Based on this, the on-off state of the path between the first end of the storage unit and the target power signal line can be effectively controlled by controlling the second transistor T2 through the gate driving signal, and when the second transistor T2 is in the on state, the compensation signal VH or VL stored at the first end of the storage unit can be applied to the target power signal line, so as to compensate the charge demand generated when the gate driving signal outputs the effective level through the compensation signal VH or VL, thereby obtaining a flat and burr-free gate driving signal waveform, which helps to improve the display effect.

[0093] Please continue reading Figures 4 to 8 In one embodiment, the gate drive circuit 10 is used to connect to the target transistor of the pixel circuit. Specifically, the output end of the gate drive circuit 10 is used to connect to the gate of the target transistor of the pixel circuit. The second transistor T2 is of the same type as the target transistor. For example, Figure 4 and Figure 6 As shown, the target transistor is an N-type transistor, and the second transistor T2 is an N-type transistor. In this case, the effective level of the gate drive signal is a high level, the target power signal line is the first power signal line, and the compensation signal VH is greater than the first power signal VGH. Figure 5 As shown, the target transistor is a P-type transistor, and the second transistor T2 is a P-type transistor. In this case, the effective level of the gate drive signal is a low level, the target power signal line is the second power signal line, and the compensation signal VL is less than the second power signal VGL. In practical applications, the same type of second transistor T2 can be selected according to the type of the target transistor in the pixel circuit driven by the gate drive circuit 10, so as to achieve effective control of the second transistor T2 by the gate drive signal.

[0094] Please continue reading Figures 4 to 8In one embodiment, the storage unit includes a capacitor C, the first electrode of the capacitor C is respectively connected to the first selection unit and the second selection unit of the same first compensation module 210, and the second electrode of the capacitor C is used to receive the reference signal Vx. The first electrode of the capacitor C is used to store the compensation signal VH or VL when the first selection unit is in the on state, so that the charge is stored through the first electrode of the capacitor C. Based on this, when the second selection unit is in the on state, the charge is released to the target power signal line through the first electrode of the capacitor C, so as to realize the charge compensation of the target power signal line, so as to obtain a flat gate drive signal waveform without burrs.

[0095] Please continue reading Figures 4 to 8 The gate drive circuit 10 includes a plurality of cascaded gate drive units GIPu. The compensation circuit 20 includes a plurality of first compensation modules 210. The number of gate drive units and first compensation modules 210 can be set according to actual needs, and no further restrictions are made here. Exemplarily, the number of gate drive units GIPu is the same as the number of first compensation modules 210.

[0096] The output end of the i-th gate driving unit GIPu is connected to the second gating unit of the i-th first compensation module 210. Wherein, i≥1. The output ends of the gate driving units GIPu of different levels are connected to different first gating units. Exemplarily, in the case where the second gating unit includes a second transistor T2, the output end of the i-th gate driving unit is connected to the gate of the second transistor T2 of the i-th first compensation module 210. For example, Figure 4 and Figure 5 In the display panel shown, the output end of the first-stage gate driving unit GIPu is connected to the gate of the first second transistor T2 in the same row, the output end of the second-stage gate driving unit GIPu is connected to the gate of the second second transistor T2 in the same row, and so on to the last-stage gate driving unit GIPu. Figure 6 In the display panel shown, the output end of the first-level gate driving unit GIPu is connected to the gate of the first second transistor T2 in the second row, the output end of the second-level gate driving unit GIPu is connected to the gate of the second second transistor T2 in the third row, and so on to the last-level gate driving unit GIPu.

[0097] The second gating unit of the i-th first compensation module 210 is used to select and conduct the path between the first end of the storage unit of the i-th first compensation module 210 and the target power signal line in response to the gate driving signal output by the i-th gate driving unit GIPu. That is, the second gating unit of the i-th first compensation module 210 is controlled by the gate driving signal output by the i-th gate driving unit GIPu, thereby controlling the on-off state between the first end of the storage unit of the i-th first compensation module 210 and the target power signal line.

[0098] Please continue reading Figures 4 to 8 In one embodiment, the second selection unit of the i-th first compensation module 210 applies the compensation signal stored at the first end of the storage unit of the i-th first compensation module 210 to the target power signal line in response to the valid pulse of the gate driving signal output by the i-th gate driving unit GIPu.

[0099] In the application, before each gate driving unit GIPu outputs a valid pulse of a gate driving signal, each first compensation module 210 is turned on in response to a valid pulse of a first control signal Reset provided by the first control signal line, so that the first end of each storage unit stores the compensation signal. Based on this, the second gating unit of the i-th first compensation module 210 applies the compensation signal stored at the first end of the storage unit of the i-th first compensation module 210 to the target power signal line in response to the valid pulse of the gate driving signal output by the i-th gate driving unit GIPu. It can be understood that the gate driving unit GIPu outputs the gate driving signal step by step starting from the first level. Therefore, starting from the second selection unit of the first compensation module 210, it responds to the effective pulse of the gate driving signal output by the gate driving unit GIPu of the corresponding level in sequence, and is turned on one by one in time-sharing until the second selection unit of the last first compensation module 210, so that when the gate driving units GIPu of each level output the effective pulse of the gate driving signal, the compensation signal is applied to the target power line through the corresponding first compensation module 210, so as to avoid the effective pulse of the gate driving signal output by the gate driving units GIPu of each level to generate burrs, so that the gate driving units GIPu of each level can respectively output flat and burr-free gate driving signals, thereby improving the display effect of the display panel.

[0100] Please continue reading Figures 4 to 6 In one embodiment, the gate drive unit GIPu is arranged in columns, and the first compensation module 210 is arranged in columns. That is, the gate drive unit GIPu and the first compensation module 210 are arranged along the column direction of the pixel circuit, respectively. In this way, by regularly arranging the gate drive unit GIPu and the first compensation module 210, it is beneficial to shorten the signal routing, reduce the occupied area, and achieve a narrow border. Exemplarily, the first compensation module 210 is arranged close to the gate drive unit GIPu. In this way, the routing between the gate drive unit GIPu and the first compensation module 210 can be further reduced, the delay caused by signal transmission can be reduced, and the timeliness of the compensation signal compensating the target power supply signal can be improved to obtain a relatively flat gate drive signal and improve the display effect of the display panel.

[0101] Please continue reading Figure 4 and Figure 5In one embodiment, the i-th first compensation module 210 is arranged in the same row as the i-th gate driving unit GIPu. Figure 5 As shown, the first compensation modules 210 and the gate driving units GIPu are arranged in columns, and the first first compensation module 210 is arranged in the same row as the first-level gate driving unit GIPu, the second first compensation module 210 is arranged in the same row as the second-level gate driving unit GIPu, and so on until the last row.

[0102] It can be understood that the second selection unit of the i-th first compensation module 210 is connected to the output end of the i-th gate driving unit GIPu. Therefore, by setting the i-th first compensation module 210 and the i-th gate driving unit GIPu in the same line, the signal routing between the i-th gate driving unit GIPu and the i-th first compensation module 210 can be shortened, the delay caused by signal transmission can be reduced, and the timeliness of the compensation signal compensating the target power supply signal can be improved to obtain a relatively flat gate driving signal and improve the display effect of the display panel.

[0103] Please continue reading Figure 6 In one embodiment, the i-th first compensation module 210 is arranged in the same row as the i+1-th gate driving unit. The first-stage gate driving unit GIPu and the last first compensation module 210 are arranged separately, or in other words, the first row is only provided with the first-stage gate driving unit GIPu, the last row is only provided with the last first compensation module 210, and the second row to the second-to-last row are respectively provided with a first compensation module 210 and a first-stage gate driving unit GIPu. Exemplarily, as Figure 6 As shown, the first compensation modules 210 and the gate driving units GIPu are arranged in columns, and the first-level gate driving unit GIPu is set separately, the first first compensation module 210 is set in the same row as the second-level gate driving unit GIPu, the second first compensation module 210 is set in the same row as the third-level gate driving unit GIPu, and so on until the second-to-last first compensation module 210 is set in the same row as the last-level gate driving unit GIPu, and the last first compensation module 210 is set separately.

[0104] It can be understood that the i-th first compensation module 210 is close to the i+1-th gate driving unit GIPu. Therefore, by setting the i-th first compensation module 210 and the i+1-th gate driving unit GIPu in the same line, the signal routing between the i-th gate driving unit GIPu and the i-th first compensation module 210 can be shortened, the delay caused by signal transmission can be reduced, and the timeliness of the compensation signal compensating the target power supply signal can be improved to obtain a relatively flat gate driving signal and improve the display effect of the display panel.

[0105] Fig. 9A schematic diagram of the structure of a display panel provided in an embodiment of the present application is shown in FIG. Fig.10 A schematic diagram of the structure of another display panel provided in an embodiment of the present application, Fig.11 A waveform diagram of a gate drive signal provided in an embodiment of the present application is shown in FIG. Fig.12 A waveform diagram of another gate drive signal provided in an embodiment of the present application. Figures 9 to 12 As shown, in one embodiment, the display panel further includes a second control signal line, and the second control signal line is used to provide a second control signal SYNC. The compensation circuit 2020 includes at least one second compensation module 220. The number of the second compensation modules 220 can be 1, 2, 3 or any other value greater than 3, which can be set according to the needs and is not limited here.

[0106] The second compensation module 220 includes a third gating unit, which is respectively connected to the second control signal line, the compensation signal line, and the target power signal line. The third gating unit receives the second control signal SYNC provided by the second control signal line, and is used to select a path between the compensation signal line and the target power signal line.

[0107] Exemplarily, the third gating unit responds to the effective pulse of the second control signal and applies the compensation signal to the target power signal line. The starting time of at least one effective pulse of the second control signal is the same as the starting time of the effective pulse of the gate drive signal. For example, the second control signal includes a plurality of effective pulses, the gate drive circuit 10 includes a plurality of gate drive units GIPu, and the starting time of some effective pulses of the second control signal corresponds to the same as the starting time of the effective pulse of the gate drive signal output by each gate drive unit GIPu.

[0108] In the application, at the start time of the effective pulse of the gate drive signal output by the gate drive circuit 10, the third selection unit starts to conduct in response to the effective pulse of the second control signal, and applies the compensation signal VH or VL to the target power signal line. That is, when the gate drive signal output by the gate drive circuit 10 is at an effective level, the third selection unit is controlled by the second control signal SYNC to conduct the path between the compensation signal line and the target power signal line, and the compensation signal VH or VL is applied to the target power signal line, thereby compensating the charge demand of the target power signal line when the gate drive circuit 10 outputs the gate drive signal at an effective level through the compensation signal VH or VL, improving the burr problem caused by the target power signal line being unable to meet the charge demand, and being able to obtain a flat and burr-free waveform such as Fig.11 and Fig.12 As shown, it helps to improve the display effect of the display panel.

[0109] Please continue reading Figures 9 to 12In one embodiment, the gate drive circuit 10 is also configured with a clock signal line, the gate drive circuit 10 is connected to the clock signal line, and the gate drive circuit 10 is used to output a gate drive signal according to two power signals and a clock signal provided by the clock signal line. Among them, the frequency of the second control signal SYNC is less than or equal to the frequency of the clock signal. Exemplarily, the frequency of the second control signal SYNC is the same as the frequency of the clock signal. That is, at the moment when the gate drive signal outputs a valid level, the level state of the second control signal SYNC is synchronously adjusted, so as to meet the requirement of controlling the third selection unit to turn on the path between the compensation signal line and the target power signal line through the second control signal SYNC when the gate drive circuit 10 outputs a gate drive signal of a valid level.

[0110] Please continue reading Figures 9 to 12 In one embodiment, the third gating unit includes a third transistor T3, a first electrode of the third transistor T3 is connected to the compensation signal line, a second electrode of the third transistor T3 is connected to the target power signal line, and a gate of the third transistor T3 is connected to the second control signal line. The third transistor T3 is used to select the path between the compensation signal line and the target power signal line in response to the second control signal SYNC provided by the second control signal line. That is, the second compensation module 220 is a 1T0C structure, which further reduces the number of transistors and capacitors C, and is conducive to achieving the design requirements of a narrow frame. The gate drive circuit 10 controls the third transistor T3 through the second control signal SYNC, and can effectively control the on-off state of the path between the compensation signal line and the target power signal line, and when the third transistor T3 is in the on state, the compensation signal VH or VL can be applied to the target power signal line, so as to compensate the charge demand generated when the gate drive signal outputs an effective level through the compensation signal VH or VL, thereby obtaining a flat and burr-free gate drive signal waveform, which helps to improve the display effect. Since the third transistor T3 has an obvious impedance, the compensation signal line and the target power signal line are not short-circuited, but charges are injected into the target power signal line.

[0111] Please continue reading Figures 9 to 12 In one embodiment, the third transistor T3 includes an N-type transistor or a P-type transistor. Fig. 9 and Fig.11 As shown, the third transistor T3 includes an N-type transistor, and the third transistor T3 is turned on in response to the second control signal SYNC of a high level, and the third transistor T3 is turned off in response to the second control signal SYNC of a low level. Fig.10 and Fig.12As shown, the third transistor T3 includes a P-type transistor, and the third transistor T3 is turned on in response to the low-level second control signal SYNC, and the third transistor T3 is turned off in response to the high-level second control signal SYNC. In practical applications, the type of the third transistor T3 can be arbitrarily selected and the corresponding second control signal line can be configured, which is not limited here.

[0112] In one embodiment, the gate drive circuit 10 includes a plurality of cascaded gate drive units GIPu, and the compensation circuit 20 includes a plurality of second compensation modules 220, wherein the number of the gate drive units GIPu is greater than or equal to the number of the second compensation modules 220. The number of the second compensation modules 220 is greater than or equal to 1, and the number of the gate drive units GIPu can be determined according to factors such as the number of rows of the pixel circuit and the driving mode, and is not specifically limited here. It can be understood that the second compensation module 220 selects the path between the conductive compensation signal line and the target power line according to the second control signal. Therefore, by controlling the timing of the second control signal, the reverse compensation of the target power signal can be achieved, and a relatively flat gate drive signal can be obtained. There is no need to set a second compensation module 220 for each gate drive unit GIPu, which can reduce the number of second compensation modules 220 and reduce the occupied area.

[0113] In one embodiment, the gate drive unit GIPu is arranged in columns, and the second compensation module 220 is arranged in columns. That is, the gate drive unit GIPu and the second compensation module 220 are arranged along the column direction of the pixel circuit, respectively. In this way, by regularly arranging the gate drive unit GIPu and the second compensation module 220, it is beneficial to shorten the signal routing, reduce the occupied area, and achieve a narrow frame. Exemplarily, the second compensation module 220 is arranged close to the gate drive unit GIPu. In this way, the routing between the gate drive unit GIPu and the second compensation module 220 can be further reduced, the delay caused by signal transmission can be reduced, and the timeliness of the compensation signal compensating the target power supply signal can be improved to obtain a relatively flat gate drive signal and improve the display effect of the display panel.

[0114] In one embodiment, the second compensation module 220 is arranged in the same line as at least part of the gate drive units GIPu. For example, when the number of the second compensation modules 220 and the gate drive units GIPu is the same, the i-th level second compensation module 220 can be arranged in the same line as the i-th level gate drive unit GIPu, i≥1. For another example, when the number of the second compensation modules 220 is less than the number of the gate drive units GIPu, one second compensation module 220 is arranged in the same line as one gate drive unit GIPu, and the gate drive units GIPu arranged in the same line with different second compensation modules 220 are different. In this way, by arranging the second compensation module 220 in the same line as at least part of the gate drive units GIPu, the second compensation module 220 and the gate drive unit GIPu can be arranged regularly, which helps to reduce the wiring between the gate drive unit GIPu and the second compensation module 220, thereby reducing the delay caused by signal transmission, and improving the timeliness of the compensation signal compensating the target power supply signal, so as to obtain a relatively flat gate drive signal and improve the display effect of the display panel.

[0115] In one embodiment, the number of rows of gate drive units GIPu between any two adjacent second compensation modules 220 is the same. The number of rows of gate drive units GIPu between any two adjacent second compensation modules 220 can be 1, 2, 3 or any other value greater than 3, which is not limited here. Fig. 9 and Fig.10 In the display panel shown, the number of rows of the gate drive unit GIPu between any two adjacent second compensation modules 220 is 1, wherein the first second compensation module 220 is arranged in the same row as the first-level gate drive unit GIPu, the second second compensation module 220 is arranged in the same row as the third-level gate drive unit GIPu, the third second compensation module 220 is arranged in the same row as the fifth-level gate drive unit GIPu, and so on. In this way, one or more adjacent gate drive units GIPu are provided with a second compensation module 220, which helps to timely apply the compensation signal to the target power signal line through the second compensation module 220 at the start time of the effective pulse of the gate drive signal output by the gate drive unit GIPu, so as to obtain a flatter and burr-free gate drive signal waveform, thereby improving the display effect of the display panel.

[0116] In one embodiment, Fig.11 and Fig.12 As shown, the start time of at least part of the effective pulses of the second control signal is the same as the start time of the effective pulses of the gate drive signals output by at least part of the gate drive units GIPu. Exemplarily, the start time of part of the effective pulses of the second control signal is the same as the start time of the effective pulses of the gate drive signals output by each gate drive unit GIPu.

[0117] In the application, at the start time of the effective pulse of the gate driving signal output by each gate driving unit GIPu, the third selection unit in the second compensation module 220 starts to respond to the effective pulse of the second control signal, turns on the path between the compensation signal line and the target power signal line, and uses the compensation signal VH or VL to charge compensate the target power signal line, so that each gate driving unit GIPu can obtain a flat and waveform-free gate driving signal waveform, and can reduce costs and occupied area.

[0118] Based on the same inventive concept, the present application further provides a method for driving a display panel, which can be applied to the aforementioned display panel. Figures 2 to 12 The driving method of the display panel provided in the embodiment of the present application may include: controlling the compensation circuit 20 of the display panel to select a path between the compensation signal line and the target power signal line.

[0119] The driving method of the above-mentioned display panel can control the compensation circuit 20 to select the path between the compensation signal line and the target power signal line, so that when the compensation circuit 20 turns on the path between the compensation signal line and the target power signal line, the compensation signal VH or VL is applied to the target power signal line, so that the charge demand for the target power signal line generated by the gate drive circuit 10 outputting the gate drive signal valid pulse is compensated by the compensation signal VH or VL, which can improve the burr problem caused by the target power signal line being unable to meet the charge demand. In other words, in the related art, the target power signal line generates burrs because it cannot meet the charge demand when the gate drive circuit 10 outputs the gate drive signal valid level. In this regard, the present application applies the compensation signal VH or VL to the target power signal line when the gate drive circuit 10 outputs the gate drive signal valid level, which is equivalent to generating burrs in the opposite direction. The two reverse burrs cancel each other out, and a flat and burr-free target power signal waveform can be obtained, and then a flat and burr-free gate drive signal waveform can be obtained, which is helpful to improve the display effect of the display panel.

[0120] In one embodiment, the difference between the absolute value of the compensation signal VH or VL and the absolute value of the target power signal is obtained according to simulation, that is, the difference VH-VGH between the compensation signal VH and the first power signal VGH, and the difference VL-VGL between the second power signal VGL and the compensation signal VL. Specifically, the voltage difference VH-VGH or VL-VGL between the absolute value of the compensation signal and the absolute value of the target power signal can be adjusted by layout load and post-simulation, wherein the layout load can be understood as the pixel circuit connected to the gate drive circuit 10. After the sample is produced, the voltage difference VH-VGH or VL-VGL between the absolute value of the compensation signal and the absolute value of the target power signal can be optimized again. In this way, the compensation signal VH or VL can be optimized by simulation to obtain a flat and burr-free gate drive signal waveform.

[0121] Fig.13 Schematic diagram of a driving method of the gate driving circuit 10 provided in an embodiment of the present application. Figures 4 to 8 as well as Fig.13 In one embodiment, the gate driving circuit 10 is configured with a first control signal line, and the compensation circuit 20 includes at least one first compensation module 210, and the first compensation module 210 includes a storage unit, a first gating unit, and a second gating unit. Figures 4 to 6 The display panel provided as shown, Fig.13 As shown, the above steps of controlling the compensation circuit 20 of the display panel to select and conduct the path between the compensation signal line and the target power signal line may include the following steps S1301 to S1303.

[0122] S1301: Control the first control signal line to output a valid pulse of the first control signal Reset, so as to conduct a path between the compensation signal line and the target power signal line through the first gating unit.

[0123] S1302: Storing the compensation signal through the storage unit, and controlling the first control signal line to output an invalid pulse of the first control signal Reset, so as to disconnect the path between the compensation signal line and the target power signal line through the first selection unit.

[0124] S1303: In response to the gate driving circuit 10 outputting a valid pulse of the gate driving signal, the second gating unit conducts a path between the compensation signal line and the target power signal line.

[0125] The effective pulse end time of the first control signal Reset is earlier than the effective pulse start time of the gate drive signal. In the application, the effective pulse of the first control signal Reset can be output through the first control signal line, so that the first gating unit is turned on in response to the effective pulse of the first control signal Reset, thereby turning on the path between the compensation signal line and the target power signal line, so that the first end of the storage unit stores the compensation signal VH or VL. When the first end potential of the storage unit is stored to the compensation signal VH or VL, the invalid pulse of the first control signal Reset can be output through the first control signal line, so that the first gating unit is turned off in response to the effective pulse of the first control signal Reset, thereby disconnecting the path between the compensation signal line and the target power signal line, so that the first end of the storage unit latches the compensation signal VH or VL. When the gate drive signal outputs a valid pulse, the first selection unit is maintained in a state of disconnecting the path between the compensation signal line and the target power signal line, and the second selection unit is turned on in response to the valid pulse of the gate drive signal output by the gate drive circuit 10, thereby turning on the path between the compensation signal line and the target power signal line, so that the compensation signal VH or VL stored at the first end of the storage unit is applied to the target power signal line, thereby compensating for the charge requirement generated by the effective level of the gate drive signal output by the gate drive circuit 10 through the compensation signal VH or VL, so as to obtain a flat and glitch-free signal output waveform.

[0126] For example, Figure 4 and Figure 6 The provided display panel includes a first compensation module 210 of 2T1C, and the first transistor T1 and the second transistor T2 are NTFTs for illustration. Before each frame scan starts, the first control signal Reset is set to a high level, and the corresponding first transistor T1 is turned on. At this time, the second transistor T2 is disconnected, and the first electrode of the capacitor C is charged to the VH potential. Then the first control signal Reset becomes a low level, the first transistor T1 and the second transistor T2 are disconnected respectively, and the charge is locked in the capacitor C. The next step of line-by-line scanning begins. Whenever the gate drive signal output by the gate drive circuit 10 becomes a high level, the corresponding second transistor T2 is turned on, and the charge in the capacitor C instantly rushes into the first power supply signal line, causing it to generate an upward burr, and then the gate drive signal will also have an upward burr. The charge in the capacitor C meets the large amount of charge demand at the moment when the gate drive signal becomes a high level. The upward burr and the downward burr generated by the gate drive signal becoming a high level offset each other, thereby obtaining a smooth and thornless waveform such as Figure 7 shown.

[0127] Another exemplary example is Figure 5The provided display panel includes a first compensation module 210 of 2T1C, and the first transistor T1 and the second transistor T2 are PTFTs for illustration. Before each frame scan starts, the first control signal Reset is set to a low level, and the corresponding first transistor T1 is turned on. At this time, the second transistor T2 is disconnected, and the first electrode of the capacitor C is charged to the VL potential. Then the first control signal Reset becomes a high level, the first transistor T1 and the second transistor T2 are disconnected respectively, and the charge is locked in the capacitor C. The next step of line-by-line scanning begins. Whenever the gate drive signal output by the gate drive circuit 10 becomes a low level, the corresponding second transistor T2 is turned on, and the charge in the capacitor C instantly rushes into the second power supply signal line, causing it to generate downward burrs, and then the gate drive signal will also have downward burrs. The charge in the capacitor C meets the large amount of charge demand at the moment when the gate drive signal becomes a low level. The downward burrs and the upward burrs generated by the gate drive signal becoming a low level offset each other, thereby obtaining a smooth and thornless waveform such as Figure 8 shown.

[0128] In one embodiment, the duration of the first control signal Reset turning on the first gating unit is obtained according to simulation. Specifically, the on-time of the first gating unit can be adjusted by layout load and post-simulation. The on-time of the first gating unit can be optimized again after the sample is produced. In this way, the on-time of the first gating unit can be optimized by simulation, so that the storage potential of the first end of the storage unit is the potential of the compensation signal VH or VL, ensuring the storage time of the storage unit, thereby obtaining a flat and glitch-free gate drive signal waveform.

[0129] Please continue reading Figures 9 to 12 In one embodiment, the display panel includes a second control signal line, the compensation circuit 20 includes at least one second compensation module 220, and the second compensation module 220 includes a third gating unit. Fig. 9 and Fig.10 In the display panel provided as shown, the above step of controlling the compensation circuit 20 of the display panel to select and conduct the path between the compensation signal line and the target power signal line may include: controlling the second control signal line to output the effective pulse of the second control signal SYNC, so as to conduct the path between the compensation signal line and the target power signal line through the third gating unit. The starting time of at least one effective pulse of the second control signal SYNC is the same as the starting time of the effective pulse of the gate drive signal output by the gate drive circuit 10.

[0130] For example, Fig. 9The provided display panel includes a second compensation module 220 of 1T0C, and the third transistor T3 is an NTFT for example. At the rising edge moment of the gate drive signal output, the second control signal SYNC is controlled to output a short high-level pulse, the third transistor T3 is turned on, and the compensation signal VH is applied to the first power supply signal VGH, so that the first power supply signal VGH can have a periodic upward burr, thereby offsetting the downward burr generated by the gate drive signal outputting an effective high level, and obtaining a smooth and burr-free waveform as shown in FIG. Fig.11 shown.

[0131] Another exemplary example is Fig.10 The provided display panel includes a second compensation module 220 of 1T0C, and the third transistor T3 is a PTFT for example. At the falling edge moment of the gate drive signal output, the second control signal SYNC is controlled to output a short low-level pulse, the third transistor T3 is turned on, and the compensation signal VL is applied to the second power supply signal VGL, so that the second power supply signal VGL can have a periodic downward burr, thereby offsetting the upward burr generated by the gate drive signal outputting an effective low level, and obtaining a smooth and burr-free waveform as shown in FIG. Fig.12 shown.

[0132] It should be understood that, although the steps in the flowchart of the accompanying drawings are displayed in sequence as indicated by the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the accompanying drawings may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least a portion of the steps or stages in other steps.

[0133] Based on the same inventive concept, an embodiment of the present application also provides a display device. Fig.14 A schematic diagram of the structure of a display device provided in an embodiment of the present application. Fig.14 In one embodiment, please continue to refer to Fig.14 , the display device 1000 includes the display panel 1 in the above embodiment. It can be understood that the display device 1000 in the embodiment of the present application can be any product or component with a display function, such as an OLED display device, a QLED display device, an electronic paper, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, a wearable device, an Internet of Things device, etc., and the embodiments disclosed in the present application are not limited to this.

[0134] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0135] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0136] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A display panel, characterized in that: It includes a gate drive circuit, a compensation circuit, a compensation signal line and two power signal lines, wherein: The gate drive circuit is connected to the two power signal lines respectively, and the gate drive circuit is used to output a gate drive signal according to two power signals respectively provided by the two power signal lines; The compensation circuit is connected to the compensation signal line and the target power signal line respectively, and is used to select a path between the compensation signal line and the target power signal line; wherein the target power signal line is one of the two power signal lines, and the absolute value of the compensation signal provided by the compensation signal line is greater than the absolute value of the target power signal provided by the target power signal line.

2. The display panel according to claim 1, characterized in that: The two power signal lines include a first power signal line and a second power signal line, the first power signal line provides a first power signal greater than the second power signal provided by the second power signal line, and the gate drive circuit is used to connect to the target transistor of the pixel circuit, wherein, The target transistor is an N-type transistor, and the target power signal line is the first power signal line; or, The target transistor is a P-type transistor, and the target power signal line is the second power signal line.

3. The display panel according to claim 1, characterized in that: The display panel further includes a first control signal line, the compensation circuit includes at least one first compensation module, the first compensation module includes a storage unit, a first gating unit and a second gating unit, wherein: In the same first compensation module, the first gating unit is respectively connected to the first control signal line, the compensation signal line, and the first end of the storage unit, the first gating unit receives a first control signal provided by the first control signal line, and the first gating unit is used to select and conduct a path between the compensation signal line and the first end of the storage unit; The second end of the storage unit receives a reference signal; In the same first compensation module, the second gating unit is respectively connected to the first end of the storage unit, the target power signal line, and the output end of the gate driving circuit, the second gating unit receives the gate driving signal, and the second gating unit is used to select and conduct the path between the first end of the storage unit and the target power signal line; Optionally, the effective pulse end time of the first control signal is earlier than the effective pulse start time of the gate drive signal; Optionally, the first end of the storage unit is used to store the compensation signal when the first gating unit is in a conducting state; The second gating unit applies the compensation signal stored at the first end of the storage unit to the target power signal line in response to the valid pulse of the gate driving signal; Optionally, the gate driving circuit is used to connect to the pixel circuit, the display panel further includes two pixel power signal lines and an initialization signal line, the pixel circuit is connected to the two pixel power signal lines and the initialization signal line respectively, and the second end of the storage unit is connected to any one of the two pixel power signal lines and the initialization signal line; Optionally, the display panel further includes at least one of a ground signal line and an external power signal line, and the second end of the storage unit is connected to any one of the ground signal line and the external power signal line.

4. The display panel according to claim 3, characterized in that: The first gating unit includes a first transistor, a first electrode of the first transistor is connected to the compensation signal line, a second electrode of the first transistor is connected to a first end of the storage unit of the same first compensation module, and a gate of the first transistor is connected to the first control signal line; Optionally, the first transistor includes a P-type transistor or an N-type transistor; Optionally, the second gating unit includes a second transistor, a first electrode of the second transistor is connected to the first end of the storage unit of the same first compensation module, a second electrode of the second transistor is connected to the target power signal line, and a gate of the second transistor is connected to the output end of the gate driving circuit; Optionally, the gate driving circuit is used to be connected to a target transistor of the pixel circuit, and the second transistor is of the same type as the target transistor; Optionally, the storage unit includes a capacitor, a first electrode of the capacitor is respectively connected to the first gating unit and the second gating unit of the same first compensation module, and a second electrode of the capacitor is used to receive the reference signal.

5. The display panel according to claim 3, characterized in that: The gate driving circuit includes a plurality of cascaded gate driving units, and the compensation circuit includes a plurality of the first compensation modules, wherein the output end of the i-th gate driving unit is connected to the second gating unit of the i-th first compensation module, i≥1; Optionally, the second gating unit of the i-th first compensation module applies the compensation signal stored at the first end of the storage unit of the i-th first compensation module to the target power signal line in response to the valid pulse of the gate driving signal output by the i-th gate driving unit; Optionally, the gate driving units are arranged in columns, and the first compensation modules are arranged in columns; Optionally, the i-th first compensation module is arranged in the same row as the i-th gate driving unit; Optionally, the i-th first compensation module is arranged in the same row as the (i+1)-th gate driving unit.

6. The display panel according to claim 1, characterized in that: The display panel further includes a second control signal line, the compensation circuit includes at least one second compensation module, the second compensation module includes a third gating unit, the third gating unit is respectively connected to the second control signal line, the compensation signal line, and the target power signal line, the third gating unit receives a second control signal provided by the second control signal line, and the third gating unit is used to select and conduct a path between the compensation signal line and the target power signal line; Optionally, the third gating unit applies the compensation signal to the target power signal line in response to a valid pulse of the second control signal; wherein a start time of at least one valid pulse of the second control signal is the same as a start time of a valid pulse of the gate drive signal; Optionally, the gate drive circuit is also configured with a clock signal line, the gate drive circuit is connected to the clock signal line, the gate drive circuit is used to output the gate drive signal according to the two power supply signals and the clock signal provided by the clock signal line, and the frequency of the second control signal is the same as the frequency of the clock signal.

7. The display panel according to claim 6, characterized in that: The gate driving circuit comprises a plurality of cascaded gate driving units, and the compensation circuit comprises a plurality of second compensation modules, wherein the number of the gate driving units is greater than or equal to the number of the second compensation modules; Optionally, the gate driving units are arranged in columns, and the second compensation modules are arranged in columns; Optionally, the second compensation module is arranged in the same row as at least part of the gate driving unit; Optionally, the number of rows of the gate driving units between any two adjacent second compensation modules is the same; Optionally, at least part of the effective pulse start time of the second control signal is the same as the effective pulse start time of at least part of the gate driving signal output by the gate driving unit.

8. The display panel according to claim 6, characterized in that: The third gating unit comprises a third transistor, a first electrode of the third transistor is connected to the compensation signal line, a second electrode of the third transistor is connected to the target power signal line, and a gate of the third transistor is connected to the second control signal line; Optionally, the third transistor includes a P-type transistor or an N-type transistor.

9. A method for driving a display panel, characterized in that: Applied to the display panel according to any one of claims 1 to 8, the driving method of the display panel comprises: The compensation module of the control gate driving circuit selects and conducts the path between the compensation signal line and the target power supply signal line.

10. A display device, characterized in that: Comprising the display panel as described in any one of claims 1-8.

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