Write word line enabling circuit and enabling control method, memory, and electronic equipment

Abstract

The present application relates to a write word line enable circuit and enable control method, memory, and electronic device. The write word line enable circuit is used to connect to a memory cell, which includes a read transistor and a write transistor, as well as a read word line and a read bit line connected to the read transistor, and a write word line and a write bit line connected to the write transistor. The write word line enable circuit includes a sensing control circuit connected to the write bit line and configured to: obtain a data signal transmitted by the write bit line and output a write control signal based on the data signal; and a startup control circuit connected to the sensing control circuit and to the write word line and configured to: output an enable signal to the write word line based on the write control signal. Using the write word line enable circuit of the present application can improve the read and write fault tolerance rate.

Description

Technical Field

[0001] The present application relates to the field of memory technology, and in particular to a write word line enable circuit and enable control method, a memory, and an electronic device. Background Art

[0002] With the development of semiconductor technology, some new memory cell dynamic random access memory (DRAM) has emerged, such as DRAM based on the 2T0C memory cell. A 2T0C memory cell may contain two transistors: one is a write transistor (Write Tr) and the other is a read transistor (Read Tr).

[0003] When writing data to the storage node (Storage Node, SN) of the 2T0C storage cell, it is necessary to open the write word line (Write Word Line, WWL), and in the data reading process of the 2T0C storage cell, the read word line (Read Word Line, RWL) needs to be selected, and after the reading is completed, it is necessary to perform a write-back operation on the storage node SN. In the process of performing the write-back operation, it is first necessary to feed back the write-back data sensed on the read bit line (Read Bit Line, RBL) to the write bit line (WBL). Thereafter, the write word line WWL will be turned on to rewrite the write-back data to the storage node SN. If the write-back operation is not performed, the data stored on the storage node SN may gradually disappear over time, resulting in errors in the storage data of the storage cell. Summary of the Invention

[0004] Based on this, it is necessary to provide a write word line enable circuit and write word line enable control method, memory, and electronic device that can improve read and write error tolerance.

[0005] In a first aspect, the present application provides a write word line enable circuit for connecting to a memory cell, wherein the memory cell includes a read transistor and a write transistor, a read word line and a read bit line connected to the read transistor, and a write word line and a write bit line connected to the write transistor, wherein the write word line enable circuit includes:

[0006] a sensing control circuit connected to the write bit line and configured to: obtain a data signal transmitted by the write bit line and output a write control signal according to the data signal;

[0007] The startup control circuit is connected to the sensing control circuit and the write word line, and is configured to output an enable signal to the write word line according to the write control signal.

[0008] The write word line enable circuit includes a sensing control circuit and a startup control circuit. The sensing control circuit is connected to the write bit line and configured to obtain a data signal transmitted by the write bit line and output a write control signal based on the data signal. The startup control circuit is connected to the sensing control circuit and the write word line and configured to output an enable signal to the write word line based on the write control signal. The enable signal issued by the startup control circuit can control the write word line to respond accurately and promptly control the turning on or off of the write transistor. This eliminates the need for precise timing control of the read and write processes of the memory cell, as required in related technologies, thereby improving read and write error tolerance.

[0009] In one embodiment, the enable signal includes a turn-on signal and a disable signal, and the working stages of the storage unit include a preprocessing stage, a precharge stage, a reading stage, a sensing stage, a write-back stage, and a data writing stage. The startup control circuit is further configured to: obtain a write disable instruction, determine the working stage of the storage unit according to the write control signal and the write disable instruction, and when the storage unit is working in the write-back stage and the data writing stage, output the turn-on signal to the write word line so that the write word line controls the write transistor to turn on; when the storage unit is working in the preprocessing stage, the precharge stage, the reading stage, and the sensing stage, output the disable signal to the write word line so that the write word line controls the write transistor to turn off.

[0010] In one embodiment, the sensing control circuit includes:

[0011] A sense amplifier circuit having a first receiving end, a second receiving end, a first output end, and a second output end; wherein the first receiving end is connected to the write bit line for receiving a data signal transmitted by the write bit line, and the second receiving end is connected to a reference signal end for receiving a reference signal; the sense amplifier circuit is configured to: when the data signal is greater than or less than the reference signal, cause the first output end and the second output end to output signals of different levels; and when the data signal is equal to the reference signal, cause the first output end and the second output end to output signals of the same level;

[0012] A NOR gate logic circuit has a first input terminal, a second input terminal, and a first logic output terminal; wherein the first input terminal is connected to the first output terminal of the sensing amplifier circuit, the second input terminal is connected to the second output terminal of the sensing amplifier circuit, and the first logic output terminal is connected to the startup control circuit.

[0013] In one embodiment, the sensing amplifier circuit further has a control terminal; the control terminal is configured to receive a sensing enable signal.

[0014] In one embodiment, the startup control circuit includes:

[0015] A NAND gate logic circuit has a third input terminal, a fourth input terminal and a second logic output terminal; wherein the second logic output terminal is connected to the write word line, the third input terminal is connected to the first logic output terminal of the sensing control circuit, and the fourth input terminal is configured to receive the write disable instruction.

[0016] In a second aspect, the present application further provides a write word line enable control method, which is applied to the write word line enable circuit in any of the above embodiments, and includes:

[0017] A sensing control circuit is used to acquire a data signal transmitted by a write bit line in a memory cell; wherein the memory cell includes a read transistor and a write transistor, and a read word line and a read bit line connected to the read transistor, and a write word line and a write bit line connected to the write transistor;

[0018] Using the sensing control circuit to output a write control signal according to the data signal;

[0019] A startup control circuit is used to output an enable signal to the write word line according to the write control signal.

[0020] The above-mentioned write word line enable control method utilizes a sensing control circuit to obtain a data signal transmitted by a write bit line in a memory cell. The memory cell includes a read transistor and a write transistor, as well as a read word line and a read bit line connected to the read transistor, and a write word line and a write bit line connected to the write transistor. The sensing control circuit outputs a write control signal based on the data signal, and a start-up control circuit outputs an enable signal to the write word line based on the write control signal. The enable signal issued by the start-up control circuit can control the write word line to accurately respond and promptly control the opening or closing of the write transistor. This eliminates the need for precise timing control of the memory cell's read and write processes, as required in related technologies, thereby improving read and write fault tolerance.

[0021] In one embodiment, the enable signal includes an enable signal and a disable signal, the working phases of the memory cell include a pre-processing phase, a pre-charging phase, a reading phase, a sensing phase, a write-back phase, and a data writing phase, and outputting the enable signal to the write word line according to the write control signal includes:

[0022] Get write disable instruction;

[0023] The working phase of the storage unit is determined according to the write control signal and the write disable instruction. When the storage unit is working in the write-back phase and the data writing phase, the enable signal is output to the write word line so that the write word line controls the write transistor to turn on. When the storage unit is working in the pre-processing phase, the pre-charging phase, the reading phase and the sensing phase, the disable signal is output to the write word line so that the write word line controls the write transistor to turn off.

[0024] In one embodiment, determining the working phase of the storage unit according to the write control signal and the write disable instruction includes:

[0025] A logical NOT operation is performed on the write control signal and the write disable instruction to obtain the enable signal, where the enable signal is used to determine the working phase of the storage unit.

[0026] In one embodiment, when the memory cell operates in a write-back phase, the data signal transmitted by the write bit line comes from the data signal fed back to the write bit line by the read bit line.

[0027] In one embodiment, outputting a write control signal according to the data signal includes:

[0028] Acquire a reference signal, and compare the magnitudes of the data signal and the reference signal;

[0029] When the data signal is greater than or less than the reference signal, two signals of different levels are output as the first output signal and the second output signal respectively; when the data signal is equal to the reference signal, two signals of the same level are output as the first output signal and the second output signal respectively;

[0030] Perform a logical negation operation on the first output signal and the second output signal to obtain the write control signal.

[0031] In one embodiment, the working stages of the storage unit include a preprocessing stage, a precharge stage, a reading stage, a sensing stage, a write-back stage and a data writing stage. When the storage unit works in the preprocessing stage, the precharge stage, the reading stage and the sensing stage, the data signal is equal to the reference signal; when the storage unit works in the write-back and data writing stages, the data signal is greater than or less than the reference signal.

[0032] In one embodiment, when the data signal is greater than the reference signal, the first output signal is a high-level signal and the second output signal is a low-level signal; when the data signal is less than the reference signal, the first output signal is a low-level signal and the second output signal is a high-level signal.

[0033] In one embodiment, the method further comprises:

[0034] In response to a sensing enable signal, the steps of acquiring a data signal transmitted by a write bit line in a memory cell and outputting a write control signal according to the data signal are performed.

[0035] In a third aspect, the present application further provides a memory, including:

[0036] at least one memory array, the memory array comprising a plurality of memory cells, the memory cells comprising a read transistor and a write transistor, a read word line and a read bit line connected to the read transistor, and a write word line and a write bit line connected to the write transistor;

[0037] At least one write word line enable circuit as described in any of the above embodiments, wherein the write word line enable circuit is respectively connected to the write bit line and the write word line in the corresponding memory array.

[0038] The memory device includes: at least one memory array, the memory array including a plurality of memory cells, the memory cells including read transistors and write transistors, a read word line and a read bit line connected to the read transistors, and a write word line and a write bit line connected to the write transistors; and at least one write word line enable circuit as described in any of the above embodiments, the write word line enable circuit being connected to the write bit line and the write word line in the corresponding memory array, respectively. By activating an enable signal issued by a control circuit, the write word line can be controlled to accurately respond, thereby timely controlling the turning on or off of the write transistor. This eliminates the need for precise timing control of the read and write processes of the memory cells, as required in related arts, thereby improving read and write fault tolerance.

[0039] In one embodiment, the memory further includes a write word line driver and a write word line decoder, the start control circuit is connected to the write word line through the write word line driver, and the write word line driver is also connected to the write word decoder.

[0040] In a fourth aspect, the present application further provides an electronic device comprising a memory as described in any of the above embodiments. A write word line enable circuit in the memory can control the write word line to accurately respond and timely control the turning on or off of the write transistor, thereby eliminating the need for precise timing control of the read and write processes of the memory cell as required in the related art, thereby improving read and write fault tolerance. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0042] Figure 1 Schematic diagram of the structure of an existing 2T0C memory cell;

[0043] Figure 2 A schematic structural diagram of a write word line enable circuit provided in an embodiment of the present application;

[0044] Figure 3 A schematic structural diagram of another write word line enable circuit provided in an embodiment of the present application;

[0045] Figure 4 A schematic structural diagram of a sensing amplifier circuit provided in an embodiment of the present application;

[0046] Figure 5 A schematic structural diagram of another write word line enable circuit provided in an embodiment of the present application;

[0047] Figure 6 A schematic structural diagram of another write word line enable circuit provided in an embodiment of the present application;

[0048] Figure 7 A flowchart of a write word line enable control method provided in an embodiment of the present application;

[0049] Figure 8 A flowchart of step S103 in a write word line enable control method provided in an embodiment of the present application;

[0050] Figure 9 A flowchart of step S102 in a write word line enable control method provided in an embodiment of the present application;

[0051] Figure 10 A schematic diagram of the structure of a memory provided in an embodiment of the present application;

[0052] Figure 11 A schematic diagram of the structure of a storage array of a memory provided in an embodiment of the present application.

[0053] Explanation of the reference numerals: 10 - storage array, storage cell 11, 20 - sense amplifier, 101 - sense control circuit, 1011 - sense amplifier circuit, 1012 - NOR gate logic circuit, 201 - start control circuit, 2011 - NAND gate logic circuit, 301 - write word line driver, 401 - write word line decoder. DETAILED DESCRIPTION

[0054] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0055] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0056] It will be understood that the terms "first," "second," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor without departing from the scope of this application. The first resistor and the second resistor are both resistors, but they are not the same resistor.

[0057] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if there is transmission of electrical signals or data between the connected circuits, modules, units, etc.

[0058] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Furthermore, the term "and / or" as used in this specification includes any and all combinations of the relevant listed items.

[0059] With the advancement of semiconductor technology, new types of dynamic random access memory (DRAM) have emerged, such as DRAM based on the 2T0C memory cell. A 2T0C memory cell contains two transistors: a write transistor (Write Tr) and a read transistor (Read Tr). The read transistor is connected to the read bit line (RBL) and read word line (RWL), while the write transistor is connected to the write bit line (WBL) and write word line (WWL).

[0060] After the read phase of the 2T0C memory cell, a write-back operation needs to be performed on the storage node SN. During the write-back operation, the write-back data sensed on the read bit line (RBL) must first be fed back to the write bit line (WBL). Afterwards, the write word line WWL is turned on to rewrite the write-back data into the storage node SN.

[0061] like Figure 1 As shown, in some traditional technical solutions, a delay circuit is used to control the moment when the write word line WWL is reopened during the write-back phase. However, the delay circuit in the traditional technology only performs a simple timing control on the entire read and write process of the storage unit. For example, assuming that the read and write process timing pre-set by the delay circuit at a certain moment indicates that the storage unit has entered the write-back phase, then regardless of whether the data signal on the write bit line WBL is synchronized as a sensing signal, the delay circuit will control the write word line WWL to be reopened, which is very likely to cause errors in the write-back data. Therefore, the traditional method of using a delay circuit to achieve write-back requires very precise control of the timing of the entire read and write process of the storage unit to ensure that the data written back into the storage node SN will not be erroneous, so the read and write fault tolerance of the traditional technology is low.

[0062] The present application provides a write word line enabling circuit for connecting to a memory cell. The write word line enabling circuit of the present application is Figure 1 Improvements to peripheral circuitry outside an array composed of memory cells are shown. The memory cells are 2T memory cells, each having at least one read transistor and one write transistor. The read transistor is connected to a read word line RWL and a read bit line RBL, and the write transistor is connected to a write word line WWL and a write bit line WBL. In some embodiments, the 2T memory cell can be a 2T0C memory cell, a 2T1C memory cell, or a 3T memory cell.

[0063] like Figure 2 As shown, the write word line enable circuit of the present application includes a sensing control circuit 101 and a start control circuit 201. The sensing control circuit 101 is connected to the write bit line WBL and is configured to: obtain the data signal transmitted by the write bit line WBL and output a write control signal based on the data signal. The start control circuit 201 is connected to the sensing control circuit 101 and the write word line WWL and is configured to: output an enable signal to the write word line WWL based on the write control signal.

[0064] The data signal transmitted by the write bit line WBL can change according to the different stages of the memory cell's read and write process. The sensing control circuit 101 can determine which stage of the read and write process the memory cell is in by acquiring the data signal transmitted by the write bit line WBL, thereby outputting a write control signal to the start control circuit 201. The start control circuit 201 can then generate an enable signal based on the write control signal to instruct the memory cell's write transistor to turn on or off.

[0065] The write word line enable circuit includes a sensing control circuit 101 and a start-up control circuit 201. The sensing control circuit 101 is connected to the write bit line WBL and is configured to receive a data signal transmitted by the write bit line WBL and output a write control signal based on the data signal. The start-up control circuit 201 is connected to the sensing control circuit 101 and the write word line WWL and is configured to output an enable signal to the write word line WWL based on the write control signal. The enable signal issued by the start-up control circuit 201 can accurately control the write word line WWL to indicate whether the write transistor of the memory cell is turned on or off. This eliminates the need for precise timing control of the read and write processes of the memory cell, as required in related art, thereby improving read and write error tolerance.

[0066] In one embodiment, the enable signal includes a turn-on signal and a disable signal, and the working stages of the storage unit include a preprocessing stage, a precharge stage, a read stage, a sensing stage, a write-back stage, and a data write stage. The startup control circuit 201 is further configured to: obtain a write disable instruction, determine the working stage of the storage unit according to the write control signal and the write disable instruction, and when the storage unit is working in the write-back stage and the data write stage, output a turn-on signal to the write word line WBL, so that the write word line WBL controls the write transistor to turn on; when the storage unit is working in the preprocessing stage, the precharge stage, the read stage, and the sensing stage, output a disable signal to the write word line WBL, so that the write word line WBL controls the write transistor to turn off.

[0067] The working phases of a storage unit can be roughly divided into the following phases: (1) pre-processing phase; (2) pre-charging phase; (3) reading phase; (4) sensing phase; (5) writing back phase; (6) data writing phase. The following describes the main working phases (reading phase, sensing phase, and writing back phase):

[0068] During the read phase, the gate of the read transistor determines whether it is turned on based on whether the data stored on SN is "0" or "1", and the voltage on the read bit line RBL connected to the read transistor changes instantaneously based on whether the gate of the read transistor is turned on. If it changes, it means that the read transistor is turned on, otherwise the read transistor is not turned on, and the stored data is determined to be 0 or 1 based on whether it is turned on.

[0069] During the sensing phase, the output end of the read bit line RBL is connected to one input end of a sense amplifier (SA) for reading, and the other input end of the sense amplifier for reading is connected to a reference signal end. The sense amplifier can compare the difference between the current or voltage on the read bit line RBL and the current or voltage at the reference signal end, and amplify this difference, so that the sense amplifier for reading can output a sensing signal. It can be understood that the magnitude of the current or voltage of the sensing signal can be used to indicate whether the data stored in the storage cell is "1" or "0". For example, if the output sensing signal is at a high level, it indicates that the data stored in the storage cell is "1", and if the output sensing signal is at a low level, it indicates that the data stored in the storage cell is "0".

[0070] In addition, after the induction phase is over, the write-back phase will be entered. This is because the data stored in the storage node (SN) of the 2T0C memory cell is usually stored based on the gate of the read transistor as a capacitor. The characteristic of capacitor storage data is that if the write-back (refresh) operation is not performed, the charge stored in the capacitor will gradually disappear over time, which will cause the stored data to be incorrect (for example, assuming that the data stored in the storage node of a certain memory cell is "1", but if the write-back operation is not performed for a long time, the charge stored in the gate of the read transistor corresponding to this storage node may disappear, causing the data stored in the SN to become "0", which in turn causes the data stored in this memory cell to be incorrect).

[0071] During the write-back phase, the read sense amplifier simultaneously transmits the sense signal to the write bit line WBL, synchronizing the data signal transmitted on the write bit line WBL with the sense signal. Subsequently, the write word line WWL is reopened to turn on the write transistor again, allowing the sense signal synchronized on the write bit line WBL to be transmitted to the storage node SN for storage, completing the write-back process. However, if the sense signal has not yet been synchronized to the write bit line WBL, the write word line WWL cannot be reopened, otherwise the data written back to the storage node SN will be erroneous.

[0072] The enable signal may include an enable signal and a disable signal. The enable control circuit 201 may be connected to the write word line WWL and control the memory cell's read transistor to turn on via the enable signal and control the memory cell's write transistor to turn off via the disable signal. When the 2TOC memory cell is in the pre-processing phase, pre-charge phase, read phase, and sensing phase, the data signal transmitted by the write bit line WBL may be synchronized with the reference signal, so that the enable signal output by the enable control circuit 201 is a disable signal. When the memory cell is in the write-back phase and data writing phase, the data signal transmitted by the write bit line WBL may be synchronized with the sense signal output by the sense amplifier used for reading, so that the enable signal output by the enable control circuit 201 is an enable signal. For example, when the memory cell is in the reading stage or the sensing stage, the sensing control circuit 101 will obtain the data signal transmitted by the write bit line WBL and maintain it as the voltage or current value of the reference signal. At this time, the start control circuit 201 will determine that the enable signal is a disable signal according to the corresponding write control signal; when the memory cell is in the write-back stage, the sensing control circuit 101 will obtain the data signal transmitted by the write bit line WBL and change it to the voltage or current value of the sensing signal. At this time, the start control circuit 201 will determine that the enable signal is a start signal according to the corresponding write control signal.

[0073] Of course, in other suitable application scenarios, the storage unit may have other stages in the reading and writing process. In other stages not mentioned in this application, the data signal transmitted by the write bit line WBL may also be adaptively changed according to the corresponding application scenario requirements or design, and this embodiment does not limit this.

[0074] In one embodiment, Figure 3As shown, the sensing control circuit 101 includes a sensing amplifier circuit 1011 and a NOR gate logic circuit 1012. The sensing amplifier circuit 1011 has a first receiving terminal, a second receiving terminal, a first output terminal (output 1), and a second output terminal (output 2). The first receiving terminal is connected to the write bit line WBL for receiving a data signal transmitted by the write bit line WBL, and the second receiving terminal is connected to the reference signal terminal for receiving a reference signal. The sensing amplifier circuit 1011 is configured to: when the data signal is greater than or less than the reference signal, the first output terminal and the second output terminal output signals of different levels; when the data signal is equal to the reference signal, the first output terminal and the second output terminal output signals of the same level. The NOR gate logic circuit 1012 has a first input terminal, a second input terminal, and a first logic output terminal (output 3). The first input terminal is connected to the first output terminal of the sensing amplifier circuit 1011, the second input terminal is connected to the second output terminal of the sensing amplifier circuit 1011, and the first logic output terminal is connected to the startup control circuit 201.

[0075] The sensing amplifier circuit 1011 may be a sense amplifier with a signal amplification function, configured to amplify the difference between the data signal and the reference signal at different stages of the memory cell, so that its first output terminal and second output terminal may output signals of the same or different levels. The signal type at the input terminal of the sensing amplifier circuit 1011 may be a voltage signal or a current signal. In some embodiments, the sense amplifier may be a sense voltage amplifier or a sense current amplifier. The level signal may include a low-level signal and a high-level signal. The low-level signal may be a signal with a level lower than the reference signal, and the high-level signal may be a signal with a level higher than the reference signal.

[0076] For example, during the read or sense phase, the sense amplifier used for reading has not yet output a sense signal to the write bit line WBL. At this time, the data signal transmitted by the write bit line WBL can be synchronized with the reference signal at the reference signal terminal. For the sense amplifier circuit 1011, the voltage or current at the first receiving terminal and the second receiving terminal are the same. Therefore, the first output terminal of the sense amplifier circuit 1011 will output a low-level signal, and the second output terminal will also output a low-level signal. During the write-back phase, the sense amplifier used for reading will also output a sense signal to the write bit line WBL. At this time, the data signal transmitted by the write bit line WBL can be synchronized with the sense signal output by the sense amplifier used for reading. Assuming that the write-back data corresponding to the sensing signal in the write-back phase is "1", the data signal transmitted by the write word line WWL can be greater than the reference signal, causing the data signal on the write word line WWL to be synchronized to be greater than the reference signal. At this time, the first output terminal of the sensing amplifier circuit 1011 will output a high-level signal, and the second output terminal will also output a low-level signal, that is, the two output terminals of the sensing amplifier circuit 1011 will output different level signals. Assuming that the write-back data corresponding to the sensing signal in the write-back phase is "0", the data signal transmitted by the write word line WWL can be less than the reference signal, causing the data signal on the write word line WWL to be synchronized to be less than the reference signal. At this time, the first output terminal of the sensing amplifier circuit 1011 will output a low-level signal, and the second output terminal will also output a high-level signal, that is, the two output terminals of the sensing amplifier circuit 1011 will also output different level signals. Therefore, when the data signal is greater than or less than the reference signal, the first output terminal and the second output terminal of the sensing amplifier circuit 1011 can always output different level signals.

[0077] Furthermore, when the data signal is equal to the reference signal, the first output terminal and the second output terminal of the sense amplifier circuit 1011 output the same level signal, specifically, the same low-level signal. After the two input terminals of the NAND gate receive the same low-level signal, its first logic output terminal will output a high-level signal to the startup control circuit 201. When the data signal is greater than or less than the reference signal, the first output terminal and the second output terminal of the sense amplifier circuit 1011 output different level signals. Specifically, the first output terminal outputs a low-level signal and the second output terminal outputs a high-level signal, or the first output terminal outputs a high-level signal and the second output terminal outputs a low-level signal. After the two input terminals of the NAND gate receive different level signals, its first logic output terminal will output a high-level signal to the startup control circuit 201.

[0078] Optionally, the reference signal may be a voltage value of half the power supply voltage VDD, i.e., 1 / 2VDD, the low-level signal may be 0, and the high-level signal may be VDD. Alternatively, the reference signal may be VDD, the low-level signal may be 1 / 2VDD, and the high-level signal may be 3 / 2VDD. Depending on the application scenario, the reference signal, the low-level signal, and the high-level signal may be set in different ways, which are not limited in this embodiment.

[0079] In one embodiment, Figure 4 As shown, the sense amplifier circuit 1011 further has a control terminal; the control terminal is configured to receive a sense enable signal (Sense Amplifier Enable).

[0080] The sense amplifier circuit 1011 and the sense amplifier for reading in the memory cell may be two separate sense amplifiers, and the sense enable signal of the sense amplifier circuit 1011 may be different from the enable signal of the sense amplifier for reading.

[0081] Optionally, the structure of the sensing amplifier circuit 1011 and the sense amplifier for reading can be the same. For example, the specific structure of the sensing amplifier circuit 1011 can be as follows: Figure 4 As shown, the control end of the sense amplifier circuit 1011 can be the gates of the transistors T1, T2 and T3. The gate of the transistor T4 in the sense amplifier circuit 1011 is used to receive the data signal output by the write bit line WBL. The gate of the transistor T5 is used to receive the reference signal. The gates of the transistors T6 and T7 serve as the first output end of the sense amplifier circuit 1011. The gates of the transistors T8 and T9 serve as the second output end of the sense amplifier circuit 1011.

[0082] Of course, the structure of the sensing amplifier circuit 1011 can also be other suitable circuit structures, and the number of transistors contained therein is not limited to Figure 4 The 9 shown in the figure can be determined according to the specific SA circuit structure, and this embodiment does not limit this.

[0083] If the control terminal of the sense amplifier circuit 1011 does not receive the sense enable signal, the sense amplifier circuit 1011 does not operate. At this time, the first output terminal and the second output terminal of the sense amplifier circuit 1011 both output low-level signals. If the control terminal of the sense amplifier circuit 1011 receives the sense enable signal, the sense amplifier circuit 1011 begins to operate. Assuming that the data signal on the write bit line WBL is equal to the reference signal, the first output terminal and the second output terminal of the sense amplifier circuit 1011 still output low-level signals. Assuming that the data signal on the write bit line WBL is less than the reference signal, the first output terminal outputs a low-level signal and the second output terminal outputs a high-level signal. Assuming that the data signal on the write bit line WBL is greater than the reference signal, the first output terminal outputs a low-level signal and the second output terminal outputs a high-level signal.

[0084] In one embodiment, Figure 5 As shown, the startup control circuit 201 includes a NAND gate logic circuit 2011, which has a third input terminal, a fourth input terminal, and a second logic output terminal output4. The second logic output terminal is connected to the write word line WWL, the third input terminal is connected to the first logic output terminal of the sensing control circuit 101, and the fourth input terminal is configured to receive a write disable command.

[0085] The third input terminal of the start-up control circuit 201 can be connected to the first logic output terminal of the NOR gate logic circuit 1012 in the sensing control circuit 101. The write disable instruction can also include a low-level signal and a high-level signal. When the write disable instruction is a low-level signal, it indicates that the write word line WWL is selected. When the write disable instruction is a high-level signal, it indicates that the write word line WWL is not selected.

[0086] For example, the working process of the write word line enable circuit is described in detail based on this embodiment. Of course, the following description is only for a better understanding of this solution and does not constitute a limitation on other embodiments.

[0087] When the write disable instruction is a low-level signal, it indicates that the write word line WWL is selected. At this time, regardless of whether the third input terminal of the NAND logic circuit 2011 receives a high-level signal or a low-level signal, the second logic output terminal of the NAND logic circuit 2011 will output a high-level signal to the write word line WWL, so that the write word line WWL can control the write transistor of the memory cell to turn on. At this time, the sense enable signal can be configured not to be sent to the sense amplifier circuit 1011, that is, the sense amplifier circuit 1011 is not operational. The data signal on WBL can be the new data signal to be written. After the write transistor is turned on, the new data signal on WBL can be smoothly written to the storage node. Furthermore, when the write disable instruction is a low-level signal, the memory cell is in the data write phase. That is, during the data write phase of the memory cell, the write word line enable circuit of this embodiment can automatically control the write transistor of the memory cell to remain turned on to facilitate writing new data to the storage node.

[0088] When the write disable instruction is a high-level signal, it indicates that the write word line WWL is not selected. At this time, the sense enable signal can be configured to be sent to the sense amplifier circuit 1011, that is, the sense amplifier circuit 1011 starts to work. At this time, there are two cases: (1) When the data signal on WBL is equal to the reference signal, the first output terminal and the second output terminal of the sense amplifier circuit 1011 output the same low-level signal, so that the output terminal of the NOR gate logic circuit 1012 will output a high-level signal and transmit it to the third input terminal of the NAND gate logic circuit 2011. Since the disable instruction received by the fourth input terminal of the NAND gate logic circuit 2011 is a high-level signal, the second logic output terminal of the NAND gate logic circuit 2011 will output a low-level signal to the write word line WWL at this time, so as to disconnect the write transistor through the write word line WWL. At this time, the stage of the memory cell can be the pre-processing stage, the pre-charging stage, the reading stage and the sensing stage. That is, in the pre-processing stage, the pre-charging stage, the reading stage and the sensing stage of the memory cell, the write word line enable circuit of this embodiment can automatically control the write transistor of the memory cell to be disconnected to avoid errors in the data stored in the storage node. (2) When the data signal on the write bit line WBL is greater than or less than the reference signal, the first output terminal and the second output terminal of the sense amplifier circuit 1011 output different level signals, so that the output terminal of the NOR gate logic circuit 1012 will output a low level signal and transmit it to the third input terminal of the NAND gate logic circuit 2011. Since the disable instruction received by the fourth input terminal of the NAND gate logic circuit 2011 is a high level signal, the second logic output terminal of the NAND gate logic circuit 2011 will output a high level signal to the write word line WWL at this time, so as to turn on the write transistor through the write word line WWL. At this time, the stage that the storage unit is in may be the write-back stage, that is, in the write-back stage of the storage unit, the write word line enable circuit of this embodiment can automatically control the write transistor of the storage unit to be turned on, so that the data signal transmitted on the write bit line WBL can be rewritten into the storage node to complete the data write-back process.

[0089] Thus, the write word line enable circuit of this embodiment can automatically turn on or off the write transistor at various stages of the 2TOC memory cell read and write process, thereby ensuring that the write transistor's on / off state meets the requirements of each stage of the memory cell read and write process. Furthermore, because this embodiment eliminates the need for highly precise control of the timing of the memory cell read and write process, as required by conventional delay circuits, it can improve read and write error tolerance.

[0090] Of course, in other suitable application scenarios, the storage unit may have other stages in the reading and writing process. In other stages not mentioned in this application, the write word line enable circuit can realize the automatic opening or closing of the write transistor and can also be adaptively changed according to the corresponding application scenario requirements or design. This embodiment does not limit this.

[0091] In one embodiment, Figure 6 As shown, the start control circuit 201 is connected to the write word line WWL through the write word line driver 301 ; wherein the write word line driver 301 is further connected to the write word line decoder 401 .

[0092] The input end of the write word line decoder 401 can be used to receive an address signal, and interpret the address signal into a write address signal and transmit it to the write word line driver 301. The write word line driver 301 can drive the write word line WWL according to the enable signal and the write address signal.

[0093] This application also provides a write word line enable control method, such as Figure 7 As shown, the write word line enable control method includes the following steps:

[0094] S101: Using a sensing control circuit to obtain a data signal transmitted by a write bit line in a memory cell; wherein the memory cell includes a read transistor and a write transistor, as well as a read word line and a read bit line connected to the read transistor, and a write word line and a write bit line connected to the write transistor.

[0095] The data signal transmitted by the write bit line WBL may vary according to the different stages of the memory cell during the read / write process. By acquiring the data signal transmitted by the write bit line WBL, it is possible to determine which stage of the read / write process the memory cell is in.

[0096] S102: Using a sensing control circuit to output a write control signal according to the data signal, wherein the write control signal can be used to form an enable signal to instruct the write transistor of the memory cell to turn on or off.

[0097] S103: using the startup control circuit to output an enable signal to the write word line according to the write control signal.

[0098] The enable signal may include a start signal and a disable signal. The start signal may control the read transistor of the memory cell to be turned on, and the disable signal may control the write transistor of the memory cell to be turned off.

[0099] The above-mentioned write word line enable control method utilizes a sensing control circuit to obtain a data signal transmitted by a write bit line in a memory cell. The memory cell includes a read transistor and a write transistor, as well as a read word line and a read bit line connected to the read transistor, and a write word line and a write bit line connected to the write transistor. The sensing control circuit outputs a write control signal based on the data signal, and a start-up control circuit outputs an enable signal to the write word line based on the write control signal. The enable signal issued by the start-up control circuit can control the write word line to accurately respond and promptly control the opening or closing of the write transistor. This eliminates the need for precise timing control of the memory cell's read and write processes, as required in related technologies, thereby improving read and write fault tolerance.

[0100] In one embodiment, the enable signal includes a start signal and a disable signal, and the working phases of the storage unit include a pre-processing phase, a pre-charge phase, a reading phase, a sensing phase, a write-back phase, and a data writing phase. Figure 8 As shown, the above step S103 includes:

[0101] S1031: Get a write disable instruction.

[0102] The write disable instruction may also include a low level signal and a high level signal. When the write disable instruction is a low level signal, it indicates that the write word line WWL is selected. When the write disable instruction is a high level signal, it indicates that the write word line WWL is not selected.

[0103] S1032: Determine the working stage of the storage unit according to the write control signal and the write disable instruction. When the storage unit works in the write-back stage and the data writing stage, an enable signal is output to the write word line WWL, so that the write word line WWL controls the write transistor to turn on; when the storage unit works in the pre-processing stage, the pre-charging stage, the reading stage and the sensing stage, a disable signal is output to the write word line WWL, so that the write word line WWL controls the write transistor to turn off.

[0104] The working stages of a memory cell can be roughly divided into the following stages: (1) pre-processing stage; (2) pre-charging stage; (3) reading stage; (4) sensing stage; (5) writing back stage; and (6) data writing stage. The description of the main stages of the memory cell can be found in the above content and will not be repeated here.

[0105] When the 2T0C memory cell is in the pre-processing stage, pre-charge stage, read stage, and sensing stage, the data signal transmitted by the write bit line WBL can be synchronized with the reference signal, so that the enable signal output by the start control circuit 201 is a disable signal. When the memory cell is in the write-back stage and the data writing stage, the data signal transmitted by the write bit line WBL can be synchronized with the sense signal output by the read sense amplifier, so that the enable signal output by the start control circuit 201 is an enable signal. For example, when the memory cell is in the read stage or the sensing stage, the sense control circuit 101 will obtain the data signal transmitted by the write bit line WBL and maintain it at the voltage or current value of the reference signal. At this time, the start control circuit 201 will determine the enable signal as a disable signal based on the corresponding write control signal. When the memory cell is in the write-back stage, the sense control circuit 101 will obtain the data signal transmitted by the write bit line WBL and convert it to the voltage or current value of the sense signal. At this time, the start control circuit 201 will determine the enable signal as an enable signal based on the corresponding write control signal.

[0106] Based on the above embodiment, in one embodiment, the above step S1032 includes: performing a logical AND operation on the write control signal and the write disable instruction to obtain an enable signal, and the enable signal is used to determine the working stage of the storage unit.

[0107] The working phase of the storage unit can be determined by the respective level states of the write control signal and the write disable instruction. For example, when the write disable instruction is a low-level signal, the phase of the storage unit can be the data write phase. When the write disable instruction is a high-level signal, it indicates that the write word line WWL is not selected. At this time, there are two cases: (1) When the data signal on the write bit line WBL is equal to the reference signal, the write control signal can be a high-level signal. At this time, the working phase of the storage unit can be the pre-processing phase, the pre-charging phase, the reading phase, and the sensing phase. (2) When the data signal on the write bit line WBL is greater than or less than the reference signal, the write control signal can be a low-level signal. At this time, the working phase of the storage unit can be the write-back phase.

[0108] Based on the above embodiment, in one embodiment, in step S1032, when the memory cell operates in the write-back phase, the data signal transmitted by the write bit line WBL is derived from the data signal fed back to the write bit line WBL by the read bit line RBL. That is, during the write-back phase, the sense amplifier used for reading also transmits the sense signal to the write bit line WBL, so that the data signal transmitted on the write bit line WBL is synchronized with the sense signal.

[0109] In one embodiment, Figure 9 As shown, the above step S102 includes:

[0110] S1021: Acquire a reference signal, and compare the magnitudes of the data signal and the reference signal.

[0111] The reference signal may be obtained from an external reference signal terminal, or may be the same as the reference signal required to be used by the storage unit during the reading and writing process.

[0112] Optionally, when the storage unit is in the pre-processing stage, pre-charging stage, reading stage, and sensing stage, the data signal may be the same as the reference signal; when the storage unit is in the write-back stage and the data writing stage, the data signal may be greater than or less than the reference signal. Of course, in other suitable application scenarios, the storage unit may also have other stages during the reading and writing process. In other stages not mentioned in this application, the data signal may also be adaptively changed according to the corresponding application scenario requirements or design, and this embodiment does not impose any restrictions thereon.

[0113] S1022: When the data signal is greater than or less than the reference signal, output two signals of different levels as the first output signal and the second output signal respectively; when the data signal is equal to the reference signal, output two signals of the same level as the first output signal and the second output signal respectively.

[0114] The level signal may include a low-level signal and a high-level signal. The low-level signal may be a level signal lower than the reference signal, and the high-level signal may be a level signal higher than the reference signal.

[0115] Exemplarily, when in the reading phase or the sensing phase, the data signal is equal to the reference signal, and the first output signal and the second output signal can be the same low-level signal. When in the write-back phase, assuming that the write-back data corresponding to the sensing signal in the write-back phase is "1", then the data signal can be greater than the reference signal at this time, then the first output signal can be a high-level signal, and the second output signal can be a low-level signal, that is, the first output signal and the second output signal are different level signals; assuming that the write-back data corresponding to the sensing signal in the write-back phase is "0", then the data signal can be less than the reference signal at this time, then the first output signal can be a low-level signal, and the second output signal can be a high-level signal, that is, the first output signal and the second output signal are still different level signals. Therefore, when the data signal is greater than or less than the reference signal, the first output signal and the second output signal can always be different level signals.

[0116] S1023: Perform a logical OR operation on the first output signal and the second output signal to obtain a write control signal.

[0117] When the first output signal and the second output signal are both low-level signals, after performing a logical OR operation, the obtained write control signal is a high-level signal, that is, the write control signal is a high-level signal at this time; when the first output signal and the second output signal are different-level signals, after performing a logical OR operation, the obtained write control signal is a low-level signal, that is, the write control signal is a low-level signal at this time.

[0118] Optionally, the reference signal may be a voltage value of half the power supply voltage (VDD), i.e., 1 / 2VDD, the low-level signal may be 0, and the high-level signal may be VDD. Alternatively, the reference signal may be VDD, the low-level signal may be 1 / 2VDD, and the high-level signal may be 3 / 2VDD. Depending on the application scenario, the reference signal, the low-level signal, and the high-level signal may be set in different ways, which are not limited in this embodiment.

[0119] In one embodiment, when the memory cell operates in the pre-processing stage, pre-charging stage, reading stage and sensing stage, the data signal is equal to the reference signal; when the memory cell operates in the write-back and data writing stages, the data signal is greater than or less than the reference signal.

[0120] For example, in the reading phase or the sensing phase, the sensing amplifier used for reading has not yet output a sensing signal to the write bit line WBL. At this time, the data signal transmitted by the write bit line WBL can be synchronized with the reference signal of the reference signal end. For the sensing amplifier circuit 1011, the voltage or current of the first receiving end and the second receiving end are the same at this time, then the first output end of the sensing amplifier circuit 1011 will output a low-level signal, and the second output end will also output a low-level signal. During the write-back phase, the sensing amplifier used for reading will also output the sensing signal to the write bit line WBL. At this time, the data signal transmitted by the write bit line WBL can be synchronized with the sensing signal output by the sensing amplifier used for reading. Assuming that the write-back data corresponding to the sensing signal in the write-back phase is "1", the data signal transmitted by the write word line WWL at this time can be greater than the reference signal, causing the data signal on the write word line WWL to be synchronized to be greater than the reference signal. At this time, the first output end of the sensing amplifier circuit 1011 will output a high-level signal, and the second output end will also output a low-level signal, that is, the two output ends of the sensing amplifier circuit 1011 will output different level signals; assuming that the write-back data corresponding to the sensing signal in the write-back phase is "0", the data signal transmitted by the write word line WWL at this time can be less than the reference signal, causing the data signal on the write word line WWL to be synchronized to be less than the reference signal. At this time, the first output end of the sensing amplifier circuit 1011 will output a low-level signal, and the second output end will also output a high-level signal, that is, the two output ends of the sensing amplifier circuit 1011 will also output different level signals. Therefore, when the data signal is greater than or less than the reference signal, the first output terminal and the second output terminal of the sense amplifier circuit 1011 can always output signals of different levels.

[0121] Furthermore, when the data signal is equal to the reference signal, the first output terminal and the second output terminal of the sense amplifier circuit 1011 output the same level signal, specifically, the same low-level signal. After the two input terminals of the NAND gate receive the same low-level signal, its first logic output terminal will output a high-level signal to the startup control circuit 201. When the data signal is greater than or less than the reference signal, the first output terminal and the second output terminal of the sense amplifier circuit 1011 output different level signals. Specifically, the first output terminal outputs a low-level signal and the second output terminal outputs a high-level signal, or the first output terminal outputs a high-level signal and the second output terminal outputs a low-level signal. After the two input terminals of the NAND gate receive different level signals, its first logic output terminal will output a high-level signal to the startup control circuit 201.

[0122] Optionally, the reference signal may be a voltage value of half the power supply voltage VDD, i.e., 1 / 2VDD, the low-level signal may be 0, and the high-level signal may be VDD. Alternatively, the reference signal may be VDD, the low-level signal may be 1 / 2VDD, and the high-level signal may be 3 / 2VDD. Depending on the application scenario, the reference signal, the low-level signal, and the high-level signal may be set in different ways, which are not limited in this embodiment.

[0123] In one embodiment, when the data signal is greater than the reference signal, the first output signal is a high level signal and the second output signal is a low level signal; when the data signal is less than the reference signal, the first output signal is a low level signal and the second output signal is a high level signal.

[0124] In one embodiment, the write word line enable control method further includes: in response to a sensing enable signal, executing the steps of acquiring a data signal transmitted by the write bit line and outputting a write control signal according to the data signal.

[0125] See Figure 4 If the control terminal of the sense amplifier circuit 1011 does not receive the sense enable signal, the sense amplifier circuit 1011 does not operate. At this time, the first output terminal and the second output terminal of the sense amplifier circuit 1011 both output low-level signals. If the control terminal of the sense amplifier circuit 1011 receives the sense enable signal, the sense amplifier circuit 1011 starts to operate. Assuming that the data signal on the WBL is equal to the reference signal, the first output terminal and the second output terminal of the sense amplifier circuit 1011 still output low-level signals. If the data signal on the WBL is less than the reference signal, the first output terminal outputs a low-level signal and the second output terminal outputs a high-level signal. If the data signal on the WBL is greater than the reference signal, the first output terminal outputs a low-level signal and the second output terminal outputs a high-level signal.

[0126] See Figure 5 Based on this embodiment, the working process of the write word line enable control method applied to the write word line enable circuit in any of the above embodiments is described in detail. Of course, the following description is only for a better understanding of this solution and does not constitute a limitation on other embodiments.

[0127] When the write disable instruction is a low-level signal, it indicates that the write word line WWL is selected. At this time, regardless of whether the third input terminal of the NAND logic circuit 2011 receives a high-level signal or a low-level signal, the second logic output terminal of the NAND logic circuit 2011 will output a high-level signal to the write word line WWL, allowing the write word line WWL to control the write transistor of the memory cell to turn on. At this time, the sense enable signal can be configured not to be sent to the sense amplifier circuit 1011, that is, the sense amplifier circuit 1011 is inoperative. The data signal on the write bit line WBL can be the new data signal to be written. After the write transistor is turned on, the new data signal on the write bit line WBL can be smoothly written to the storage node. Furthermore, when the write disable instruction is a low-level signal, the memory cell is in the data write phase. That is, during the data write phase of the memory cell, the write word line enable control method of this embodiment can automatically control the write transistor of the memory cell to remain turned on to facilitate writing new data to the storage node.

[0128] When the write disable instruction is a high-level signal, it indicates that the write word line WWL is not selected. At this time, the sense enable signal can be configured to be sent to the sense amplifier circuit 1011, that is, the sense amplifier circuit 1011 starts to work. At this time, there are two cases: (1) When the data signal on the write bit line WBL is equal to the reference signal, the first output terminal and the second output terminal of the sense amplifier circuit 1011 output the same low-level signal, so that the output terminal of the NOR gate logic circuit 1012 will output a high-level signal and transmit it to the third input terminal of the NAND gate logic circuit 2011. Since the disable instruction received by the fourth input terminal of the NAND gate logic circuit 2011 is a high-level signal, the second logic output terminal of the NAND gate logic circuit 2011 will output a low-level signal to the write word line WWL at this time, so as to disconnect the write transistor through the write word line WWL. At this time, the stage of the memory cell can be the pre-processing stage, the pre-charging stage, the reading stage and the sensing stage. That is, in the pre-processing stage, the pre-charging stage, the reading stage and the sensing stage of the memory cell, the write transistor of the memory cell can be automatically controlled to be disconnected by the write word line enable control method of this embodiment to avoid errors in the data stored in the storage node. (2) When the data signal on the write bit line WBL is greater than or less than the reference signal, the first output terminal and the second output terminal of the sense amplifier circuit 1011 output different level signals, so that the output terminal of the NOR gate logic circuit 1012 will output a low level signal and transmit it to the third input terminal of the NAND gate logic circuit 2011. Since the disable instruction received by the fourth input terminal of the NAND gate logic circuit 2011 is a high level signal, the second logic output terminal of the NAND gate logic circuit 2011 will output a high level signal to the write word line WWL at this time, so as to turn on the write transistor through the write word line WWL. At this time, the stage that the storage unit is in may be the write-back stage, that is, in the write-back stage of the storage unit, the write word line enable control method of this embodiment can automatically control the write transistor of the storage unit to be turned on, so that the data signal transmitted on the write bit line WBL can be rewritten into the storage node to complete the data write-back process.

[0129] Thus, the write word line enable control method of this embodiment can be used to automatically turn on or off the write transistor at various stages of the 2T0C memory cell read and write process. This ensures that the write transistor's on / off state meets the requirements of each stage of the 2T0C memory cell read and write process. Furthermore, because this embodiment eliminates the need for highly precise timing control of the 2T0C memory cell read and write process, as required in conventional techniques, it can improve read and write error tolerance.

[0130] The present application also provides a memory, such as Figure 10As shown, the memory includes: at least one memory array, the memory array including a plurality of memory cells, the memory cells including read transistors and write transistors, a read word line and a read bit line connected to the read transistors, and a write word line and a write bit line connected to the write transistors; and at least one write word line enable circuit according to any of the above embodiments, the write word line enable circuit being connected to the write bit line and the write word line in the corresponding memory array, respectively.

[0131] Generally, a memory may include at least one memory array, and a read bit line in a memory array may be connected to a SA circuit for reading, where SA is a sense amplifier (SA). The SA circuit amplifies and outputs the sensed signal of the read bit line, and the sensed signal is also output to the write bit line to implement data write-back. For example, see Figure 11 , Figure 11 The memory array 10 includes a memory array including at least one sense amplifier 20 for reading. The memory array 10 also includes a plurality of memory cells 11 arranged in an array, each memory cell 11 including two transistors. W-BL1, W-BL2, and W-BL3 are write bit lines, W-WL1, W-WL2, and W-WL3 are write word lines, R-BL1, R-BL2, and R-BL3 are read bit lines, R-WL1, R-WL2, and R-WL3 are read word lines, and VREF is a reference signal (the reference signal here is a voltage signal, but in other suitable embodiments, the reference signal may also be a current signal).

[0132] Each memory array also has a corresponding peripheral circuit. Of course, in some embodiments, two adjacent memory arrays may share a peripheral circuit or a portion of the circuit. The peripheral circuit includes a sense amplifier, which not only amplifies the read signal but also performs a write-back operation. The write-back operation requires triggering by the write word line enable circuit.

[0133] The memory device includes at least one memory array, the memory array including multiple memory cells, each memory cell including a read transistor and a write transistor, as well as a read word line and a read bit line connected to the read transistor, and a write word line and a write bit line connected to the write transistor; and at least one write word line enable circuit as described in any of the above embodiments, the write word line enable circuit being connected to the write bit line and the write word line in the corresponding memory array. By activating an enable signal issued by the control circuit, the write word line can be controlled to accurately respond, thereby timely controlling the turning on or off of the write transistor. This eliminates the need for precise timing control of the read and write processes of the memory cell, as required in related art, thereby improving read and write fault tolerance.

[0134] Alternatively, a memory array may be equipped with only one write word line enable circuit, which is connected to the write bit lines and write word lines in the memory array in a one-to-one correspondence. In other words, generally, only one write word line enable circuit is needed to meet the write word line enable requirements of the entire memory array. Therefore, in the design of the actual physical location of the memory array, in a memory array, such as Figure 9 As shown, the write word line enable circuit can be designed at the intersection area, so that the design area occupied is extremely small. Figure 9 As shown, the periphery of the memory array can also be designed as the location of a write word line WWL decoder (WWL Decoder), a read word line sense amplifier (RBL SA), and a read word line decoder (RBL Decoder).

[0135] In one embodiment, Figure 6 As shown, the memory further includes a write word line driver and a write word line decoder. The start control circuit is connected to the write word line through the write word line driver, and the write word line driver is also connected to the write word line decoder.

[0136] The present application also provides an electronic device including the memory of the above embodiment. A write word line enable circuit in the memory can control the write word line to accurately respond and timely control the turn-on or turn-off of the write transistor, thereby eliminating the need for precise timing control of the read and write processes of the memory cell as required in the related art, thereby improving read and write fault tolerance.

[0137] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present application. The schematic descriptions of these terms throughout this specification do not necessarily refer to the same embodiment or example.

[0138] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0139] The above embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A write word line enable circuit, configured to be connected to a memory cell, wherein the memory cell comprises a read transistor and a write transistor, and a read word line and a read bit line connected to the read transistor, and a write word line and a write bit line connected to the write transistor, wherein: include: a sensing control circuit connected to the write bit line and configured to: obtain a data signal transmitted by the write bit line and output a write control signal according to the data signal; The sensing control circuit includes: A sense amplifier circuit having a first receiving end, a second receiving end, a first output end, and a second output end; wherein the first receiving end is connected to the write bit line for receiving a data signal transmitted by the write bit line, and the second receiving end is connected to a reference signal end for receiving a reference signal; the sense amplifier circuit is configured to: when the data signal is greater than or less than the reference signal, cause the first output end and the second output end to output signals of different levels; and when the data signal is equal to the reference signal, cause the first output end and the second output end to output signals of the same level; a NOR gate logic circuit having a first input terminal, a second input terminal, and a first logic output terminal; wherein the first input terminal is connected to the first output terminal of the sense amplifier circuit, the second input terminal is connected to the second output terminal of the sense amplifier circuit, and the first logic output terminal is connected to the startup control circuit; The startup control circuit is connected to the sensing control circuit and the write word line, and is configured to output an enable signal to the write word line according to the write control signal.

2. The write word line enable circuit according to claim 1, wherein: The enable signal includes a turn-on signal and a turn-off signal. The working stages of the storage unit include a preprocessing stage, a precharge stage, a reading stage, a sensing stage, a write-back stage, and a data writing stage. The startup control circuit is further configured to: obtain a write-disable instruction, determine the working stage of the storage unit according to the write control signal and the write-disable instruction, and when the storage unit is working in the write-back stage and the data writing stage, output the turn-on signal to the write word line so that the write word line controls the write transistor to turn on; when the storage unit is working in the preprocessing stage, the precharge stage, the reading stage, and the sensing stage, output the turn-off signal to the write word line so that the write word line controls the write transistor to turn off.

3. The write word line enable circuit according to claim 1, wherein: The sensing amplifier circuit further has a control terminal; the control terminal is configured to receive a sensing enable signal.

4. The write word line enable circuit according to any one of claims 1 to 3, wherein: The startup control circuit includes: A NAND gate logic circuit has a third input terminal, a fourth input terminal and a second logic output terminal; wherein the second logic output terminal is connected to the write word line, the third input terminal is connected to the first logic output terminal of the sensing control circuit, and the fourth input terminal is configured to receive a write disable instruction.

5. A write word line enable control method, characterized in that: The write word line enable control method is applied to the write word line enable circuit according to any one of claims 1 to 4, and the write word line enable control method includes: A sensing control circuit is used to acquire a data signal transmitted by a write bit line in a memory cell; wherein the memory cell includes a read transistor and a write transistor, and a read word line and a read bit line connected to the read transistor, and a write word line and a write bit line connected to the write transistor; Using the sensing control circuit to output a write control signal according to the data signal; A startup control circuit is used to output an enable signal to the write word line according to the write control signal.

6. The write word line enable control method according to claim 5, wherein: The enable signal includes an enable signal and a disable signal. The working phases of the storage unit include a pre-processing phase, a pre-charging phase, a reading phase, a sensing phase, a write-back phase, and a data writing phase. Outputting the enable signal to the write word line according to the write control signal includes: Get write disable instruction; The working phase of the storage unit is determined according to the write control signal and the write disable instruction. When the storage unit is working in the write-back phase and the data writing phase, the enable signal is output to the write word line so that the write word line controls the write transistor to turn on. When the storage unit is working in the pre-processing phase, the pre-charging phase, the reading phase and the sensing phase, the disable signal is output to the write word line so that the write word line controls the write transistor to turn off.

7. The write word line enable control method according to claim 6, wherein: The determining the working phase of the storage unit according to the write control signal and the write disable instruction includes: A logical NOT operation is performed on the write control signal and the write disable instruction to obtain the enable signal, where the enable signal is used to determine the working phase of the storage unit.

8. The write word line enable control method according to claim 6, wherein: When the memory cell operates in a write-back phase, the data signal transmitted by the write bit line comes from the data signal fed back to the write bit line by the read bit line.

9. The write word line enable control method according to claim 5, wherein: Outputting a write control signal according to the data signal includes: Acquire a reference signal, and compare the magnitudes of the data signal and the reference signal; When the data signal is greater than or less than the reference signal, two signals of different levels are output as the first output signal and the second output signal respectively; when the data signal is equal to the reference signal, two signals of the same level are output as the first output signal and the second output signal respectively; Perform a logical negation operation on the first output signal and the second output signal to obtain the write control signal.

10. The write word line enable control method according to claim 9, wherein: The working phases of the storage unit include a pre-processing phase, a pre-charging phase, a reading phase, a sensing phase, a write-back phase, and a data writing phase. When the storage unit is working in the pre-processing phase, the pre-charging phase, the reading phase, and the sensing phase, the data signal is equal to the reference signal. When the storage unit operates in the write-back and data writing phases, the data signal is greater than or less than the reference signal.

11. The write word line enable control method according to claim 9, wherein: When the data signal is greater than the reference signal, the first output signal is a high level signal and the second output signal is a low level signal; when the data signal is less than the reference signal, the first output signal is a low level signal and the second output signal is a high level signal.

12. The write word line enable control method according to claim 5, wherein: Also includes: In response to a sensing enable signal, the steps of acquiring a data signal transmitted by a write bit line in a memory cell and outputting a write control signal according to the data signal are performed.

13. A memory, characterized in that: include: at least one memory array, the memory array comprising a plurality of memory cells, the memory cells comprising a read transistor and a write transistor, a read word line and a read bit line connected to the read transistor, and a write word line and a write bit line connected to the write transistor; At least one write word line enable circuit according to any one of claims 1 to 4, wherein the write word line enable circuit is connected to the write bit line and the write word line in the corresponding memory array respectively.

14. The memory according to claim 13, wherein: The memory further includes a write word line driver and a write word line decoder. The start control circuit is connected to the write word line through the write word line driver. The write word line driver is also connected to the write word decoder.

15. An electronic device, characterized in that: The method comprises the memory as claimed in any one of claims 13 to 14.

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