A dram-based in-memory logic operation circuit and system

Abstract

The application belongs to the technical field of integrated circuits, and discloses an in-memory logic operation circuit and system based on DRAM. The in-memory logic operation circuit comprises two DRAM units and a sense amplifier for generating a logic operation result. The in-memory logic operation circuit defines a group of logic input signals as the storage content of the DRAM units, defines another group of logic input signals as the readout control signals of the circuit, and defines the double-phase output signals of the sense amplifier as the positive and negative phase output results of the logic operation. On this basis, the in-memory logic operation system provided by the application comprises at least one in-memory logic operation circuit, a write word line, a write bit line, a read word line decoding and driving circuit, a logic configuration circuit, and a control circuit. The application provides an in-memory logic operation circuit scheme while keeping the storage function of the in-memory logic operation circuit from being destroyed, and improves the compatibility of the in-memory logic operation and the memory array.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of integrated circuits, and more particularly, relates to a dynamic random access memory (DRAM) based in-memory logic operation circuit and system. BACKGROUND

[0002] In the application scenarios of face recognition, target detection, wearable health detection, etc. of edge computing, due to the limited resources of mobile edge devices, the memory wall bottleneck problem of the traditional von Neumann architecture is very prominent. Computing in memory (CIM) is a new architecture suitable for deep neural network (DNN) operation which is data-centered. By embedding part of the matrix calculation-based operation logic into the memory architecture, the high latency and high power consumption data communication between the memory and the processor is avoided, and the energy consumption and computation delay are reduced. Computing in memory is a targeted method to solve the above-mentioned memory wall problem, which greatly improves the hardware processing performance of deep neural network applications.

[0003] In the implementation of computing in memory of deep neural networks, the computing architecture based on DRAM is a widely concerned technical route. DRAM uses the amount of charge stored in the capacitor at the storage node as a physical state variable. Generally, a high amount of charge is used as a logical "1", and a low amount of charge is used as a logical "0". In the current computing scheme based on DRAM, a group of input data is generally configured as a group of input signals of the storage and calculation unit, and the input value is represented by the pulse width or amplitude of the voltage pulse. Another group of input data is generally configured as the storage content of the storage and calculation unit, and the calculation result is represented by the values of basic electrical parameters such as voltage, current and charge between the storage and calculation unit and the storage unit, mainly including logical operation, multiplication and addition operation, etc.

[0004] Focusing on the computing strategy in DRAM, in recent years, many papers have provided storage and calculation circuit solutions based on DRAM. The DRISA system based on 1T1C has realized the in-memory deployment of logical operations such as addition and shift. The system composed of DARAM units based on 3T1C has realized the in-memory deployment of multiplication and addition represented by analog voltage values. However, most of the existing in-memory logic operation circuits based on DRAM are based on the principle of analog charge sharing, which greatly reduces the readout margin compared to the readout operation of the conventional storage DRAM chip during the calculation process. Although the existing complex operation circuit based on DRAM has improved the calculation density and parallelism, it still has the problems of low calculation precision and complex peripheral circuit. Moreover, most of the existing operation circuits based on DRAM adjust the unit and array structure to realize the operation function, so that the DRAM storage and calculation system no longer supports the conventional storage function.

[0005] In summary, how to provide programmable in-memory logic computing function while ensuring compatibility of logic computing and storage array storage function, improve the computing accuracy of hardware accelerators for deep neural network and other applications, and reduce the complexity of peripheral circuit, is still a key problem in the field of in-memory computing. SUMMARY

[0006] In view of the above defects or improvement needs of the prior art, the present application provides a DRAM-based in-memory logic operation circuit and system, which aims to provide programmable in-memory logic computing function while ensuring compatibility of logic computing and storage function, and improve the computing accuracy.

[0007] To achieve the above-mentioned purpose, according to the first aspect of the present application, a DRAM-based in-memory logic operation circuit is provided, comprising: a DRAM-based in-memory logic computing unit and a sense amplifier; wherein the in-memory logic computing unit comprises a first storage unit and a second storage unit;

[0008] The first storage unit and the second storage unit each comprise a write tube TW and N connected read tubes TR, N≥1; the gate of the write tube TW is connected to a write word line, the source is connected to a write bit line, and the drain is connected to the first end of the N connected read tubes TR, and the node of the connection is a storage node; the second end of the N connected read tubes TR is connected to a read word line, and the third end is connected to a read bit line;

[0009] The read bit lines of the first storage unit and the second storage unit are connected together and connected to the positive input terminal of the sense amplifier; the signal received by the positive input terminal is compared with the reference signal received by the inverting input terminal of the sense amplifier, and a logic operation result is generated;

[0010] Wherein, the first group of logic input signals (Din1, Din1') of the in-memory logic operation circuit correspond to the storage node voltages of the first storage unit and the second storage unit, which represent logic "1" when the read tube TR is turned on, and represent logic "0" when the read tube TR is turned off; the second group of logic input signals (Din2, Din2') correspond to the read word line signals connected to the first storage unit and the second storage unit, which represent logic "1" when read enabled, and represent logic "0" when standby.

[0011] Further, when N=1, the first end of the read tube TR is the gate, the second end is the drain, and the third end is the source;

[0012] When N=2, the connection mode of the two read tubes TR is: the drain of one read tube is connected to ground, the gate is connected to the drain of the write tube TW, and the source is connected to the drain of the other read tube; the gate of the other read tube is connected to the read word line, and the source is connected to the read bit line.

[0013] According to a second aspect of the present application, a logic operation method based on the in-memory logic operation circuit of the first aspect is provided, including a read operation and a logic "not" operation, specifically: storing a first logic input signal Din1(A) to the storage node of the first storage unit, inputting the inverse signal of Din1(A) to the storage node of the second storage unit;

[0014] The read word line signal connected to the first storage unit is used as the first storage unit read control signal, and the read word line signal connected to the second storage unit is used as the second storage unit read control signal;

[0015] When the first storage unit read control signal is read enable and the second storage unit read control signal is standby, the non-inverted output signal of the sense amplifier is the first storage unit readout signal Dout(A), and the inverted output signal is the "not" operation result of the first storage unit

[0016] When the first storage unit read control signal is standby and the second storage unit read control signal is read enable, the non-inverted output signal of the sense amplifier is the second storage unit readout signal and the inverted output signal is the "not" operation result of the second storage unit

[0017] Further, it also includes a logic "and / not and" operation, specifically:

[0018] Storing a first logic input signal Din1(A) to the storage node of the first storage unit, inputting the inverse signal of Din1(A) to the storage node of the second storage unit;

[0019] The read word line signal connected to the first storage unit is the second logic input signal Din2(B), and the read word line signal connected to the second storage unit is the standby signal representing logic "0";

[0020] Then the sense amplifier outputs the "and" and "not and" mutually inverted logic output potential signals Dout(A·B) and

[0021] Further, it also includes a logic "or / not or" operation, specifically:

[0022] ​​The first logic input signal Din1(A) is stored to the storage node of the first storage unit, and the inverse signal of Din1(A) is input to the storage node of the second storage unit. The read word line signal connected to the first storage unit is a read enable signal representing logic "1", and the read word line signal connected to the second storage unit is the second logic input signal Din2'(B).

[0023] The "or" and "NOR" logic output potential signals Dout(A+B) and Dout(A+B)' output by the sensitive amplifier are inverse to each other.

[0024] The "XOR" and "XOR" logic output potential signals Dout(A B) and Dout(A B)' output by the sensitive amplifier are inverse to each other.

[0025] Further, it also includes a logic "XOR" operation, specifically:

[0026] The first logic input signal Din1(A) is stored to the storage node of the first storage unit, and the inverse signal of Din1(A) is input to the storage node of the second storage unit. The read word line signal connected to the first storage unit is a read enable signal representing logic "1", and the read word line signal connected to the second storage unit is the second logic input signal Din2'(B).

[0027] The read word line signal connected to the first storage unit is a read enable signal representing logic "1", and the read word line signal connected to the second storage unit is the second logic input signal Din2'(B).

[0028] The "XOR" and "XOR" logic output potential signals Dout(A B) and Dout(A B)' output by the sensitive amplifier are inverse to each other.

[0029] According to a third aspect of the present application, a DRAM-based in-memory computing system is provided, comprising: at least one in-memory logic computing unit, at least one sensitive amplifier, a write word line decoding and driving circuit, a write bit line decoding and driving circuit, a read word line decoding and driving circuit, a logic configuration circuit, and a control circuit; wherein the in-memory logic computing unit and the sensitive amplifier correspond to the in-memory logic computing unit and the sensitive amplifier of the first aspect.

[0030] The in-memory logic computing units are connected to form an array structure, the first storage unit and the second storage unit in the same in-memory logic computing unit are located in the same column, and the in-memory logic computing units in each column share a common read bit line and a common sensitive amplifier, so that each in-memory logic computing unit in the same column and the sensitive amplifier in the column can form the in-memory logic operation circuit of the first aspect, and the in-memory logic computing units in each column share a common write bit line.

[0031] The first storage unit and the second storage unit in each row of the in-memory logic calculation unit use respective corresponding read word lines RWL1 and RWL2 and respective corresponding write word lines; the in-memory logic operation units in the same row share the same RWL1 and RWL2 and perform parallel logical operations between them;

[0032] The write word line decoding and driving circuit is configured to, under the control of the control circuit, convert external address signals into write word line signals of the array;

[0033] The write bit line decoding and driving circuit is configured to, under the control of the control circuit, convert external data signals into write bit line signals of the array;

[0034] The read word line decoding and driving circuit is configured to, under the control of the control circuit, convert external address signals into read word line signals of the array;

[0035] The logic configuration circuit is configured to, under the control of the control circuit, switch the configured logic input signals to enable the in-memory logic operation circuit to perform logical operations.

[0036] Further, the logic input signal configuration for the in-memory logic operation circuit includes configuration of a first group of logic input signals (Din1, Din1') and configuration of a second group of logic input signals (Din2, Din2') to enable any one or more of reading and logical NOT operation, logical AND / NOT operation, logical OR / NOT operation, and logical XOR operation;

[0037] The first group of logic input signals (Din1, Din1') is configured to store the first logic input signal Din1(A) to the storage node of the first storage unit and input the inverse signal of Din1(A) to the storage node of the second storage unit;

[0038] The second group of logic input signals (Din2, Din2') is configured to be logic "1" and logic "0" when reading and logical NOT operation is performed, to be Din2(B) and logic "0" when logical AND / NOT operation is performed, to be logic "1" and Din2'(B) when logical OR / NOT operation is performed, and to be Din2(B) and the inverse signal of Din2(B) when logical XOR operation is performed.​

[0039] According to a fourth aspect of the present application, there is provided an in-memory computing hardware accelerator, on which the DRAM-based in-memory computing system of the third aspect is deployed.

[0040] In general, the above technical solutions conceived by the present application can achieve the following beneficial effects:

[0041] (1) The DRAM-based in-memory logic operation circuit in the present application directly uses DRAM cells (first and second storage cells) to construct an in-memory logic computing unit, without damaging the conventional access function of DRAM, and realizes in-memory logic computation without modifying the structure of the storage cells and the read-write circuit, with a simple structure. The terminals of the write transistor TW are directly connected to the write word line and the write bit line, and the terminals of the read transistor TR are directly connected to the read word line and the read bit line, so that when the array is applied to an in-memory logic operation system, the peripheral circuit structure does not need to be changed. Moreover, the input of the in-memory logic operation circuit of the present application is pure digital logic, and there is no loss of precision due to truncation when performing complex logic operations, with higher precision compared to existing in-memory logic circuits that represent input values through the pulse width or amplitude of a voltage pulse.

[0042] (2) Further, based on the in-memory logic operation circuit of the present application, one or more of the conventional access, "NOT", "AND / NOT", "OR / NOT", and "XOR" logic computations can be realized by configuring two groups of logic input signals.

[0043] (3) Further, the in-memory computing system composed of the in-memory logic operation circuit of the present application fully utilizes the parallel readout characteristics of the array, and realizes parallel computation of logic operations without changing the peripheral circuit structure.

[0044] (4) Further, the in-memory computing system in the present application is deployed on an in-memory computing hardware accelerator, and in the process of multiplying and accumulating the input data and the weight data, the weight data in the DRAM storage array is not damaged and can be reused in multiple computing processes, which can improve the accuracy of the computation.

[0045] In summary, the present application provides an in-memory logic operation circuit solution while maintaining the storage function of the in-memory logic operation circuit, and improves the compatibility of in-memory logic operation and memory arrays. BRIEF DESCRIPTION OF DRAWINGS

[0046] Figure 1 FIG. 1 is a structural schematic diagram of the DRAM-based in-memory logic operation circuit in an embodiment of the present application;

[0047] Figure 2The schematic diagram of the in-memory logic operation circuit based on 2T DRAM and the input signal setting scheme provided by the embodiment of the present application is shown in Figure 1, wherein, Figure 2 (a) in Figure 1 is the in-memory logic operation circuit, and (b) is the schematic diagram of the input signal setting scheme.

[0048] Figure 3 The circuit schematic diagram and truth table of the in-memory logic operation circuit of DRAM for implementing logic normal reading and "NOT" operation provided by the embodiment of the present application are shown in Figure 2, wherein, Figure 3 (a) in Figure 2 is the circuit schematic diagram for implementing logic normal reading and "NOT" operation, and (b) is the corresponding truth table.

[0049] Figure 4 The circuit schematic diagram and truth table of the in-memory logic operation circuit of DRAM for implementing logic "AND / NOT" operation provided by the embodiment of the present application are shown in Figure 3, wherein, Figure 4 (a) in Figure 3 is the circuit schematic diagram for implementing logic "AND / NOT" operation, and (b) is the corresponding truth table.

[0050] Figure 5 The circuit schematic diagram and truth table of the in-memory logic operation circuit of DRAM for implementing logic "OR / NOT" operation provided by the embodiment of the present application are shown in Figure 4, wherein, Figure 5 (a) in Figure 4 is the circuit schematic diagram for implementing logic "OR / NOT" operation, and (b) is the corresponding truth table.

[0051] Figure 6 The circuit schematic diagram and truth table of the in-memory logic operation circuit of DRAM for implementing logic "XOR / NOT" operation provided by the embodiment of the present application are shown in Figure 5, wherein, Figure 6 (a) in Figure 5 is the circuit schematic diagram for implementing logic "XOR / NOT" operation, and (b) is the corresponding truth table.

[0052] Figure 7 The schematic diagram of the in-memory computing system structure based on DRAM provided by the embodiment of the present application is shown in Figure 6.

[0053] Figure 8 The configuration mode schematic diagram of the in-memory computing system of DRAM for implementing normal reading and logic "NOT", "AND / NOT", "OR / NOT", and "XOR / NOT" operations provided by the embodiment of the present application is shown in Figure 7.

[0054] Figure 9 The parallel operation schematic diagram of the in-memory computing system of DRAM provided by the embodiment of the present application is taken as an example of the input vector and weight vector multiplication and addition operation in the neural network convolutional computing application.

[0055] In all the drawings, the same reference signs are used to represent the same elements or structures, wherein,

[0056] 1 is the in-memory logic calculation unit, 2 is the sensitive amplifier, 3 is the logic configuration circuit, 4 is the write word line decoder and drive circuit, 5 is the write bit line decoder and drive circuit, 6 is the read word line decoder and drive circuit, 7 is the control circuit; 11 is the first memory unit, 12 is the second memory unit, 111 and 121 are the first MOSFETs, and 112 and 122 are the second MOSFETs. Detailed Implementation

[0057] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0058] In this invention, the terms "first," "second," etc., used in the invention and accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0059] Example 1

[0060] like Figure 1 As shown, this embodiment of the invention provides a DRAM-based in-memory logic operation circuit, mainly including: a DRAM-based in-memory logic calculation unit 1, and a sensitive amplifier 2 for generating logic operation results; the in-memory logic calculation unit 1 includes a first memory unit and a second memory unit connected by read bit lines; wherein, the first memory unit and the second memory unit are DRAM units.

[0061] The first storage unit includes a write tube TW and N read tubes TR, and the second storage unit includes a write tube TW and N read tubes TR, where N≥1;

[0062] When N=1, the gate of the write transistor TW in the first or second memory cell is connected to the write word line, the source is connected to the write bit line, and the drain is connected to the gate of the read transistor TR. The node where the write transistor TW and the read transistor TR are connected is called the memory node; the drain of the read transistor TR is connected to the read word line, and the source is connected to the read bit line.

[0063] When N > 1, the gate of the write transistor TW in the first or second memory cell is connected to the write word line, the source is connected to the write bit line, and the drain is connected to the first end of the N connected read transistors TR. This connected node is called a memory node. The second end of the N connected read transistors TR is connected to the read word line, and the third end of the N connected read transistors TR is connected to the read bit line.

[0064] The read bit line connected with the first storage unit and the second storage unit is connected with the positive input terminal of the sensitive amplifier 2; the signal received by the positive input terminal is compared with the reference signal amplitude of the reverse input terminal of the sensitive amplifier 2 to generate a logic operation result; wherein the positive and reverse output signals of the sensitive amplifier are defined as the positive and reverse output results of the logic operation; the signal received by the positive input terminal of the sensitive amplifier 2 is the current or voltage signal after the logic operation of the first storage unit and the second storage unit.

[0065] It should be noted that when N>1, the connection mode between the N read-out tubes TR in the embodiment of the present application is not limited, as long as the N read-out tubes TR can be equivalent to the function of the read-out tube TR when N=1 after connection. As one of the implementation modes, when N=2, the connection mode between the two read-out tubes TR (denoted as TR1 and TR2) is as follows:

[0066] The drain of the first read-out tube TR1 is grounded, the gate is connected with the drain of the write-in tube TW, the source is connected with the drain of the second read-out tube TR2, the gate of the second read-out tube TR2 is connected with the read word line, and the source of the second read-out tube TR2 is connected with the read bit line.

[0067] As a specific implementation mode, the above-mentioned storage-in logic operation circuit defines a group of logic input signals as the voltage level of the storage node, and assumes that the storage node represents logic "1" when the read-out tube TR is turned on, and represents logic "0" when the read-out tube TR is turned off; another group of logic input signals is defined as the potential signal input to the read-out tube TR through the read word line connected with the first storage unit and the second storage unit (i.e. the read word line signal connected with the two storage units), and assumes that any potential signal represents logic "1" when reading is enabled, and represents logic "0" otherwise (i.e. when not reading, or when in standby).

[0068] In the embodiments of the present application, the gate of the write-in tube TW is connected with the write word line (WWL for short), the source is connected with the write bit line (WBL for short), and the drain is connected with the gate of the read-out tube TR; the node connected with the read-out tube TR is called the storage node; the drain of the read-out tube TR is connected with the read word line (RWL for short), and the source is connected with the read bit line (RBL for short).

[0069] Next, taking N=1 as an example, a DRAM-based storage-in logic operation circuit is illustrated as shown in (a) of FIG. 1, and the corresponding mode of the physical signal and the logic information of the DRAM-based storage-in logic operation circuit is illustrated as shown in (b) of FIG. 1. Figure 2 Figure 2 As shown in (a) of FIG. 1, the DRAM-based storage-in logic operation circuit includes a read-out tube TR, a write-in tube TW, a first storage unit and a second storage unit.

[0070] As shown in (b) of FIG. 1, the DRAM-based storage-in logic operation circuit includes a read-out tube TR, a write-in tube TW, a first storage unit and a second storage unit.​Figure 2 As shown in (a) of FIG. 1, the DRAM-based in-memory logic operation circuit includes a DRAM-based in-memory logic computing unit 1 and a sense amplifier 2 for generating a logic operation result. The in-memory logic computing unit 1 includes a first storage unit 11 and a second storage unit 12. The first storage unit is composed of a first MOS transistor 111 (write-in transistor of the first storage unit) and a second MOS transistor 112 (read-out transistor of the first storage unit), and the drain of the first MOS transistor 111 is connected to the gate of the second MOS transistor 112. The second storage unit is composed of a first MOS transistor 121 (write-in transistor of the second storage unit) and a second MOS transistor 122 (read-out transistor of the second storage unit), and the drain of the first MOS transistor 121 is connected to the gate of the second MOS transistor 122. The gate terminals of the write-in transistors of the two groups of storage units (the first storage unit 11 and the second storage unit 12) are connected to a WWL, the source terminals of the write-in transistors of the two groups of storage units are connected to a WBLL and a WBLR respectively, the drain terminals of the read-out transistors of the two groups of storage units are connected to a RWL1 and a RWL2 respectively, and the source terminals of the two groups of storage units are connected to each other and connected to the non-inverting input terminal of the sense amplifier 2 through an RBL. The signal received by the input terminal is compared with the reference signal received by the inverting input terminal of the sense amplifier 2, and the positive and negative phase output potential signals of the sense amplifier 2 are the current logic output operation result.

[0071] The first group of logic input signals (Din1, Din1') of the DRAM-based in-memory logic computing unit represent the storage node voltages of the first storage unit 11 and the second storage unit 12, and a high voltage represents a logic "1" and a low voltage represents a logic "0"; in other embodiments, a high voltage can represent a logic "0" and a low voltage can represent a logic "1", which is related to the transmission characteristics of the MOS transistor. The second group of logic input signals (Din2, Din2') represent the signals input through the read word line RWL1 at the drain terminal of the first storage unit 11 and the signals input through the read word line RWL2 at the drain terminal of the second storage unit 12 respectively, and a logic "1" is represented by a read enable signal and a logic "0" is represented by a standby signal.

[0072] Embodiment 2

[0073] The embodiment of the present application provides a logic operation method based on the in-memory logic operation circuit in embodiment 1, which involves four kinds of logic operations and their corresponding embodiments, namely one "NOT" operation, one "AND / NAND" operation, one "OR / NOR" operation and one "XOR / XNOR" operation. Referring to Figure 2 , in combination with Figures 3-5 , the DRAM-based in-memory logic computing unit in the present embodiment is described.

[0074] By configuring the logic input signals, the in-memory logic operation circuit in the embodiment of the present application can realize normal reading and at the same time realize "NOT" operation, as shown in the following table: Figure 3 Specifically, as shown in the following table:

[0075] The first logic input signal Din1(A) is stored to the storage node of the first storage unit 11, and when N=1, the storage node is the node connected between the drain of the first MOS tube 111 as the write-in tube and the gate of the second MOS tube 112 as the read-out tube in the first storage unit 11; the inverted signal of the first logic input signal Din1(A) is stored to the storage node of the second storage unit 12, and when N=1, the storage node is the node connected between the drain of the first MOS tube 121 as the write-in tube and the gate of the second MOS tube 122 as the read-out tube in the second storage unit 12. The signal values of the first logic input signal Din1(A) and the first logic input signal Din1(A) correspond to the conductive levels of the respective read-out tubes, and in the embodiment of the present application, the signal value 0 corresponds to the off level of the read-out tube, and the signal value 1 corresponds to the conductive level of the read-out tube.

[0076] The read word line signal connected to the first storage unit is taken as the first storage unit read control signal, and the read word line signal connected to the second storage unit is taken as the second storage unit read control signal, when the first storage unit read control signal is read enable and the second storage unit read control signal is standby, the non-inverted output signal of the sense amplifier is the first storage unit read-out signal, and the inverted output signal of the sense amplifier is the "NOT" operation result of the first storage unit. When the first storage unit read control signal is standby and the second storage unit read control signal is read enable, the non-inverted output signal of the sense amplifier is the second storage unit read-out signal, and the inverted output signal of the sense amplifier is the "NOT" operation result of the second storage unit. Wherein, read enable means the signal value is 1, and standby means the signal value is 0.

[0077] As shown in the following table: Figure 3 As an example, the read word line signal connected to the first storage unit is taken as the second logic input signal Din2(1), and the read word line signal connected to the second storage unit is taken as the second logic input signal Din2'(0), the second logic input signal Din2(1) with the signal value 1 is input to the drain terminal of the first storage unit 11 through the read word line RWL1; and the second logic input signal Din2'(0) with the signal value 0 is input to the drain terminal of the second storage unit 12 through the read word line RWL2. Wherein, the signal value 1 corresponds to the read enable level of the RWL, thereby generating the read-out current corresponding to the storage node level; and the signal value 0 corresponds to the standby level of the RWL.

[0078] ​​The source terminals of the first storage unit 11 and the second storage unit 12 are connected to the non-inverting input terminal of the sensitive amplifier 2 through the RBL, and a reference signal is connected to the inverting input terminal of the sensitive amplifier 2, and the reference signal is configured as a voltage or current signal capable of distinguishing 1 and 0 results. The sensitive amplifier 2 compares the electrical signals at the non-inverting input terminal and the inverting input terminal, and generates the logic output potential signals of the conventional reading result and the "not" operation result which are mutually inverted, Dout(A) and

[0079] The DRAM-based in-memory logic operation circuit provided by the present application can be used to implement the logic "and / not and" operation. As shown in the specific method is as follows: Figure 4

[0080] The first logic input signal Din1(A) is stored to the storage node of the first storage unit 11, and when N=1, the storage node is the node connected between the drain of the first MOS tube 111 as the writing tube and the gate of the second MOS tube 112 as the reading tube in the first storage unit 11; the inverted signal of the first logic input signal Din1(A) is stored to the storage node of the second storage unit 12, and when N=1, the storage node is the node connected between the drain of the first MOS tube 121 as the writing tube and the gate of the second MOS tube 122 as the reading tube in the first storage unit 12. Among them, the signal value corresponds to the conduction level of the reading tube; in the embodiment of the present application, the signal value of 0 corresponds to the off level of the reading tube. The reading word line signal connected to the first storage unit is the second logic input signal Din2(B), that is, the second logic input signal Din2(B) is input to the drain terminal of the first storage unit 11 through the RWL1; the reading word line signal connected to the second storage unit is the standby signal representing logic "0", that is, the second logic input signal Din2'(0) with a signal value of 0 is input to the drain terminal of the second storage unit 12 through the RWL2. Among them, the signal value of 1 corresponds to the reading enable level of the RWL, thereby generating the reading current corresponding to the level of the storage node; the signal value of 0 corresponds to the standby level of the RWL.

[0081] The source terminals of the first storage unit 11 and the second storage unit 12 are connected to the non-inverting input terminal of the sensitive amplifier 2 through the RBL, and a reference signal is connected to the inverting input terminal of the sensitive amplifier 2, and the reference signal is configured as a voltage or current signal capable of distinguishing 1 and 0 results. The sensitive amplifier 2 compares the electrical signals at the non-inverting input terminal and the inverting input terminal, and generates the logic output potential signals of the conventional reading result and the "not" operation result which are mutually inverted, Dout(A) and

[0082]

[0083] ​​The embodiment of the present application provides a DRAM-based in-memory logic operation circuit which can be used for implementing logic OR / NOT operation. Figure 5 As shown in the figure, the specific method is as follows:

[0084] The first logic input signal Din1(A) is stored to the storage node of the first storage unit 11, and when N=1, the storage node is the node connected between the drain of the first MOS tube 111 as a writing tube and the gate of the second MOS tube 112 as a reading tube in the first storage unit 11; the inverse signal of the first logic input signal Din1(A) is stored to the storage node of the second storage unit 12, and when N=1, the storage node is the node connected between the drain of the first MOS tube 121 as a writing tube and the gate of the second MOS tube 122 as a reading tube in the first storage unit 12. The first logic input signal Din1(A) is stored to the storage node of the first storage unit 11, and when N=1, the storage node is the node connected between the drain of the first MOS tube 111 as a writing tube and the gate of the second MOS tube 112 as a reading tube in the first storage unit 11; the inverse signal of the first logic input signal Din1(A) is stored to the storage node of the second storage unit 12, and when N=1, the storage node is the node connected between the drain of the first MOS tube 121 as a writing tube and the gate of the second MOS tube 122 as a reading tube in the first storage unit 12.

[0085] The read word line signal connected to the first storage unit is a read enable signal representing logic 1, that is, the second logic input signal Din2(1) with a signal value of 1 is input to the drain terminal of the first storage unit 11 through RWL1; the read word line signal connected to the second storage unit is the second logic input signal Din2'(B), that is, the second logic input signal Din2'(B) is input to the drain terminal of the second storage unit 12 through RWL2. Wherein, the signal value of 1 corresponds to the RWL level as a read enable level, thereby generating a reading current corresponding to the level of the storage node; in the embodiment of the present application, the signal value of 0 corresponds to the standby level of the RWL level.

[0086] The source terminals of the first storage unit 11 and the second storage unit 12 are commonly connected to the non-inverting input terminal of the sensitive amplifier 2 through RBL, and the reference signal is connected to the inverting input terminal of the sensitive amplifier 2, and the reference signal is configured as a voltage or current signal which can distinguish 1 and 0 results. The sensitive amplifier 2 compares the electrical signals of the non-inverting input terminal and the inverting input terminal, and generates logic output potential signals of OR and NOR which are inverse to each other, Dout(A+B) and

[0087] The present application provides a DRAM-based in-memory logic operation circuit which can be used for implementing logic XOR / XOR operation. As shown in the figure, the specific method is as follows: Figure 6 As shown in the figure, the specific method is as follows:

[0088] The first logic input signal Din1(A) is stored to the storage node of the first storage unit 11, and when N=1, the storage node is the node connected between the drain of the first MOS tube 111 as a writing tube and the gate of the second MOS tube 112 as a reading tube in the first storage unit 11; the inverse signal of the first logic input signal Din1(A) is stored to the storage node of the second storage unit 12, and when N=1, the storage node is the node connected between the drain of the first MOS tube 121 as a writing tube and the gate of the second MOS tube 122 as a reading tube in the first storage unit 12. When N=1, the storage node in the second storage cell 12 is the node in the first storage cell 12 where the drain of the first MOS transistor 121 (actually a write transistor) and the gate of the second MOS transistor 122 (actually a read transistor) are connected. The signal value corresponds to the read transistor's on-state level; in this embodiment, a signal value of 0 corresponds to the read transistor's off-state level.

[0089] The read word line signal connected to the first memory cell is the second logic input signal Din2(B), which is input to the drain terminal of the first memory cell 11 through RWL1; the read word line signal connected to the second memory cell is the inverted signal of the second logic input signal Din2(B). The inverted signal of the second logic input signal Din2(B) The RWL2 input is used to the drain terminal of the second storage cell 12. A signal value of 1 corresponds to a read enable level in the RWL, thereby generating a read current corresponding to the storage node level; a signal value of 0 corresponds to a standby level in the RWL.

[0090] The source terminals of the first storage cell 11 and the second storage cell 12 are connected to the non-inverting input of the sensitive amplifier 2 via RBL. A reference signal is connected to the inverting input of the sensitive amplifier 2, configured as a voltage or current signal capable of distinguishing between 1 and 0 results. The sensitive amplifier 2 compares the electrical signals at the non-inverting and inverting inputs, generating logic output potential signals Dout(A⊙B) that are inversely related to each other ("XNOR" and "XOR").

[0091] Example 3

[0092] like Figure 7 As shown, this embodiment of the invention provides a DRAM-based in-memory computing system, including at least one in-memory logic computing unit 1 in the in-memory logic operation circuit of the above embodiment 1. Figure 7 The DRAM CIM cell includes at least one sensitive amplifier 2 (SA) in the in-memory logic operation circuit of the above embodiment 1, a write word line decoder and driver circuit 4, a write bit line decoder and driver circuit 5, a read word line decoder and driver circuit 6, a logic configuration circuit 3, and a control circuit 7.

[0093] The connection between the in-memory logic computing units 1 forms an array structure. Two memory cells (first and second memory cells) of the same in-memory logic computing unit 1 are located in the same column. The in-memory logic computing units in each column share a read bit line and share the same sense amplifier, so that each in-memory logic computing unit 1 in the same column and the sense amplifier 2 in the column can form the in-memory logic operation circuit in the above-mentioned embodiment 1. The in-memory logic computing units in each column share the same write bit line. The first memory cell and the second memory cell in each row of in-memory logic computing units 1 use a read word line corresponding to each of them, respectively. The two read word lines are respectively referred to as RWL1 and RWL2. The first memory cell and the second memory cell in each row of in-memory logic computing units 1 use a write word line corresponding to each of them, respectively. The two write word lines are respectively referred to as WWL1 and WWL2. The in-memory logic computing units in the same row that share the same RWL1 and RWL2 can perform parallel logic operations.

[0094] The write word line decoding and driving circuit is used for converting the external address signal into each write word line signal of the array under the control of the control circuit.

[0095] The write bit line decoding and driving circuit is used for converting the external data signal into each write bit line signal of the array under the control of the control circuit.

[0096] The read word line decoding and driving circuit is used for converting the external address signal into each read word line signal of the array under the control of the control circuit.

[0097] The logic configuration circuit is used for switching the normal reading and logic computing tasks of the in-memory logic operation circuit under the control of the control circuit. Specifically, by configuring the logic input signals of the in-memory logic operation circuit, any one or more of the normal access and the logic operations of NOT, AND / NOT, OR / NOT, and XNOR can be realized.

[0098] The control circuit is used for controlling each circuit part of the in-memory computing system.

[0099] Referring to Figure 2 , the in-memory computing system shows an in-memory logic operation circuit based on two groups of two-transistor DRAMs and sense amplifiers. It can be understood that the in-memory computing system in the embodiment can also include other forms of in-memory logic operation circuits, such as two groups of three-transistor DRAMs and sense amplifiers.

[0100] As shown in Figure 8 , as a preferred implementation, the logic configuration circuit configures the logic input signals of the in-memory logic operation circuit, including:

[0101] For the first set of logic input signals, the charge level stored in the memory cell is configured during writing via the corresponding write bit lines connected to the in-memory logic operation units (first memory cell and second memory cell). Specifically: the first logic input signal Din1(A) is stored in the memory node of the first memory cell 11, and the first logic input signal... ( The inverted signal of Din1(A) is stored in the storage node of the second storage unit 12.

[0102] For the second set of logic input signals, the read bit lines connected to the first and second storage cells are configured during readout. Specifically:

[0103] Access and NOT operations: Identified by the symbol m1, DRAM cells (first storage cell 11 or second storage cell 12) directly form an array to perform regular access operations or NOT operations. Control circuit 7 controls logic configuration circuit 3 to select signals with a value of logic 1 and a value of logic 0 to RWL1 and RWL2 respectively, and directly applies the single-column strobe read enable signal generated by address decoding required for regular read operations to the drain terminal of the read transistor, which is used to enable data readout in regular access operations.

[0104] The XOR operation is identified by the symbol m2. Each pair of DRAM cells (first memory cell 11 and second memory cell 12) forms a group, which, together with the sensitive amplifier 2, constitutes the in-memory logic operation circuit. The two DRAM memory cells are respectively based on the first memory cell 11 and the second memory cell 12 in the in-memory logic operation circuit. The control circuit 7 controls the logic configuration circuit 3 to select the second logic input signal Din2(B) to RWL1, and selects the inverted signal of the second logic input signal. RWL1 and RWL2 apply input signals to the two DRAM cells through the drain terminals of the read transistors.

[0105] AND operation: Identified by the symbol m3, each pair of DRAM cells (first memory cell 11 and second memory cell 12) forms a group, which, together with the sensitive amplifier 2, constitutes the in-memory logic operation circuit. The two DRAM memory cells are based on the first memory cell 11 and the second memory cell 12 in the in-memory logic operation circuit, respectively. The control circuit 7 controls the logic configuration circuit 3 to select the second logic input signal Din2(B) to RWL1 and select a signal with a logic value of 0 to RWL2. RWL1 and RWL2 apply input signals to the two DRAM cells through the drain terminals of the read transistors.

[0106] OR operation: Identified by the symbol m4, each pair of DRAM cells (first memory cell 11 and second memory cell 12) forms a group, which together with the sensitive amplifier 2 constitutes the in-memory logic operation circuit. The two DRAM memory cells are based on the first memory cell 11 and the second memory cell 12 in the in-memory logic operation circuit, respectively. The control circuit 7 controls the logic configuration circuit 3 to send a signal with a logic value of 1 to RWL1 and to send the second logic input signal Din2′(B) to RWL2. RWL1 and RWL2 apply input signals to the two DRAM cells through the drain terminals of the read transistors.

[0107] Example 4

[0108] This invention provides an in-memory computing hardware accelerator, on which the DRAM-based in-memory computing system described in Embodiment 3 is deployed, enabling various algorithm calculations, such as neural networks.

[0109] Specifically, by decomposing the multiplication and accumulation calculation into a step-by-step logical calculation, the multiplication and accumulation calculation of input data and weight data in the neural network is realized. During each calculation, the weight data in the DRAM storage array is not destroyed and can be reused in multiple calculations.

[0110] like Figure 9 As shown, taking the multiplication and addition operation w1·in1+w2·in1 between the input vector and weight vector in a neural network convolution calculation application as an example, this illustrates that the DRAM-based in-memory computing system provided in this embodiment of the invention can achieve non-destructive parallel weight computation based on DRAM. The specific steps are as follows: The multiplication and addition operation is deployed in separate steps. First, the AND operation of w1·in1 and w2·in1 is completed in the first and second in-memory computing circuits. Then, the addition of the AND operation result is completed. Finally, the sum operation is completed in the third in-memory computing circuit. The "carry" result calculation C = (w1·in1)·(w2·in1) is completed in the fourth memory calculation circuit.

[0111] In the first and second in-memory logic operation circuits, the positive and negative phase weights are combined and represented as potential signals stored in the DRAM cells. The controller controls the positive and negative phase values ​​of different weights in the neural network to be written into the corresponding DRAM cells via WBL, such as... Figure 9 middle As shown; the positive and negative phase inputs are represented as the potential signals of the array RWL. The controller controls the positive input and logic 0 to pass through the RWL input array, as follows. Figure 9 As shown in (in1,0); they share the same RWL group, that is, they share the same group (in iThe in-memory logic operation circuit of the (w2·in1, 0) data can perform "and / nand" operation in parallel, and generate logic operation output potential signals in parallel through different RBLs connected to different sense amplifiers, as shown in Figure 9 w1·in1 and w2·in1. It can be seen that in the calculation process, the weights stored in the DRAM unit will not be destroyed, and can be repeatedly calculated with different groups (in i , in i ′ ) data.

[0112] In the third in-memory logic operation circuit, the positive and negative phase "and" operation results w1·in1 are represented as potential signals stored in the DRAM unit, and the controller controls the positive and negative phase "and" operation results to be written into the corresponding DRAM unit through WBL, as shown in Figure 9 ; the positive and negative phase "and" operation results are represented as potential signals of the array RWL, and input into the array through RWL, as shown in Figure 9 ; and the "XOR / nand" logic operation output potential signals are generated through RBL connected to the sense amplifier, as shown in Figure 9 .

[0113] In the fourth in-memory logic operation circuit, the positive and negative phase "and" operation results w1·in1 are represented as potential signals stored in the DRAM unit, and the controller controls the positive and negative phase "and" operation results to be written into the corresponding DRAM unit through WBL, as shown in Figure 9 ; the positive phase "and" operation results and logic 0, i.e. (w2·in1, 0), are represented as potential signals of the array RWL, and input into the array through RWL, as shown in Figure 9 ; and the "and / nand" logic operation output potential signals are generated through RBL connected to the sense amplifier, as shown in Figure 9 C=(w1·in1)·(w2·in1) in

[0114] ​​​In summary, the in-memory logic operation circuit provided by the application comprises two DRAM units and a sense amplifier for generating a logic operation result.

[0115] The DRAM-based logic operation circuit provided by the application has a logic operation function, can realize "not" "and / nand", "or / nor" and "XOR" logic calculation, and can form a complex logic operation system on this basis.

[0116] The in-memory computing system of the application fully utilizes the parallel readout characteristics of the array to realize parallel calculation of the logic operation.

[0117] Unlike the existing input value represented by the pulse width or amplitude of the voltage pulse, the logic operation input provided by the application is pure digital logic, can complete fixed-point number bit-by-bit multiplication, bit-by-bit search and other operations without precision loss, and has higher precision compared with complex operations.

[0118] Those skilled in the art will readily understand that the above description is only a preferred embodiment of the application and is not intended to limit the application, and any modifications, equivalent replacements and improvements made within the spirit and principles of the application shall be included in the protection scope of the application.

Claims

1. A DRAM-based in-memory logic operation circuit, comprising: Comprise: DRAM-based in-memory logic computing unit and a sense amplifier; wherein the in-memory logic computing unit comprises a first storage unit and a second storage unit; Both the first storage unit and the second storage unit comprise a write transistor TW and N connected read transistors TR, N≥1; the gate of the write transistor TW is connected to a write word line, the source is connected to a write bit line, and the drain is connected to the first end of the N connected read transistors TR, and the node connected is a storage node; the second end of the N connected read transistors TR is connected to a read word line, and the third end is connected to a read bit line; The read bit lines of the first storage unit and the second storage unit are connected together and connected to the positive input terminal of the sense amplifier; the signal received by the positive input terminal is compared with the reference signal received by the inverting input terminal of the sense amplifier to generate a logic operation result; Wherein, the first group of logic input signals (Din1, Din1') of the in-memory logic operation circuit correspond to the storage node voltages of the first storage unit and the second storage unit, and the storage node voltages represent logic "1" when the read transistor TR is turned on and represent logic "0" when the read transistor TR is turned off; the second group of logic input signals (Din2, Din2') correspond to the read word line signals connected to the first storage unit and the second storage unit, and the read word line signals represent logic "1" when enabled and represent logic "0" when standby.

2. The in-memory logic operation circuit of claim 1, wherein, When N=1, the first end of the read transistor TR is the gate, the second end is the drain, and the third end is the source; When N=2, the connection mode of the two read transistors TR is: the drain of one read transistor is connected to ground, the gate is connected to the drain of the write transistor TW, and the source is connected to the drain of the other read transistor; the gate of the other read transistor is connected to the read word line, and the source is connected to the read bit line.

3. A logic operation method based on the in-memory logic operation circuit according to claim 1 or 2, characterized by, It includes read operation and logic "not" operation, specifically: store the first logic input signal Din1(A) to the storage node of the first storage unit, and input the inverse signal Din1'(A) of Din1(A) to the storage node of the second storage unit; The read word line signal connected to the first storage unit is used as the first storage unit read control signal, and the read word line signal connected to the second storage unit is used as the second storage unit read control signal; When the first memory cell read control signal is read enable and the second memory cell read control signal is standby, the non-inverting output signal of the sense amplifier is the first memory cell readout signal Dout(A) and the inverting output signal is the "not" operation result of the first memory cell When the first storage unit read control signal is standby and the second storage unit read control signal is read enable, the non-inverting output signal of the sensitive amplifier is the second storage unit read signal The inverting output signal is the "non" operation result of the second storage unit 4. The logic operation method according to claim 3, wherein It also includes logic "and / not and" operation, specifically: The first logic input signal Dinl(A) is stored to the storage node of the first storage element, and the inverted signal of Dinl(A) is input to the storage node of the second storage element. The first logic input signal Dinl(A) is stored to the storage node of the first storage element, and the inverted signal of Dinl(A) is input to the storage node of the second storage element. The read word line signal connected to the first storage unit is the second logic input signal Din2(B), and the read word line signal connected to the second storage unit is the standby signal representing logic "0"; The sensitive amplifier outputs the logic output potential signal Dout(A·B) and 5. The logic operation method according to claim 3 or 4, wherein It also includes logic "or / not or" operation, specifically: The first logic input signal Dinl(A) is stored to the storage node of the first storage element, and the inverted signal of Dinl(A) is input to the storage node of the second storage element. The first logic input signal Dinl(A) is stored to the storage node of the first storage element, and the inverted signal of Dinl(A) is input to the storage node of the second storage element. The read word line signal connected to the first storage unit is the read enable signal representing logic "1", and the read word line signal connected to the second storage unit is the second logic input signal Din2'(B); The "or" and "nand" logic output potential signals Dout(A+B) and 6. The logic operation method according to claim 5, wherein It also includes logic "XOR" operation, specifically: The first logic input signal Dinl(A) is stored to the storage node of the first storage element, and the inverted signal of Dinl(A) is input to the storage node of the second storage element. The first logic input signal Dinl(A) is stored to the storage node of the first storage element, and the inverted signal of Dinl(A) is input to the storage node of the second storage element. The read word line signal connected to the first storage unit is the second logic input signal Din2(B), and the read word line signal connected to the second storage unit is the inverse signal of Din2(B) then the sensitive amplifier outputs the logic output potential signals Dout(A^B) and Dout(A V B) which are opposite phase to each other 7. A DRAM-based in-memory computing system, comprising: Comprise: At least one in-memory logic computing unit, at least one sense amplifier, write word line decoding and driving circuit, write bit line decoding and driving circuit, read word line decoding and driving circuit, logic configuration circuit, and control circuit; wherein the in-memory logic computing unit and the sense amplifier correspond to the in-memory logic computing unit and the sense amplifier of claim 1 or 2; The connections between the in-memory logic computing units form an array structure, the first memory cell and the second memory cell in the same in-memory logic computing unit are located in the same column, and the in-memory logic computing units in each column share the same read bit line and the same sense amplifier, so that each in-memory logic computing unit in the same column and the sense amplifier in the column can form the in-memory logic operation circuit of claim 1 or 2, and the in-memory logic computing units in each column share the same write bit line; The first memory cell and the second memory cell in each row of in-memory logic computing units use their respective read word lines RWL1 and RWL2 and their respective write word lines, and the in-memory logic operation units in the same row that share the same RWL1 and RWL2 perform parallel logic operations; The write word line decoding and driving circuit is used for converting external address signals into each write word line signal of the array under the control of the control circuit; The write bit line decoding and driving circuit is used for converting external data signals into each write bit line signal of the array under the control of the control circuit; The read word line decoding and driving circuit is used for converting external address signals into each read word line signal of the array under the control of the control circuit; The logic configuration circuit is used for switching the configured logic input signals under the control of the control circuit, so that the in-memory logic operation circuit implements logic operations.

8. The DRAM-based processing-in-memory system of claim 7, wherein, The logic input signal configuration of the in-memory logic operation circuit includes configuration of the first group of logic input signals (Din1, Din1') and configuration of the second group of logic input signals (Din2, Din2'), to implement any one or more of reading and logic "not" operation, logic "and / not" operation, logic "or / not" operation, and logic "XOR / XOR" operation; wherein the first set of logic input signals (Din1, Din1') are configured to store the first logic input signal Din1(A) to the storage node of the first storage cell and the inverted signal of Din1(A) is input to the storage node of the second storage cell; The second group of logic input signals (Din2, Din2') are configured by the read word lines RWL1 and RWL2 connected to the first and second storage units, and when the read and logic "not" operation is implemented, the second group of logic input signals (Din2, Din2') are configured as logic "1" and logic "0"; when the logic "and / not" operation is implemented, the second group of logic input signals (Din2, Din2') are configured as Din2(B) and logic "0"; when the logic "or / not" operation is implemented, the second group of logic input signals (Din2, Din2') are configured as logic "1" and Din2'(B); and when the logic "XOR" operation is implemented, the second group of logic input signals (Din2, Din2') are configured as Din2(B) and the inverted signal of Din2(B) 9. An in-memory computing hardware accelerator, comprising: The in-memory computing hardware accelerator is deployed with the DRAM-based in-memory computing system of claim 7 or 8.

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