Redundancy-based hardware failure time division multiplexing detection circuit and detection method

Abstract

The invention discloses a redundancy-based hardware failure time division multiplexing detection circuit and method, and the method comprises the steps: enabling the counting of an input selection counter to be connected with a first input completion mark outputted by an upstream circuit, and enabling the counting of an output selection counter to be connected with a second input completion mark outputted by a downstream circuit; the output end of the input selection counter is connected with the enabling end of the input selector muxin, and the output end of the output selection counter is connected with the enabling end of the output selector muxout; the input end of the input selector muxin is connected with the output of the upstream circuit, the output end of the input selector muxin is connected with the input end of the redundant circuit, the input end of the output selector muxout is connected with the output of the hardware circuit, and the output end of the output selector muxout is connected with one input end of the comparator; the input end of the redundant circuit is connected with the output end of the input selector muxin, the output end of the redundant circuit is connected with the other input end of the comparator, and the output end of the comparator is connected with the control register.

Description

Technical Field

[0001] The invention belongs to the technical field of time division multiplexing detection, and in particular relates to a redundant hardware failure time division multiplexing detection circuit and detection method. Background Art

[0002] In the process of system-on-chip communication, system reliability is an important indicator of communication. Redundancy technology is one of the most effective means to improve system reliability, which exchanges system reliability at the expense of hardware resources. When part of the logic of the device causes hardware circuit failure, such as a transient fault during the operation of the device, the use of redundancy technology in the relevant logic can automatically detect and report the error, so that the device can continue to work within an acceptable range.

[0003] At present, the commonly used redundancy technology inspection methods are divided into software redundancy method and hardware redundancy method. The software redundancy method stores the software running results and compares the software and hardware output results at the end of each simulation to determine whether there is a hardware failure during this simulation. The hardware redundancy method adds redundant circuits to the hardware circuits so that the redundant circuits and the functional circuits perform the same operations. At the end of each simulation, the output results of the redundant circuits and the functional circuits are compared to determine whether there is a hardware failure during this simulation.

[0004] Considering that the software redundancy method requires software adaptation during hardware simulation, it is impossible to achieve full coverage in hardware simulation, which may lead to missed faults. For the hardware redundancy method, increasing the coverage of redundant logic will directly affect the error detection capability. Too much redundant logic may cause the entire system to be too large and power consumption to be too high. Too little redundant logic may cause some hardware failures to be undetectable. Summary of the invention

[0005] The purpose of the present invention is to overcome the problem that the larger the circuit area to be detected, the more redundant logic there is, resulting in the system area and power consumption failing to meet the requirements, and propose a redundant hardware failure time-division multiplexing detection circuit and detection method.

[0006] In order to achieve the above object, the present invention adopts the following technical scheme: A redundant hardware failure time-division multiplexing detection circuit includes a counter, a selector, a redundant circuit and a comparator; the counter includes an input selection counter and an output selection counter, and the selector includes an input selector mux_in and an output selector mux_out; The count enable of the input selection counter is connected to the first input completion flag output by the upstream circuit, the count enable of the output selection counter is connected to the second input completion flag output by the downstream circuit, the output end of the input selection counter is connected to the enable end of the input selector mux_in, and the output end of the output selection counter is connected to the enable end of the output selector mux_out; The input end of the input selector mux_in is connected to the output of the upstream circuit, the output end of the input selector mux_in is connected to the input end of the redundant circuit, the input end of the output selector mux_out is connected to the output of the hardware circuit, and the output end of the output selector mux_out is connected to one input end of the comparator; The input end of the redundant circuit is connected to the output end of the input selector mux_in, the output end of the redundant circuit is connected to the other input end of the comparator, and the output end of the comparator is connected to the control register.

[0007] Furthermore, the enable end of the redundant circuit is connected to the clock gating, the input end of the clock gating is connected to the input clock and the redundant enable, the output end of the clock gating is connected to the clock input end of the redundant circuit, and the clock gating is used to provide a clock for the redundant circuit.

[0008] Furthermore, the count value of the input selection counter is incremented after the input data transmission from the upstream circuit to the hardware circuit is completed; the count value of the output selection counter is incremented after the output data transmission from the hardware circuit to the downstream circuit is completed.

[0009] Furthermore, the enable terminal of the input selector mux_in is connected to the count value of the input selection counter 1 , and the enable terminal of the output selector mux_out is connected to the count value of the output selection counter 2 .

[0010] Furthermore, the input selector mux_in selects the input data of the hardware circuit having the same number as the count value of the input selection counter and inputs it into the redundant circuit, and the calculation result of the redundant circuit is input into one input terminal of the comparator; The output selector mux_out selects the output data of the hardware circuit having the same count value as the output selection counter as the calculation result of the hardware circuit, and the calculation result of the hardware circuit is input into the other input terminal of the comparator.

[0011] Furthermore, eight hardware circuits are provided, and the eight hardware circuits are hardware circuits numbered 0 to 7 obtained by instantiating the same hardware circuit. The counter adopts a three-bit counter, corresponding to eight counting values ​​from 0 to 7. The value of the counter is polled from 0 to 7 once, and after self-incrementing to 7, the value of the counter jumps to 0, and a new round of self-incrementing operation begins.

[0012] Furthermore, the output terminal of the comparator outputs a comparison result between the calculation result of the redundant circuit and the calculation result of the hardware circuit.

[0013] Furthermore, the calculation results of the redundant circuit are compared with the calculation results of the hardware circuit in the following specific manner: in one round of hardware failure detection, the calculation results of the redundant circuit and the calculation results of the hardware circuit are continuously input into the comparator at the same time, and the comparator compares the calculation results of the redundant circuit with the calculation results of the hardware circuit bit by bit. During one comparison process, the serial number of the hardware circuit matched by the redundant circuit is constant. After eight comparisons, one round of hardware failure detection for hardware circuit 0 to hardware circuit 7 is completed.

[0014] A redundant hardware failure time-division multiplexing detection method is provided. The redundant hardware failure time-division multiplexing detection circuit is used. The calculation of the hardware circuit and the calculation of the redundant circuit are independent and equivalent to each other. The comparator starts a bitwise AND operation after receiving the calculation result of the redundant circuit and the calculation result of the hardware circuit each time.

[0015] Further, the output terminal of the comparator outputs a calculation error signal; When there is no hardware failure, the results of the bitwise AND operation are all 1, and the calculation error signal output by the comparator is low level; When there is a hardware failure, the result of the bitwise AND operation is not all 1, the calculation error signal output by the comparator is high, the comparator circuit issues a fault alarm message, the fault alarm message is output to the control register, and the control register issues a control command to discard the calculation result of the hardware circuit and perform the next round of comparison until the calculation error signal output by the comparator is low.

[0016] Compared with the prior art, the present invention has the following beneficial technical effects: The present invention proposes a redundant hardware failure time-division multiplexing detection circuit, comprising a counter, a selector, a redundant circuit and a comparator; the counter comprises an input selection counter and an output selection counter, and the selector comprises an input selector mux_in and an output selector mux_out; by detecting the hardware failure of the circuit to be tested at a relatively small redundant circuit area cost, as a safety mechanism for the hardware circuit to be tested, the problem that the larger the area of ​​the circuit to be tested, the more redundant logics there are, resulting in the system area and power consumption failing to meet the requirements is solved; if the hardware circuit is 0-7, the redundant circuit area only accounts for 12.8% of the total area of ​​the hardware circuit.

[0017] Furthermore, the present invention proposes a redundant hardware failure time-division multiplexing detection circuit, in which the enable end of the redundant circuit is connected to the clock gating, the input end of the clock gating is connected to the input clock and the redundant enable, and the output end of the clock gating is connected to the clock input end of the redundant circuit. The clock gating is used to provide a clock for the redundant circuit, and the clock of the redundant circuit can be selectively shut down to reduce dynamic power consumption.

[0018] The present invention proposes a redundant hardware failure time-division multiplexing detection method, in which the hardware circuit and the redundant circuit perform logical operations in a mutually independent and equivalent manner, which can ensure real-time failure detection and error reporting of the hardware circuit, fault isolation and recovery after fault detection, and prevent hardware error propagation. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The drawings in the specification are used to provide further understanding of the present invention and constitute a part of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute improper limitations on the present invention.

[0020] Figure 1 The present invention is a structural block diagram of a redundant hardware failure time-division multiplexing detection circuit. DETAILED DESCRIPTION

[0021] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0022] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0023] Embodiment 1 A redundant hardware failure time-division multiplexing detection circuit includes a counter, a selector, a redundant circuit and a comparator; the counter includes an input selection counter and an output selection counter, and the selector includes an input selector mux_in and an output selector mux_out; The count enable of the input selection counter is connected to the first input completion flag output by the upstream circuit, the count enable of the output selection counter is connected to the second input completion flag output by the downstream circuit, the output end of the input selection counter is connected to the enable end of the input selector mux_in, and the output end of the output selection counter is connected to the enable end of the output selector mux_out; The input end of the input selector mux_in is connected to the output of the upstream circuit, the output end of the input selector mux_in is connected to the input end of the redundant circuit, the input end of the output selector mux_out is connected to the output of the hardware circuit, and the output end of the output selector mux_out is connected to one input end of the comparator; The input end of the redundant circuit is connected to the output end of the input selector mux_in, the output end of the redundant circuit is connected to the other input end of the comparator, and the output end of the comparator is connected to the control register.

[0024] This embodiment introduces a redundant circuit, which can automatically switch to the redundant circuit when the main circuit fails, thereby maintaining the normal operation of the system. This redundant design significantly improves the fault tolerance and reliability of the system and reduces the system downtime caused by hardware failures. By using the combination of counters (input selection counters and output selection counters) and selectors (input selector mux_in and output selector mux_out), accurate control of the input and output processes can be achieved, and the output of the main circuit and the redundant circuit can be compared at the appropriate time. The comparator can quickly identify potential faults in the main circuit and provide the system with real-time fault detection capabilities. The design structure of the detection circuit is relatively independent and easy to integrate with other hardware modules. At the same time, by increasing the number and type of redundant circuits, the fault tolerance and adaptability of the system can be further improved to meet higher requirements of application scenarios. By directly outputting the fault detection results to the control register through the comparator, the system can quickly locate and isolate the fault point. This not only simplifies the troubleshooting process, but also improves the efficiency and accuracy of fault handling.

[0025] The enable end of the redundant circuit is connected to the clock gating, the input end of the clock gating is connected to the input clock and the redundant enable, the output end of the clock gating is connected to the clock input end of the redundant circuit, and the clock gating is used to provide a clock for the redundant circuit.

[0026] The count value of the input selection counter is incremented after the input data transmission from the upstream circuit to the hardware circuit is completed; the count value of the output selection counter is incremented after the output data transmission from the hardware circuit to the downstream circuit is completed.

[0027] The enable terminal of the input selector mux_in is connected to the count value of the input selection counter 1, and the enable terminal of the output selector mux_out is connected to the count value of the output selection counter 2.

[0028] The input selector mux_in selects the input data of the hardware circuit with the same number as the count value of the input selection counter and inputs it into the redundant circuit, and the calculation result of the redundant circuit is input into one input terminal of the comparator; The output selector mux_out selects the output data of the hardware circuit having the same count value as the output selection counter as the calculation result of the hardware circuit, and the calculation result of the hardware circuit is input into the other input terminal of the comparator.

[0029] Eight hardware circuits are set, and the eight hardware circuits are hardware circuits numbered 0 to 7 obtained by instantiating the same hardware circuit. The counter uses a three-bit counter, corresponding to eight counting values ​​from 0 to 7. The value of the counter is polled from 0 to 7 once, and after self-incrementing to 7, the value of the counter jumps to 0, and a new round of self-incrementing operation begins.

[0030] A three-bit counter, or 3-bit counter, is a type of counter used to count pulses or events, with a counting range from 0 (3'd0 or 3'b000) to 7 (3'd7 or 3'b111). A 3-bit counter is a sequential circuit in a digital circuit, consisting of a register and an adder (or flip-flop). Due to the 3-bit binary representation, its counting range is from 0 (3'd0 or 3'b000) to 7 (3'd7 or 3'b111), with a total of 8 states. Whenever a pulse signal is received, the state inside the counter increases by 1, starting from 0 (3'd0 or 3'b000), increasing to 7 (3'd7 or 3'b111) in sequence, and then looping back to 0 (3'd0 or 3'b000). The operation of the counter is controlled by the clock signal, and the counting operation is usually performed on the rising or falling edge of the clock signal. Most counters also have a reset function, allowing the state of the counter to be reset to the initial value (usually 0).

[0031] The output end of the comparator outputs a comparison result between the calculation result of the redundant circuit and the calculation result of the hardware circuit.

[0032] The specific method for comparing the calculation results of the redundant circuit with the calculation results of the hardware circuit is: in one round of hardware failure detection, the calculation results of the redundant circuit and the calculation results of the hardware circuit are continuously input into the comparator at the same time, and the comparator compares the calculation results of the redundant circuit with the calculation results of the hardware circuit bit by bit. During one comparison process, the serial number of the hardware circuit matched by the redundant circuit is constant. After eight comparisons, one round of hardware failure detection for hardware circuit 0 to hardware circuit 7 is completed.

[0033] Embodiment 2 A redundant hardware failure time-division multiplexing detection method uses a redundant hardware failure time-division multiplexing detection circuit described in Example 1. The calculation of the hardware circuit and the calculation of the redundant circuit are independent and equivalent to each other. The comparator starts a bitwise AND operation after receiving the calculation result of the redundant circuit and the calculation result of the hardware circuit each time.

[0034] The output terminal of the comparator outputs a calculation error signal; When there is no hardware failure, the results of the bitwise AND operation are all 1, and the calculation error signal output by the comparator is low level; When there is a hardware failure, the result of the bitwise AND operation is not all 1, the calculation error signal output by the comparator is high, the comparator circuit issues a fault alarm message, the fault alarm message is output to the control register, and the control register issues a control command to discard the calculation result of the hardware circuit and perform the next round of comparison until the calculation error signal output by the comparator is low.

[0035] The hardware circuit and the redundant circuit perform independent calculations at the same time. This parallel processing mechanism can significantly reduce the impact of a single point of failure on the entire system. When the hardware circuit fails, the redundant circuit can continue to work normally, thereby ensuring the continuity and accuracy of the system calculation. By comparing the calculation results of the hardware circuit and the redundant circuit after each calculation cycle, this method can detect and identify hardware failures in real time. The bitwise AND operation of the comparator can quickly locate the difference. Once an inconsistency is detected, an error signal is immediately output, thereby achieving instant fault detection. When a hardware failure is detected, the system can automatically discard the calculation results of the erroneous hardware circuit and immediately enable the next round of comparison. This mechanism ensures that the system can automatically recover from hardware failures and continue to perform correct calculation tasks without human intervention.

[0036] Embodiment 3 like Figure 1As shown, a redundant hardware failure time-division multiplexing detection circuit provided in this embodiment includes two 3-bit counters, two selectors, one redundant circuit (logical copy of the hardware circuit), one clock gating, and one comparator; one of the two counters is an input selection counter, and the count value is incremented after the input data transmission from the upstream circuit to the hardware circuit is completed during each simulation process, and the other counter is an output selection counter, and the count value is incremented after the output data transmission from the hardware circuit to the downstream circuit is completed during each simulation process; one of the two selectors mux_in is the input selection control of the redundant circuit, and its enable end is connected to the count value of counter 1; the other selector mux_out is the output selection control of the redundant circuit, and its enable end is connected to the count value of counter 2; one clock gating is the clock gating of the redundant circuit, which is connected to the redundant circuit enable; one comparator is a comparison circuit for the output result of the redundant circuit and the hardware circuit matched by its current simulation.

[0037] Now, the specific structure of the hardware failure detection circuit is described with two counters, two selectors, one redundant circuit, one clock gating, and one comparator: Figure 1 As shown, the present embodiment is a time-division multiplexing detection circuit for hardware failure based on redundancy, including using clock gating to provide clock for redundant circuits, and then using mux_in to select the same input source as the hardware circuit with the same ID number and count value of counter 1 for the redundant circuit, and after the upstream circuit completes the data input to the hardware circuit during each simulation, the count value of counter 1 is incremented. Mux_out is used to select the hardware circuit with the same ID number and count value of counter 2 for the redundant circuit to compare the output data, and after all the output data of each simulation is transmitted to the downstream circuit, the count value of counter 2 is incremented.

[0038] like Figure 1 As shown in the figure, when the counter is incremented, the hardware circuit ID numbers obtained by instantiating the same hardware circuit are 0~7, corresponding to Figure 1 The hardware circuits 0 to 7 in the simulation are hardware circuits 0 to 7. Therefore, the bit width of the two counters is 3 bits, corresponding to 8 count values ​​from 0 to 7, which is consistent with the number of hardware circuits. During the simulation, the counter value is polled from 0 to 7 once, and after self-incrementing to 7, the value of the counter jumps to 0 in the next simulation, and a new round of self-increment operation begins. During a simulation, the serial number of the corresponding hardware circuit matched by the redundant circuit remains constant, that is, after 8 simulations, a round of hardware failure detection of hardware circuits 0 to 7 is completed, which is the time-division multiplexing redundant circuit and hardware circuit output result comparison method.

[0039] During each simulation, the output of the redundant circuit and the output of the hardware circuit that is consistent with the count value in counter 2 are continuously input into the comparator at the same time, and a bit-by-bit comparison is performed between the redundant circuit calculation result and the hardware circuit calculation result in the comparator. The output of the comparator is the detection result of the hardware failure.

[0040] The count enable of counter 1 is connected to the input completion flag 1 output by the upstream circuit, and the output end is connected to the enable end of mux_in.

[0041] The count enable of counter 2 is connected to the input completion flag 2 output by the downstream circuit, and the output end is connected to the enable end of mux_out.

[0042] The input end of mux_in is connected to the 8 sets of outputs of the upstream circuit, and the output end is connected to the input end of the redundant circuit.

[0043] The input of mux_out is connected to the output of 8 hardware circuits, and the output is connected to the input of the comparator.

[0044] The input end of the redundant circuit is connected to the output end of mux_in, and the input end is connected to the input end of the comparator.

[0045] The input end of the clock gating is connected to the input clock and the redundancy enable, and the output end is connected to the clock input end of the redundant circuit.

[0046] One input end of the comparator is connected to the output end of the hardware circuit, the other input end is connected to the output end of the redundant circuit, and the output end is the output of the detection circuit.

[0047] The principle of a redundant hardware failure time-division multiplexing detection circuit in this embodiment is as follows: a counter, a selector, a redundant circuit, a clock gating, and a comparator are used to complete real-time detection of the correctness of the output data of the hardware circuit.

[0048] The hardware redundancy technology in the redundant hardware failure time-division multiplexing detection circuit of the present embodiment uses a parallel computing method to automatically match the redundant circuit with the corresponding hardware circuit and perform polling operations under time-division multiplexing while the actual hardware circuit is running, synchronously and equivalently simulate the operation of the hardware circuit, and complete the failure detection and error reporting of the hardware circuit in real time, thereby facilitating the timely repair and error isolation of the hardware circuit and preventing error propagation.

[0049] In the simulation stage, the control register first turns on the clock gating enable to provide a clock for the redundant circuit, so that the redundant circuit enters an idle state and waits for data input from mux_in.

[0050] In digital circuits, the clock gating enable signal is usually controlled by a control register. One or more bits of the control register are used as enable signals to control the switch state of the clock gating cell. Software or hardware logic is allowed to dynamically turn on or off the clock gating function by modifying the value of the control register, thereby controlling which parts of the circuit will receive the clock signal and which parts will be in low power or sleep state because the clock signal is blocked.

[0051] Start data transmission from the upstream circuit to hardware circuits 0~7 and mux_in, where hardware circuits 0~7 are different instances of the same hardware circuit, and their hardware circuits are consistent and synchronously perform logical operations under different input data. After receiving the data, mux_in selects a certain output of the mux_in input terminal to the redundant circuit according to the counter value in the current counter 1. Assuming that the count value in the current counter 1 is 3'd1 (3-bit binary number 3'd1 is decimal 1), it means that the first input of the mux_in input terminal is selected as the input of the redundant circuit, that is, the input of hardware circuit 1 and the redundant circuit in the current simulation is consistent. This simulation can detect whether there is hardware failure in hardware circuit 1. The operations in mux_in are all combinational logic, so it can be guaranteed that the logical operations in hardware circuit 1 and the redundant circuit in the current simulation are executed synchronously.

[0052] When the counter receives the "input completion flag 1" sent by the upstream circuit, it indicates that the data transmission from the upstream circuit to the hardware circuits 0~7 in this simulation is completed. At this time, the count value in counter 1 is incremented, that is, it jumps from 3'd1 to 3'd2 (3-bit binary number 3'd2 is decimal 2). When the upstream circuit transmits data to the hardware circuit and mux_in again, the input of hardware circuit 2 is matched with the redundant circuit, that is, the input of the redundant circuit is consistent with the input of hardware circuit 2.

[0053] Since the operation logic executed in the hardware circuit is relatively complex, the signal propagation and logic processing in the digital circuit requires a certain amount of time, which is called propagation delay or logic delay. Usually, the corresponding output result cannot be obtained immediately within the same clock beat (or the same clock cycle) of the input signal. Therefore, when the count value in counter 1 switches, hardware circuit 1 may not have completed the execution process of the logic operation. Correspondingly, the logic operation in the redundant circuit may not be completed. Therefore, during the logic operation between hardware circuits 0~7 and the redundant circuit, the value of counter 2 remains 3'd1, that is, the two input ends of the comparator are connected to the output of hardware circuit 1 and the redundant circuit respectively. When the data at any input end of the comparator changes, a bitwise AND operation of the two sets of data is performed.

[0054] When counter 2 receives the "input completion flag 2" from the downstream circuit, it indicates that hardware circuits 0~7 and the redundant circuit have completed the logic operation of all input data in this simulation, and have output the operation result corresponding to the last data output by the upstream circuit when the count value of counter 1 is 3'd1 to the comparator. At this time, the count value in counter 2 is incremented, that is, from 3'd1 to 3'd2. When the simulation data is output next time, the output of hardware circuit 2 is matched with that of the redundant circuit, that is, the output of the redundant circuit is compared with that of hardware circuit 2.

[0055] After adding the redundant circuit, there are two independent operation logics in the system: the hardware circuit 1 and the redundant circuit perform logical operations in an independent and equivalent manner. Mutually independent means that the calculation module of the hardware circuit 1 and the calculation module of the redundant circuit are independent of each other. Equivalence means that the calculation module of the hardware circuit 1 and the calculation module of the redundant circuit are equivalent. When there is no error in the circuit, the calculation module of the hardware circuit 1 and the calculation module of the redundant circuit have the same input. The comparator starts the bitwise AND operation after receiving the logical operation result of the hardware circuit and the redundant circuit.

[0056] Under normal circumstances without hardware failure, the results of the two sets of independent operation logic processing should be the same. When the results are consistent, that is, the results of the bitwise AND are all 1, it means that there is no hardware failure in hardware circuit 1 in this simulation, and the operation result is reliable. At this time, the calculation error signal output by the comparator is low, so that the downstream circuit can use the operation result of hardware circuit 1 as input for subsequent operations.

[0057] When hardware failure occurs, due to the operational independence of hardware circuit 1 and redundant circuit, the operation results are inconsistent, causing the comparator circuit to give a fault alarm. Specifically, the comparator pulls up the output calculation error signal. The alarm information is directly output to the control register module, and the control register module issues a control command to discard the result of the current simulation of hardware circuit 1. At the same time, the instruction queue is requested to issue the simulation command corresponding to this simulation again, and the next round of simulation is carried out until the calculation error signal output by the comparator is low.

[0058] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit its protection scope. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in the field should understand that after reading the present invention, those skilled in the art can still make various changes, modifications or equivalent substitutions to the specific implementation methods of the invention, but these changes, modifications or equivalent substitutions are all within the protection scope of the pending claims of the invention.

Claims

1. A redundant hardware failure time division multiplexing detection circuit, characterized in that: It includes a counter, a selector, a redundant circuit and a comparator; the counter includes an input selection counter and an output selection counter, and the selector includes an input selector mux_in and an output selector mux_out; The count enable of the input selection counter is connected to the first input completion flag output by the upstream circuit, the count enable of the output selection counter is connected to the second input completion flag output by the downstream circuit, the output end of the input selection counter is connected to the enable end of the input selector mux_in, and the output end of the output selection counter is connected to the enable end of the output selector mux_out; The input end of the input selector mux_in is connected to the output of the upstream circuit, the output end of the input selector mux_in is connected to the input end of the redundant circuit, the input end of the output selector mux_out is connected to the output of the hardware circuit, and the output end of the output selector mux_out is connected to one input end of the comparator; The input end of the redundant circuit is connected to the output end of the input selector mux_in, the output end of the redundant circuit is connected to the other input end of the comparator, and the output end of the comparator is connected to the control register.

2. A redundant hardware failure time division multiplexing detection circuit according to claim 1, characterized in that: The enable end of the redundant circuit is connected to the clock gating, the input end of the clock gating is connected to the input clock and the redundant enable, the output end of the clock gating is connected to the clock input end of the redundant circuit, and the clock gating is used to provide a clock for the redundant circuit.

3. A redundant hardware failure time division multiplexing detection circuit according to claim 1, characterized in that: The count value of the input selection counter is incremented after the input data transmission from the upstream circuit to the hardware circuit is completed; the count value of the output selection counter is incremented after the output data transmission from the hardware circuit to the downstream circuit is completed.

4. The redundant hardware failure time division multiplexing detection circuit according to claim 1, characterized in that: The enable terminal of the input selector mux_in is connected to the count value of the input selection counter 1, and the enable terminal of the output selector mux_out is connected to the count value of the output selection counter 2.

5. The redundant hardware failure time division multiplexing detection circuit according to claim 1, characterized in that: The input selector mux_in selects the input data of the hardware circuit with the same number as the count value of the input selection counter and inputs it into the redundant circuit, and the calculation result of the redundant circuit is input into one input terminal of the comparator; The output selector mux_out selects the output data of the hardware circuit having the same count value as the output selection counter as the calculation result of the hardware circuit, and the calculation result of the hardware circuit is input into the other input terminal of the comparator.

6. A redundant hardware failure time division multiplexing detection circuit according to claim 1, characterized in that: Eight hardware circuits are set, and the eight hardware circuits are hardware circuits numbered 0 to 7 obtained by instantiating the same hardware circuit. The counter uses a three-bit counter, corresponding to eight counting values ​​from 0 to 7. The value of the counter is polled from 0 to 7 once, and after self-incrementing to 7, the value of the counter jumps to 0, and a new round of self-incrementing operation begins.

7. A redundant hardware failure time division multiplexing detection circuit according to claim 6, characterized in that: The output end of the comparator outputs a comparison result between the calculation result of the redundant circuit and the calculation result of the hardware circuit.

8. A redundant hardware failure time division multiplexing detection circuit according to claim 7, characterized in that: The specific method for comparing the calculation results of the redundant circuit with the calculation results of the hardware circuit is: in one round of hardware failure detection, the calculation results of the redundant circuit and the calculation results of the hardware circuit are continuously input into the comparator at the same time, and the comparator compares the calculation results of the redundant circuit with the calculation results of the hardware circuit bit by bit. During one comparison process, the serial number of the hardware circuit matched by the redundant circuit is constant. After eight comparisons, one round of hardware failure detection for hardware circuit 0 to hardware circuit 7 is completed.

9. A redundant hardware failure time division multiplexing detection method, using a redundant hardware failure time division multiplexing detection circuit as claimed in any one of claims 1 to 8, characterized in that: The calculation of the hardware circuit and the calculation of the redundant circuit are independent and equivalent to each other. The comparator starts a bitwise AND operation after receiving the calculation result of the redundant circuit and the calculation result of the hardware circuit each time.

10. A redundant hardware failure time division multiplexing detection method according to claim 9, characterized in that: The output terminal of the comparator outputs a calculation error signal; When there is no hardware failure, the results of the bitwise AND operation are all 1, and the calculation error signal output by the comparator is low level; When there is a hardware failure, the result of the bitwise AND operation is not all 1, the calculation error signal output by the comparator is high, the comparator circuit issues a fault alarm message, the fault alarm message is output to the control register, and the control register issues a control command to discard the calculation result of the hardware circuit and perform the next round of comparison until the calculation error signal output by the comparator is low.

Images