Using shadow and active latches to transpose information to achieve efficient die area in processing system

Abstract

Systems and methods for transposing information in a processing system using shadow latches and active latches to achieve efficient die area. An example storage device includes a group of active latches and shadow latches, where the active / shadow storage device receives a first matrix including values, and the active latches are enabled within a first clock cycle such that the values are stored in the active latches. The shadow latch copies the value stored in the active latch. Values replicated in the shadow latch are read during a second clock cycle, wherein at least one value included in the second matrix is stored in the at least one active latch during the second clock cycle.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Application No. 63 / 362,876, filed on April 12, 2022, entitled “TRANSPOSING INFORMATION USING SHADOW LATCHES AND ACTIVE LATCHES FOR EFFICIENT DIE AREA IN PROCESSING SYSTEM,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to transposing information using hardware elements, and more particularly to transposing information using latches. Background Art

[0004] Neural networks are used for various purposes and are increasingly becoming a technological foundation. For example, a neural network may be utilized to perform object classification on an image acquired via a user device (e.g., a smartphone). In this example, the neural network may represent a convolutional neural network that applies convolutional layers, pooling layers, and one or more fully connected layers to classify objects depicted in an image. As another example, a neural network may be utilized to convert text between languages. For this example, the neural network may represent a recurrent neural network.

[0005] Often, information may need to be transposed as part of neural network training or at inference time. For example, a first matrix may be used to store information such as input data, weight data, etc. In this example, the first matrix may be multiplied by a second matrix or vector (e.g., a column vector). As can be appreciated, multiplying a first matrix by a second matrix or a first matrix by a column vector requires that the number of columns in the first matrix equals the number of rows in the second matrix or column vector. Therefore, for some multiplications, it may be necessary to transpose the first matrix to switch the row and column indices of the matrix.

[0006] Currently, hardware techniques for transposing matrices, for example in a streaming context, require a large number of hardware elements that consume a large amount of die area. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A is a block diagram illustrating a matrix processor system including an example active / shadow storage device for transposing data and an example matrix processor for processing data.

[0008] Figure 1B is a block diagram illustrating details of an example active / shadow storage device included in a matrix processor system.

[0009] Figure 1C is a block diagram illustrating the details of entering data into active / shadow storage.

[0010] Figure 1D is a block diagram illustrating the details of reading transposed data from active / shadow storage.

[0011] Figure 2A is a block diagram illustrating an example of writing data into active latches included in an example active / shadow storage device.

[0012] Figure 2B is a block diagram illustrating an example of storing data in shadow latches included in an example active / shadow storage device.

[0013] Figure 2C is a block diagram illustrating an example of writing new data into active latches and reading data from shadow latches.

[0014] Figure 3 is a flow chart of an example process for transposing data using active / shadow storage.

[0015] Figure 4 is a block diagram illustrating an example vehicle including a vehicle processor system.

[0016] Embodiments of the present disclosure and their advantages can be best understood by referring to the following detailed description. It should be understood that the same reference numerals are used to identify the same elements shown in one or more figures, wherein the illustrations in the figures are for illustrating embodiments of the present disclosure, rather than for limiting the present disclosure. DETAILED DESCRIPTION

[0017] The present application describes techniques for enabling data to be transposed in a streaming context while efficiently utilizing die area. As will be described, information can be streamed during processor operation, where the information can be quickly transposed when needed. The processor can be, for example, a matrix processor for performing neural network processing. It will be appreciated that it may be necessary to transpose a matrix, such as a portion of an input image, a feature map, a filter, or a kernel, to allow a matrix to be multiplied by another matrix or vector. Therefore, transposing information can be a necessary step in processing layers such as convolutional layers in a neural network. As described later, the techniques described herein utilize an array or combination of active latches and shadow latches (referred to herein as active / shadow storage devices) to efficiently transpose information while limiting the die area required for the transposition.

[0018] To transpose data, such as a matrix, using hardware elements, an example technique may use an array or combination of flip-flops (e.g., a set of 2D flip-flops). Each flip-flop may be used to store a bit included in the matrix. Thus, if the matrix is ​​a 4×3 matrix including 12 values, there may be 12 flip-flops for storing these values. It will be appreciated that the 12 values ​​may require more than one bit, and therefore there may be more than 12 flip-flops for storing these values. To transpose a 4×3 matrix, the outputs of the flip-flops may be ordered so that the values ​​are rotated around the diagonal of the matrix. In this way, a 4×3 matrix may be output (e.g., read out) as a 3×4 matrix.

[0019] While using a single flip-flop for each bit included in the matrix may allow transposing the data, this is not allowed in a streaming context. For example, given that the matrix cannot be read or written within a certain number of clock cycles (e.g., a single clock cycle, a clock cycle for each row of the matrix, etc.), full pipelining cannot be used. As known to those skilled in the art, the inability to work in a streaming context will preclude the use of this technique because new inputs cannot be written until all outputs have been read. Therefore, throughput and overall processing speed will be limited.

[0020] Another example technique for transposing data may include using two flip-flops for each bit. This may allow data to be transposed in a streaming context, for example allowing new information to be written while old information is being read. For example, the two flip-flops for each bit may include a first flip-flop and a second flip-flop. After the information is written to the flip-flop, the second flip-flop may receive a copy of the information from the first flip-flop. Then, while the new information is written to the first flip-flop, the information may be read from the second flip-flop. However, this example technique may greatly increase the required die area allocated to the transposed data. The increased complexity and cost, as well as the possible reduced space for other hardware elements in the processor may lead to a disfavor in favor of using two flip-flops for each bit.

[0021] The techniques described herein advantageously allow the use of two latches for each bit of the matrix to be transposed. A latch, such as an SR latch, may require much less die area than a flip-flop, which, for example, may be formed from two latches. Furthermore, the conventional structure may be suitable for scripted physical placement, which may enhance the manufacture of active / shadow storage devices.

[0022] As described below, the two latches may include an active latch and a shadow latch. For example, the values ​​included in the matrix may be written to the active latch in one or more clock cycles. In this example, these values ​​may then be stored in the shadow latch. Then, while the values ​​are read from the shadow latch, the new values ​​included in the new matrix may be written to the active latch. In this way, the technology described herein allows streaming of information to be transposed during the operation of the processor.

[0023] To control the operation of the active latch and the shadow latch, different clock gates may be used. For example, the active latch may be controlled via a first clock gate signal, while the shadow latch may be controlled via a second clock gate signal. Thus, in this example, the active latch and the shadow latch may be enabled at specific times to ensure proper operation of the active / shadow storage device.

[0024] In some embodiments, the active latch can be transparent on the high phase of the clock when input data is ready. The shadow latch can be transparent on the low phase of the clock when data is ready to move from the active latch to the shadow latch. Thus, in some embodiments, the same clock (e.g., at least Figure 1B shown).

[0025] In some embodiments, this innovation can be used for algorithms other than pure transposition. For example, a circuit can read the diagonal elements of an array one at a time. Without the techniques described herein, this cannot be done naively without stopping the row write before completing the diagonal read.

[0026] block diagram

[0027] Figure 1A 1 is a block diagram illustrating a matrix processor system 100 including an example active / shadow storage device 110 for transposing data and an example matrix processor 120 for processing data. For example, the matrix processor system 100 may be used to compute the forward pass of each layer of a neural network. In some embodiments, the neural network may represent a convolutional neural network in which image or video information is processed.

[0028] In the illustrated example, input data 102A is provided to the matrix processor system 100. As described above, the input data 102A may represent an input image, one or more feature maps, or a portion thereof. For example, the portion may represent a particular window of the input data that will be multiplied by weight data (e.g., one or more kernels or filters). The input data 102A may also represent information input to a layer of a neural network, such as a convolution, transformer, or fully connected network, that will be multiplied by weight information (e.g., a weight matrix).

[0029] As known to those skilled in the art, it may be necessary to transpose the input data 102A to multiply the input data 102A with other input data 102B. For example, the input data 102A may represent a 20×10 matrix including 120 values. In this example, the input data 102B may represent a 20×4 matrix including 80 values. Therefore, in order to multiply these matrices, the input data 102A is transposed into a 10×20 matrix.

[0030] The matrix processor system 100 includes an active / shadow storage device 110 for transposing input data 102A into transposed data 112. As described above, as will be described in more detail, the active / shadow storage device 110 includes a plurality of active latches and shadow latches. Each active latch can be connected to an individual shadow latch in the storage device 110. In some embodiments, the active / shadow storage device 110 can include an array of active latches and shadow latches. For example, there can be an array of groups of active latches and shadow latches organized in rows and columns. In this example, there can be 32×32, 20×20, 36×48, etc. groups of active latches and shadow latches.

[0031] The input data 102A may be written to the active latches in one or more clock cycles. For example, in each clock cycle, a certain amount of data (e.g., obtained from external memory) may be written to the active / shadow storage device 110. In some embodiments, the amount of data may be 8 bits, 10 bits, 16 bits, 32 bits, etc. In some implementations, as will be described below with reference to Figure 1B As described above, the number of clock cycles may correspond to the number of rows included in the input data 102A.

[0032] In this manner, the matrix processor 120 may determine a processing result 122 associated with the multiplication of the input data 102A and the input data 102B. For example, the processing result 122 may represent an output associated with the multiplication of the input data and the weights in a layer of a neural network. For example, the processing result 122 may also represent an output associated with a portion of the processing performed in a layer of a neural network. In some embodiments, the processing result 122 may represent one or more windows of input information (e.g., an input image, a feature map, etc.) convolved with one or more filters or kernels.

[0033] Although Figure 1A Input data 102A is shown being transposed, for example via active / shadow storage 110 , but in some embodiments input data B 102B may be transposed.

[0034] An example matrix processor 120 is described in greater detail with respect to US Pat. No. 11,157,287, US Pat. No. 11409692, and US Pat. No. 11,157,441, the entire contents of which are incorporated herein by reference and made a part of the present disclosure as if set forth herein.

[0035] Figure 1B 1 is a block diagram illustrating details of an example active / shadow storage device 110 included in a matrix processor system 120. Active / shadow storage device 110 includes a plurality of latches, which may be characterized as active latches (e.g., 'A' latches) or shadow latches (e.g., 'B' latches). In some embodiments, individual active latches may be associated with individual shadow latches to form a group of latches, such as active latch 160 and shadow latch 162. Each group of latches may be used for individual bits of input data (e.g., a matrix of values), such that each bit of input data is associated with two latches included in active / shadow storage device 110.

[0036] An active latch, such as active latch 160, can receive corresponding bits of input data. For example, the input data can include a matrix of values ​​to be transposed. In this example, each value of the matrix (e.g., a specific row and column element of the matrix) can be represented by one or more bits. Therefore, each active latch can receive one of these bits for storage.

[0037] In some embodiments, active latch 160 may represent a set of active latches. For example, each active latch in the set of active latches may be used to store a bit associated with a larger value (e.g., a byte, word, integer, floating point number, etc.). Similarly, shadow latch 162 may represent a set of shadow latches that receive information from the set of active latches. In this manner, active / shadow storage 110 may be used to transpose a matrix of values, which are bytes, words, integers, etc.

[0038] It will be appreciated that the values ​​included in the value matrix may be provided to the active / shadow storage device 110 in one or more cycles. For example, the values ​​may be provided from an element (e.g., memory, Figure 1B10 (not shown) is obtained and provided to the active / shadow storage device 110 via a bus. The width or bandwidth of the bus may cause the value to be provided in more than one clock cycle. In some embodiments, the number of clock cycles may be based on the size of the matrix. For example, the number of clock cycles may correspond to the number of rows included in the matrix. In this example, the active latches included in the same column of the active / shadow storage device 110 or otherwise assigned to the column or associated with the column may receive the corresponding bits in the same clock cycle (for example, since the data is being transposed, the active latches of the same column may be associated with the rows included in the matrix). As another example, the number of clock cycles may correspond to the number of columns included in the matrix. In this example, the active latches included in the same row of the active / shadow storage device 110 or otherwise assigned to the row or associated with the row may receive the corresponding bits in the same clock cycle.

[0039] After the bits included in the value matrix are stored in the active latch, the shadow latch can store a copy of the bits. For example, the shadow latch 162 can receive the bits stored in the active latch 160. Figure 2A-2C As shown, the shadow latch can copy the information in the active latch at a specific clock edge (eg, rising clock edge, falling clock edge). For example, the shadow latch 162 can be enabled substantially simultaneously to store bits included in the value matrix.

[0040] Subsequently, the information stored in the shadow latches can be read in one or more clock cycles. For example, each row of shadow latches included in the active / shadow storage device 110 can be addressed, and the bits stored therein can be read from the shadow latches. As another example, each column of shadow latches included in the active / shadow storage device 110 can be addressed, and the bits stored therein can be read from the shadow latches. As shown, a matrix of values ​​can be read, thereby transposing the matrix. For example, the values ​​can be flipped on the diagonal of the matrix.

[0041] The number of clock cycles used to read information can optionally be based on the number of columns included in the value matrix. For example, if the value matrix is ​​an M×N matrix, where each value is one bit, there may be M clock cycles used to write N bits of information into the active latch. In this example, there may be N clock cycles used to read M bits of information from the shadow latch.

[0042] It will be appreciated that new information (e.g., a new matrix of values) may be stored in the active latches in one or more clock cycles while the information stored in the shadow latches is being read. During operation of the active / shadow storage device 110, such as during steady-state operation, the active latches may be written to while the shadow latches are being read. Advantageously, the active latches and the shadow latches may store different data such that during steady-state operation, the matrix may be streamed to the storage device 110 and then transposed in a streaming context.

[0043] In some embodiments, the active / shadow storage device 110 may write information to the active latches at each clock cycle, while also reading information from the shadow latches at the same clock cycle. For example, a square matrix may cause the same number of writes to be performed as the number of reads. With respect to the example of the M×N matrix described above, if M is the same as N, there may be M clock cycles for writing M bits of information into the active latches, and there may be M clock cycles for reading M bits of information from the shadow latches. However, in some embodiments, a non-square matrix may cause a different number of writes to be performed than the number of reads. For an M×N matrix, where M is 10 and N is 16, there may be 16-bit writes to the active latches for 10 cycles, and 10-bit reads from the shadow latches for 16 cycles. Thus, the pipeline (e.g., streaming) of the matrix may be adjusted according to the dimensions of the matrix. For example, the storage device 110 may limit the extent to which new information is written to the active latches (e.g., relative to the above example, the storage device 110 may be written to in 10 clock cycles out of every 16 clock cycles).

[0044] In order to allow the use of latches, and thus reduce die area compared to using another technique for transposing matrices (e.g., flip-flops), clock 150 can be gated separately for active latches and shadow latches. For example, clock gate 152A can be opened or closed to enable or disable the active latch. As another example, clock gate 152B can be opened or closed to enable or disable the shadow latch. In the illustrated embodiment, the same clock is used so that the active latch and the shadow latch use opposite edges of the clock (e.g., high phase, low phase).

[0045] In this manner, the active latch and the shadow latch may be controlled separately. In some embodiments, the clock gates 152A and 152B may be switched according to instructions executed by the matrix processor system 100. In some embodiments, the active latch and the shadow latch may be set to be active on opposite edges of the clock 150. For example, the active latch may be enabled based on the rising edge of the clock 150, while the shadow latch may be enabled based on the falling edge of the clock 150 (e.g., or vice versa). Figure 2A-2CAdditional details associated with opening or closing active latches and shadow latches are described.

[0046] Figure 1C is a block diagram illustrating details of inputting data into active / shadow storage 110. Example input data 170 is included in Figure 1C , where input data 170 represents a 3×3 matrix. It will be appreciated that the dimensions of the matrix and the latches included in storage device 110 are arbitrary, and the techniques described herein can be applied to different data structures. Input data 170 includes values ​​R to Z, where each value represents a bit, byte, word, etc. as described above.

[0047] An example implementation of inputting input data 170 into storage device 110 is illustrated. In this example, the first row of values ​​is input into the upper row of active latches. The second row of values ​​is input into the middle row of active latches. The third row of values ​​is input into the bottom row of active latches.

[0048] Figure 1D 1 is a block diagram illustrating details of reading transposed data 172 from active / shadow storage device 110. As shown, information can be read from storage device 110 such that input data 170 is transposed to transposed data 172. As described above, information can be input into storage device 110 in one or more cycles. For example, the first row of values ​​described above can be input during one clock step, and the second row of values ​​can be input during the next clock step. The values ​​input into storage device 110 and thus stored in the active latch as described herein can then be stored by the shadow latch.

[0049] In the illustrated example, the top row of transposed data 172 is read from the leftmost shadow latch. The middle row of transposed data 172 is read from the middle shadow latch. The bottom of transposed data 172 is read from the rightmost shadow latch. As can be appreciated, as described herein, while data is being read from the shadow latches, new data (e.g., new input data to be transposed) can be stored in the active latches. In this way, data can be transposed in a streaming manner.

[0050] Figure 2Ais a block diagram illustrating an example of writing data to an active latch 210 included in an example active / shadow storage device 110. An active latch 210 (e.g., an 'A' latch) may represent an individual active latch included in the storage device 110, such as the active latch 160. In the illustrated example, a value A 202 is written to the active latch 210. As described herein, the value A 202 may be a bit included in a value matrix. For example, the matrix may be an M×N bit matrix (e.g., M*N bits). In this example, there may be at least M×N active latches and M×N shadow latches (e.g., 2*M*N latches). As another example, the matrix may be divided into two or more matrices depending on the number of latches included in the active / shadow storage device 110.

[0051] To store the value A 202 in the active latch 210, the clock gate 152A may be enabled. As shown, the clock gate 152A is set to be enabled so that the active latch 210 can store the value A 202. To write the value matrix to the active latch 110, one or more clock cycles may be required. Figure 2A , multiple clock cycles of clock 150 are illustrated, where rising edges 210A-210N cause the activity latch to be enabled. For example, clock gate 152A may be set to be enabled (eg, logic '1'), and the activity latch is enabled based on the clock being positive (eg, '1' logic).

[0052] exist Figure 2A , the shadow latch 220 is disabled based on the clock gate 152B being set to disabled (eg, logic '0'). As will be described below, the shadow latch 220 may be enabled to replicate the value A 202.

[0053] Figure 2B is a block diagram illustrating an example of storing data in shadow latches 220 included in an example active / shadow storage device 110. After the active latches are written to the active / shadow storage device 110, such as active latches 210, the shadow latches may be enabled to store a copy of the information stored in the active latches.

[0054] In the example shown, clock gate 152B has been set to enabled (e.g., logic '1') so that on falling edge 212 of clock 150, shadow latches 220 are enabled. In addition to shadow latches 220, in some embodiments, all shadow latches 220 may be enabled to copy the values ​​in their corresponding active latches. Clock gate 152A may optionally be set to disabled so that new information (e.g., a new matrix of values) is not written into the active latches.

[0055] Figure 2C2 is a block diagram illustrating an example of writing new data into the active latch 210 and reading data from the shadow latch 220. Figure 2B As shown, shadow latch 220 stores value A 202 at falling edge 212 of clock 150. To ensure that active / shadow storage device 110 operates in a streaming context, such that during steady-state operation, information can be written / read within the same clock cycle, new information can be written to active latch 210 while old information is being read from shadow latch 220.

[0056] In the example shown, clock gate 152A is set to enabled, while clock gate 152B is set to disabled. Thus, new information (e.g., value B 204) can be written to active latch 210. For example, at a rising edge 214A of clock 150, value B 204 can be stored in active latch 210. With clock gate 152B set to disabled, shadow latch 220 can hold value A 202 at a subsequent falling edge of clock 150. Advantageously, value A 202 can be read during a clock cycle such that new information (e.g., value B 204) is written while old information (e.g., value A 202) is being read.

[0057] Regarding steady-state operation, it will be appreciated that the value of the new information can be written to the active latch in one or more clock cycles. Similarly, during these clock cycles, the old information can be read from the shadow latch.

[0058] Example Flowchart

[0059] Figure 3 is a flow chart of an example process 300 for transposing data using active / shadow storage. For convenience, the process 300 will be described as being performed by the matrix processor system 100.

[0060] At block 302, the system causes input data to be stored in active latches of an active / shadow storage device. During system operation, input data to be transposed may be obtained (e.g., based on instructions, such as software instructions). This information may be provided to an active / shadow storage device that includes multiple sets of active latches and shadow latches. Each set of active latches and shadow latches may be associated with a bit of the input data. Figure 2A As shown, the input data may be stored in the active latch within one or more clock cycles. For example, the active latch may be enabled via the first clock gate signal being set to enabled.

[0061] At block 304, the system copies the active latch data into the shadow latch. The second clock gate signal may be enabled, and optionally, the first clock gate signal may be set to be disabled, which causes the shadow latch to be enabled. After being enabled, the shadow latch may store (e.g., duplicate or copy) information stored in the active latch.

[0062] At block 306, the system reads data from the shadow latches while new data is being written to at least some of the active latches. Figure 2C As shown, the information stored in the shadow latches can be read in one or more clock cycles. The information can be read so that the value obtained in block 302 can be transposed (e.g., flipped diagonally). While the information is being read, at least some of the active latches can be enabled in one or more clock cycles so that new information is stored in the active latches.

[0063] Vehicle Block Diagram

[0064] Figure 4 A block diagram of a vehicle 400 (e.g., vehicle 102) is illustrated. The vehicle 400 may include one or more motors 402 that cause movement of the vehicle 400. The motors 402 may include, for example, induction motors, permanent magnet motors, etc. As known to those skilled in the art, a battery 404 (e.g., one or more battery packs, each battery pack including a plurality of batteries) may be used to power the motors 402.

[0065] Vehicle 400 also includes a propulsion system 406 that can be used to set the gear (eg, propulsion direction) of the vehicle. For an electric vehicle, propulsion system 406 can adjust the operation of electric motor 402 to change the propulsion direction.

[0066] In addition, the vehicle includes a matrix processor system 100 configured to transpose information as described herein. The matrix processor system 100 can process data, such as images received from image sensors (e.g., cameras 104A-104N) located around the vehicle 400. The matrix processor system 100 can additionally output information to and receive information (e.g., user input) from a display 408 included in the vehicle 400.

[0067] Other embodiments

[0068] All processes described herein can be embodied and fully automated via software code modules that are executed by a computing system including one or more computers or processors. The code modules can be stored in any type of non-transitory computer-readable medium or other computer storage device. Some or all of these methods can be embodied in dedicated computer hardware.

[0069] It will be apparent from this disclosure that there are many other variations in addition to those described herein. For example, depending on the embodiment, certain actions, events, or functions of any algorithm described herein may be performed in a different order, may be added, merged, or omitted entirely (e.g., not all described actions or events are necessary for algorithm practice). In addition, in some embodiments, actions or events may be performed concurrently, such as by multithreading, interrupt handling, or multiple processors or processor cores, or on other parallel architectures, rather than sequentially. In addition, different tasks or processes may be performed by different machines and / or computing systems that may work together.

[0070] The various illustrative logic blocks, modules, and engines described in conjunction with the embodiments disclosed herein may be implemented or executed by a machine designed to perform the functions described herein, such as a processing unit or processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof. The processor may be a microprocessor, but in an alternative, the processor may be a controller, a microcontroller, or a state machine, a combination thereof, or the like. The processor may include a circuit system configured to process computer executable instructions. In another embodiment, the processor includes an FPGA or other programmable device that performs logic operations without processing computer executable instructions. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration. Although primarily described herein with respect to digital technology, the processor may also primarily include analog components. For example, some or all of the signal processing algorithms described herein may be implemented in an analog circuit system or a mixed analog and digital circuit system. The computing environment may include any type of computer system, including but not limited to a microprocessor-based computer system, a mainframe computer, a digital signal processor, a portable computing device, a device controller, or a computing engine within an appliance, etc.

[0071] Unless otherwise specifically stated, conditional language such as "can," "could," "might," or "may" is understood in the context of being generally used to convey that certain embodiments include and other embodiments do not include certain features, elements, and / or steps. Thus, such conditional language generally does not indicate that one or more embodiments require the features, elements, and / or steps in any way, nor does it indicate that one or more embodiments must include logic for deciding whether to include or perform such features, elements, or steps in any particular embodiment with or without user input or prompting.

[0072] Unless specifically stated otherwise, negative language, such as the phrase "at least one of X, Y, or Z," should be understood along with the context generally used to indicate that an item, term, etc. can be X, Y, Z, or any combination thereof (e.g., X, Y, and / or Z). Thus, such disjunctive language is generally not intended to, and should not, imply that certain embodiments require that at least one of X, at least one of Y, or at least one of Z are all present.

[0073] Any process description, element or block in the flowcharts described herein and / or shown in the drawings should be understood to potentially represent a code module, segment or portion, which includes one or more executable instructions for implementing a specific logical function or element in the process. Alternative implementations are included within the scope of the embodiments described herein, where elements or functions may be deleted, executed out of the order shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved.

[0074] Unless expressly stated otherwise, articles such as "a" or "an" should generally be interpreted as including one or more of the items. Thus, phrases such as "a device configured to..." are intended to include one or more of the referenced devices. Such one or more referenced devices may also be collectively configured to perform the references. For example, "a processor configured to perform references A, B, and C" may include a first processor configured to perform reference A, the first processor working in conjunction with a second processor configured to perform references B and C.

[0075] It should be emphasized that many changes and modifications may be made to the above-described embodiments, and its elements should be understood as one of other acceptable examples. All such modifications and changes are intended to be included within the scope of the present disclosure.

Claims

1. A matrix processor system, comprising: An active / shadow storage device, comprising a set of active latches and shadow latches, wherein the active / shadow storage device is configured to: receiving a first matrix comprising a plurality of values, enabling the active latch during one or more first clock cycles so that the value is stored in the active latch, causing the shadow latch to copy the value stored in the active latch, and The values ​​replicated in the shadow latches are read from the shadow latches during one or more second clock cycles, wherein the values ​​are transposed compared to the first matrix, and wherein at least one value included in the second matrix is ​​stored in at least one active latch during the one or more second clock cycles. 2 . The system of claim 1 , wherein the active latch is configured to be enabled at a first edge of a clock signal. 3 . The system of claim 2 , wherein the shadow latch is configured to be enabled at a second edge of the clock signal opposite to the first edge.

4. The system of claim 1, wherein the active latch is associated with a first clock gate, and wherein the shadow latch is associated with a second clock gate.

5. The system of claim 4, wherein the first clock gate and the second clock gate are enabled on opposite edges of a clock signal.

6. The system of claim 4, wherein instructions set the first clock gate and the second clock gate.

7. The system of claim 1, wherein the value is a corresponding bit.

8. The system of claim 1, wherein the active latch is enabled based on a particular clock gate being set to be enabled, and wherein the shadow latch is disabled.

9. The system of claim 1, wherein the shadow latch copies the value based on a particular clock gate being set to be enabled, and wherein the active latch is disabled.

10. The system of claim 1, wherein the value is read based on a first clock gate being set to disabled, wherein the particular clock gate is associated with the shadow latch, and wherein a second clock gate associated with the active latch is set to enabled.

11. The system of claim 1 , wherein the individual groups include individual active latches connected to individual shadow latches.

12. The system of claim 1, wherein the first matrix is ​​associated with an input of a neural network layer.

13. The system of claim 1, wherein the transposed values ​​are provided as input to a matrix processor.

14. A method implemented by a matrix processor system, the matrix processor system being configured to transpose input data, wherein the method comprises: causing the input data to be stored in an active latch included in an active / shadow storage device of the matrix processor system, wherein the active / shadow storage device includes a plurality of groups of active latches and shadow latches, wherein an individual group includes an individual active latch connected to an individual shadow latch; copying information stored in the active latch to the shadow latch; as well as For at least some of the active latches, new input data are stored in the active latches while the copied information is read from the shadow latches, wherein the copied information read from the shadow latches is transposed compared to the input data.

15. The method of claim 14, wherein information stored in the active latch is replicated based on a particular clock gate being set to be enabled, wherein the particular clock gate is associated with the shadow latch.

16. The method of claim 14, wherein the input data is stored in the active latch based on a particular clock gate being set to be enabled, wherein the particular clock gate is associated with the active latch.

17. The method of claim 16, wherein the new input data is stored in the active latch based on the particular clock gate being set to enabled, wherein a different clock gate associated with the shadow latch is set to disabled.

18. The method of claim 14, wherein the input data is associated with an input to a neural network layer.

19. The method of claim 14, wherein the transposed replicated information is provided as input to a matrix processor.

20. The method of claim 14, wherein the active latch is associated with a first clock gate, and wherein the shadow latch is associated with a second clock gate.

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