Semiconductor device

Abstract

The invention discloses a semiconductor device. The semiconductor device includes: a substrate; a well layer of a second conductivity type; a ring layer of a second conductivity type; a dielectric layer; one part of a plurality of electric connection bulges of the first metal layer penetrates through the first contact hole and is in contact and electric connection with the ring layer, and the other part of the plurality of electric connection bulges of the first metal layer penetrates through the second contact hole and is in contact and electric connection with the well layer; and the second metal layer is at least partially arranged in the second contact hole and is positioned between the electric connection bulge and the well layer. Therefore, the first metal layer and the second metal layer are arranged in the active region, only the first metal layer is arranged in the transition region, the first metal layer is made of copper, and the second metal layer is made of titanium nitride, so that thermal breakdown caused by charge concentration in the active region can be avoided, charge accumulation in the transition region during avalanche breakdown can be improved, and the service life of the device is prolonged. Therefore, the current can flow out of the transition region close to the terminal region more easily to realize current discharge, and the avalanche tolerance of the terminal region of the semiconductor device can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device. Background Art

[0002] With the continuous development of semiconductor technology, the terminal process of semiconductor devices is also constantly improving. For semiconductor devices, the PN junction at the edge of the chip is a curved surface, where the electric field lines are relatively concentrated, the electric field strength is strong, and the voltage per unit length is large, which makes it easier for voltage breakdown to occur. To improve this situation, terminal structures are designed at the edge of the chip to optimize the electric field strength and increase the breakdown voltage.

[0003] In the related art, the terminal structure of the IGBT device includes an active region, a transition region and a terminal region; the transition region of the device includes a P-type voltage-resistant ring, field oxide, Ti / TiN metal and a metal field plate. Among them, the transition region metal is interconnected with the active region metal, and Ti / TiN metal exists in both the transition region and the active region. When the device undergoes avalanche breakdown, the avalanche breakdown current generated in the terminal region will flow out through the transition region contact hole and the active region contact hole indiscriminately. When the avalanche current is large, the active region will easily overheat, causing thermal breakdown of the device, resulting in irreversible damage. Summary of the invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, one object of the present invention is to provide a semiconductor device, the structural design of which can effectively improve the avalanche withstand capability of the semiconductor device.

[0005] According to the present invention, the semiconductor device comprises: a substrate, the substrate having a first main surface and a second main surface on the opposite side of the first main surface, the first main surface and the second main surface are arranged at intervals in the first direction; a drift layer of the first conductivity type, the drift layer is arranged on the substrate and is located between the first main surface and the second main surface; a well layer of the second conductivity type, the semiconductor device comprises a terminal region, a transition region and an active region, the terminal region is arranged circumferentially on the outside of the active region, the transition region is arranged circumferentially on the outside of the active region and is located between the active region and the terminal region, the well layer is arranged on the side of the drift layer facing the first main surface and corresponds to the active region, the surface of the well layer on the side away from the drift layer in the first direction constitutes a part of the first main surface, and the thickness of the well layer extends from the first main surface along the first direction toward the second main surface; a ring layer of the second conductivity type, the ring layer is arranged on the side of the drift layer facing the first main surface and is opposite to the transition region Correspondingly, a surface of one side of the ring layer in a first direction away from the drift layer constitutes a part of the first main surface, and the thickness of the ring layer is extended from the first main surface along the first direction toward the second main surface; a dielectric layer, the dielectric layer is arranged on the first main surface, a portion of the dielectric layer corresponding to the transition zone is provided with a first contact hole, and a portion of the dielectric layer corresponding to the active zone is provided with a second contact hole; a first metal layer, the first metal layer is arranged on the dielectric layer, the first metal layer is provided with a plurality of electrical connection protrusions, a portion of the plurality of electrical connection protrusions penetrates the first contact hole and is electrically connected to the ring layer, another portion of the plurality of electrical connection protrusions penetrates the second contact hole and is electrically connected to the well layer, and the material of the first metal layer includes copper; a second metal layer, the second metal layer is located in the active zone, the second metal layer is at least partially arranged in the second contact hole and is located between the electrical connection protrusion and the well layer, and the material of the second metal layer includes titanium nitride.

[0006] Therefore, by setting the first metal layer and the second metal layer in the active area and only setting the first metal layer in the transition area, and the material of the first metal layer includes copper, and the material of the second metal layer includes titanium nitride, not only can thermal breakdown caused by charge concentration in the active area be avoided, but also charge accumulation in the transition area during avalanche breakdown can be improved, so that the current can flow out of the transition area close to the terminal area more easily to achieve current unloading, which can improve the avalanche tolerance of the terminal area of ​​the semiconductor device.

[0007] In some examples of the present invention, the second metal layer includes a first metal segment and a second metal segment, the second contact hole has a bottom and a side, the first metal segment is arranged at the bottom of the second contact hole and is in contact and electrically connected with the well layer, a portion of the plurality of electrical connection protrusions corresponding to the active area is in contact and electrically connected with the first metal segment, the second metal segment is arranged at the side of the second contact hole and is connected to the first metal segment, and the plurality of electrical connection protrusions are arranged opposite to the dielectric layer via the second metal segment.

[0008] In some examples of the present invention, the second metal layer is a titanium nitride metal layer.

[0009] In some examples of the present invention, the second metal layer is a titanium metal layer.

[0010] In some examples of the present invention, the second metal layer is a composite metal layer of titanium and titanium nitride.

[0011] In some examples of the present invention, there are multiple first contact holes and multiple second contact holes, the electrical connection protrusions include a first electrical connection protrusion and a second electrical connection protrusion, the first electrical connection protrusion is located in the transition area, the second electrical connection protrusion is located in the active area, there are multiple first electrical connection protrusions and they are arranged one-to-one with multiple first contact holes, there are multiple second electrical connection protrusions and they are arranged one-to-one with multiple second contact holes, a second metal layer is arranged in each of the multiple second contact holes, and the total area of ​​the multiple first contact holes is smaller than the total area of ​​the multiple second contact holes.

[0012] In some examples of the present invention, the area of ​​a single first contact hole is greater than the area of ​​a single second contact hole, and the volume of a single first electrical connection protrusion is greater than the volume of a single second electrical connection protrusion.

[0013] In some examples of the present invention, when the first main surface is observed in a plane, (602) the first contact hole extends circumferentially and has a first width, the first width of the first contact hole is set to L1, the second contact hole has a second length and a second width smaller than the second length, the second width of the second contact hole is set to L2, L1 and L2 satisfy the relationship: 3μm≤L1≤10μm, 0.2μm≤L2≤1μm.

[0014] In some examples of the present invention, a groove is further included, wherein the groove is arranged in the thickness direction of the active area to penetrate the well layer from the first main surface to reach the drift layer, and the length direction of the groove extends in the third direction of the semiconductor device. There are multiple grooves, and the multiple grooves are spaced apart in the second direction of the semiconductor device. The projection of the second contact hole in the first direction is located between the projections of two adjacent grooves in the first direction, wherein the first direction, the second direction and the third direction are perpendicular to each other.

[0015] In some examples of the present invention, the thickness of the first metal layer in the first direction is greater than the thickness of the second metal layer in the first direction.

[0016] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0018] Figure 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention;

[0019] Figure 2 is a partial cross-sectional view of a semiconductor device according to an embodiment of the present invention;

[0020] Figure 3 is a partial cross-sectional view of a semiconductor device according to an embodiment of the present invention;

[0021] Figure 4 is a schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0022] Reference numerals:

[0023] 100. Semiconductor devices;

[0024] 101. terminal area; 102. transition area; 103. active area;

[0025] 20. substrate; 201. first main surface; 202. second main surface;

[0026] 30. drift layer; 40. well layer; 50. ring layer;

[0027] 60, dielectric layer; 601, first contact hole; 602, second contact hole;

[0028] 70, first metal layer; 701, transition zone metal layer; 702, emitter metal layer; 703, first electrical connection protrusion; 704, second electrical connection protrusion;

[0029] 80, second metal layer; 801, first metal segment; 802, second metal segment;

[0030] 902, groove; 904, gate bus metal layer; 905, gate metal layer;

[0031] 91. Terminal region metal layer; 92. Stop ring; 93. Third contact hole. DETAILED DESCRIPTION

[0032] Embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. Embodiments of the present invention are described in detail below.

[0033] Reference below Figure 1-Figure 4 A semiconductor device 100 according to an embodiment of the present invention is described. The semiconductor device 100 may be an IGBT device. In the following description, N and P represent the conductivity type of the semiconductor. In the present invention, the first conductivity type is set as N type and the second conductivity type is set as P type for description.

[0034] Combination Figure 1-Figure 4 As shown, the semiconductor device 100 according to the present invention may mainly include: a substrate 20; a drift layer 30 of a first conductivity type; a well layer 40 of a second conductivity type; a ring layer 50 of a second conductivity type; a dielectric layer 60; a first metal layer 70 and a second metal layer 80.

[0035] Among them, the substrate 20 has a first main surface 201 and a second main surface 202 on the opposite side of the first main surface 201. The first main surface 201 and the second main surface 202 are arranged at intervals in the first direction. Layout design can be performed on both the first main surface 201 and the second main surface 202, which can provide sufficient layout space for the semiconductor device 100.

[0036] Furthermore, a drift layer 30 of the first conductive type is disposed on the substrate 20 and is located between the first main surface 201 and the second main surface 202. The drift layer 30 can not only withstand a large blocking voltage to prevent the device from breaking down in the cut-off state, but also optimize the on-resistance, switching speed and other conductivity characteristics of the semiconductor device 100 by controlling parameters such as the doping concentration and thickness of the drift layer 30.

[0037] Furthermore, the semiconductor device 100 also includes a terminal region 101, a transition region 102 and an active region 103. The terminal region 101 is circumferentially arranged on the outside of the active region 103, and the transition region 102 is circumferentially arranged on the outside of the active region 103 and is located between the active region 103 and the terminal region 101. This can optimize the electric field strength at the edge of the semiconductor device 100 and improve the breakdown voltage of the semiconductor device 100.

[0038] Further, the well layer 40 of the second conductivity type is arranged on the side of the drift layer 30 facing the first main surface 201 and corresponding to the active area 103. The surface of the well layer 40 on the side away from the drift layer 30 in the first direction constitutes a part of the first main surface 201. The thickness of the well layer 40 extends from the first main surface 201 along the first direction toward the second main surface 202. Specifically, the well layer 40 can be used to adjust and control the carrier distribution in the semiconductor device 100. The well layer 40 is arranged on the side of the drift layer 30 facing the first main surface 201 and corresponding to the active area 103, which can help optimize the electrical performance of the semiconductor device 100, such as reducing the on-resistance, improving the switching speed, etc.

[0039] Furthermore, a ring layer 50 of the second conductivity type is arranged on a side of the drift layer 30 facing the first main surface 201 and corresponding to the transition zone 102. A surface of the ring layer 50 on one side in the first direction away from the drift layer 30 constitutes a part of the first main surface 201. The thickness of the ring layer 50 extends from the first main surface 201 along the first direction toward the second main surface 202. The ring layer 50 at least partially extends into the active area 103 and contacts the well layer 40. The thickness of the ring layer 50 in the first direction is greater than the thickness of the well layer 40 in the first direction. This can not only help optimize the electric field distribution of the semiconductor device 100 and optimize the electrical performance of the transition zone 102, but also improve the withstand voltage characteristics of the semiconductor device 100.

[0040] Further, the dielectric layer 60 is disposed on the first main surface 201, and a first contact hole 601 is disposed in a portion of the dielectric layer 60 corresponding to the transition region 102, and a second contact hole 602 is disposed in a portion of the dielectric layer 60 corresponding to the active region 103. Specifically, the dielectric layer 60 mainly plays the role of insulation and isolation, and a gap opening is formed in the dielectric layer 60 along the first direction by etching or placing the dielectric layer 60. The first contact hole 601 and the second contact hole 602 are both disposed at the gap opening of the dielectric layer 60, so that leakage of current passing through the first contact hole 601 and the second contact hole 602 can be prevented, and the stability and reliability of the operation of the semiconductor device 100 can be enhanced.

[0041] Further, the first metal layer 70 is disposed on the dielectric layer 60, and the first metal layer 70 is provided with a plurality of electrical connection protrusions, a part of the plurality of electrical connection protrusions penetrates the first contact hole 601 and is in contact and electrically connected with the ring layer 50, and another part of the plurality of electrical connection protrusions penetrates the second contact hole 602 and is in contact and electrically connected with the well layer 40. Specifically, the electrical connection protrusions have a conductive function, and the electrical connection between the first metal layer 70 and the ring layer 50 and the electrical connection between the first metal layer 70 and the well layer 40 can be achieved through the electrical connection protrusions, so that the current path at the first contact hole 601 and the second contact hole 602 can be optimized, and good current conduction performance at the first contact hole 601 and the second contact hole 602 can be ensured, so that poor contact at the first contact hole 601 and the second contact hole 602 can be avoided, and the current and voltage can be effectively transmitted between the first metal layer 70 and the well layer 40 and the ring layer 50, and the normal working performance of the semiconductor device 100 can be ensured.

[0042] Furthermore, the material of the first metal layer 70 includes AlCu or AlSiCu to achieve the circuit performance and signal transmission speed of the semiconductor device 100 , and can also conduct away the heat generated when the semiconductor device 100 is working, thereby improving the reliability and stability of the semiconductor device 100 .

[0043] Furthermore, the second metal layer 80 is located in the active area 103, and the second metal layer 80 is at least partially arranged in the second contact hole 602 and located between the electrical connection protrusion and the well layer 40. The electrical connection protrusion can ensure the electrical connection between the second metal layer 80 and the well layer 40, and at the same time, the resistance between the first metal layer 70 and the well layer 40 can be increased.

[0044] Furthermore, the material of the second metal layer 80 includes titanium nitride. Titanium nitride has good electrical conductivity and heat resistance, which can not only ensure the normal transmission of the active area 103 signal, but also improve the stability of the semiconductor device 100 at high temperature.

[0045] In this configuration, the first metal layer 70 exists in part of the transition zone 102, and the first metal layer 70 and the second metal layer 80 exist in part of the active zone 103, wherein the material of the first metal layer 70 includes AlCu or AlSiCu, and the material of the second metal layer 80 includes titanium nitride. Specifically, the second metal layer 80 exists only in the active zone 103, so that there is a contact barrier between the second metal layer 80 and the silicon substrate 20 in the active zone 103, so that the contact barrier at the active zone 103 is different from that at the transition zone 102, and the contact barrier at the transition zone 102 is lower than the contact barrier at the active zone 103, and the contact resistance of the transition zone 102 is lower than the contact resistance of the active zone 103, so that the current can flow out of the transition zone 102 more easily. When avalanche breakdown occurs, a large amount of charges are released from the first contact hole 601 of the transition region 102. This not only avoids thermal breakdown caused by charge concentration in the active region 103, but also effectively improves charge accumulation in the transition region 102 during avalanche breakdown, thereby improving the avalanche tolerance of the semiconductor device 100 and improving the reliability of the semiconductor device 100.

[0046] It should be noted that a portion of the electrical connection protrusion corresponding to the active area 103 is in contact with and electrically connected to the second metal layer 80 , and the second metal layer 80 is in contact with and electrically connected to the well layer 40 .

[0047] In some embodiments of the present invention, the structural design of the semiconductor device 100 is described only with respect to the active region 103 and the transition region 102 , and does not include the FRD region.

[0048] Combination Figure 1 , Figure 2 and Figure 3 As shown, the second metal layer 80 includes a first metal segment 801 and a second metal segment 802, the second contact hole 602 has a bottom and a side, the first metal segment 801 is arranged at the bottom of the second contact hole 602 and is in contact and electrically connected with the well layer 40, a portion of a plurality of electrical connection protrusions corresponding to the active area 103 is in contact and electrically connected with the first metal segment 801, the second metal segment 802 is arranged at the side of the second contact hole 602 and is connected to the first metal segment 801, and a plurality of electrical connection protrusions are arranged opposite to the dielectric layer 60 via the second metal segment 802.

[0049] In this way, the second metal layer 80 is formed by the plurality of first metal segments 801 and the plurality of second metal segments 802, so that the second metal layer 80 can be better fitted and connected with the metal protrusions of the first metal layer 70, and the second metal layer 80 can also be in contact and connected with the second contact hole 602 of the active area 103. In addition, space can also be provided to facilitate the arrangement of the second metal layer 80 between the portion of the plurality of electrical connection protrusions corresponding to the active area 103 and the dielectric layer 60, and the corresponding portions of the three are in contact and electrically connected, which can ensure the integrity and rationality of the structure of the semiconductor device 100.

[0050] Combination Figure 1 , Figure 2 and Figure 3 As shown, the second metal layer 80 is a titanium nitride metal layer. Specifically, titanium nitride has good electrical conductivity and heat resistance. Using titanium nitride as the material of the second metal layer 80 can not only improve the electrical conductivity of the semiconductor device 100 and make the signal transmission speed of the semiconductor device 100 faster, but also ensure the stability of the second metal layer 80 at high temperatures, thereby improving the stability of the semiconductor device 100 at high temperatures.

[0051] Furthermore, the titanium nitride metal layer can serve as a barrier layer to prevent metals such as copper from diffusing into the substrate 20 to form spikes under high temperature or other conditions.

[0052] In addition, the titanium nitride metal layer has relatively high hardness and wear resistance, which can not only improve the structural strength of the semiconductor device 100 , but also facilitate the processing of the second metal layer 80 .

[0053] Combination Figure 1 , Figure 2 and Figure 3 As shown, the second metal layer 80 is a titanium metal layer. Specifically, the titanium metal layer also has good electrical conductivity and heat resistance. Using titanium as the material of the second metal layer 80 can also improve the electrical conductivity of the semiconductor device 100, make the signal transmission speed of the semiconductor device 100 faster, and ensure the stability of the second metal layer 80 at high temperatures, thereby improving the stability of the semiconductor device 100 at high temperatures.

[0054] Furthermore, the titanium metal layer can also be used as a barrier layer to prevent metals such as copper from diffusing into the substrate 20 to form spikes under high temperature or other conditions. Compared with the titanium nitride metal layer, the conductivity of the titanium metal layer is slightly higher than that of the titanium nitride metal layer. Using the titanium metal layer as the second metal layer 80 can optimize the conductivity of the active area 103 of the semiconductor device 100.

[0055] Furthermore, the titanium metal layer has good adhesion. Using the titanium metal layer as the second metal layer 80 can make the second metal layer 80 fit better with other structures.

[0056] Combination Figure 1 , Figure 2 and Figure 3As shown, the second metal layer 80 is a composite metal layer of titanium and titanium nitride. Specifically, the composite metal layer of titanium and titanium nitride also has good electrical conductivity and heat resistance. The composite material of titanium and titanium nitride is used to form the second metal layer 80, which can also improve the electrical conductivity of the semiconductor device 100, make the signal transmission speed of the semiconductor device 100 faster, and ensure the stability of the second metal layer 80 at high temperatures, thereby improving the stability of the semiconductor device 100 at high temperatures.

[0057] Furthermore, the titanium and titanium nitride composite metal layer can have both high hardness and adhesion. The use of the titanium and titanium nitride composite metal layer to form the second metal layer 80 can not only improve the structural strength and deformation resistance of the semiconductor device 100, but also improve the adhesion of the second metal layer 80. In addition, the titanium and titanium nitride composite metal layer can also serve as a barrier layer to prevent metals such as copper from diffusing into the substrate 20 to form spikes under high temperature or other conditions.

[0058] In some embodiments of the present invention, the material of the second metal layer 80 is titanium nitride and / or titanium, depending on specific process requirements and performance requirements.

[0059] Combination Figure 1 , Figure 2 and Figure 3 As shown, further, the first metal layer 70 also includes a gate metal layer 905, a gate bus metal layer 904 is arranged on the first main surface 201 and at least partially corresponds to the transition region 102, the gate metal layer 905 penetrates the dielectric layer 60 and is in contact and electrically connected with the gate bus metal layer 904, the gate bus metal layer 904 is C-shaped, and the open position of the gate bus metal layer 904 is the position where the emitter metal layer 702 and the transition region metal layer 701 are connected. The gate bus at the gate bus metal layer 904 can connect the gate driver to the gate of each power semiconductor device, thereby controlling the on and off of each power semiconductor device, and multiple power semiconductor devices can be connected in parallel or in series through the gate bus.

[0060] Combination Figure 1 , Figure 2 and Figure 3 As shown, there are multiple first contact holes 601 and multiple second contact holes 602, the electrical connection protrusions include a first electrical connection protrusion 703 and a second electrical connection protrusion 704, the first electrical connection protrusion 703 is located in the transition area 102, and the second electrical connection protrusion 704 is located in the active area 103, there are multiple first electrical connection protrusions 703 and are arranged one-to-one with the multiple first contact holes 601, and there are multiple second electrical connection protrusions 704 and are arranged one-to-one with the multiple second contact holes 602.

[0061] Specifically, by arranging a plurality of first electrical connection protrusions 703 in a one-to-one correspondence with a plurality of first contact holes 601, the transition zone metal layer 701 is electrically connected to the ring layer 50 of the transition zone 102, and there are multiple electrical connection points. By arranging a plurality of second electrical connection protrusions 704 in a one-to-one correspondence with a plurality of second contact holes 602, the emitter metal layer 702 is electrically connected to the well layer 40 of the active zone 103, and there are multiple electrical connection points. In this way, signal transmission between the transition zone metal layer 701 and the ring layer 50, and signal transmission between the emitter metal layer 702 and the well layer 40 can be achieved, thereby ensuring the normal operation of the transition zone 102 and the active zone 103, and ensuring the stability and reliability of the semiconductor device 100.

[0062] Furthermore, the total area of ​​the plurality of first contact holes 601 is smaller than the total area of ​​the plurality of second contact holes 602 .

[0063] Combination Figure 1 , Figure 2 and Figure 3 As shown, the area of ​​a single first contact hole 601 is larger than the area of ​​a single second contact hole 602, and the volume of a single first electrical connection protrusion 703 is larger than the volume of a single second electrical connection protrusion 704. Specifically, the larger the total area of ​​the contact holes, the better the current conduction performance. By making the area of ​​a single first contact hole 601 larger than the area of ​​a single second contact hole 602, the current conduction performance of the transition region 102 can be made better, so that the current can flow out of the transition region 102 more easily, thereby improving the charge distribution of the transition region 102 and the active region 103, optimizing the working performance of the semiconductor device 100, making it easier for the current to flow out of the transition region 102, and improving the current discharge capacity of the region of the semiconductor device 100 close to the terminal region 101, thereby further improving the charge distribution of the transition region 102 and the active region 103, and optimizing the working performance of the semiconductor device 100.

[0064] Furthermore, when observed in a plane of the first main surface, the first contact hole 601 is circumferentially extended and has a first width, the first width of the first contact hole 601 is set to L1, the second contact hole 602 has a second length and a second width smaller than the second length, the second width of the second contact hole 602 is set to L2, L1 and L2 satisfy the relationship: 3μm≤L1≤10μm, 0.2μm≤L2≤1μm, such a setting can make the areas of the first contact hole 601 and the second contact hole 602 within a reasonable range, and can ensure the performance of the semiconductor device 100 while improving the current discharge capacity of the area of ​​the semiconductor device 100 close to the terminal area 101.

[0065] In addition, the semiconductor device 100 further includes a first conductive type cut-off ring 92, which is disposed on a side of the drift layer 30 facing the first main surface 201 and corresponds to the terminal region 101. A surface of the cut-off ring 92 on one side away from the drift layer 30 in a first direction constitutes a part of the first main surface 201. The thickness of the cut-off ring 92 extends from the first main surface 201 along the first direction toward the second main surface 202. The first metal layer 70 further includes a terminal region metal layer 91, which is located in the terminal region 101. A third contact hole 93 is provided in a portion of the dielectric layer 60 corresponding to the terminal area 101. The terminal area metal layer 91 at least partially penetrates the third contact hole 93 and is in contact and electrically connected with the cut-off ring 92. Since the transition area metal layer 91 is electrically connected with the emitter metal layer 702, a large number of holes flow to the transition area 102 and the active area 103. The terminal area metal layer 91 is a floating metal layer. With such a configuration, the contact electrical connection between the floating metal layer and the cut-off ring can store some holes, thereby supplementing the holes when the semiconductor device 100 needs it.

[0066] Combination Figure 1 , Figure 2 and Figure 3 As shown, the semiconductor device 100 also includes a groove 902, which is arranged in the thickness direction of the active region 103 from the first main surface 201 to penetrate the well layer 40 and reach the drift layer 30. The length direction of the groove 902 extends in the third direction of the semiconductor device 100. There are multiple grooves 902, and the multiple grooves 902 are arranged at intervals in the second direction of the semiconductor device 100. The projection of the second contact hole 602 in the first direction is located between the projections of two adjacent grooves 902 in the first direction, wherein the first direction, the second direction and the third direction are perpendicular to each other.

[0067] Specifically, a groove 902 is formed from the first main surface 201 along the first direction toward the second main surface 202, and the thickness direction of the groove 902 penetrates the second conductive type well layer 40 from the first main surface 201 to reach the first conductive type drift layer 30. There are multiple grooves 902, and the grooves 902 are connected to the dielectric layer at the first main surface 201. The multiple grooves 902 are spaced apart in the second direction of the semiconductor device 100. In this way, the distribution of carriers in the active area 103 can be regulated, the electric field distribution of the semiconductor device 100 can be improved, the voltage resistance and current handling capacity of the semiconductor device 100 can be improved, and the stability and reliability of the semiconductor device 100 can be improved.

[0068] Combination Figure 1 , Figure 2 and Figure 3As shown, the thickness of the first metal layer 70 in the first direction is greater than the thickness of the second metal layer 80 in the first direction. Specifically, the second metal layer 80 is disposed on one side of the second metal layer 80 close to the first main surface 201. By making the thickness of the first metal layer 70 in the first direction greater than the thickness of the second metal layer 80 in the first direction, the flatness of the surface of the semiconductor device 100 can be ensured, and the structural design of the semiconductor device 100 can be optimized.

[0069] The semiconductor device 100 according to the present invention has good working performance, can improve the avalanche resistance of the semiconductor device 100 , and improve the stability and reliability of the semiconductor device 100 .

[0070] In addition, this design is applicable to all semiconductor chips. The coding design layer is the metal contact hole layer. The coding design position can be any metal electrode and any position that does not affect the overall structure and performance of the device. The coding rules can be binary, quaternary, or ASCII codes. At the same time, different sizes or patterns can be designed for digital distinction, and corresponding digital, QR code, and other encodings can be directly performed.

[0071] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0072] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example.

[0073] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A semiconductor device, characterized in that: include: A substrate (20), the substrate (20) having a first main surface (201) and a second main surface (202) on the opposite side of the first main surface (201), the first main surface (201) and the second main surface (202) being arranged at intervals in a first direction; A drift layer (30) of a first conductivity type, the drift layer (30) being arranged on the substrate (20) and located between the first main surface (201) and the second main surface (202); a well layer (40) of a second conductivity type, the semiconductor device (100) comprising a terminal region (101), a transition region (102) and an active region (103), the terminal region (101) being circumferentially arranged outside the active region (103), the transition region (102) being circumferentially arranged outside the active region (103) and being located between the active region (103) and the terminal region (101), the well layer (40) being arranged on a side of the drift layer (30) facing the first main surface (201) and corresponding to the active region (103), a surface of a side of the well layer (40) in a first direction away from the drift layer (30) constituting a part of the first main surface (201), and a thickness of the well layer (40) extending from the first main surface (201) along a first direction toward the second main surface (202); a ring layer (50) of a second conductivity type, the ring layer (50) being arranged on a side of the drift layer (30) facing the first main surface (201) and corresponding to the transition region (102); a surface of the ring layer (50) on one side facing away from the drift layer (30) in a first direction constituting a portion of the first main surface (201); and a thickness of the ring layer (50) extending from the first main surface (201) along a first direction toward the second main surface (202); a dielectric layer (60), the dielectric layer (60) being arranged on the first main surface (201), a portion of the dielectric layer (60) corresponding to the transition region (102) being provided with a first contact hole (601), and a portion of the dielectric layer (60) corresponding to the active region (103) being provided with a second contact hole (602); a first metal layer (70), the first metal layer (70) being arranged on the dielectric layer (60), the first metal layer (70) being provided with a plurality of electrical connection protrusions, a portion of the plurality of electrical connection protrusions penetrating the first contact holes (601) and being in contact and electrically connected with the ring layer (50), another portion of the plurality of electrical connection protrusions penetrating the second contact holes (602) and being electrically connected with the well layer (40), the material of the first metal layer (70) comprising copper; A second metal layer (80), the second metal layer (80) is located in the active area (103), the second metal layer (80) is at least partially disposed in the second contact hole (602) and is located between the electrical connection protrusion and the well layer (40), and the material of the second metal layer (80) includes titanium nitride.

2. The semiconductor device according to claim 1, wherein: The second metal layer (80) comprises a first metal segment (801) and a second metal segment (802); the second contact hole (602) has a bottom and a side; the first metal segment (801) is arranged at the bottom of the second contact hole (602) and is in contact and electrically connected with the well layer (40); a portion of the plurality of electrical connection protrusions corresponding to the active area (103) is in contact and electrically connected with the first metal segment (801); the second metal segment (802) is arranged at the side of the second contact hole (602) and is connected to the first metal segment (801); and the plurality of electrical connection protrusions are arranged opposite to the dielectric layer (60) via the second metal segment (802).

3. The semiconductor device according to claim 2, wherein: The second metal layer (80) is a titanium nitride metal layer.

4. The semiconductor device according to claim 2, wherein: The second metal layer (80) is a titanium metal layer.

5. The semiconductor device according to claim 2, wherein: The second metal layer (80) is a composite metal layer of titanium and titanium nitride.

6. The semiconductor device according to claim 1, wherein: The first contact hole (601) and the second contact hole (602) are both multiple, the electrical connection protrusions include a first electrical connection protrusion (703) and a second electrical connection protrusion (704), the first electrical connection protrusion (703) is located in the transition area (102), and the second electrical connection protrusion (704) is located in the active area (103), the first electrical connection protrusion (703) is multiple and is arranged in a one-to-one correspondence with the multiple first contact holes (601), the second electrical connection protrusion (704) is multiple and is arranged in a one-to-one correspondence with the multiple second contact holes (602), the multiple second contact holes (602) are all provided with a second metal layer (80), and the total area of ​​the multiple first contact holes (601) is smaller than the total area of ​​the multiple second contact holes (602).

7. The semiconductor device according to claim 6, wherein: The area of ​​a single first contact hole (601) is greater than the area of ​​a single second contact hole (602), and the volume of a single first electrical connection protrusion (703) is greater than the volume of a single second electrical connection protrusion (704).

8. The semiconductor device according to claim 7, wherein: When the first main surface is observed in a plane, the first contact hole (601) is circumferentially extended and has a first width. The first width of the first contact hole (601) is set to L1. The second contact hole (602) has a second length and a second width smaller than the second length. The second width of the second contact hole (602) is set to L2. L1 and L2 satisfy the relationship: 3μm≤L1≤10μm, 0.2μm≤L2≤1μm.

9. The semiconductor device according to claim 1, wherein: The semiconductor device (100) further comprises a groove (902), wherein the groove (902) is arranged in the thickness direction of the active region (103) and penetrates the well layer (40) from the first main surface (201) to reach the drift layer (30), and the length direction of the groove (902) extends in the third direction of the semiconductor device (100). There are a plurality of grooves (902), and the plurality of grooves (902) are arranged at intervals in the second direction of the semiconductor device (100). The projection of the second contact hole (602) in the first direction is located between the projections of two adjacent grooves (902) in the first direction, wherein the first direction, the second direction and the third direction are perpendicular to each other.

10. The semiconductor device according to claim 1, wherein: The thickness of the first metal layer (70) in the first direction is greater than the thickness of the second metal layer (80) in the first direction.

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