A super junction MOSFET device and preparation method thereof

Abstract

The present invention relates to the technical field of MOSFET devices, and in particular to a super junction MOSFET device and a preparation method thereof, wherein the device comprises: a substrate, M epitaxial layers, a cut-off layer, a well region, a source metal layer, a gate and a drain metal layer; the M epitaxial layers are located on the substrate; the cut-off layer is located on the M epitaxial layers; a well region is provided in the left and right regions of the cut-off layer respectively; the source metal layer and the gate are both located on the cut-off layer, the source metal layer is located on the well region, the gate is located between the source metal layers, and the gate covers the spacing region between the well regions and a part of the well region, and the drain metal layer is located under the substrate; each epitaxial layer is provided with a floating P+ region, the floating P+ region of each epitaxial layer is arranged corresponding to a well region, and the floating P+ regions of two adjacent epitaxial layers are arranged in an alternating manner. The device improves the reliability and stability of the super junction MOSFET device, and enables the device to have better avalanche tolerance and lower on-resistance.

Description

Technical Field

[0001] The present invention relates to the technical field of MOSFET devices, and in particular to a super junction MOSFET device and a preparation method thereof. Background Art

[0002] Compared with traditional MOSFET devices, Super Junction (SJ) MOSFET (Metal Oxide Semiconductor Field Effect Transistor) has a characteristic that the blocking ability of the device is maintained by the P column, which provides local charge compensation to ensure a low electric field for the entire device. At the same time, a higher doping concentration can be used in the N-doped vertical electron conduction path. Therefore, the super junction MOSFET not only has super strong blocking ability and high breakdown voltage, but also has ultra-low on-resistance.

[0003] However, the single pulse avalanche breakdown energy (EAS) of existing super junction MOSFET devices is poor, and the electric field may approach the surface of the device during breakdown, thereby affecting the quality of the gate oxide on the surface of the device and causing damage to the device. As a result, existing super junction MOSFET devices have low reliability and stability. Summary of the invention

[0004] The embodiments of the present application provide a super junction MOSFET device and a preparation method, thereby solving the technical problem that the single pulse avalanche breakdown energy of the existing super junction MOSFET devices in the prior art is poor, resulting in low reliability and stability of the existing super junction MOSFET devices. The reliability and stability of the super junction MOSFET devices are improved, and the device has the technical effect of having better avalanche tolerance, less reverse recovery charge, lower on-resistance, better forward characteristics and other advantages.

[0005] In a first aspect, an embodiment of the present invention provides a super junction MOSFET device, comprising: a substrate, an M-layer epitaxial layer, a cut-off layer, a well region, a source metal layer, a gate and a drain metal layer;

[0006] The M epitaxial layer is located on the substrate;

[0007] The cut-off layer is located on the M epitaxial layer;

[0008] The well region is respectively provided in the left and right regions of the cut-off layer;

[0009] The source metal layer and the gate are both located on the cutoff layer, the source metal layer is located on the well region, the gate is located between the source metal layers, and the gate covers the spacing region between the well regions and a part of the well region, and the drain metal layer is located under the substrate;

[0010] Each epitaxial layer is provided with a floating P+ region, and the floating P+ region of each epitaxial layer is arranged corresponding to a well region. The floating P+ regions of two adjacent epitaxial layers are staggered, and M is an even number greater than 0.

[0011] Optionally, the M layers of epitaxial layers include: an epitaxial layer of a first epitaxial region, an epitaxial layer of a second epitaxial region, and an epitaxial layer of a third epitaxial region, which are stacked in sequence in a direction from the substrate to the cut-off layer, wherein the number of epitaxial layers in each epitaxial region is an even number, and the M layers of epitaxial layers are used to determine that a certain epitaxial region is a target pressure-bearing region by increasing the thickness of a floating P+ region of the epitaxial layer of the epitaxial region.

[0012] Optionally, when the thickness of the floating P+ zone in the first epitaxial region is greater than the thickness of the floating P+ zone in the second epitaxial region, and the thickness of the floating P+ zone in the second epitaxial region is consistent with the thickness of the floating P+ zone in the third epitaxial region, the first epitaxial region is the target pressure-bearing region, and the first epitaxial region is used to improve impact resistance.

[0013] Optionally, when the thickness of the floating P+ zone of the second epitaxial region is greater than the thickness of the floating P+ zone of the first epitaxial region, and the thickness of the floating P+ zone of the first epitaxial region is consistent with the thickness of the floating P+ zone of the third epitaxial region, the second epitaxial region is the target pressure-bearing region, and the second epitaxial region is used to increase the breakdown voltage.

[0014] Optionally, when the thickness of the floating P+ region in the third epitaxial region is greater than the thickness of the floating P+ region in the first epitaxial region, and the thickness of the floating P+ region in the first epitaxial region is consistent with the thickness of the floating P+ region in the second epitaxial region, the third epitaxial region is the target pressure-bearing region, and the third epitaxial region is used to reduce the on-resistance.

[0015] Optionally, the thickness of the floating P+ zone in the target pressure-bearing area is gradually reduced, and the thickness of the floating P+ zone of the smallest epitaxial layer in the target pressure-bearing area is consistent with the thickness of the floating P+ zone of the epitaxial layer of the epitaxial area other than the target pressure-bearing area.

[0016] Optionally, in each epitaxial layer, the thickness of the floating P+ region of the epitaxial layer is consistent with the thickness of the epitaxial layer.

[0017] Optionally, the well region includes: a P well region, an N+ contact region and a P+ contact region;

[0018] The P-well region is located in the cut-off layer, the N+ contact region and the P+ contact region are located in the P-well region, and the surface of the N+ contact region, the surface of the P+ contact region, the surface of the P-well region and the surface of the cut-off layer are located in the same horizontal plane;

[0019] The N+ contact region is correspondingly arranged under the gate and the source metal layer;

[0020] The P+ contact region contacts the N+ contact region, and the P+ contact region is correspondingly arranged under the source metal layer.

[0021] Optionally, it further includes: a passivation layer, the passivation layer is located between the gate and the source metal layer, and the passivation layer wraps the gate;

[0022] The gate comprises: a gate oxide layer and a polysilicon gate;

[0023] The gate oxide layer is located on the cut-off layer, the gate oxide layer is located between the source metal layers, and the gate oxide layer covers the spacing area between the well regions and a part of the well region;

[0024] The polysilicon gate is located on the gate oxide layer.

[0025] Based on the same inventive concept, in a second aspect, the present invention further provides a method for preparing a super junction MOSFET device, which is used to prepare the super junction MOSFET device as described in the first aspect, and the method comprises:

[0026] forming M epitaxial layers on the substrate;

[0027] forming a cut-off layer on the M epitaxial layer;

[0028] A well region is respectively provided in the left and right regions in the cut-off layer;

[0029] Forming a source metal layer and a gate on the cutoff layer, wherein the source metal layer is located on the well region, the gate is located between the source metal layers, and the gate covers the spacing region between the well regions and a part of the well region;

[0030] forming a drain metal layer under the substrate;

[0031] Each epitaxial layer is provided with a floating P+ region, and the floating P+ region of each epitaxial layer is arranged corresponding to a well region. The floating P+ regions of two adjacent epitaxial layers are staggered, and M is an even number greater than 0.

[0032] One or more technical solutions in the embodiments of the present invention have at least the following technical effects or advantages:

[0033] In an embodiment of the present invention, M epitaxial layers are located on the substrate, and M is an even number greater than 0. The cutoff layer is located on the M epitaxial layers, and a scenic area is provided in the left area and the right area of ​​the cutoff layer. The source metal layer and the gate are both located on the cutoff layer, and the source metal layer is located on the well area. The gate is located between the source metal layers, and the gate covers the spacing area between the well areas and part of the well area. The drain metal layer is located under the substrate. In this way, the entire super junction MOSFET device structure is realized. In the entire device, each epitaxial layer is provided with a floating P+ area, and the floating P+ area of ​​each epitaxial layer is arranged corresponding to a well area, and the floating P+ areas of two adjacent epitaxial layers are staggered. The floating P+ areas in the M epitaxial layers are arranged alternately on the left and right to achieve better charge balance. By setting the floating P+ area, the breakdown position of the device can be accurately controlled, the avalanche tolerance of the device can be improved, the loss of the gate oxide layer can be avoided, and the reliability and stability of the device can be improved. Furthermore, due to the provision of the floating P+ region, the drift region area in the M-layer epitaxial layer is increased, the on-resistance is reduced, and the reverse recovery charge of the diode is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present invention. Also, throughout the accompanying drawings, the same reference figures are used to represent the same components. In the drawings:

[0035] Figure 1 A schematic diagram of the structure of a super junction MOSFET device in an embodiment of the present invention is shown;

[0036] Figure 2 A schematic diagram showing the structure of M=16 epitaxial layers in an embodiment of the present invention is shown;

[0037] Figure 3 A schematic diagram of a structure in which a first epitaxial layer is formed on a substrate in an embodiment of the present invention is shown;

[0038] Figure 4 A schematic diagram of a structure in which a floating P+ region is formed in the first epitaxial layer in an embodiment of the present invention is shown;

[0039] Figure 5 A schematic diagram showing a structure of forming a second epitaxial layer on the first epitaxial layer and forming a floating P+ region in the second epitaxial layer in an embodiment of the present invention;

[0040] Figure 6 A schematic diagram of the structure of forming an M-layer epitaxial layer in an embodiment of the present invention is shown;

[0041] Figure 7 A schematic diagram of a structure in which a cut-off layer is formed on an M-layer epitaxial layer and a P-well region is formed in the cut-off layer in an embodiment of the present invention is shown;

[0042] Figure 8 A schematic diagram of the structure of forming an N+ contact region and a P+ contact region in an embodiment of the present invention is shown;

[0043] Fig. 9 A schematic diagram showing the structure of the M-layer epitaxial layer of the device of Example 1 in the embodiment of the present invention is shown;

[0044] Fig.10 A simulation diagram of electric field distribution of a device of Example 1 in an embodiment of the present invention is shown;

[0045] Fig.11 A schematic diagram showing the structure of the M-layer epitaxial layer of the device of Example 2 in the embodiment of the present invention is shown;

[0046] Fig.12 A simulation diagram of electric field distribution of a device of Example 2 in an embodiment of the present invention is shown;

[0047] Fig.13 A schematic diagram showing the structure of the M-layer epitaxial layer of the device of Example 3 in the embodiment of the present invention is shown;

[0048] Fig.14 A simulation diagram of electric field distribution of a device of Example 3 in an embodiment of the present invention is shown;

[0049] Fig.15 A schematic flow chart of the steps of a method for preparing a super junction MOSFET device in an embodiment of the present invention is shown.

[0050] In the accompanying drawings, 110, substrate; 120, epitaxial layer; 121, floating P+ region; 130, cut-off layer; 140, well region; 150, source metal layer; 160, gate; 170, drain metal layer; 180, passivation layer; 141, P-well region; 142, N+ contact region; 143, P+ contact region; 161, gate oxide layer; 162, polysilicon gate. DETAILED DESCRIPTION

[0051] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0052] Embodiment 1

[0053] A first embodiment of the present invention provides a super junction MOSFET device, such as Figure 1 As shown, it includes: a substrate 110, M epitaxial layers 120, a cutoff layer 130, a well region 140, a source metal layer 150, a gate 160 and a drain metal layer 170. The M epitaxial layer 120 is located on the substrate 110. The cutoff layer 130 is located on the M epitaxial layer 120. A well region 140 is provided in the left and right regions of the cutoff layer 130 respectively. The source metal layer 150 and the gate 160 are both located on the cutoff layer 130, and the source metal layer 150 is located on the well region 140. The gate 160 is located between the source metal layers 150, and the gate 160 covers the spacing region between the well regions 140 and a part of the well region 140. The drain metal layer 170 is located under the substrate 110. Each epitaxial layer 120 is provided with a floating P+ region 121 , and the floating P+ region 121 of each epitaxial layer 120 is arranged corresponding to a well region 140 . The floating P+ regions 121 of two adjacent epitaxial layers 120 are staggered, and M is an even number greater than 0.

[0054] It should be noted that Figure 1 In FIG. 1 , the epitaxial layers 120 are divided by dotted lines. Figure 1 As shown, the structure of the floating P+ region 121 of each epitaxial layer 120 of the M-layer epitaxial layer 120 is specifically set as follows: the floating P+ region 121 of the epitaxial layer 120 of the odd-numbered layers in the M-layer is set correspondingly to a well region 140 in the cut-off layer 130, and the floating P+ region 121 of the epitaxial layer 120 of the even-numbered layers in the M-layer is set correspondingly to another well region 140 in the cut-off layer 130. In this way, the floating P+ regions 121 in the M-layer epitaxial layer 120 are arranged alternately left and right to achieve better charge balance. The floating P+ region 121 of the M-layer epitaxial layer 120 is used to accurately control the breakdown position of the device to avoid loss of the gate oxide layer 161. The substrate 110 is an N+ type substrate, that is, an N-type heavily doped substrate. The material of the substrate 110 includes but is not limited to semiconductor materials such as silicon, silicon carbide, and gallium nitride. The epitaxial layer 120 is an N-type epitaxial layer, that is, an N-type lightly doped epitaxial layer. The cut-off layer 130 is an N-type epitaxial layer. The material of the source metal layer 150 includes but is not limited to conductive metals such as aluminum and copper. The source metal layer 150 serves as the source of the device. The material of the drain metal layer 170 includes but is not limited to conductive metals such as aluminum and copper. The drain metal layer 170 serves as the drain of the device. The range of M can be selected from 10-16. The thickness range of one epitaxial layer 120 is 4-6um, and the thickness range of M epitaxial layers 120 is 40-60um.

[0055] In this embodiment, M layers of epitaxial layers 120 are located on the substrate 110, and M is an even number greater than 0. The cut-off layer 130 is located on the M layers of epitaxial layers 120, and a scenic area is provided in the left area and the right area of ​​the cut-off layer 130. The source metal layer 150 and the gate 160 are both located on the cut-off layer 130, and the source metal layer 150 is located on the well area 140. The gate 160 is located between the source metal layers 150, and the gate 160 covers the spacing area between the well areas 140 and a part of the well area 140. The drain metal layer 170 is located under the substrate 110. In this way, the entire super junction MOSFET device structure is realized. In the entire device, each epitaxial layer 120 is provided with a floating P+ area 121, and the floating P+ area 121 of each epitaxial layer 120 is arranged corresponding to a well area 140, and the floating P+ areas 121 of two adjacent epitaxial layers 120 are staggered. The floating P+ regions 121 in the M-layer epitaxial layer 120 are arranged alternately on the left and right to achieve better charge balance. By setting the floating P+ region 121, the breakdown position of the device can be accurately controlled, the avalanche tolerance of the device can be improved, the loss of the gate oxide layer 161 can be avoided, and the reliability and stability of the device can be improved. In addition, due to the setting of the floating P+ region 121, the drift region area in the M-layer epitaxial layer 120 is increased, the on-resistance is reduced, and the reverse recovery charge of the diode is reduced.

[0056] Next, combine Figure 1 The specific structure of the super junction MOSFET device of this embodiment is described in detail:

[0057] The left region and the right region in the stop layer 130 each have a well region 140. Figure 1 As shown, the left and right regions in the cut-off layer 130 are relative regions, such as the left region in the cut-off layer 130 is the region on the left side of the cut-off layer 130, and the right region in the cut-off layer 130 is the region on the right side of the cut-off layer 130. Each well region 140 includes: a P well region 141 (i.e., a Pwell region), an N+ contact region 142, and a P+ contact region 143. The P well region 141 is located in the cut-off layer 130, and the N+ contact region 142 and the P+ contact region 143 are located in the P well region 141. The surface of the N+ contact region 142, the surface of the P+ contact region 143, the surface of the P well region 141, and the surface of the cut-off layer 130 are located in the same horizontal plane. The N+ contact region 142 is correspondingly arranged below the gate 160 and the source metal layer 150. The P+ contact region 143 contacts the N+ contact region 142, and the P+ contact region 143 is correspondingly arranged below the source metal layer 150.

[0058] like Figure 1Taking the well region 140 in the left area of ​​the cut-off layer 130 as an example, in the well region 140 in the left area of ​​the cut-off layer 130, the P well region 141 is located in the cut-off layer 130, the N+ contact region 142 and the P+ contact region 143 are located in the P well region 141, and the surface of the N+ contact region 142, the surface of the P+ contact region 143, the surface of the P well region 141 and the surface of the cut-off layer 130 are located in the same horizontal plane. The N+ contact region 142 is correspondingly arranged under the gate 160 and the source metal layer 150. The P+ contact region 143 contacts the N+ contact region 142, that is, the P+ contact region 143 is located on the left side of the N+ contact region 142, and the P+ contact region 143 is correspondingly arranged under the source metal layer 150. It should be noted that the source metal layer 150 corresponding to the left area of ​​the cut-off layer 130 covers the left part of the P+ contact region 143 and the N+ contact region 142. The gate 160 covers the right part of the N+ contact region 142.

[0059] Similarly, in the well region 140 in the right region of the cutoff layer 130, the P well region 141 is located in the cutoff layer 130, the N+ contact region 142 and the P+ contact region 143 are located in the P well region 141, and the surface of the N+ contact region 142, the surface of the P+ contact region 143, the surface of the P well region 141 and the surface of the cutoff layer 130 are located in the same horizontal plane. The N+ contact region 142 is correspondingly arranged under the gate 160 and the source metal layer 150. The P+ contact region 143 contacts the N+ contact region 142, that is, the P+ contact region 143 is located on the right side of the N+ contact region 142, and the P+ contact region 143 is correspondingly arranged under the source metal layer 150. It should be noted that the source metal layer 150 corresponding to the right region of the cutoff layer 130 covers the right side portion of the P+ contact region 143 and the N+ contact region 142. The gate 160 covers the left side portion of the N+ contact region 142.

[0060] The device of this embodiment further includes a passivation layer 180, which is located between the gate 160 and the source metal layer 150, and the passivation layer 180 wraps the gate 160. The material of the passivation layer 180 includes but is not limited to insulating materials such as silicon nitride and silicon dioxide.

[0061] The gate 160 includes: a gate oxide layer 161 and a polysilicon gate 162. The gate oxide layer 161 is located on the cutoff layer 130, the gate oxide layer 161 is located between the source metal layer 150, and the gate oxide layer 161 covers the spacing area between the well regions 140 and a part of the well region 140. Among them, the spacing area between the well regions 140 is the area between two well regions 140. The part of the well region 140 is the area covered by the gate oxide layer 161 or the gate 160, such as in the well region 140 in the left area of ​​the cutoff layer 130, the gate 160 covers the right part of the N+ contact region 142, and in the well region 140 in the right area of ​​the cutoff layer 130, the gate 160 covers the left part of the N+ contact region 142. The material of the gate oxide layer 161 includes but is not limited to silicon dioxide. The polysilicon gate 162 is located on the gate oxide layer 161. The material of the polysilicon gate 162 is polysilicon.

[0062] In the M epitaxial layers 120, for each epitaxial layer 120, the thickness of the floating P+ region 121 of the epitaxial layer 120 is consistent with the thickness of the epitaxial layer 120. In this way, firstly, a better forward current path is ensured, and secondly, charge balance is more easily formed.

[0063] The M-layer epitaxial layer 120 includes: an epitaxial layer 120 of a first epitaxial region, an epitaxial layer 120 of a second epitaxial region, and an epitaxial layer 120 of a third epitaxial region, which are stacked in sequence from the substrate 110 to the stop layer 130, wherein the number of epitaxial layers 120 in each epitaxial region is an even number, and the M-layer epitaxial layer 120 is used to determine that an epitaxial region is a target pressure-bearing region by increasing the thickness of a floating P+ region 121 of the epitaxial layer 120 of the epitaxial region.

[0064] Specifically, Figure 2 The M=16 epitaxial layers 120 shown are stacked in sequence from the substrate 110 to the stop layer 130, i.e., from the bottom to the top of the M epitaxial layers 120, with the epitaxial layers 120 of the first epitaxial region, the epitaxial layers 120 of the second epitaxial region, and the epitaxial layers 120 of the third epitaxial region. Figure 2, the epitaxial layers 120 of the first epitaxial region are the bottom four epitaxial layers 120 of the 16 epitaxial layers 120, that is, according to the order of the M epitaxial layers 120 from bottom to top, the 1st epitaxial layer 120 to the 4th epitaxial layer 120 form the epitaxial layers 120 of the first epitaxial region. The epitaxial layers 120 of the second epitaxial region are the middle eight epitaxial layers 120 of the 16 epitaxial layers 120, that is, according to the order of the M epitaxial layers 120 from bottom to top, the 5th epitaxial layer 120 to the 12th epitaxial layer 120 form the epitaxial layers 120 of the second epitaxial region. The epitaxial layers 120 of the third epitaxial region are the top four epitaxial layers 120 of the 16 epitaxial layers 120, that is, according to the order of the M epitaxial layers 120 from bottom to top, the 13th epitaxial layer 120 to the 16th epitaxial layer 120 form the epitaxial layers 120 of the third epitaxial region.

[0065] The number of epitaxial layers 120 in each epitaxial region is an even number, indicating that the floating P+ regions 121 appear in pairs to achieve charge balance. For super junction devices, achieving charge balance is a prerequisite for ensuring that the breakdown voltage BV is sufficiently high. That is, the epitaxial layers 120 in each epitaxial region appear in groups, that is, the floating P+ regions 121 appear in pairs, and the thickness of the pairs of floating P+ regions 121 in the M layers of epitaxial layers 120 is consistent. For example, the first epitaxial layer 120 and the second epitaxial layer 120 are a group of epitaxial layers 120, the floating P+ region 121 of the first epitaxial layer 120 and the floating P+ region 121 of the second epitaxial layer 120 are a pair, and the floating P+ region 121 of the first epitaxial layer 120 and the floating P+ region 121 of the second epitaxial layer 120 are consistent in thickness. The third epitaxial layer 120 and the fourth epitaxial layer 120 form a group of epitaxial layers 120, the floating P+ region 121 of the third epitaxial layer 120 and the floating P+ region 121 of the fourth epitaxial layer 120 form a pair, the floating P+ region 121 of the third epitaxial layer 120 and the floating P+ region 121 of the fourth epitaxial layer 120 have the same thickness, and so on.

[0066] The thickness of the epitaxial layer 120 and the thickness of the floating P+ region 121 in different epitaxial regions in the M-layer epitaxial layer 120 are controlled to accurately achieve the breakdown position, as follows:

[0067] First, when the thickness of the floating P+ zone 121 in the first epitaxial region is greater than the thickness of the floating P+ zone 121 in the second epitaxial region, and the thickness of the floating P+ zone 121 in the second epitaxial region is consistent with the thickness of the floating P+ zone 121 in the third epitaxial region, the first epitaxial region is the target pressure-bearing zone, and the first epitaxial region is used to improve impact resistance.

[0068] Specifically, Figure 2As shown, the thickness of the floating P+ region 121 of the epitaxial layer 120 of the first epitaxial region is greater than the thickness of the floating P+ region 121 of the second epitaxial region, indicating that there is at least one group of first target epitaxial layers in the first epitaxial region, and the first target epitaxial layer is the epitaxial layer 120 of the first epitaxial region whose thickness of the floating P+ region 121 is greater than the thickness of the floating P+ region 121 of the second epitaxial region, and a group of first target epitaxial layers is two adjacent first target epitaxial layers forming a pair of floating P+ regions 121. Figure 2 Taking the M=16 layers of epitaxial layers 120 shown as an example, in the first epitaxial region, only the thickness of the floating P+ region 121 of the first epitaxial layer 120 and the floating P+ region 121 of the second epitaxial layer 120 is greater than the thickness of the floating P+ region 121 of the second epitaxial region. Or, only the thickness of the floating P+ region 121 of the third epitaxial layer 120 and the floating P+ region 121 of the fourth epitaxial layer 120 is greater than the thickness of the floating P+ region 121 of the second epitaxial region. Or, the thickness of the floating P+ region 121 of the first epitaxial layer 120, the floating P+ region 121 of the second epitaxial layer 120, the floating P+ region 121 of the third epitaxial layer 120, and the floating P+ region 121 of the fourth epitaxial layer 120 are all greater than the thickness of the floating P+ region 121 of the second epitaxial region.

[0069] The thickness of the floating P+ zone 121 in the second epitaxial region and the thickness of the floating P+ zone 121 in the third epitaxial region indicate that the thickness of the floating P+ zone 121 of each epitaxial layer 120 in the second epitaxial region is consistent, the thickness of the floating P+ zone 121 of each epitaxial layer 120 in the third epitaxial region is consistent, and the thickness of the floating P+ zone 121 of each epitaxial layer 120 in the second epitaxial region is consistent with the thickness of the floating P+ zone 121 of each epitaxial layer 120 in the third epitaxial region.

[0070] The first situation indicates that the floating P+ region 121 of the first epitaxial region is the floating P+ region 121 with the largest thickness among the three epitaxial regions. When the thickness of the floating P+ region 121 in the first epitaxial region is greater than that of the floating P+ region 121 in the second epitaxial region, and the thickness of the floating P+ region 121 in the second epitaxial region is consistent with that of the floating P+ region 121 in the third epitaxial region, the first epitaxial region is the target pressure-bearing region. In this way, the first epitaxial region is the highest position of the electric field, and the first epitaxial region is far away from the surface gate oxide position. When the device of this embodiment is subjected to a large stress shock, the main heat generation position is at the bottom of the device (i.e., the first epitaxial region), and the heat rise at the gate oxide at the weakest part of the device is less, and the device has a strong impact resistance. In this way, the reliability and stability of the super junction MOSFET device are improved, so that the device has better avalanche tolerance, less reverse recovery charge, lower on-resistance, and better forward characteristics.

[0071] Second, when the thickness of the floating P+ zone 121 in the second epitaxial region is greater than the thickness of the floating P+ zone 121 in the first epitaxial region, and the thickness of the floating P+ zone 121 in the first epitaxial region is consistent with the thickness of the floating P+ zone 121 in the third epitaxial region, the second epitaxial region is the target pressure-bearing region, and the second epitaxial region is used to increase the breakdown voltage.

[0072] Specifically, Figure 2 As shown, the thickness of the floating P+ region 121 in the second epitaxial region is greater than the thickness of the floating P+ region 121 in the first epitaxial region, indicating that there is at least one set of second target epitaxial layers in the second epitaxial region, and the second target epitaxial layer is the epitaxial layer 120 of the second epitaxial region whose thickness of the floating P+ region 121 is greater than the thickness of the floating P+ region 121 in the first epitaxial region, and a set of second target epitaxial layers is two adjacent layers of second target epitaxial layers forming a pair of floating P+ regions 121. Figure 2 Taking the M=16 epitaxial layers 120 shown as an example, in the second epitaxial region, only the thickness of the floating P+ region 121 of the 5th epitaxial layer 120 and the floating P+ region 121 of the 6th epitaxial layer 120 is greater than the thickness of the floating P+ region 121 of the first epitaxial region. Or, only the thickness of the floating P+ region 121 of the 7th epitaxial layer 120 and the floating P+ region 121 of the 8th epitaxial layer 120 is greater than the thickness of the floating P+ region 121 of the first epitaxial region. Or, the thickness of the floating P+ region 121 of the 5th epitaxial layer 120, the floating P+ region 121 of the 6th epitaxial layer 120, the floating P+ region 121 of the 7th epitaxial layer 120, and the floating P+ region 121 of the 8th epitaxial layer 120 are all greater than the thickness of the floating P+ region 121 of the first epitaxial region. Or, the thickness of the floating P+ zone 121 of the 5th epitaxial layer 120, the thickness of the floating P+ zone 121 of the 6th epitaxial layer 120, the thickness of the floating P+ zone 121 of the 7th epitaxial layer 120, the thickness of the floating P+ zone 121 of the 8th epitaxial layer 120, the thickness of the floating P+ zone 121 of the 9th epitaxial layer 120 and the thickness of the floating P+ zone 121 of the 10th epitaxial layer 120 are all greater than the thickness of the floating P+ zone 121 of the first epitaxial zone. Or, the thickness of the floating P+ zone 121 of the 5th epitaxial layer 120, the thickness of the floating P+ zone 121 of the 6th epitaxial layer 120, the thickness of the floating P+ zone 121 of the 7th epitaxial layer 120, the thickness of the floating P+ zone 121 of the 8th epitaxial layer 120, the thickness of the floating P+ zone 121 of the 9th epitaxial layer 120, the thickness of the floating P+ zone 121 of the 10th epitaxial layer 120, the thickness of the floating P+ zone 121 of the 11th epitaxial layer 120 and the thickness of the floating P+ zone 121 of the 12th epitaxial layer 120 are all greater than the thickness of the floating P+ zone 121 of the first epitaxial zone, and so on.

[0073] The thickness of the floating P+ zone 121 in the first epitaxial region and the thickness of the floating P+ zone 121 in the third epitaxial region indicate that the thickness of the floating P+ zone 121 of each epitaxial layer 120 in the first epitaxial region is consistent, the thickness of the floating P+ zone 121 of each epitaxial layer 120 in the third epitaxial region is consistent, and the thickness of the floating P+ zone 121 of each epitaxial layer 120 in the first epitaxial region is consistent with the thickness of the floating P+ zone 121 of each epitaxial layer 120 in the third epitaxial region.

[0074] The second situation indicates that the floating P+ region 121 of the second epitaxial region is the thickest floating P+ region 121 among the three epitaxial regions. When the thickness of the floating P+ region 121 in the second epitaxial region is greater than that of the floating P+ region 121 in the first epitaxial region, and the thickness of the floating P+ region 121 in the first epitaxial region is consistent with the thickness of the floating P+ region 121 in the third epitaxial region, the second epitaxial region is the target pressure-bearing region. In this way, the electric field is more evenly distributed, and the breakdown position is close to the middle position of the M-layer epitaxial layer 120, so that the device has better avalanche tolerance and achieves a higher breakdown voltage, which is suitable for applications with higher requirements for reverse withstand voltage and breakdown voltage. This improves the reliability and stability of the super junction MOSFET device, and makes the device have less reverse recovery charge, lower on-resistance, and better forward characteristics.

[0075] The third type is that when the thickness of the floating P+ zone 121 of the third epitaxial region is greater than the thickness of the floating P+ zone 121 of the first epitaxial region, and the thickness of the floating P+ zone 121 of the first epitaxial region is consistent with the thickness of the floating P+ zone 121 of the second epitaxial region, the third epitaxial region is the target pressure-bearing region, and the third epitaxial region is used to reduce the on-resistance.

[0076] Specifically, Figure 2 As shown, the thickness of the floating P+ region 121 of the third epitaxial region is greater than the thickness of the floating P+ region 121 of the first epitaxial region, indicating that there is at least one set of third target epitaxial layers in the third epitaxial region, and the third target epitaxial layer is the epitaxial layer 120 of the third epitaxial region whose thickness of the floating P+ region 121 is greater than the thickness of the floating P+ region 121 of the first epitaxial region, and a set of second target epitaxial layers is two adjacent third target epitaxial layers forming a pair of floating P+ regions 121. Figure 2Taking the M=16 epitaxial layers 120 shown as an example, in the third epitaxial region, only the thickness of the floating P+ region 121 of the 13th epitaxial layer 120 and the floating P+ region 121 of the 14th epitaxial layer 120 is greater than the thickness of the floating P+ region 121 of the first epitaxial region. Or, only the thickness of the floating P+ region 121 of the 15th epitaxial layer 120 and the floating P+ region 121 of the 16th epitaxial layer 120 is greater than the thickness of the floating P+ region 121 of the first epitaxial region. Or, the thickness of the floating P+ region 121 of the 13th epitaxial layer 120, the floating P+ region 121 of the 14th epitaxial layer 120, the floating P+ region 121 of the 15th epitaxial layer 120, and the floating P+ region 121 of the 16th epitaxial layer 120 are all greater than the thickness of the floating P+ region 121 of the first epitaxial region. And so on.

[0077] The thickness of the floating P+ zone 121 in the first epitaxial region and the thickness of the floating P+ zone 121 in the second epitaxial region indicate that the thickness of the floating P+ zone 121 of each epitaxial layer 120 in the first epitaxial region is consistent, the thickness of the floating P+ zone 121 of each epitaxial layer 120 in the second epitaxial region is consistent, and the thickness of the floating P+ zone 121 of each epitaxial layer 120 in the first epitaxial region is consistent with the thickness of the floating P+ zone 121 of each epitaxial layer 120 in the second epitaxial region.

[0078] The third scenario indicates that the floating P+ region 121 of the third epitaxial region is the floating P+ region 121 with the largest thickness among the three epitaxial regions. When the thickness of the floating P+ region 121 of the third epitaxial region is greater than the thickness of the floating P+ region 121 of the first epitaxial region, and the thickness of the floating P+ region 121 of the first epitaxial region is consistent with the thickness of the floating P+ region 121 of the second epitaxial region, the third epitaxial region is the target pressure-bearing region. The third epitaxial region can improve the avalanche withstand voltage performance of the device. In addition, the N-type drift region reserved on the surface of the epitaxial layer 120 and the cut-off layer 130 is larger, so that the forward on-resistance of the device will be better, which promotes the reduction of the on-resistance of the device, thereby improving the reliability and stability of the super junction MOSFET device. It can also make the device have less reverse recovery charge, lower on-resistance, and better forward characteristics.

[0079] In addition, the thickness of the floating P+ zone 121 in the target pressure-bearing area is gradually reduced, and the thickness of the floating P+ zone 121 of the smallest epitaxial layer 120 in the target pressure-bearing area is consistent with the thickness of the floating P+ zone 121 of the epitaxial layer 120 in the epitaxial area except the target pressure-bearing area.

[0080] For example, take the second case as an example, that is, Figure 2The floating P+ region 121 of the second epitaxial region shown is taken as an example of the floating P+ region 121 with the largest thickness among the three epitaxial regions. In the second epitaxial region, assuming that the thickness of the floating P+ region 121 of the 12th epitaxial layer 120 and the thickness of the floating P+ region 121 of the 11th epitaxial layer 120 are the largest thicknesses, the thickness of the floating P+ region 121 of the 12th epitaxial layer 120 and the thickness of the floating P+ region 121 of the 11th epitaxial layer 120 are both 6um. The thickness of the floating P+ region 121 of the 10th epitaxial layer 120 and the thickness of the floating P+ region 121 of the 9th epitaxial layer 120 are the second largest thicknesses, and the thickness of the floating P+ region 121 of the 10th epitaxial layer 120 and the thickness of the floating P+ region 121 of the 9th epitaxial layer 120 are both 5.5um. The thickness of the floating P+ region 121 of the 8th epitaxial layer 120 and the thickness of the floating P+ region 121 of the 7th epitaxial layer 120 are both 5um. The thickness of the floating P+ region 121 of the 6th epitaxial layer 120 and the thickness of the floating P+ region 121 of the 5th epitaxial layer 120 are the minimum thicknesses, and the thickness of the floating P+ region 121 of the 6th epitaxial layer 120 and the thickness of the floating P+ region 121 of the 5th epitaxial layer 120 are both 4um. The thickness of the floating P+ region 121 of the first epitaxial region and the thickness of the floating P+ region 121 of the third epitaxial region are both 4um.

[0081] This arrangement makes the thickness of the floating P+ region 121 in the target pressure-bearing region gradually change, which can make the electric field distribution in the target pressure-bearing region more uniform, reduce the electric field concentration in the target pressure-bearing region, and thus slightly increase the breakdown voltage.

[0082] In this embodiment, by controlling the thickness of the floating P+ region 121 in the M-layer epitaxial layer 120, the position of the device breakdown electric field is precisely controlled, so that the device has better avalanche tolerance and improves the reliability and stability of the super junction MOSFET device. In addition, compared with the traditional super junction MOSFET device structure, by setting the floating P+ region 121 in the epitaxial layer 120, the forward recovery charge of the device of this embodiment will be less. In addition, the area of ​​the N-epitaxial region (i.e., the N drift region) of this device is larger, so that the device of this embodiment has lower resistance and better forward characteristics.

[0083] The preparation process of the super junction MOSFET device of this embodiment is:

[0084] (1) Select a suitable N+ type substrate 110.

[0085] (2) If Figure 3 As shown, a first N- epitaxial layer 120 is grown on an N+ type substrate 110 .

[0086] (3) If Figure 4As shown, a silicon dioxide dielectric layer and a photoresist are deposited on the surface of the first epitaxial layer 120 , and after the photoresist is exposed, the silicon dioxide dielectric layer is etched. After etching, P+ ions are implanted to form a first floating P+ region 121 , that is, the floating P+ region 121 of the first epitaxial layer 120 .

[0087] (4) If Figure 5 As shown, a second epitaxial layer 120 is generated on the first epitaxial layer 120. In addition, a silicon dioxide dielectric layer and a photoresist are deposited on the surface of the second epitaxial layer 120. After the photoresist is exposed, the silicon dioxide dielectric layer is etched. After etching, P+ ions are implanted to form a second floating P+ region 121, that is, the floating P+ region 121 of the second epitaxial layer 120.

[0088] (5) If Figure 6 As shown, steps (3)-(4) are repeated to form M layers of epitaxial layers 120 and floating P+ regions 121 of each epitaxial layer 120. Optionally, in the process of growing M layers of epitaxial layers 120, the thickness of each epitaxial layer 120 is not exactly the same, and the thickness of most epitaxial layers 120 is designed to be around 4um, i.e., 3.8-4.2um. The thickness of a selected portion of the epitaxial layer 120 is set at 5-6um to obtain different structural characteristics. Under different epitaxial thickness settings, the device will obtain different structural advantages. In terms of process, the method of adjusting the thickness of the epitaxial layer 120 will not introduce any new costs, and only adjusting the thickness of the epitaxial layer 120 will not affect the breakdown characteristics of the device structure.

[0089] (6) Figure 7 As shown, a stop layer 130 is formed on the Mth epitaxial layer 120. A silicon dioxide dielectric layer and a photoresist are deposited on the surface of the stop layer 130. After the photoresist is exposed, the silicon dioxide dielectric layer is etched. After etching, P+ ions are implanted to form a P well region 141.

[0090] (7) Figure 8 As shown, a sidewall is formed on the silicon dioxide dielectric layer, and N+ ions are injected into the P well region 141 to form an N+ contact region 142. A silicon dioxide dielectric layer and a photoresist are deposited on the surface of the stop layer 130, and after the photoresist is exposed, the silicon dioxide dielectric layer is etched. After etching, P+ ions are injected to form a P+ contact region 143.

[0091] (9) Figure 1As shown, a gate oxide layer 161 is grown on the cut-off layer 130, and a polysilicon gate 162 is formed on the gate oxide layer 161, thereby obtaining the gate 160. A passivation layer 180 is formed on the cut-off layer 130 and the gate 160. A hole is punched in the passivation layer 180 to form a source metal layer 150. Among them, the gate oxide layer 161 is located between the source metal layers 150, and the gate oxide layer 161 covers the spacing area between the well regions 140 and a part of the well region 140. The polysilicon gate 162 is located on the gate oxide layer 161, and the width of the polysilicon gate 162 and the gate oxide layer 161 is consistent. A drain metal layer 170 is formed under the substrate 110.

[0092] In this embodiment, in the process of preparing the super junction MOSFET device, without additional processes and costs, the thickness of the floating P+ region 121 of the selected epitaxial layer 120 is directly adjusted, which can quickly and conveniently realize the precise control of the position of the device breakdown electric field, so that the device has better avalanche tolerance and improves the reliability and stability of the super junction MOSFET device. In addition, compared with the traditional super junction MOSFET device structure, by setting the floating P+ region 121 in the epitaxial layer 120, the forward recovery charge of the device of this embodiment will be less. In addition, the area of ​​the N-epitaxial region (i.e., the N drift region) of the device is larger, so that the device of this embodiment has a lower resistance and better forward characteristics.

[0093] Below, three examples are used to show the device structure manufactured by the preparation method of this embodiment, as well as the thickness process and device advantages of the floating P+ region 121 of the epitaxial layer 120 of the device:

[0094] Example 1, Example 2 and Example 3 are all super MOSFET devices with M=16 epitaxial layers 120 manufactured by the preparation method of this embodiment. The three device structures differ only in the thickness of the selected epitaxial layer 120, and the other components are the same. Therefore, these three examples are compared.

[0095] Example 1

[0096] Example 1 shows Figure 2 The first situation of the M-layer epitaxial layer 120 is shown. Fig. 9 As shown, among the 16 epitaxial layers 120, the thickness of the floating P+ region 121 of the first epitaxial layer 120 and the second epitaxial layer 120 is 5um, and the thickness of the floating P+ region 121 of the other epitaxial layers 120 is 4um. The breakdown voltage of the device structure of Example 1 is measured by simulation software to be 707V. Fig.10 As shown, the electric field strength of the floating P+ region 121 of the first epitaxial layer 120 and the second epitaxial layer 120 is red, indicating that the electric field strength of the floating P+ region 121 of the first epitaxial layer 120 and the second epitaxial layer 120 is large. Fig.10 , Fig.12 and Fig.14 In the figure, the horizontal axis represents the width of each layer of the device, and the vertical axis represents the thickness of each layer of the device. The more the area in the figure is red, the greater the electric field strength. The more the area in the figure is blue, the smaller the electric field strength.

[0097] The highest electric field position of the device of Example 1 is below the device, far from the surface gate oxide layer 161. Therefore, when the device is subjected to a large stress shock, the main heat generation position is at the bottom of the device, and the heat rise at the gate oxide layer 161, the weakest part of the device, is less, making the device strong in impact resistance. In addition, the bottom of the epitaxial layer of the device of Example 1 uses a larger epitaxial width, which can control the highest electric field position to the bottom of the device epitaxy. When breakdown occurs, the heat generation position is close to the bottom of the chip, and it is easier to dissipate heat through the metal at the bottom. In this way, in some extreme application conditions, such as single pulse avalanche withstand (EAS), the temperature of the gate oxide layer 161 at the weaker position of the entire chip is lower, thereby improving the single pulse avalanche withstand of the chip and improving the reliability of the chip.

[0098] Example 2

[0099] Example 2 shows Figure 2 The second situation of the M-layer epitaxial layer 120 is shown. Fig.11 As shown, among the 16 epitaxial layers 120, the thickness of the floating P+ region 121 of the 9th epitaxial layer 120, the 10th epitaxial layer 120, the 11th epitaxial layer 120 and the 12th epitaxial layer 120 is 5um, and the thickness of the floating P+ region 121 of the other epitaxial layers 120 is 4um. The breakdown voltage of the device structure of Example 2 is measured by simulation software to be 713V, and the breakdown voltage of the device of Example 2 is the highest breakdown voltage among the three examples. Fig.12 As shown, the electric field strength of the floating P+ region 121 of the 9th epitaxial layer 120, the 10th epitaxial layer 120, the 11th epitaxial layer 120 and the 12th epitaxial layer 120 is redder, indicating that the electric field strength of the floating P+ region 121 of the 9th epitaxial layer 120, the 10th epitaxial layer 120, the 11th epitaxial layer 120 and the 12th epitaxial layer 120 is larger.

[0100] from Fig.12It can be seen that the electric field distribution in the epitaxial layer 120 is relatively uniform, and the breakdown position is close to the middle of the device. Therefore, the breakdown voltage of the structure of Example 2 is relatively high, and it is suitable for applications with high requirements for reverse withstand voltage and breakdown voltage. The middle part of the epitaxial layer of the Example 2 device uses a relatively large epitaxial width, the electric field is concentrated in the middle of the epitaxial layer, and the electric field in the middle is relatively more uniform, so that a higher breakdown voltage BV can be obtained. It can also be verified by simulation that the reverse leakage under reverse cutoff conditions will also be lower, which makes the example device have lower losses in cutoff application conditions and is more suitable for application in long-term shutdown scenarios.

[0101] Example 3

[0102] Example 3 shows Figure 2 The third situation of the M-layer epitaxial layer 120 is shown. Fig.13 As shown, among the 16 epitaxial layers 120, the thickness of the floating P+ region 121 of the 15th epitaxial layer 120 and the 16th epitaxial layer 120 is 5um, and the thickness of the floating P+ region 121 of the other epitaxial layers 120 is 4um. The breakdown voltage of the device structure of Example 3 is measured by simulation software to be 702V. Fig.14 As shown, the electric field intensity of the floating P+ region 121 of the 15th epitaxial layer 120 and the 16th epitaxial layer 120 is red, indicating that the electric field intensity of the floating P+ region 121 of the 15th epitaxial layer 120 and the 16th epitaxial layer 120 is relatively large.

[0103] The top of the epitaxial layer of the device in Example 3 has a larger epitaxial width, that is, the N-type drift region reserved on the surface of the M-layer epitaxial layer 120 is larger, so that the electric field is located at the top of the device, thereby making the forward conduction resistance of the device in Example 3 superior to that of the devices in the first two examples. The device will obtain better conduction characteristics, with lower resistance during forward conduction, and is suitable for long-term open working environments. The conduction loss under long-term open working conditions is lower, and the heat generation of the device will be reduced, thereby reducing the operating cost.

[0104] Embodiment 2

[0105] Based on the same inventive concept, the second embodiment of the present invention also provides a method for preparing a super junction MOSFET device, such as Fig.15 As shown, for preparing the super junction MOSFET device as described in Example 1, the method includes:

[0106] S201, forming M epitaxial layers on the substrate;

[0107] S202, forming a cutoff layer on the M epitaxial layer;

[0108] S203, providing a well region in the left and right regions of the cut-off layer respectively;

[0109] S204, forming a source metal layer and a gate on the cutoff layer, wherein the source metal layer is located on the well regions, the gate is located between the source metal layers, and the gate covers the spacing regions between the well regions and a part of the well regions;

[0110] S205, forming a drain metal layer under the substrate;

[0111] Each epitaxial layer is provided with a floating P+ region, and the floating P+ region of each epitaxial layer is arranged corresponding to a well region. The floating P+ regions of two adjacent epitaxial layers are staggered, and M is an even number greater than 0.

[0112] Since the preparation method of the super junction MOSFET device introduced in this embodiment is the preparation method adopted for implementing the super junction MOSFET device in the first embodiment of the present application, based on the super junction MOSFET device introduced in the first embodiment of the present application, the technical personnel of the field can understand the specific implementation method of the preparation method of the super junction MOSFET device of the present embodiment and its various variations, so how the preparation method of the super junction MOSFET device implements the super junction MOSFET device in the first embodiment of the present application is not introduced in detail here. As long as the technical personnel of the field implement the preparation method adopted by the super junction MOSFET device in the first embodiment of the present application, it belongs to the scope of protection of the present application.

[0113] Those skilled in the art will appreciate that, although the preferred embodiments of the present invention have been described, those skilled in the art, once informed of the basic creative concept, may make additional changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0114] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A super junction MOSFET device, characterized in that: include: Substrate, M epitaxial layer, cut-off layer, well region, source metal layer, gate and drain metal layer; The M epitaxial layer is located on the substrate; The cut-off layer is located on the M epitaxial layer; The well region is respectively provided in the left and right regions of the cut-off layer; The source metal layer and the gate are both located on the cutoff layer, the source metal layer is located on the well region, the gate is located between the source metal layers, and the gate covers the spacing region between the well regions and a part of the well region, and the drain metal layer is located under the substrate; Each epitaxial layer has only one floating P+ region, and the floating P+ region of each epitaxial layer is arranged corresponding to one well region, and the floating P+ regions of two adjacent epitaxial layers are arranged alternately, and M is an even number greater than 0; The floating P+ region of the epitaxial layer of the odd-numbered layers in the M layer is arranged correspondingly to a well region in the cutoff layer, and the floating P+ region of the epitaxial layer of the even-numbered layers in the M layer is arranged correspondingly to another well region in the cutoff layer.

2. The super junction MOSFET device according to claim 1, characterized in that: The M layers of epitaxial layers include: an epitaxial layer of a first epitaxial region, an epitaxial layer of a second epitaxial region, and an epitaxial layer of a third epitaxial region, which are stacked in sequence from the substrate to the cut-off layer, wherein the number of epitaxial layers in each epitaxial region is an even number, and the M layers of epitaxial layers are used to determine that an epitaxial region is a target pressure-bearing region by increasing the thickness of a floating P+ region of the epitaxial layer of the epitaxial region.

3. The super junction MOSFET device according to claim 2, characterized in that: When the thickness of the floating P+ zone of the first epitaxial region is greater than the thickness of the floating P+ zone of the second epitaxial region, and the thickness of the floating P+ zone of the second epitaxial region is consistent with the thickness of the floating P+ zone of the third epitaxial region, the first epitaxial region is the target pressure-bearing region, and the first epitaxial region is used to improve impact resistance.

4. The super junction MOSFET device according to claim 2, characterized in that: When the thickness of the floating P+ zone of the second epitaxial region is greater than the thickness of the floating P+ zone of the first epitaxial region, and the thickness of the floating P+ zone of the first epitaxial region is consistent with the thickness of the floating P+ zone of the third epitaxial region, the second epitaxial region is the target pressure-bearing region, and the second epitaxial region is used to increase the breakdown voltage.

5. The super junction MOSFET device according to claim 2, characterized in that: When the thickness of the floating P+ zone in the third epitaxial region is greater than the thickness of the floating P+ zone in the first epitaxial region, and the thickness of the floating P+ zone in the first epitaxial region is consistent with the thickness of the floating P+ zone in the second epitaxial region, the third epitaxial region is the target pressure-bearing region, and the third epitaxial region is used to reduce the on-resistance.

6. The super junction MOSFET device according to claim 2, characterized in that: The thickness of the floating P+ zone in the target pressure-bearing area is gradually reduced, and the thickness of the floating P+ zone of the smallest epitaxial layer in the target pressure-bearing area is consistent with the thickness of the floating P+ zone of the epitaxial layer of the epitaxial area other than the target pressure-bearing area.

7. The super junction MOSFET device according to claim 1, characterized in that: In each epitaxial layer, the thickness of the floating P+ region of the epitaxial layer is consistent with the thickness of the epitaxial layer.

8. The super junction MOSFET device according to claim 1, characterized in that: The well region includes: a P well region, an N+ contact region and a P+ contact region; The P-well region is located in the cut-off layer, the N+ contact region and the P+ contact region are located in the P-well region, and the surface of the N+ contact region, the surface of the P+ contact region, the surface of the P-well region and the surface of the cut-off layer are located in the same horizontal plane; The N+ contact region is correspondingly arranged under the gate and the source metal layer; The P+ contact region contacts the N+ contact region, and the P+ contact region is correspondingly arranged under the source metal layer.

9. The super junction MOSFET device according to claim 1, characterized in that: Also includes: A passivation layer, wherein the passivation layer is located between the gate and the source metal layer, and the passivation layer wraps the gate; The gate comprises: a gate oxide layer and a polysilicon gate; The gate oxide layer is located on the cut-off layer, the gate oxide layer is located between the source metal layers, and the gate oxide layer covers the spacing area between the well regions and a part of the well region; The polysilicon gate is located on the gate oxide layer.

10. A method for preparing a super junction MOSFET device, characterized in that: For preparing a super junction MOSFET device according to any one of claims 1 to 9, the method comprises: forming M epitaxial layers on the substrate; forming a cut-off layer on the M epitaxial layer; A well region is respectively provided in the left and right regions in the cut-off layer; Forming a source metal layer and a gate on the cutoff layer, wherein the source metal layer is located on the well region, the gate is located between the source metal layers, and the gate covers the spacing region between the well regions and a part of the well region; forming a drain metal layer under the substrate; Each epitaxial layer is provided with a floating P+ region, and the floating P+ region of each epitaxial layer is arranged corresponding to a well region. The floating P+ regions of two adjacent epitaxial layers are staggered, and M is an even number greater than 0.

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