Integrated communication system channel test system and method based on software radio architecture
By adopting a channel testing system based on software radio architecture in the integrated communication system, using upper computer testing software and hardware abstraction layer equipment to generate and parse test data packets, the problem of lack of effective means for channel testing between multiple hardware modules is solved, and the more Efficient channel debugging and integration efficiency.
Patent Information
- Application Number
- CN202411642580.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-18
- Publication Date
- 2025-02-18
AI Technical Summary
In the existing integrated communication system, the connectivity test between multiple hardware modules connected through the backplane bus lacks effective means and methods, resulting in large channel debugging time and labor overhead and low integration efficiency.
Adopt a comprehensive communication system channel testing system based on software radio architecture, which includes a comprehensive communication system hardware platform and computer testing software, through a general channel module, a security and confidentiality module, a general control module, a general switching module, a general information processing module and a general The combination of storage modules realizes the testing of channels between multiple hardware modules. The upper computer testing software is connected to the general control module, generates and sends test data packets, parses and sends them through the hardware abstraction layer device to the target hardware module, and receives and checks the response data packets to determine whether the channel is normal.
The time and labor overhead of channel debugging of integrated communication system are shortened, the integration efficiency of integrated communication system is improved, and an effective channel testing method between multiple hardware modules is provided.
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Figure CN119484370A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of wireless communication and software radio, and in particular to a comprehensive communication system channel testing system and method based on software radio architecture. Background Art
[0002] Software radio is a wireless communication technology that uses modern software to manipulate and control traditional pure hardware circuits. It transfers radio functions traditionally implemented in hardware to software execution. Its frequency band, air interface protocol and functions can be upgraded through software downloads and updates without completely replacing the hardware. In the field of communications, software radio technology can overcome the tight coupling between communication equipment software and hardware by building a universal and open hardware platform, effectively solving the shortcomings of a wide variety of communication system hardware platforms, single functions, and poor interoperability, achieving cross-domain communications, reducing the types of equipment, and reducing production and maintenance costs. It represents the future development direction of communication systems.
[0003] Existing integrated communication systems mostly use multiple hardware modules connected through a backplane bus, and each module implements different functions. How to test the connectivity between hardware modules on the hardware backplane becomes a problem. In an integrated communication system implemented using a software radio architecture, all hardware and software modules comply with software radio related standard specifications. Therefore, an integrated communication system using a software radio architecture provides a feasible way and means to implement channel testing between modules. Summary of the invention
[0004] The object of the present invention is to provide a comprehensive communication system channel testing system and method which can shorten the time and manpower cost of comprehensive communication system channel debugging and improve the integration efficiency of the comprehensive communication system.
[0005] The technical solution to achieve the purpose of the present invention is: an integrated communication system channel test system based on software radio architecture, including an integrated communication system hardware platform and a host computer test software, wherein the integrated communication system hardware platform is composed of a universal channel module, a security module, a universal control module, a universal switching module, a universal information processing module, and a universal storage module connected by a backplane module bus, and the host computer test software is connected to the universal control module, wherein:
[0006] The universal channel module is connected to the analog RF front end of the integrated communication system, and includes RF front end, RF control, and intermediate frequency processing functions to achieve unified processing of RF transceiver signals of the communication system;
[0007] The security module decrypts the encrypted data received by the communication channel module, sends it to the general information processing module for processing via the general exchange module, and encrypts the data to be sent to the general channel module, and sends it via the radio frequency front end;
[0008] The general control module implements the system's hardware health management, business management, resource scheduling, waveform deployment and control of the reconstruction process;
[0009] The universal switching module realizes the data exchange and interconnection between the hardware modules of the communication system and the synchronization of the clock and the reference frequency;
[0010] The general information processing module processes the channel baseband signal;
[0011] The universal storage module implements the storage of data collected during the system communication service process.
[0012] Furthermore, the universal control module is provided with a software platform, which includes an operating system, a transmission mechanism, a core framework, and a hardware abstraction layer device running in order from bottom to top, wherein:
[0013] The operating system runs on the hardware module and provides hardware device driver, memory management, process management, real-time task scheduling, and multi-threading support functions for the software platform;
[0014] The transmission mechanism runs on the operating system and provides a standard communication method and interface for the interoperability of software components running on the same or different programmable devices;
[0015] The core framework runs on the basis of the operating system and transmission mechanism, provides unified software and hardware management and file system management functions for the software platform, and provides standard methods and interfaces for the deployment, operation and configuration of application software on programmable devices;
[0016] The hardware abstraction layer device runs on the basis of the core framework, is used to receive host computer test commands and test data packets, call the underlying hardware driver to send the data packets to the corresponding hardware module, and the host computer test software and the hardware abstraction layer device are connected through a transmission mechanism.
[0017] Furthermore, each hardware module of the integrated communication system hardware platform has a different logical address, and the target hardware module to which the data packet is sent is determined according to the logical address.
[0018] Furthermore, the channel test system is completed by sending a test data packet to the integrated communication system hardware platform through the host computer test software, the front part of the test data packet is the logical address of the destination hardware module to which the data packet is sent, and the back part is the test protocol data of the test data packet.
[0019] Furthermore, the general control module is provided with a common buffer for storing system test data packets.
[0020] Furthermore, the general information processing module and the general storage module are expanded to multiple modules according to system requirements.
[0021] Furthermore, the hardware abstraction layer device is deployed on the general control module, or on other hardware modules of the system, and the deployed hardware modules must meet the following conditions:
[0022] The hardware module is provided with a software radio platform including an operating system, a transmission mechanism, and a core framework;
[0023] The hardware module is provided with an external hardware interface for connecting to the host computer test software.
[0024] A method for testing a channel of an integrated communication system based on a software radio architecture, the method is based on the integrated communication system channel testing system based on the software radio architecture, and the method comprises the following steps:
[0025] Step 1: The integrated communication system is powered on and relevant initialization work is completed, and the host computer test software is started;
[0026] Step 2, the host computer test software connects to the hardware abstraction layer device of the general control module;
[0027] Step 3: The host computer test software generates a test data packet for the target hardware module to be tested and sends it to the hardware abstraction layer device of the general control module;
[0028] Step 4: The hardware abstraction layer device parses the test data packet, determines the target hardware module of the data packet according to the logical address contained in the data packet, and calls the target hardware module interface function to send the test data packet to the target hardware module;
[0029] Step 5: The target hardware module receives the test data packet and generates a response data packet according to the test protocol, and sends the response data packet to the public buffer of the general control module;
[0030] Step 6: The hardware abstraction layer device of the general control module reads the target hardware module response data packet from the public buffer and sends it to the host computer test software;
[0031] Step 7: The host computer test software receives the response data packet and checks the data packet based on the test protocol to determine whether the channel between the system general control module and the target hardware module is normal.
[0032] Compared with the prior art, the present invention has the following significant advantages: (1) It proposes a testing system and a testing method for channels between multiple hardware modules based on a software radio architecture, which solves the problem of lack of effective means and methods for connectivity testing between multiple hardware modules connected through a backplane bus in an integrated communication system; (2) It shortens the time and manpower expenditure for debugging related channels in the integrated communication system, thereby improving the integration efficiency of the integrated communication system. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] Figure 1 It is a structural schematic diagram of the integrated communication system channel testing system based on software radio architecture of the present invention.
[0034] Figure 2 It is a structural diagram of the software platform in the universal control module of the present invention.
[0035] Figure 3 The present invention is a flowchart of a method for testing a channel of an integrated communication system based on a software radio architecture.
[0036] Figure 4 It is a structural schematic diagram of the host computer sending a test data packet in the present invention. DETAILED DESCRIPTION
[0037] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.
[0038] like Figure 1 As shown, the present invention is an integrated communication system channel test system based on software radio architecture, including an integrated communication system hardware platform and host computer test software, wherein the integrated communication system hardware platform is formed by connecting a universal channel module, a security and confidentiality module, a universal control module, a universal switching module, a universal information processing module, and a universal storage module through a backplane module bus, and the host computer test software is connected to the universal control module, wherein:
[0039] The universal channel module is connected to the analog RF front end of the integrated communication system, and includes RF front end, RF control, and intermediate frequency processing functions to achieve unified processing of RF transceiver signals of the communication system;
[0040] The security module decrypts the encrypted data received by the communication channel module, sends it to the general information processing module for processing via the general exchange module, and encrypts the data to be sent to the general channel module, and sends it via the radio frequency front end;
[0041] The general control module implements the system's hardware health management, business management, resource scheduling, waveform deployment and control of the reconstruction process;
[0042] The universal switching module realizes the data exchange and interconnection between the hardware modules of the communication system and the synchronization of the clock and the reference frequency;
[0043] The general information processing module processes the channel baseband signal;
[0044] The universal storage module implements the storage of data collected during the system communication service process.
[0045] like Figure 2 As shown, the general control module is provided with a software platform, which includes an operating system, a transmission mechanism, a core framework, and a hardware abstraction layer device running in sequence from bottom to top, wherein:
[0046] The operating system runs on the hardware module and provides hardware device driver, memory management, process management, real-time task scheduling, and multi-threading support functions for the software platform;
[0047] The transmission mechanism runs on the operating system and provides a standard communication method and interface for the interoperability of software components running on the same or different programmable devices;
[0048] The core framework runs on the basis of the operating system and transmission mechanism, provides unified software and hardware management and file system management functions for the software platform, and provides standard methods and interfaces for the deployment, operation and configuration of application software on programmable devices;
[0049] The hardware abstraction layer device runs on the basis of the core framework, is used to receive host computer test commands and test data packets, call the underlying hardware driver to send the data packets to the corresponding hardware module, and the host computer test software and the hardware abstraction layer device are connected through a transmission mechanism.
[0050] As a specific example, each hardware module of the integrated communication system hardware platform has a different logical address, and the target hardware module to which the data packet is sent is determined according to the logical address.
[0051] As a specific example, the channel test system is completed by sending a test data packet to the integrated communication system hardware platform through the host computer test software. The front part of the test data packet is the logical address of the destination hardware module to which the data packet is sent, and the back part is the test protocol data of the test data packet.
[0052] As a specific example, the general control module is provided with a public buffer for storing system test data packets.
[0053] As a specific example, the general information processing module and the general storage module can be expanded into multiple modules according to the actual waveform loading and business data storage requirements of the system.
[0054] As a specific example, the hardware abstraction layer device is not limited to being deployed on the general control module, but can be deployed on other hardware modules of the system. The deployed hardware modules must meet the following conditions:
[0055] The hardware module is provided with a software radio platform including an operating system, a transmission mechanism, and a core framework;
[0056] The hardware module is provided with an external hardware interface for connecting to the host computer test software.
[0057] like Figure 3 As shown, a comprehensive communication system channel testing method based on software radio architecture includes the following steps:
[0058] Step 1: The integrated communication system is powered on and relevant initialization work is completed, and the host computer test software is started;
[0059] Step 2, the host computer test software connects to the hardware abstraction layer device of the general control module;
[0060] Step 3: The host computer test software generates a test data packet for the target hardware module to be tested and sends it to the hardware abstraction layer device of the general control module;
[0061] Step 4: The hardware abstraction layer device parses the test data packet, determines the target hardware module of the data packet according to the logical address contained in the data packet, and calls the target hardware module interface function to send the test data packet to the target hardware module;
[0062] Step 5: The target hardware module receives the test data packet and generates a response data packet according to the test protocol, and sends the response data packet to the public buffer of the general control module;
[0063] Step 6: The hardware abstraction layer device of the general control module reads the target hardware module response data packet from the public buffer and sends it to the host computer test software;
[0064] Step 7: The host computer test software receives the response data packet and checks the data packet based on the test protocol to determine whether the channel between the system general control module and the target hardware module is normal.
[0065] Example
[0066] like Figure 1 As shown, this embodiment provides an integrated communication system channel test system based on software radio architecture, including an integrated communication system hardware platform and host computer test software, wherein the integrated communication system hardware platform is composed of a universal channel module, a security and confidentiality module, a universal control module, a universal switching module, a universal information processing module, and a universal storage module connected through a backplane module bus, and the host computer test software is connected to the universal control module.
[0067] like Figure 3 As shown, the integrated communication system channel testing method based on software radio architecture provided in this embodiment includes the following steps:
[0068] Step 1: The integrated communication system is powered on and relevant initialization work is completed. The host computer test software is started. The initialization work includes initializing relevant hardware modules, configuring the addresses of various hardware modules, starting the software radio platform, etc.
[0069] Step 2, the host computer test software connects to the hardware abstraction layer device of the universal control module. In this embodiment, the host computer software connects to the hardware abstraction layer device through the external Ethernet port set on the universal control module through the hardware abstraction layer device IP address + port number;
[0070] Step 3: The host computer test software generates a test data packet for the target hardware module to be tested and sends it to the hardware abstraction layer device of the general control module, such as Figure 4 As shown, the front part of the data packet is the logical address of the destination hardware module to which the data packet is sent, and the back part is the data packet content;
[0071] The hardware modules on the backplane module have different logical addresses. The module to which the data packet is sent is determined according to the logical address. Table 1 shows the logical addresses corresponding to the modules used in this embodiment.
[0072] Table 1 Logical addresses of target hardware modules
[0073]
[0074] Step 4: The hardware abstraction layer device parses the test data packet in the write function, determines the target hardware module of the data packet according to the logical address contained in the data packet, and calls the target hardware module interface function to send the test data packet to the target hardware module. In this embodiment, the hardware abstraction layer device write function is:
[0075] Mhal_Write(unsigned char*message,UINT16 length)
[0076] Where message is the data packet generated in step 3 containing the logical address information of the target hardware module, and length is the length of the data packet;
[0077] Step 5: The target hardware module receives the test data packet and generates a response data packet according to the test protocol, and sends the response data packet to the public buffer of the general control module;
[0078] The test protocol is formulated when each module software is implemented, that is, the unified regulations for sending and receiving related data packets between two hardware modules. In this embodiment, a channel test is performed between the general control module and the general information processing module, wherein the general control module sends two test data packets in the following format to the general information processing module:
[0079] Test data packet 1: 00A2, 0011, 0022, 0033, 0044
[0080] Test data packet 2: 00A2, 0404, 0303, 0202, 0101
[0081] After receiving the two packets of data, the general information processing module sends two response data packets in the following format to the public buffer of the general control module:
[0082] Response packet 1: 00A0, 00FF, 00EE, 00DD, 00CC
[0083] Response data packet 2: 00A0, 0C0C, 0D0D, 0E0E, 0F0F;
[0084] Step 6: The hardware abstraction layer device of the general control module reads the target hardware module response data packet from the public buffer and sends it to the host computer test software, as follows:
[0085] Start the public buffer read thread in the hardware abstraction layer device. When data is detected in the public buffer, the data read thread will transparently transmit the data to the host computer test software. The format of the hardware abstraction layer device reading response data packet function is:
[0086] MHAL_Read(unsigned char*message)
[0087] The read response data packet is located in message.
[0088] Step 7: The host computer test software receives the response data packet and checks the data packet based on the test protocol to determine whether the channel between the system general control module and the target hardware module is normal;
[0089] The local database of the host computer test software stores the preset response data packet format of each hardware module. When executing a module test, the received data packet is compared with the preset response packet to determine whether the tested channel is normal.
[0090] The present invention and its implementation methods are described schematically above, and the description is not restrictive. The drawings show only one implementation method of the present invention, and the actual structure and method are not limited thereto. Therefore, if a person skilled in the art is inspired by it and, without departing from the purpose of the invention, designs a structure, method flow and embodiment similar to the scheme without creativity, they shall all fall within the protection scope of the present invention.
Claims
1. A comprehensive communication system channel test system based on software radio architecture, characterized in that: It includes an integrated communication system hardware platform and host computer test software, wherein the integrated communication system hardware platform is formed by connecting a general channel module, a security and confidentiality module, a general control module, a general switching module, a general information processing module, and a general storage module through a backplane module bus, and the host computer test software is connected to the general control module, wherein: The universal channel module is connected to the analog RF front end of the integrated communication system, and includes RF front end, RF control, and intermediate frequency processing functions to achieve unified processing of RF transceiver signals of the communication system; The security module decrypts the encrypted data received by the communication channel module, sends it to the general information processing module for processing via the general exchange module, and encrypts the data to be sent to the general channel module, and sends it via the radio frequency front end; The general control module implements the system's hardware health management, business management, resource scheduling, waveform deployment and control of the reconstruction process; The universal switching module realizes the data exchange and interconnection between the hardware modules of the communication system and the synchronization of the clock and the reference frequency; The general information processing module processes the channel baseband signal; The universal storage module implements the storage of data collected during the system communication service process.
2. The integrated communication system channel test system based on software radio architecture according to claim 1, characterized in that: The universal control module is provided with a software platform, which includes an operating system, a transmission mechanism, a core framework, and a hardware abstraction layer device running in order from bottom to top, wherein: The operating system runs on the hardware module and provides hardware device driver, memory management, process management, real-time task scheduling, and multi-threading support functions for the software platform; The transmission mechanism runs on the operating system and provides a standard communication method and interface for the interoperability of software components running on the same or different programmable devices; The core framework runs on the basis of the operating system and transmission mechanism, provides unified software and hardware management and file system management functions for the software platform, and provides standard methods and interfaces for the deployment, operation and configuration of application software on programmable devices; The hardware abstraction layer device runs on the basis of the core framework, is used to receive host computer test commands and test data packets, call the underlying hardware driver to send the data packets to the corresponding hardware module, and the host computer test software and the hardware abstraction layer device are connected through a transmission mechanism.
3. The integrated communication system channel test system based on software radio architecture according to claim 1, characterized in that: Each hardware module of the integrated communication system hardware platform has a different logical address, and the target hardware module to which the data packet is sent is determined according to the logical address.
4. The integrated communication system channel test system based on software radio architecture according to claim 1, characterized in that: The channel test system is completed by sending a test data packet to the integrated communication system hardware platform through the host computer test software. The front part of the test data packet is the logical address of the destination hardware module to which the data packet is sent, and the back part is the test protocol data of the test data packet.
5. The integrated communication system channel test system based on software radio architecture according to claim 1, characterized in that: The general control module is provided with a public buffer for storing system test data packets.
6. The integrated communication system channel test system based on software radio architecture according to claim 1, characterized in that: The general information processing module and the general storage module are expanded to multiple modules according to system requirements.
7. The integrated communication system channel test system based on software radio architecture according to claim 2, characterized in that: The hardware abstraction layer device is deployed on the general control module, or on other hardware modules of the system. The deployed hardware modules must meet the following conditions: The hardware module is provided with a software radio platform including an operating system, a transmission mechanism, and a core framework; The hardware module is provided with an external hardware interface for connecting to the host computer test software.
8. A method for testing a channel of an integrated communication system based on a software radio architecture, characterized in that: The method is based on the integrated communication system channel test system based on software radio architecture according to any one of claims 1 to 7, and the method comprises the following steps: Step 1: The integrated communication system is powered on and relevant initialization work is completed, and the host computer test software is started; Step 2, the host computer test software connects to the hardware abstraction layer device of the general control module; Step 3: The host computer test software generates a test data packet for the target hardware module to be tested and sends it to the hardware abstraction layer device of the general control module; Step 4: The hardware abstraction layer device parses the test data packet, determines the target hardware module of the data packet according to the logical address contained in the data packet, and calls the target hardware module interface function to send the test data packet to the target hardware module; Step 5: The target hardware module receives the test data packet and generates a response data packet according to the test protocol, and sends the response data packet to the public buffer of the general control module; Step 6: The hardware abstraction layer device of the general control module reads the target hardware module response data packet from the public buffer and sends it to the host computer test software; Step 7: The host computer test software receives the response data packet and checks the data packet based on the test protocol to determine whether the channel between the system general control module and the target hardware module is normal.
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