Method of manufacturing display device

Abstract

In a method of manufacturing a display device, the method includes positioning a substrate; forming a functional layer on the substrate; forming a mask including an opening on the functional layer; radiating pulsed light including a plurality of pulses through the opening of the mask; and removing the functional layer radiated with the pulsed light.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0105131 filed in the Korean Intellectual Property Office on August 10, 2023, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] Aspects of one or more embodiments are directed to a method of manufacturing a display device. Background Art

[0004] The display device visually displays data. The display device displays images using light emitting diodes. The use of display devices has become more diverse, and various designs have been tried to improve the quality of display devices.

[0005] The above information disclosed in this Background section is only for enhancement of understanding of the background technology and therefore the information discussed in this Background section does not necessarily constitute prior art. Summary of the invention

[0006] Aspects of one or more embodiments are directed to a method of manufacturing a display device.

[0007] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the embodiments presented in the disclosure.

[0008] According to some embodiments of the present disclosure, a method for manufacturing a display device includes: positioning a substrate; forming a functional layer on the substrate; forming a mask including an opening on the functional layer; radiating pulsed light including multiple pulses through the opening of the mask; and removing the functional layer radiated with the pulsed light.

[0009] According to some embodiments, the method may further include: after positioning the substrate, forming a pixel defining layer including a plurality of openings on the substrate, the pixel electrodes being located in the plurality of openings.

[0010] According to some embodiments, the mask may include a plurality of openings, and the mask may be formed such that the plurality of openings of the mask are positioned on a region in which the pixel defining layer is located.

[0011] According to some embodiments, the functional layer irradiated with the pulse light may be at least a portion of the functional layer on the pixel defining layer.

[0012] According to some embodiments, forming the functional layer on the substrate may further include: forming a lower functional layer on the pixel electrode and the pixel defining layer; and forming an upper functional layer on the lower functional layer.

[0013] According to some embodiments, the lower functional layer may include at least one of a hole injection layer and a hole transport layer.

[0014] According to some embodiments, the upper functional layer may include at least one of an electron injection layer and an electron transport layer.

[0015] According to some embodiments, the method may further include forming an emission layer in the opening of the pixel defining layer between forming the lower functional layer and forming the upper functional layer.

[0016] According to some embodiments, a size of the opening of the mask may be smaller than a size of a region in which the pixel defining layer is located.

[0017] According to some embodiments, the pulsed light may be emitted from a flash lamp.

[0018] According to some embodiments, the pulse light may be light having a wavelength band of ultraviolet light, visible light, or infrared light.

[0019] According to some embodiments, the method may further include forming a light absorbing layer on the pixel defining layer.

[0020] According to some embodiments, the light absorbing layer may contact an upper surface of the pixel defining layer.

[0021] According to some embodiments, a size of the light absorbing layer may be smaller than a size of a region in which the pixel defining layer is located.

[0022] According to some embodiments, the light absorbing layer may include molybdenum (Mo) or aluminum (Al).

[0023] According to some embodiments, the method may further include exhausting a residue of the removed portion of the functional layer through an opening of the chamber in which the substrate is located.

[0024] According to some embodiments, the method may further include forming a transparent anti-deposition plate under the mask.

[0025] According to some embodiments, the method may further include collecting and discharging residues of the removed portion of the functional layer onto a transparent anti-deposition plate.

[0026] According to some embodiments of the present disclosure, a method for manufacturing a display device includes: positioning a substrate; forming a pixel defining layer including an opening on the substrate, wherein a pixel electrode is located in the opening; forming a functional layer on the pixel electrode and the pixel defining layer; forming a mask including an opening, such that the opening of the mask is positioned in a region in which the pixel defining layer is located; radiating light emitted from a flash lamp through the opening of the mask; and removing the functional layer on the pixel defining layer to which the light emitted from the flash lamp is radiated.

[0027] According to some embodiments, the method may further include forming a light absorbing layer in contact with an upper surface of the pixel defining layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other aspects, features and characteristics of certain embodiments of the present disclosure will become more apparent from the following description in conjunction with the accompanying drawings, in which:

[0029] Figure 1 is a schematic plan view of a display device according to some embodiments;

[0030] Figure 2A and Figure 2B is an equivalent circuit diagram of a pixel according to some embodiments;

[0031] Figure 3A and Figure 3B is a schematic cross-sectional view of a display device according to some embodiments;

[0032] Figure 4A and Figure 4B is a cross-sectional view of a circuit device layer of a display device according to some embodiments; and

[0033] FIG. 5A to FIG. 8B is a schematic cross-sectional view illustrating a method of manufacturing a display device according to some embodiments. DETAILED DESCRIPTION

[0034] Reference will now be made in more detail to aspects of some embodiments shown in the accompanying drawings, in which the same reference numerals always refer to the same elements. In this regard, the present embodiment may have different forms and should not be construed as being limited to the description set forth herein. Therefore, the embodiments are described below only by reference to the accompanying drawings to explain aspects of the present description. As used herein, the term "and / or" includes any and all combinations of one or more of the related listed items. Throughout the disclosure, the expression "at least one of a, b, and c" means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or any combination of a, b, and / or c.

[0035] Since the present disclosure allows for various changes and multiple embodiments, specific embodiments will be shown in the drawings and described in detail in the written description. A full understanding of the embodiments, the advantages of the embodiments, and the purposes achieved by implementing the present disclosure is obtained with reference to the drawings used to illustrate the embodiments. However, the present disclosure is not limited to the embodiments disclosed below, but can be implemented in various different forms.

[0036] Hereinafter, aspects of some embodiments of the present disclosure will be described in more detail by explaining one or more embodiments with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals represent the same elements, and repeated explanations thereof will not be given.

[0037] In the following embodiments, terms such as first and second are not limited to the terms and are used only for the purpose of distinguishing one component from another.

[0038] In the following embodiments, a singular expression in the present specification includes a plural expression unless the context clearly indicates otherwise.

[0039] In the following embodiments, terms such as including or having indicate the presence of features or elements described in the specification, and do not exclude the possibility that one or more other features or elements may be added.

[0040] In the following embodiments, when various components such as films, regions, and components are referred to as being over or on other components, this includes the case where the component is directly on the other component and the case where the other component is located therebetween.

[0041] For convenience of explanation, in the drawings, the size of the components may be enlarged or reduced. For example, for convenience of description, the size and thickness of each component shown in the drawings are arbitrarily shown, and therefore the present disclosure is not necessarily limited to the drawings.

[0042] When the embodiment is implemented in other ways, a specific process order may be performed differently from the described order. For example, two processes described in succession may be performed substantially simultaneously (or synchronously), or may be performed in an order opposite to the described order.

[0043] In this specification, the expression "A and / or B" means the case of A, B, or A and B. In addition, the expression "at least one of A and B" means the case of A, B, or A and B.

[0044] In the following embodiments, when films, regions, components, etc. are described as being connected, this also includes the case where the films, regions, and components are directly connected, and / or the case where other films, regions, and components are located between these films, regions, and components and are indirectly connected thereto. For example, in this specification, when films, regions, components, etc. are described as being electrically connected, this also includes the case where the films, regions, and components are directly electrically connected, and / or the case where other films, regions, and components are located between these films, regions, and components and are electrically connected thereto and indirectly connected thereto.

[0045] The x-axis, y-axis, and z-axis are not limited to the three axes in the Cartesian coordinate system, and can be broadly interpreted as including these axes. For example, the x-axis, y-axis, and z-axis can be orthogonal to each other, but can also refer to different directions that are not orthogonal to each other.

[0046] Figure 1 is a schematic plan view of a display device 1 according to some embodiments.

[0047] refer to Figure 1 , the display device 1 includes a display area DA and a peripheral area PA as a non-display area. Pixels P including an organic light emitting device OLED are arranged in the display area DA to provide a specific image. The peripheral area PA is an area in which an image is not provided, and includes a scan driver and a data driver, which provide electrical signals to be applied to the pixels P of the display area DA, and a power line, which provides power such as a driving voltage and a common voltage.

[0048] Figure 2A and Figure 2B is an equivalent circuit diagram of a pixel P according to some embodiments.

[0049] refer to Figure 2A , each pixel P includes a pixel circuit PC connected to a scan line SL and a data line DL and an organic light emitting device OLED connected to the pixel circuit PC.

[0050] The pixel circuit PC includes a driving thin film transistor T1, a switching thin film transistor T2 and a storage capacitor Cst. The switching thin film transistor T2 is connected to the scan line SL and the data line DL, and transmits a data signal Dm input through the data line DL to the driving thin film transistor T1 according to a scan signal Sn input through the scan line SL.

[0051] The storage capacitor Cst is connected to the switching thin film transistor T2 and the driving voltage line PL, and stores a voltage corresponding to a difference between a voltage received from the switching thin film transistor T2 and a driving voltage ELVDD supplied to the driving voltage line PL.

[0052] The driving thin film transistor T1 may be connected to the driving voltage line PL and the storage capacitor Cst, and in response to the voltage value stored in the storage capacitor Cst, the driving thin film transistor T1 may control the driving current flowing from the driving voltage line PL into the organic light emitting device OLED. The organic light emitting device OLED may emit light with a certain brightness by the driving current.

[0053] exist Figure 2A In the embodiment, the pixel P includes two thin film transistors and one storage capacitor, but the present disclosure is not limited thereto.

[0054] refer to Figure 2BThe pixel circuit PC may include a driving thin film transistor T1, a switching thin film transistor T2, a compensation thin film transistor T3, a first initialization thin film transistor T4, a first light emission control thin film transistor T5, a second light emission control thin film transistor T6 and a second initialization thin film transistor T7.

[0055] The drain electrode of the driving thin film transistor T1 may be electrically connected to the organic light emitting device OLED via the second light emission control thin film transistor T6. The driving thin film transistor T1 receives the data signal Dm according to the switching operation of the switching thin film transistor T2 to provide a driving current to the organic light emitting device OLED.

[0056] The gate electrode of the switching thin film transistor T2 is connected to the first scan line SLn, and the source electrode is connected to the data line DL. The drain electrode of the switching thin film transistor T2 is connected to the source electrode of the driving thin film transistor T1 and may be connected to the driving voltage line PL via the first emission control thin film transistor T5.

[0057] The switching thin film transistor T2 is turned on according to the first scan signal Sn received through the first scan line SLn to perform a switching operation of transmitting the data signal Dm received through the data line DL to the source electrode of the driving thin film transistor T1 .

[0058] The gate electrode of the compensation thin film transistor T3 may be connected to the first scan line SLn. The source electrode of the compensation thin film transistor T3 may be connected to the drain electrode of the driving thin film transistor T1, and may be connected to the pixel electrode of the organic light emitting device OLED through the second light emission control thin film transistor T6. The drain electrode of the compensation thin film transistor T3 may be connected to any one electrode of the storage capacitor Cst, the source electrode of the first initialization thin film transistor T4, and the gate electrode of the driving thin film transistor T1. The compensation thin film transistor T3 is turned on according to the first scan signal Sn received through the first scan line SLn to connect the gate electrode and the drain electrode of the driving thin film transistor T1 to each other and realize a diode connection on the driving thin film transistor T1.

[0059] The gate electrode of the first initialization thin film transistor T4 may be connected to the second scan line SLn-1. The drain electrode of the first initialization thin film transistor T4 may be connected to the initialization voltage line VL. The source electrode of the first initialization thin film transistor T4 may be connected to any one electrode of the storage capacitor Cst, the drain electrode of the compensation thin film transistor T3, and the gate electrode of the driving thin film transistor T1. The first initialization thin film transistor T4 may be turned on according to the second scan signal Sn-1 received through the second scan line SLn-1 to perform an initialization operation of transmitting the initialization voltage VINT to the gate electrode of the driving thin film transistor T1 and initializing the voltage of the gate electrode of the driving thin film transistor T1.

[0060] The gate electrode of the first emission control thin film transistor T5 may be connected to the emission control line EL. The source electrode of the first emission control thin film transistor T5 may be connected to the driving voltage line PL. The drain electrode of the first emission control thin film transistor T5 is connected to the source electrode of the driving thin film transistor T1 and the drain electrode of the switching thin film transistor T2.

[0061] The gate electrode of the second light emission control thin film transistor T6 may be connected to the light emission control line EL. The source electrode of the second light emission control thin film transistor T6 may be connected to the drain electrode of the driving thin film transistor T1 and the source electrode of the compensation thin film transistor T3. The drain electrode of the second light emission control thin film transistor T6 may be electrically connected to the pixel electrode of the organic light emitting device OLED. The first light emission control thin film transistor T5 and the second light emission control thin film transistor T6 are simultaneously turned on according to the light emission control signal En received through the light emission control line EL to transmit the driving voltage ELVDD to the organic light emitting device OLED and allow the driving current to flow into the organic light emitting device OLED.

[0062] The gate electrode of the second initialization thin film transistor T7 may be connected to the third scan line SLn+1. The source electrode of the second initialization thin film transistor T7 may be connected to the pixel electrode of the organic light emitting device OLED. The drain electrode of the second initialization thin film transistor T7 may be connected to the initialization voltage line VL. The second initialization thin film transistor T7 may be turned on according to the third scan signal Sn+1 received through the third scan line SLn+1 to initialize the pixel electrode of the organic light emitting device OLED.

[0063] Any one electrode of the storage capacitor Cst may be connected to the gate electrode of the driving thin film transistor T1, the drain electrode of the compensation thin film transistor T3, and the source electrode of the first initialization thin film transistor T4. The other electrode of the storage capacitor Cst may be connected to the driving voltage line PL.

[0064] The opposite electrode of the organic light emitting device OLED receives the common power voltage ELVSS. The organic light emitting device OLED receives a driving current from the driving thin film transistor T1 to emit light.

[0065] The pixel circuit PC is not limited to the reference Figure 2A and Figure 2B The number and circuit design of thin film transistors and storage capacitors are described, and the number and circuit design may be changed in various ways.

[0066] Figure 3A and Figure 3B is a schematic cross-sectional view of a display device according to some embodiments.

[0067] refer to Figure 3A, the display area DA includes a first pixel area PA1, a second pixel area PA2, and a third pixel area PA3 in which organic light-emitting devices (e.g., a first organic light-emitting device OLED1, a second organic light-emitting device OLED2, and a third organic light-emitting device OLED3) are arranged, and includes a non-pixel area NPA between adjacent pixel areas. The pixel area in the specification corresponds to an area in which light is actually emitted (that is, a light-emitting area).

[0068] The first organic light emitting device OLED1, the second organic light emitting device OLED2, and the third organic light emitting device OLED3 can realize different colors. For example, the first organic light emitting device OLED1 can realize red, the second organic light emitting device OLED2 can realize green, and the third organic light emitting device OLED3 can realize blue. According to some embodiments, the display area DA may further include a fourth organic light emitting device that realizes white.

[0069] In order to achieve ultra-high definition, the substrate 100 may include a semiconductor material such as a Group IV semiconductor, a Group III-V semiconductor, or a Group II-VI semiconductor. The substrate 100 may include a silicone layer. That is, the substrate 100 may be a semiconductor substrate including a semiconductor material. According to some embodiments, the substrate 100 may be a C-MOS substrate. Therefore, an OLED display device using a substrate 100 including a semiconductor material may be referred to as an OLED on silicon (OLEDoS). OLEDoS may be mainly used for extended reality (XR), and may achieve an ultra-high definition greater than or equal to 8K in a small area of ​​about 1 inch to about 2 inches. When a semiconductor substrate is used, it is possible to densely control pixels arranged with ultra-high definition. In a different statement, in a micro display device in a pixel P (reference Figure 1 In the case where the semiconductor substrate has a length of about 2 μm to about 4 μm in a first direction (eg, X direction or −X direction) of about 2 μm to about 4 μm, a semiconductor substrate may be used. However, the present disclosure is not limited thereto.

[0070] The type of substrate 100 may not be limited to a semiconductor substrate. For example, the substrate 100 may include glass, metal, or a polymer resin. In addition, the substrate 100 may include a polymer resin such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. The substrate 100 may be modified in various ways and, for example, may have a multilayer structure including two layers each containing such a polymer resin and a barrier layer located between the two layers and including an inorganic material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0071] The circuit device layer 110 including the pixel circuit PC is provided on the substrate 100. The pixel circuit PC includes the above-mentioned Figure 2A and Figure 2B The thin film transistor and the storage capacitor described. Layers constituting the thin film transistor and the storage capacitor, such as a semiconductor layer and an electrode layer, may be arranged with an insulating layer therebetween. The pixel circuit PC is arranged at each of the first organic light emitting device OLED1, the second organic light emitting device OLED2, and the third organic light emitting device OLED3.

[0072] The first organic light-emitting device OLED1, the second organic light-emitting device OLED2, and the third organic light-emitting device OLED3 each include a pixel electrode, an intermediate layer including an emission layer, and an opposite electrode. The first organic light-emitting device OLED1, the second organic light-emitting device OLED2, and the third organic light-emitting device OLED3 may be respectively located in the first opening OP1, the second opening OP2, and the third opening OP3 of the pixel defining layer 120 to correspond thereto.

[0073] The first organic light-emitting device OLED1 includes a first pixel electrode 211, a first intermediate layer 221, and a first opposing electrode 231. The second organic light-emitting device OLED2 includes a second pixel electrode 212, a second intermediate layer 222, and a second opposing electrode 232. The third organic light-emitting device OLED3 includes a third pixel electrode 213, a third intermediate layer 223, and a third opposing electrode 233.

[0074] The end portions of the first pixel electrode 211, the second pixel electrode 212 and the third pixel electrode 213 are respectively covered with a pixel defining layer 120, and the central portions of the first pixel electrode 211, the second pixel electrode 212 and the third pixel electrode 213 are respectively exposed through the first opening OP1, the second opening OP2 and the third opening OP3 of the pixel defining layer 120, and are respectively in contact with the first intermediate layer 221, the second intermediate layer 222 and the third intermediate layer 223 through the first opening OP1, the second opening OP2 and the third opening OP3 of the pixel defining layer 120.

[0075] That is, the pixel defining layer 120 includes a covering portion 120C and a first opening OP1, a second opening OP2, and a third opening OP3, wherein the covering portion 120C covers the ends of the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213, and the central portions of the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213 are exposed through the first opening OP1, the second opening OP2, and the third opening OP3, respectively.

[0076] The first intermediate layer 221, the second intermediate layer 222 and the third intermediate layer 223, each including an emission layer, can be located in an area where the first pixel electrode 211, the second pixel electrode 212 and the third pixel electrode 213 are exposed by the pixel defining layer 120, the first relative electrode 231, the second relative electrode 232 and the third relative electrode 233 can be located above the first intermediate layer 221, the second intermediate layer 222 and the third intermediate layer 223, respectively, and light can be emitted from the intermediate layer between the pixel electrode and the relative electrode, and therefore, the pixel area is defined by the pixel defining layer 120.

[0077] The pixel defining layer 120 may be made of an organic material or an inorganic material. When the pixel defining layer 120 is made of an organic material, the pixel defining layer 120 may include one or more organic insulating materials selected from the group consisting of polyimide, polyamide, an acrylic resin layer, benzocyclobutene, and a phenolic resin layer. When the pixel defining layer 120 is made of an inorganic material, the pixel defining layer 120 may be formed to include silicon oxide (SiO x ), silicon nitride (SiN x ) and / or a single layer or multiple layers of silicon oxynitride (SiON).

[0078] The first pixel electrode 211 , the second pixel electrode 212 , and the third pixel electrode 213 may be an island type arranged to correspond to the first pixel region PA1 , the second pixel region PA2 , and the third pixel region PA3 , respectively, and may be spaced apart from each other on the circuit device layer 110 .

[0079] The first pixel electrode 211 , the second pixel electrode 212 , and the third pixel electrode 213 may each be a reflective electrode or a transmissive electrode.

[0080] When the first pixel electrode 211, the second pixel electrode 212 and the third pixel electrode 213 are each a reflective electrode, the first pixel electrode 211, the second pixel electrode 212 and the third pixel electrode 213 may include a reflective film made of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr) or a compound thereof. Optionally, the first pixel electrode 211, the second pixel electrode 212 and the third pixel electrode 213 may include the above-mentioned reflective film and a transparent conductive oxide (TCO) film above and / or below the above-mentioned reflective film. According to some embodiments, the first pixel electrode 211, the second pixel electrode 212 and the third pixel electrode 213 may include three layers of ITO / Ag / ITO.

[0081] When the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213 are each a transmissive electrode, the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213 may be a transparent conductive oxide (TCO) layer. Alternatively, the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213 may be a metal film including silver (Ag) or a silver (Ag) alloy, or a multi-layer transparent conductive oxide layer formed on the above metal film.

[0082] The first intermediate layer 221, the second intermediate layer 222, and the third intermediate layer 223 may be island-type arranged to correspond to the first pixel area PA1, the second pixel area PA2, and the third pixel area PA3, respectively, and may be spaced apart from each other. The first intermediate layer 221, the second intermediate layer 222, and the third intermediate layer 223 are respectively located on the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213 through the first opening OP1, the second opening OP2, and the third opening OP3 of the pixel defining layer 120.

[0083] refer to Figure 3A and Figure 3B , the first intermediate layer 221 may be located on the first pixel electrode 211 in the first opening OP1 of the pixel defining layer 120. The second intermediate layer 222 may be located on the second pixel electrode 212 in the second opening OP2 of the pixel defining layer 120. The third intermediate layer 223 may be located on the third pixel electrode 213 in the third opening OP3 of the pixel defining layer 120. The first intermediate layer 221 includes a first emission layer 221b. The first emission layer 221b may be an organic emission layer that emits, for example, red light. The second intermediate layer 222 includes a second emission layer 222b. The second emission layer 222b may be an organic emission layer that emits, for example, green light. The third intermediate layer 223 includes a third emission layer 223b. The third emission layer 223b may be an organic emission layer that emits, for example, blue light.

[0084] The first intermediate layer 221 may further include a first lower functional layer 221a below the first emission layer 221b and / or a first upper functional layer 221c above the first emission layer 221b. The second intermediate layer 222 may further include a second lower functional layer 222a below the second emission layer 222b and / or a second upper functional layer 222c above the second emission layer 222b. The third intermediate layer 223 may further include a third lower functional layer 223a below the third emission layer 223b and / or a third upper functional layer 223c above the third emission layer 223b.

[0085] The first lower functional layer 221a, the second lower functional layer 222a, and the third lower functional layer 223a may each include a hole injection layer (HIL) and / or a hole transport layer (HTL). The first upper functional layer 221c, the second upper functional layer 222c, and the third upper functional layer 223c may each include an electron transport layer (ETL) and / or an electron injection layer (EIL). The first lower functional layer 221a, the second lower functional layer 222a, and the third lower functional layer 223a and / or the first upper functional layer 221c, the second upper functional layer 222c, and the third upper functional layer 223c may adjust the energy level of the emission layer to the pixel electrode or the relative electrode to help the emission layer to effectively emit light.

[0086] The emission layer can be formed using various known light-emitting materials, which can be formed using known hosts and dopants. In the case of dopants, both known fluorescent dopants and known phosphorus dopants can be used.

[0087] For example, the host may be 4,4′-N,N′-dicarbazole-biphenyl (Alq3C CBP), 9,10-di(naphthalene-2-yl)anthracene (ADN), distyrylanthracene (DSA), or the like, but is not limited thereto.

[0088] The hole injection layer material may be a known hole injection layer material, for example, a phthalocyanine compound such as copper phthalocyanine, 4,4',4"-tris(3-methylphenylphenylamino)triphenylamine (m-MTDATA), N,N'-di(1-naphthyl)-N,N'-diphenylbenzidine (NPB), TDATA, 2-TNATA, polyaniline / dodecylbenzenesulfonic acid (PANI / DBSA), poly(3,4-ethylenedioxythiophene) / poly(4-styrenesulfonate) (PEDOT / PSS), polyaniline / camphorsulfonic acid (PANI / CSA) or polyaniline / poly(4-styrenesulfonate) (PANI / PSS), but is not limited thereto.

[0089] The hole transport layer material can be a known hole transport layer material, for example, a carbazole derivative such as N-phenylcarbazole and polyvinylcarbazole, or an amine derivative with an aromatic condensed ring such as NPB, N,N'-bis(3-methylphenyl)-N,N'-diphenyl-[1,1-biphenyl]-4,4'-diamine (TPD) and N,N'-di(naphthalene-1-yl)-N,N'-diphenylbenzidine (α-NPD).

[0090] The electron transport layer material can be arbitrarily selected from known electron transport layer forming materials. For example, the electron transport layer material can be a quinoline derivative, particularly tris(8-hydroxyquinoline)aluminum (Alq 3 ), TAZ or Balq known materials, but not limited thereto.

[0091] The electron injection layer can be LiF, NaCl, CsF, Li 2 Any material known as an electron injection layer forming material such as O or BaO.

[0092] The first lower functional layer 221a, the second lower functional layer 222a and the third lower functional layer 223a and the first upper functional layer 221c, the second upper functional layer 222c and the third upper functional layer 223c can be formed in a single-layer structure or a multi-layer structure, and the first lower functional layer 221a, the second lower functional layer 222a and the third lower functional layer 223a and the first upper functional layer 221c, the second upper functional layer 222c and the third upper functional layer 223c can be omitted.

[0093] The first relative electrode 231, the second relative electrode 232, and the third relative electrode 233 may be an island type arranged to correspond to the first pixel area PA1, the second pixel area PA2, and the third pixel area PA3 and may be spaced apart from each other. The first relative electrode 231, the second relative electrode 232, and the third relative electrode 233 may be located on the first intermediate layer 221, the second intermediate layer 222, and the third intermediate layer 223, respectively.

[0094] The first relative electrode 231, the second relative electrode 232 and the third relative electrode 233 may be fluorescent electrodes or reflective electrodes. The first relative electrode 231, the second relative electrode 232 and the third relative electrode 233 may include at least one material of silver (Ag), magnesium (Mg), aluminum (Al), ytterbium (Yb), calcium (Ca), lithium (Li) and gold (Au). For example, the first relative electrode 231, the second relative electrode 232 and the third relative electrode 233 may have a single layer or multiple layers including at least one of silver (Ag), magnesium (Mg), aluminum (Al), ytterbium (Yb), calcium (Ca), lithium fluoride / calcium (LiF / Ca), lithium fluoride / aluminum (LiF / Al), aluminum (Al) and gold (Au). In some embodiments, the first relative electrode 231, the second relative electrode 232 and the third relative electrode 233 may each include a transparent conductive oxide (TCO) film. According to some embodiments, the first relative electrode 231, the second relative electrode 232, and the third relative electrode 233 may each include a metal film including silver (Ag) and magnesium (Mg), and the amount of silver (Ag) may be greater than the amount of magnesium (Mg). According to some embodiments, the first relative electrode 231, the second relative electrode 232, and the third relative electrode 233 may be arranged in a multilayer structure of ytterbium / silver (Yb / Ag): magnesium / indium tin oxide (Mg / ITO).

[0095] refer to Figure 3B, the first light absorbing layer 401 and the second light absorbing layer 402 may be located on the pixel defining layer 120. In detail, the first light absorbing layer 401 and the second light absorbing layer 402 may be located on the covering portion 120C of the pixel defining layer 120. In another statement, the first light absorbing layer 401 may be located between the first opening OP1 and the second opening OP2 of the pixel defining layer 120. In another statement, the first light absorbing layer 401 may be located between the first organic light emitting device OLED1 and the second organic light emitting device OLED2. The second light absorbing layer 402 may be located between the second opening OP2 and the third opening OP3 of the pixel defining layer 120. In another statement, the second light absorbing layer 402 may be located between the second organic light emitting device OLED2 and the third organic light emitting device OLED3.

[0096] The first light absorbing layer 401 and the second light absorbing layer 402 may contact the upper surface of the pixel defining layer 120. The size of each of the first light absorbing layer 401 and the second light absorbing layer 402 may be smaller than the size of the area of ​​the covering portion 120C of the pixel defining layer 120 (or the area in which the pixel defining layer 120 is located). The area of ​​the covering portion 120C of the pixel defining layer 120 corresponds to the non-pixel area NPA, and thus the size of each of the first light absorbing layer 401 and the second light absorbing layer 402 may be smaller than the size of the non-pixel area NPA. The first light absorbing layer 401 and the second light absorbing layer 402 may each include molybdenum (Mo) or aluminum (Al).

[0097] Figure 4A and Figure 4B is a cross-sectional view of a circuit device layer of a display device according to some embodiments.

[0098] refer to Figure 4A The driving thin film transistor T1 may include a driving semiconductor layer A1, a driving gate electrode G1, a driving source electrode S1 and a driving drain electrode D1, the switching thin film transistor T2 may include a switching semiconductor layer A2, a switching gate electrode G2, a switching source electrode S2 and a switching drain electrode D2, and the storage capacitor Cst may include a first storage capacitor CE1 and a second storage capacitor CE2.

[0099] The gate insulating layer 103 may be located between the driving semiconductor layer A1 and the switching semiconductor layer A2 and the driving gate electrode G1 and the switching gate electrode G2, the dielectric layer 105 may be located between the first storage capacitor CE1 and the second storage capacitor CE2, the interlayer insulating layer 107 may be located between the driving gate electrode G1 and the switching gate electrode G2 and the driving source electrode S1, the driving drain electrode D1, the switching source electrode S2 and the switching drain electrode D2, and the planarizing insulating layer 109 may be located on the driving source electrode S1, the driving drain electrode D1, the switching source electrode S2 and the switching drain electrode D2.

[0100] The gate insulating layer 103 may be made of a material such as silicon nitride (SiN x ) and / or silicon oxide (SiO x ) of an inorganic material. The dielectric layer 105 and the interlayer insulating layer 107 may be a layer including, for example, silicon oxide (SiO x ), silicon nitride (SiN x ) of the above inorganic material and / or aluminum oxide (Al 2 O 3 ) or a single layer or multiple layers. The planarization insulating layer 109 may include an organic material including a general polymer such as polymethyl methacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenol group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluoride polymer, a p-xylene polymer, a vinyl alcohol polymer, and a blend thereof, but the present disclosure is not limited thereto.

[0101] Figure 4A A case where the storage capacitor Cst overlaps the driving thin film transistor T1 and the switching thin film transistor T2 and the driving gate electrode G1 is the first storage capacitor CE1 is illustrated, but the present disclosure is not limited thereto.

[0102] refer to Figure 4B , the storage capacitor Cst may be placed so as not to overlap with the driving thin film transistor T1. For example, the first storage capacitor CE1 and the driving gate electrode G1 may include the same material, the second storage capacitor CE2 may include the same material as the driving source electrode S1 and the driving drain electrode D1, and the interlayer insulating layer 107 may be located between the first storage capacitor CE1 and the second storage capacitor CE2.

[0103] According to reference Figure 4A and Figure 4B In the described embodiments, although the driving gate electrode G1 of the driving thin film transistor T1 and the switching gate electrode G2 of the switching thin film transistor T2 are described as being located above the driving semiconductor layer A1 and the switching semiconductor layer A2, the present disclosure is not limited thereto. According to some embodiments, the driving gate electrode G1 and the switching gate electrode G2 may be located below the driving semiconductor layer A1 and the switching semiconductor layer A2, respectively. Depending on the positions of the driving gate electrode G1 and the switching gate electrode G2, in some embodiments, the driving semiconductor layer A1 and the switching semiconductor layer A2 may be located directly above the inorganic buffer layer 101, and in some embodiments, the driving gate electrode G1 and the switching gate electrode G2 may be located directly below the inorganic buffer layer 101.

[0104] FIG. 5A to FIG. 8B is a schematic cross-sectional view of a method of manufacturing a display device according to some embodiments.

[0105] refer to FIG. 5A to FIG. 8B , a method for manufacturing a display device may include: positioning a substrate 100; forming a lower functional layer 220a and an upper functional layer 220c on the substrate 100; forming a mask 500 including mask openings 501OP and 502OP on the lower functional layer 220a and the upper functional layer 220c; radiating a pulse light 600 including a plurality of pulses through the mask openings 501OP and 502OP of the mask 500; and removing the lower functional layer 220a and the upper functional layer 220c radiated with the pulse light 600.

[0106] refer to Figure 5A and Figure 5B , the method of manufacturing a display device may include: after positioning a substrate 100, forming a pixel defining layer 120 including a plurality of openings OP1, OP2, and OP3 on the substrate 100, and the pixel electrodes 211, 212, and 213 are located in the plurality of openings OP1, OP2, and OP3. In detail, the method of manufacturing a display device may include: forming a pixel defining layer 120 including a first opening OP1 in which a first pixel electrode 211 is located, a second opening OP2 in which a second pixel electrode 212 is located, and a third opening OP3 in which a third pixel electrode 213 is located.

[0107] Forming the functional layers 220a and 220c on the substrate 100 may include forming a lower functional layer 220a on the substrate 100 and forming an upper functional layer 220c on the lower functional layer 220a. The upper functional layer 220c and the lower functional layer 220a may be continuously arranged on the substrate 100. The lower functional layer 220a may include at least one of a HIL and a HTL. The upper functional layer 220c may include at least one of an EIL and an ETL.

[0108] The method of manufacturing a display device may include: between forming a lower functional layer 220a on a substrate 100 and forming an upper functional layer 220c on the substrate 100, forming a first emission layer 221b, a second emission layer 222b, and a third emission layer 223b on the substrate 100. The first emission layer 221b may emit red light, the second emission layer 222b may emit green light, and the third emission layer 223b may emit blue light. The first emission layer 221b may be arranged to correspond to the first opening OP1 of the pixel defining layer 120, the second emission layer 222b may be arranged to correspond to the second opening OP2 of the pixel defining layer 120, and the third emission layer 223b may be arranged to correspond to the third opening OP3 of the pixel defining layer 120.

[0109] like Figure 5B As shown in Figure 5ADifferently, the method for manufacturing a display device may further include forming a first light absorbing layer 401 and a second light absorbing layer 402 on the pixel defining layer 120. The first light absorbing layer 401 and the second light absorbing layer 402 may be located on a region of the covering portion 120C of the pixel defining layer 120 (a region in which the pixel defining layer 120 is located). The first light absorbing layer 401 may be located between the first opening OP1 and the second opening OP2 of the pixel defining layer 120, and the second light absorbing layer 402 may be located between the second opening OP2 and the third opening OP3 of the pixel defining layer 120. The size 401S of the first light absorbing layer 401 and the size 402S of the second light absorbing layer 402 may be equal to or smaller than the size of the region of the covering portion 120C of the pixel defining layer 120 (or a region in which the pixel defining layer 120 is located or a non-pixel area NPA).

[0110] The first light absorbing layer 401 and the second light absorbing layer 402 may include molybdenum (Mo) or aluminum (Al). The first light absorbing layer 401 and the second light absorbing layer 402 may be arranged to contact the upper surface of the pixel defining layer 120. The lower functional layer 220a and the upper functional layer 220c may be continuously arranged on the first light absorbing layer 401 and the second light absorbing layer 402.

[0111] refer to Fig. 6A and Figure 6B , a mask 500 may be positioned on the substrate 100 on which the lower functional layer 220a and the upper functional layer 220c are located. The mask 500 may include a plurality of mask openings 501OP and 502OP.

[0112] The mask 500 may be arranged so that the plurality of mask openings 501OP and 502OP of the mask 500 are located on an area of ​​the covering portion 120C of the pixel defining layer 120 (an area in which the pixel defining layer 120 is located or a non-pixel area NPA). In another formulation, the mask 500 may be arranged so that the plurality of mask openings 501OP and 502OP of the mask 500 are aligned on an area of ​​the covering portion 120C of the pixel defining layer 120 (an area in which the pixel defining layer 120 is located or a non-pixel area NPA). In detail, the mask 500 may be arranged so that the first mask opening 501OP is located on an area of ​​the covering portion 120C of the pixel defining layer 120 located between the first opening OP1 and the second opening OP2 of the pixel defining layer 120 (an area in which the pixel defining layer 120 is located or a non-pixel area NPA). The mask 500 may be arranged such that the second mask opening 502OP is located on a region of the cover portion 120C of the pixel defining layer 120 located between the second opening OP2 and the third opening OP3 of the pixel defining layer 120 (a region in which the pixel defining layer 120 is located or a non-pixel area NPA).

[0113] The pulse light 600 including a plurality of pulses may be radiated through the mask openings 501OP and 502OP of the mask 500. The flash lamp may emit the pulse light 600 including a plurality of pulses, and radiate the pulse light 600 to at least a portion of the functional layers 220a and 220c located on the region of the cover portion 120C of the pixel defining layer 120 (the region in which the pixel defining layer 120 is located or the non-pixel region NPA) through the mask openings 501OP and 502OP of the mask 500. In detail, through the first mask opening 501OP of the mask 500, the pulse light 600 may be radiated to the lower functional layer 220a and the upper functional layer 220c located on the region of the cover portion 120C of the pixel defining layer 120 located between the first opening OP1 and the second opening OP2. The pulse light 600 may be radiated onto the lower and upper functional layers 220 a and 220 c located on a region of the cover portion 120C of the pixel defining layer 120 between the second and third openings OP2 and OP3 through the second mask opening 502OP of the mask 500 .

[0114] The pulse light 600 may be light having a wavelength band of ultraviolet light, visible light, or infrared light. The interval between pulses of the pulse light 600 emitted from the flash lamp or the intensity of the pulse light 600 may be adjusted.

[0115] Side leakage current may be generated in the functional layers 220a and 220c located on the cover portion 120C of the pixel defining layer 120. At least a portion of the functional layers 220a and 220c located on the cover portion 120C of the pixel defining layer 120 may be removed to prevent or reduce the side leakage current flowing to the functional layers 220a and 220c located on the cover portion 120C of the pixel defining layer 120, thereby improving the reliability of the display device.

[0116] A photon curing method may be used to remove at least a portion of the functional layers 220a and 220c located on an area of ​​the cover portion 120C of the pixel defining layer 120 (an area in which the pixel defining layer 120 is located or a non-pixel area NPA) irradiated with the pulse light 600 through the mask openings 501OP and 502OP of the mask 500. In detail, a photon curing method may be used to remove at least a portion of the functional layers 220a and 220c located on an area of ​​the cover portion 120C of the pixel defining layer 120 between the first opening OP1 and the second opening OP2 (an area in which the pixel defining layer 120 is located or a non-pixel area NPA) irradiated with the pulse light 600 through the first mask opening 501OP of the mask 500. At least a portion of the functional layers 220a and 220c on the region of the covering portion 120C between the second opening OP2 and the third opening OP3 of the pixel defining layer 120 (the region in which the pixel defining layer 120 is located or the non-pixel region NPA) irradiated with the pulse light 600 through the second mask opening 502OP of the mask 500 may be removed using a photon curing method. When the pulse light 600 is irradiated to at least a portion of the functional layers 220a and 220c through the mask openings 501OP and 502OP of the mask 500, at least a portion of the functional layers 220a and 220c irradiated with the pulse light 600 may be instantaneously heated and may be removed using a photon curing method. According to the photon curing method, at least a portion of the functional layers 220a and 220c located on the pixel defining layer 120 may be removed without damaging the display device.

[0117] At least a portion of the functional layers 220a and 220c located on the covering portion 120C of the pixel defining layer 120 can be removed to prevent or reduce side leakage current, and therefore the size of a mask opening 501OP or 502OP of the mask 500 can be smaller than the size of the area of ​​the covering portion 120C of the pixel defining layer 120 (the area in which the pixel defining layer 120 is located or the non-pixel area NPA).

[0118] According to the prior art, by forming electrode lines on the pixel defining layer and applying a pulse voltage to the electrode lines, a Joule heating method can be used to remove the functional layer adjacent to the electrode lines. When the electrode lines are placed and the pulse voltage is applied to the electrode lines, it may be difficult to apply a uniform pulse voltage on the front surface of the panel and ensure regular heating.

[0119] When at least a portion of the functional layers 220a and 220c can be removed using a photon curing method by radiating pulsed light 600 through mask openings 501OP and 502OP of the mask 500 to at least a portion of the functional layers 220a and 220c located on the cover portion 120C of the pixel defining layer 120, an electrode line for applying a pulse voltage or a technique for controlling regular heating is not required, and thus, the efficiency of the manufacturing process of the display device can be improved. The light emitted from the flash lamp can be radiated through the mask openings 501OP and 502OP of the mask 500, and thus, the time required for the manufacturing process of the display device can be reduced.

[0120] refer to Figure 6B , the first light absorbing layer 401 and the second light absorbing layer 402 may be located on the covering portion 120C of the pixel defining layer 120. The pulse light 600 may be radiated to the light absorbing layers 401 and 402 located on the covering portion 120C of the pixel defining layer 120 through the mask openings 501OP and 502OP of the mask 500. The first light absorbing layer 401 and the second light absorbing layer 402 may include molybdenum (Mo) or aluminum (Al). The light absorbing layers 401 and 402 may absorb the pulse light 600, and thus the degree of local heating or transient heating of at least a portion of the functional layers 220a and 220c located on the covering portion 120C of the pixel defining layer 120 around the light absorbing layers 401 and 402 may be increased, and at least a portion of the functional layers 220a and 220c located on the covering portion 120C of the pixel defining layer 120 may be effectively removed.

[0121] refer to Fig. 7A , the method of manufacturing a display device may further include discharging residues of at least a portion of the functional layers 220a and 220c removed through an opening of a chamber 700 in which the substrate 100 is located. The substrate 100 may be located in the chamber 700, and light may be irradiated through the mask openings 501OP and 502OP of the mask 500. The chamber 700 in which the substrate 100 is located may include an opening, and residues of at least a portion of the functional layers 220a and 220c removed by irradiating the pulse light 600 may be discharged through the opening of the chamber 700.

[0122] refer to Figure 7B The method of manufacturing a display device may further include forming a transparent anti-deposition plate 800 under the mask 500, and collecting and discharging residues of at least the removed portions of the functional layers 220a and 220c on the transparent anti-deposition plate 800. Fig. 7AIn contrast, a transparent anti-deposition plate 800 may be located below the mask 500. The pulse light 600 radiated through the mask openings 501OP and 502OP of the mask 500 may pass through the transparent anti-deposition plate 800 located below the mask 500. At least a portion of the residue of the functional layers 220a and 220c removed by radiating the pulse light 600 may be collected and discharged on the transparent anti-deposition plate 800. The transparent anti-deposition plate 800 may include a material that is reused by cleaning the residue of at least a portion of the attached functional layers 220a and 220c.

[0123] refer to Fig. 8A and Figure 8B , at least a portion of the functional layers 220a and 220c located on the cover portion 120C of the pixel defining layer 120, to which the pulse light 600 is radiated, may be removed. Therefore, the first lower functional layer 221a and the first upper functional layer 221c may be arranged to correspond to the first opening OP1 of the pixel defining layer 120, and the second lower functional layer 222a and the second upper functional layer 222c may be arranged to correspond to the second opening OP2 of the pixel defining layer 120. In addition, the third lower functional layer 223a and the third upper functional layer 223c may be arranged to correspond to the third opening OP3 of the pixel defining layer 120. After removing at least a portion of the lower functional layer 220a and the upper functional layer 220c, the opposing electrodes 231, 232, and 233 may be continuously arranged on the functional layers 220a and 220c.

[0124] The first pixel electrode 211, the first intermediate layer 221, and the first opposing electrode 231 may be arranged to correspond to the first opening OP1 of the pixel defining layer 120. The first intermediate layer 221 may include a first lower functional layer 221a, a first emission layer 221b, and a first upper functional layer 221c. The first organic light-emitting device OLED1 including the first pixel electrode 211, the first intermediate layer 221, and the first opposing electrode 231 may be located in the first opening OP1 of the pixel defining layer 120. The second pixel electrode 212, the second intermediate layer 222, and the second opposing electrode 232 may be arranged to correspond to the second opening OP2 of the pixel defining layer 120. The second intermediate layer 222 may include a second lower functional layer 222a, a second emission layer 222b, and a second upper functional layer 222c. The second organic light-emitting device OLED2 including the second pixel electrode 212, the second intermediate layer 222, and the second opposing electrode 232 may be located in the second opening OP2 of the pixel defining layer 120. The third pixel electrode 213, the third intermediate layer 223, and the third opposing electrode 233 may be arranged to correspond to the third opening OP3 of the pixel defining layer 120. The third intermediate layer 223 may include a third lower functional layer 223a, a third emission layer 223b, and a third upper functional layer 223c. The third organic light emitting device OLED3 including the third pixel electrode 213, the third intermediate layer 223, and the third opposing electrode 233 may be located in the third opening OP3 of the pixel defining layer 120.

[0125] like Figure 8B As shown in , according to some embodiments, the first light absorbing layer 401 and the second light absorbing layer 402 may be located on the covering portion 120C of the pixel defining layer 120. In detail, the first light absorbing layer 401 may be located on the covering portion 120C of the pixel defining layer 120 between the first opening OP1 and the second opening OP2 of the pixel defining layer 120. The second light absorbing layer 402 may be located on the covering portion 120C of the pixel defining layer 120 between the second opening OP2 and the third opening OP3 of the pixel defining layer 120.

[0126] According to the embodiments as described above, a method of manufacturing a display device having relatively improved efficiency and reliability of a manufacturing process may be realized. The scope of the present disclosure may not be limited to this effect.

[0127] Although the present disclosure has been specifically shown and described with reference to some embodiments of the present disclosure, it will be understood by those skilled in the art that this is only an example and that various changes and equivalents can be made according to the present disclosure. Therefore, the scope of the present disclosure needs to be determined by the technical spirit of the claims.

[0128] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the appended claims and their equivalents.

Claims

1. A method for manufacturing a display device, the method comprising: positioning the substrate; forming a functional layer on the substrate; forming a mask including an opening on the functional layer; radiating pulsed light including a plurality of pulses through the openings of the mask; as well as The functional layer irradiated with the pulse light is removed.

2. The method according to claim 1, further comprising: After positioning the substrate, a pixel defining layer including a plurality of openings is formed on the substrate, and pixel electrodes are located in the plurality of openings.

3. The method according to claim 2, wherein: The mask includes a plurality of openings; and The mask is arranged such that the plurality of openings of the mask are on a region where the pixel defining layer is located.

4. The method according to claim 3, wherein: The functional layer irradiated with the pulse light is at least a portion of the functional layer on the pixel defining layer.

5. The method according to claim 2, wherein: Forming the functional layer on the substrate further comprises: forming a lower functional layer on the pixel electrode and the pixel defining layer; and An upper functional layer is formed on the lower functional layer.

6. The method according to claim 5, wherein: The lower functional layer includes at least one of a hole injection layer and a hole transport layer.

7. The method according to claim 5, wherein: The upper functional layer includes at least one of an electron injection layer and an electron transport layer.

8. The method according to claim 5, further comprising: An emission layer is formed in the opening of the pixel defining layer between forming the lower functional layer and forming the upper functional layer.

9. The method according to claim 2, wherein: The size of the opening of the mask is smaller than the size of the region in which the pixel defining layer is located.

10. The method according to claim 1, wherein: The pulsed light is emitted from a flash lamp.

11. The method according to claim 1, wherein: The pulse light is light having a wavelength band of ultraviolet light, visible light, or infrared light.

12. The method according to claim 2, further comprising: A light absorbing layer is formed on the pixel defining layer.

13. The method according to claim 12, wherein: The light absorbing layer contacts an upper surface of the pixel defining layer.

14. The method according to claim 12, wherein: The size of the light absorbing layer is smaller than the size of the region in which the pixel defining layer is located.

15. The method according to claim 12, wherein: The light absorbing layer includes molybdenum or aluminum.

16. The method according to claim 1, further comprising: Residues of the removed portion of the functional layer are discharged through an opening of a chamber in which the substrate is located.

17. The method according to claim 1, further comprising: A transparent anti-deposition plate is formed under the mask.

18. The method according to claim 17, further comprising: The residue of the removed portion of the functional layer is collected and discharged onto the transparent anti-deposition plate.

19. A method for manufacturing a display device, the method comprising: positioning the substrate; forming a pixel defining layer including an opening on the substrate, wherein the pixel electrode is located in the opening; forming a functional layer on the pixel electrode and the pixel defining layer; forming a mask including an opening such that the opening of the mask is positioned in a region in which the pixel defining layer is located; radiating light emitted from a flash lamp through the opening of the mask; as well as The functional layer on the pixel defining layer irradiated with the light emitted from the flash lamp is removed.

20. The method according to claim 19, further comprising: A light absorbing layer is formed in contact with an upper surface of the pixel defining layer.

Images