Method and apparatus for automatic matching of verification procedures

Abstract

The application relates to the communication field and provides a method and device for automatically matching a check program. The method comprises the following steps: determining a first signal bit and a first check bit of a first message frame; searching for a first check program set matched with the first redundant section from a first check program library, wherein the first check program library comprises check programs corresponding to various different controllers used for bench test; determining a first check result corresponding to each first check program based on the first signal bit; and screening a target check program matched with a check mode of a target controller from the first check program set based on the first check bit and the first check result. The application can automatically match the target check program corresponding to the check mode of each controller used for bench test, is not affected by the increase of the controller used for bench test or the replacement of the controller used for bench test, and can meet the demand of building various bench test environments.

Description

Technical Field

[0001] This application relates to the field of communications, and more particularly to a method and apparatus for an automatic matching and verification program. Background Technology

[0002] CRC (Cyclic Redundancy Check) is a commonly used error checking method in the field of data communication. Before conducting bench tests, it is usually necessary to perform CRC checks on the messages transmitted by the controller to ensure the correctness and integrity of the messages before forwarding them to the test object (such as the electronic control unit of a range extender or engine), thereby ensuring that the controller can effectively control the test object.

[0003] Different controllers may have different CRC check methods, and the corresponding CRC check programs are generally different for different CRC check methods.

[0004] For test benches equipped with multiple different controllers, although it is possible to perform CRC checks on messages transmitted from these controllers by writing a specific CRC check program, this program needs to be rewritten whenever one or more of the controllers need to be replaced. This approach is not only labor-intensive and inefficient, but also has high maintenance costs and poor flexibility, making it difficult to meet the needs of setting up various test bench environments. Summary of the Invention

[0005] In view of this, embodiments of this application provide a method and apparatus for automatically matching verification programs to solve the problem in the prior art that for test benches equipped with multiple different controllers, whenever it is necessary to replace one or more of the multiple different controllers currently equipped on the test bench, the specific CRC verification program needs to be rewritten, which is not only labor-intensive and inefficient, but also has high maintenance costs and poor flexibility, making it difficult to meet the needs of building various test bench environments.

[0006] A first aspect of this application provides a method for automatically matching and verifying a program, comprising:

[0007] Obtain the message frame set sent by the controller group currently mounted on the test bench, wherein the controller group includes at least two different target controllers, the message frame set includes at least two first message frames, and one first message frame corresponds to one target controller;

[0008] For each target controller, the first signal bit and the first check bit of the first message frame are determined, wherein the first signal bit includes a first valid signal segment and a first redundant segment;

[0009] The first set of verification programs that matches the first redundant segment is searched in the first verification program library, wherein the first set of verification programs includes at least one first verification program, and the first verification program library includes verification programs corresponding to various different controllers used for bench testing.

[0010] Based on the first signal bit, determine the first verification result corresponding to each first verification procedure;

[0011] Based on the first check bit and the first check result, a target check program that matches the check method of the target controller is selected from the first check program set.

[0012] A second aspect of this application provides an apparatus for automatically matching and verifying a program, comprising:

[0013] The acquisition module is configured to acquire the message frame set sent by the controller group currently mounted on the test bench, wherein the controller group includes at least two different target controllers, the message frame set includes at least two first message frames, and one first message frame corresponds to one target controller.

[0014] The first determining module is configured to determine the first signal bit and the first check bit of the first message frame for each target controller, wherein the first signal bit includes a first valid signal segment and a first redundant segment.

[0015] The lookup module is configured to search for a first set of verification programs that matches the first redundant segment from a first verification program library, wherein the first set of verification programs includes at least one first verification program, and the first verification program library includes verification programs corresponding to various different controllers used for bench testing.

[0016] The second determining module is configured to determine the first verification result corresponding to each first verification procedure based on the first signal bit.

[0017] The filtering module is configured to select a target verification program that matches the verification method of the target controller from the first set of verification programs based on the first verification bit and the first verification result.

[0018] A third aspect of this application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the above-described method.

[0019] A fourth aspect of this application provides a readable storage medium storing a computer program that, when executed by a processor, implements the steps of the above-described method.

[0020] Compared with the prior art, the beneficial effects of the embodiments of this application include at least the following: before setting up the test bench (which is equipped with one or more different target controllers) and conducting the test bench test, firstly, the message frame set sent by the controller group is obtained; then, for each target controller, the first signal bit and the first check bit of the first message frame are determined; then, the first check program set matching the first redundancy segment is searched from the first check program library; then, based on the first signal bit, the first check result corresponding to each first check program in the first check program set is determined; finally, based on the first check bit and the first check result, a target check program matching the check method of the target controller is selected from the first check program set. The above method enables automatic matching of target verification programs to each controller mounted on the test bench with their corresponding verification methods. This method is unaffected by adding or replacing controllers on the test bench, offering high flexibility and meeting the needs of setting up various test bench environments. It eliminates the need to write specific CRC verification programs for multiple different controllers currently mounted on the test bench, and also eliminates the need to rewrite specific CRC verification programs every time a controller(s) are added or replaced on the test bench. Therefore, it significantly reduces workload, improves work efficiency, and lowers maintenance costs. At the same time, it effectively reduces communication anomalies caused by mismatches between the target controller's verification method and verification program. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram illustrating one application scenario of this application.

[0023] Figure 2 This is a flowchart illustrating an automatic matching and verification procedure provided in an embodiment of this application;

[0024] Figure 3 This is a schematic diagram of the storage structure in a first verification program library provided in an embodiment of this application;

[0025] Figure 4 This is a schematic diagram of the overall process of an automatic matching and verification program provided in an embodiment of this application;

[0026] Figure 5 This is a flowchart illustrating an automatic matching and verification procedure, which is an application example provided in an embodiment of this application.

[0027] Figure 6 This is a schematic diagram of the structure of an automatic matching and verification program device provided in an embodiment of this application;

[0028] Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0029] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0030] The following describes in detail, with reference to the accompanying drawings, a method and apparatus for an automatic matching and verification program according to embodiments of this application.

[0031] Figure 1 This is a schematic diagram illustrating an application scenario according to an embodiment of this application. The application scenario may include a server 101, a host computer 102 (also referred to as a benchtop host computer), a controller group 103, a benchtop 104, and a target ECU (Electronic Control Unit) 105. The host computer 102 can establish communication connections with the target controller 103, the benchtop 104, and the target ECU 105 via CAN (Controller Area Network) bus, Ethernet, etc.; the host computer 102 can establish a communication connection with the server 101 via a wired network or a wireless network. The host computer 102 and the benchtop 104 constitute a benchtop system.

[0032] Server 101 can be a single server, a server cluster consisting of several servers, or a cloud computing service center; this embodiment of the application does not limit this.

[0033] Server 101 contains a first verification program library, which stores verification programs (also known as generator polynomials) for various controllers used in bench testing. Different controllers may have different verification methods (verification algorithms), and different verification methods typically correspond to different verification programs.

[0034] In some implementations, the controller developers can provide verification programs for various controllers used in bench testing, corresponding to different verification methods. These verification programs can be stored uniformly in a first verification program library, which is directly accessible to the bench system.

[0035] The host computer 102 can be any electronic device with a user interface that supports communication with the server 101, the target controller 103, the test bench 104, and the target ECU 105. Specifically, it can be a computer, mobile phone, tablet, panel, touch screen, etc.

[0036] Controller group 103 includes at least two controllers with different structures and / or functions. Specifically, the type and number of controllers to be mounted on the test bench can be selected according to the actual needs of the test bench environment to be built. As an example, if a test bench environment needs to be equipped with target controller 1, target controller 2, target controller 3, and target controller 4, then controller group 103 includes target controller 1, target controller 2, target controller 3, and target controller 4. Among them, target controller 1, target controller 2, target controller 3, and target controller 4 are controllers with different structures and / or functions.

[0037] Bench 104, or test bench, refers to different test benches that require different technical support systems. For example, a gasoline engine bench requires technical support systems for air intake, fuel injection, and ignition control. An aircraft engine bench, on the other hand, requires technical support systems for fuel supply, power supply, engine monitoring, fire suppression, explosion prevention, and environmental monitoring.

[0038] The target ECU 105, also known as the bench test object, can specifically be an electronic control unit (ECU) of a car engine, range extender, etc.

[0039] Figure 2 This is a flowchart illustrating an automatic matching and verification procedure provided in an embodiment of this application. Figure 2 The method of automatic matching and verification program can be provided by Figure 1 The host computer 102 of the test bench system executes the commands. For example... Figure 2 As shown, the method of this automatic matching and verification program includes the following steps:

[0040] Step S201: Obtain the message frame set sent by the controller group currently mounted on the test bench, wherein the controller group includes at least two different target controllers, the message frame set includes at least two first message frames, and one first message frame corresponds to one target controller.

[0041] As an example, suppose a test bench currently carries target controller 1, target controller 2, and target controller 3, where target controller 1, target controller 2, and target controller 3 are controllers with different structures and / or functions. Then, controller group 103 includes target controllers 1 to 3. Before the test bench environment is set up and the test bench begins, target controller 1 can send the first message frame 1 to the host computer 102, target controller 2 can send the first message frame 2 to the host computer 102, and target controller 3 can send the first message frame 3 to the host computer 102. That is, each of target controllers 1 to 3 sends its own first message frame to the host computer 102. Alternatively, controller group 103 can collect the first message frames 1, 2, and 3 that target controllers 1 to 3 need to send to the host computer 102, form a message frame set, and then send the message frame set to the host computer 102. For example, the first message frame 1 may be a message frame that includes a first control command (such as a start control command) from the target controller 1 to the target ECU 105; the first message frame 2 may be a message frame that includes a second control command (such as an engine torque control command) from the target controller 2 to the target ECU 105; and the third message frame 3 may be a message frame that includes a third control command (such as a generator torque control command) from the target controller 3 to the target ECU 105.

[0042] Step S202: For each target controller, determine the first signal bit and the first check bit of the first message frame, wherein the first signal bit includes a first valid signal segment and a first redundant segment.

[0043] The first signal bit is the information code in the first message frame. The first check bit is the checksum of the first message frame. The first valid signal segment is the information code in the first signal bit. The first redundancy segment, also known as the C segment, is the length information of the redundancy code in the first signal bit.

[0044] Assume the total length of the first message frame is X bits, the length of the first signal bit is Y bits, the length of the first check bit is Z bits, the length of the first valid signal segment is A bits, and the length of the first redundant segment is B bits, where Y = A + B. The length of the first check bit is the same as the length of the first redundant segment. For a given (X,Y) code, there exists a polynomial F(x) with a highest power of XY = Z. A check code for Y bits of information can be generated based on F(x), and F(x) is called the generator polynomial of this check code.

[0045] As an example, suppose the first message frame 1 of target controller 1 is 7D 00 27 10 08 00 0E 16, then its first signal bit is 7D 00 27 10 08 00 0E; the first check bit is 16; the first valid signal segment in the first signal bit is 7D 00 27 10 08 00; and the first redundant segment in the first signal bit is 0E.

[0046] Step S203: Search for a first set of verification programs that matches the first redundant segment from the first verification program library. The first set of verification programs includes at least one first verification program, and the first verification program library includes verification programs corresponding to various controllers used for bench testing.

[0047] Figure 3 This is a schematic diagram of the storage structure in a first verification program library provided in an embodiment of this application.

[0048] Please see Figure 3 The first verification program library has multiple storage structures, one of which is used to store a type of verification program. For example, the storage structure CRC8 is used to store a series of verification programs with the CRC8 verification method; the storage structure CRC16 is used to store a series of verification programs with the CRC16 verification method; and the storage structure CRC32 is used to store a series of verification programs with the CRC32 verification method.

[0049] Step S204: Based on the first signal bit, determine the first verification result corresponding to each first verification procedure.

[0050] Specifically, the first signal bit of the first message frame is substituted into each of the first verification procedures in the first verification procedure set to calculate the first verification result corresponding to each first verification procedure.

[0051] Step S205: Based on the first verification bit and the first verification result, select a target verification program from the first verification program set that matches the verification method of the target controller.

[0052] Specifically, the consistency between the first check bit of the first message frame and the first check result of each first check procedure can be compared to obtain the comparison result. Then, based on the comparison result, a target check procedure that matches the check method of the target controller can be selected from the set of first check procedures.

[0053] The technical solution provided in this application, before setting up the test bench (which carries one or more different target controllers) and conducting the test bench test, firstly, acquires the message frame set sent by the controller group; then, for each target controller, determines the first signal bit and the first check bit of the first message frame; next, searches for a first set of check programs that matches the first redundancy segment in the first check program library; then, based on the first signal bit, determines the first check result corresponding to each first check program in the first set of check programs; finally, based on the first check bit and the first check result, selects a target check program from the first set of check programs that matches the check method of the target controller. The above method enables automatic matching of target verification programs to each controller mounted on the test bench with their corresponding verification methods. This method is unaffected by adding or replacing controllers on the test bench, offering high flexibility and meeting the needs of setting up various test bench environments. It eliminates the need to write specific CRC verification programs for multiple different controllers currently mounted on the test bench, and also eliminates the need to rewrite specific CRC verification programs every time a controller(s) are added or replaced on the test bench. Therefore, it significantly reduces workload, improves work efficiency, and lowers maintenance costs. At the same time, this method effectively reduces communication anomalies caused by mismatches between the target controller's verification method and verification program.

[0054] In some embodiments, determining the first signal bit and the first check bit of the first message frame includes:

[0055] Read the message parsing file;

[0056] Based on the message parsing file, the first message frame is identified and its fields are divided to determine the first signal bit and the first check bit of the first message frame.

[0057] The message parsing file can be a DBC (Database CAN) parsing file. This file contains rules and explanations defining how the host computer identifies and segments message frames.

[0058] In some implementations, the written message parsing file can be pre-stored in the host computer 102 or the server 101 for easy access and use by the host computer 102 at any time.

[0059] As an example, suppose the host computer 102 receives a set of message frames sent by the controller group 103, including first message frame 1 (corresponding to target controller 1), first message frame 2 (corresponding to target controller 2), and first message frame 3 (corresponding to target controller 3). Then, the host computer 102 can first read the pre-stored DBC parsing file from the local machine or the server 101, and then, according to the relevant rules for identifying and dividing the fields of message frames defined in the DBC parsing file, identify and divide the fields of first message frame 1, first message frame 2, and first message frame 3 respectively, to obtain the first signal bit and the first check bit corresponding to first message frame 1, first message frame 2, and first message frame 3, as well as the first valid signal segment and the first redundant segment in the first signal bit.

[0060] By parsing the message file, the first signal bit, the first check bit, and the first valid signal segment and the first redundant segment in the first signal bit of each first message frame can be quickly and accurately identified and divided.

[0061] In some embodiments, searching for a first set of check programs that matches the first redundant segment from a first check program library includes:

[0062] Obtain the classification tag information corresponding to each verification program in the first verification program library;

[0063] Based on the classification label information and the first redundant segment, at least one first verification program is selected from the first verification program library to form a first verification program set.

[0064] Classification tagging information is used to distinguish each storage structure and its series of stored check programs in the first check program library. Each storage structure and its series of stored check programs carry the same identifier. For example, such as... Figure 3 The storage structure CRC8 shown is identified as "CRC8". Therefore, all the verification programs stored in this storage structure CRC8 also carry the identifier "CRC8".

[0065] The following section uses the first message frame 1 corresponding to the target controller 1 as an example to explain in detail how to find the first set of verification programs that matches the first redundant segment of the first message frame 1 from the first verification program library.

[0066] Assume the first message frame 1 corresponding to target controller 1 is 7D 00 27 10 08 00 0E 16; its first redundancy segment is 0E, and the redundancy code length CRC8 corresponding to the first redundancy segment 0E is . The host computer 102 can first search for classification tag information that matches the redundancy code length "CRC8" of the first redundancy segment 0E from the first verification program library. Among them, the classification tag information "CRC8" of the storage structure CRC8 matches the redundancy code length "CRC8" of the first redundancy segment 0E. Then, a series of verification programs stored in the storage structure CRC8 can be determined as the first verification program and form a first verification program set.

[0067] By utilizing classification marker information and the first redundant segment, a series of first verification programs that match the first redundant segment of the first message frame can be quickly and accurately found from the first verification program library. This helps reduce the computational load of the test bench system, saves computing power, and improves the efficiency of automatic matching of subsequent verification programs.

[0068] In some embodiments, based on the first check bit and the first check result, a target check program that matches the check method of the target controller is selected from the first set of check programs, including:

[0069] The first verification program in the first verification program set whose first verification result matches the first verification bit is determined as a candidate verification program;

[0070] If there is only one candidate checker, then the candidate checker will be the target checker that matches the checker method of the target controller.

[0071] Continuing with the first message frame 1 in the example above, the first redundancy segment of the first message frame 1 is 0E, and its redundancy code length is CRC8. The host computer 102 finds a series of first check programs in the first check program set from the first check program library, which are a series of check programs in the storage structure CRC8. Suppose that the storage structure CRC8 stores the following check programs: ①CRC8; ②CRC8_SAE_J1850; ③CRC8_SAE_J1850-ZERO; ④CRC8_8H2F; ⑤CRC8_CDMA2000; ⑥CRC8_DVB_S2. Then, check programs ① to ⑥ can all be determined as first check programs, forming a first check program set.

[0072] Next, the first signal bit "7D 00 27 10 08 00 0E" of the first message frame 1 is substituted into the first verification procedures (generator polynomials) ① to ⑥ mentioned above to calculate the first verification result corresponding to each first verification procedure. If the first verification results of the first verification procedures ① to ⑥ are 26, A1, AB, 16, 29, and 20 respectively, then the first verification result of the first verification procedure ④ (which is 16) is consistent with the first verification bit of the first message frame 1 (which is 16), and the first verification procedure ④ (CRC8_8H2F) can be determined as a candidate verification procedure.

[0073] In the example above, there is one candidate verification program. Therefore, the candidate verification program (i.e., the first verification program ④) is determined as the target verification program that matches the verification method of the target controller 1.

[0074] During the selection of target verification programs, the host computer extracts only the first signal bit from the first message frame and substitutes the first signal bit into each of the first verification programs in the first verification program set for calculation, instead of substituting the complete first message frame into each of the first verification programs for calculation. This helps to improve calculation efficiency, reduce the amount of computation, and save computing power.

[0075] After the target verification procedure is determined, the host computer can automatically associate other valid information of the first message frame (including the redundancy code length information of the first redundant segment of the first message frame, the first signal bit, and the first check bit) to form an independent and complete final verification procedure.

[0076] In other embodiments, after determining the first verification procedure in the first verification procedure set whose first verification result matches the first verification bit as a candidate verification procedure, the method further includes:

[0077] If the number of candidate check procedures is at least two, then at least two candidate check procedures will be combined into a second check procedure set.

[0078] Obtain the second message frame sent by the target controller;

[0079] The second signal bit and the second check bit of the second message frame are determined, wherein the second signal bit includes a second valid signal segment and a second redundant segment, and the second redundant segment is different from the first redundant segment;

[0080] Based on the second signal bit, determine the second verification result corresponding to each candidate verification procedure in the second verification procedure set;

[0081] Based on the second check bit and the second check result, from the second check procedure

[0082] Select a target verification program from the set that matches the verification method of the target controller.

[0083] As an example, suppose the host computer 102 finds seven first verification programs in the first verification program library that match the redundancy code length of the first redundant segment of the first message frame 2 of the target controller 2. These are denoted as first verification programs 1 to 7. Among them, the first verification results of first verification programs 2, 3, and 5 are consistent with the first check bit of the first message frame 2. Then, first verification programs 2, 3, and 5 are determined as candidate verification programs 1, 2, and 3. The number of candidate verification programs is 3, and these candidate verification programs 1, 2, and 3 can be combined into a second verification program set.

[0084] Next, the host computer 102 continues to receive the second message frame (next message frame) sent by the target controller 2, or the second message frame of the target controller 2 is sent by the controller group 103. The host computer 102 identifies and divides the second message frame according to the relevant rules for identifying and segmenting message frames defined in the DBC parsing file, to determine the second signal bit and the second check bit of the second message frame. Then, the second signal bit is substituted into candidate check procedures 1, 2, and 3 in the second check procedure set to calculate the second check result corresponding to candidate check procedures 1, 2, and 3.

[0085] If only the second verification result of candidate verification procedure 1 matches the second verification bit of the second message frame, then candidate verification procedure 1 can be determined as the target verification procedure that matches the verification method of target controller 2.

[0086] If the second verification result of candidate verification programs 1 and 2 is consistent with the second verification bit of the second message frame, then the host computer 102 continues to receive the third message frame sent by the target controller 2, repeats the above steps, and selects the only target verification program that matches the verification method of the target controller 2.

[0087] For the same target controller, the length of the redundancy code of the first redundant segment of the first message frame is different from the length of the redundancy code of the second redundant segment of the second message frame. This ensures the uniqueness of each message frame and prevents the host computer of the test bench system from getting stuck in a loop of invalid calculations because the message frames sent by the target controller are unchanged. This helps to improve computing efficiency and save computing power.

[0088] In some other embodiments, after determining the first verification procedure in the first verification procedure set whose first verification result matches the first verification bit as a candidate verification procedure, the method further includes:

[0089] If the number of candidate verification programs is zero, a refresh request is sent to the server so that the server refreshes the first verification program library based on the refresh request to obtain the second verification program library.

[0090] Search the second check program library for a third check program set that matches the first redundant segment, wherein the third check program set includes at least one third check program;

[0091] Based on the first signal bit, determine the third verification result corresponding to each third verification procedure;

[0092] Based on the first verification bit and the third verification result, a target verification program that matches the verification method of the target controller is selected from the third verification program set.

[0093] Continuing with the first message frame 2 in the example above, if the first verification results of the first verification procedures 1 to 7 are all inconsistent with the first verification bit of the first message frame 2, then the number of candidate verification procedures is 0. At this time, the host computer 102 sends a refresh request to the server 101. After receiving the refresh request, the server 101 refreshes the first verification procedure library to obtain the second verification procedure library. The controller development personnel will periodically or irregularly upload the newly developed verification procedures to the first verification procedure library of the server 101, and can also maintain and manage the verification procedures in the first verification procedure library.

[0094] After receiving the refresh completion notification from the server 101, the host computer 102 searches the second verification program library for a third verification program set that matches the first redundant segment of the first message frame 2. Based on the rules for identifying and segmenting message frames defined in the DBC parsing file, it identifies and segments the first message frame 2 to determine the first signal bit and the second check bit. Then, it substitutes the first signal bit into each of the third verification programs in the third verification program set to calculate the corresponding third verification result. Finally, the third verification program whose third verification result matches the first check bit is selected as a candidate verification program. Finally, based on the candidate verification programs, a target verification program matching the verification method of the target controller is determined.

[0095] The above method can refresh the verification programs in the first verification program library in a timely manner, which is beneficial to improving the efficiency of the host computer automatically matching the verification program corresponding to the verification method of the target controller.

[0096] In some embodiments, the above method may further include the following steps:

[0097] Obtain the control signal value input from the test bench;

[0098] Based on the target verification procedure and control signal values, a control message frame is generated.

[0099] Send control message frames to the target ECU.

[0100] Specifically, the host computer 102 acquires the control signal value input from the test bench 104. This control signal value can be a parameter value related to the function of the target ECU 105 (such as a range extender), such as a start signal value, engine torque signal value, engine speed signal value, generator torque signal value, generator speed signal value, etc. Then, based on the target verification program corresponding to the target controller and the control signal value, a control message frame is generated, and the control message frame is sent to the target ECU 105 to realize the target controller's control over the target ECU 105.

[0101] Figure 4 This is a schematic diagram of the overall process of an automatic matching and verification procedure provided in an embodiment of this application. Figure 5 This is a flowchart illustrating an application example of an automatic matching and verification procedure of this application.

[0102] Please see Figure 4 and Figure 5Before the test bench is set up (equipped with multiple different target controllers) and the bench test is conducted, the controller group 103 first sends the first message frames of each target controller to the host computer 102. The host computer 102 receives the first message frames of each target controller, and then parses each first message frame to determine the first signal bit and the first check bit (CRC check bit) of the first message frame, as well as the first valid signal segment and the first redundant segment (also called C segment) in the first signal bit. Next, the host computer 102 searches for the first set of first verification programs that matches the first redundant segment from the first verification program library of the server 101 according to the redundancy code length of the first redundant segment of the first message frame. The host computer 102 calculates the first verification result of each first verification program in the first set of first verification programs according to the first signal bit of the first message frame. The host computer 102 determines whether only one first verification program has a first verification result that matches the first check bit (CRC check bit). If only one first verification program has a first verification result that matches the first check bit (CRC check bit), then the target verification program is output. The host computer 102 receives the control signal value sent by the test bench 104, generates a control message frame based on the target verification program and the control signal value, and sends the control message frame to the target ECU 105 to realize the target controller's control of the target ECU 105. If there is not only one first verification program whose first verification result matches the first verification bit (CRC check bit), then the first verification program whose first verification result matches the first verification bit is determined as a candidate verification program, forming a second verification program set. The host computer 102 continues to receive the second message frame sent by the controller group 103, and parses the second message frame to determine the second signal bit and the second verification bit, as well as the second valid signal segment and the second redundant segment in the second signal bit. Then, it substitutes the second signal bit into each candidate verification program in the second verification program set to calculate the second verification result of each candidate verification program. If there is only one second verification result that matches the second verification bit, then the target verification program is output; otherwise, it continues to receive the third message frame sent by the controller group 103 and repeats the above steps until a unique target verification program is determined.

[0103] By applying the technical solution of this application, when setting up different test bench environments and equipping multiple different controllers, the system can automatically match the corresponding target verification program for each controller. This eliminates the need for engineers to write specific CRC verification programs for the multiple different controllers currently mounted on the test bench, and also eliminates the need to rewrite specific CRC verification programs every time a controller(s) are added or replaced on the test bench. This significantly reduces the workload for engineers, streamlines the handover process of program files, assists in channel matching during the test bench setup phase, improves work efficiency, and lowers maintenance costs. Simultaneously, it effectively reduces communication anomalies caused by mismatches between the target controller's verification method and verification program.

[0104] All of the above-mentioned optional technical solutions can be combined in any way to form the optional embodiments of this application, and will not be described in detail here.

[0105] The following are embodiments of the apparatus described in this application, which can be used to execute the embodiments of the method described in this application. For details not disclosed in the apparatus embodiments of this application, please refer to the embodiments of the method described in this application.

[0106] Figure 6 This is a schematic diagram of the structure of an automatic matching and verification program device provided in an embodiment of this application.

[0107] like Figure 6 As shown, the apparatus for the automatic matching and verification program includes:

[0108] The acquisition module 601 is configured to acquire the message frame set sent by the controller group currently mounted on the test bench, wherein the controller group includes at least two different target controllers, and the message frame set includes at least two first message frames, with one first message frame corresponding to one target controller.

[0109] The first determining module 602 is configured to determine the first signal bit and the first check bit of the first message frame for each target controller, wherein the first signal bit includes a first valid signal segment and a first redundant segment.

[0110] The lookup module 603 is configured to look up a first set of verification programs that matches the first redundant segment from a first verification program library, wherein the first set of verification programs includes at least one first verification program, and the first verification program library includes verification programs corresponding to various different controllers used for bench testing.

[0111] The second determining module 604 is configured to determine the first verification result corresponding to each first verification procedure based on the first signal bit.

[0112] The filtering module 605 is configured to filter a target verification program that matches the verification method of the target controller from the first set of verification programs based on the first verification bit and the first verification result.

[0113] In some embodiments, the first determining module 602 described above includes:

[0114] The read unit is configured to read message parsing files;

[0115] The identification unit is configured to identify and segment the first message frame based on the message parsing file to determine the first signal bit and the first check bit of the first message frame.

[0116] In some embodiments, the search module 603 described above includes:

[0117] The information acquisition unit is configured to acquire the classification tag information corresponding to each verification program in the first verification program library;

[0118] The filtering unit is configured to filter at least one first verification program from the first verification program library based on the classification label information and the first redundant segment, forming a first verification program set.

[0119] In some embodiments, the filtering module 605 described above includes:

[0120] The first determining unit is configured to determine the first verification program in the first set of verification programs whose first verification result matches the first verification bit as a candidate verification program;

[0121] The second determining unit is configured to determine the candidate verification program as the target verification program that matches the verification method of the target controller if the number of candidate verification programs is one.

[0122] In some embodiments, the filtering module 605 described above further includes:

[0123] The constituent unit is configured to form a second set of check procedures if the number of candidate check procedures is at least two.

[0124] The message acquisition unit is configured to acquire the second message frame sent by the target controller;

[0125] The third determining unit is configured to determine the second signal bit and the second check bit of the second message frame, wherein the second signal bit includes a second valid signal segment and a second redundant segment, and the second redundant segment is different from the first redundant segment;

[0126] The fourth determining unit is configured to determine the second verification result corresponding to each candidate verification procedure in the second verification procedure set based on the second signal bit.

[0127] The first filtering unit is configured to select a target verification program from the second set of verification programs that matches the verification method of the target controller, based on the second verification bit and the second verification result.

[0128] In some embodiments, the filtering module 605 described above further includes:

[0129] The refresh unit is configured to send a refresh request to the server if the number of candidate check programs is zero, so that the server refreshes the first check program library based on the refresh request to obtain the second check program library.

[0130] The lookup unit is configured to look up a third set of check programs that matches the first redundant segment from a second check program library, wherein the third set of check programs includes at least one third check program.

[0131] The fifth determining unit is configured to determine the third verification result corresponding to each third verification procedure based on the first signal bit;

[0132] The second filtering unit is configured to select a target verification program from the third set of verification programs that matches the verification method of the target controller, based on the first verification bit and the third verification result.

[0133] In some embodiments, the above-described apparatus further includes:

[0134] The signal acquisition module is configured to acquire the control signal values ​​input from the test bench;

[0135] The message generation module is configured to generate control message frames based on the target verification program and control signal values.

[0136] The sending module is configured to send control message frames to the target ECU.

[0137] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0138] Figure 7 This is a schematic diagram of the electronic device 7 provided in an embodiment of this application. Figure 7 As shown, the electronic device 7 of this embodiment includes a processor 701, a memory 702, and a computer program 703 stored in the memory 702 and executable on the processor 701. When the processor 701 executes the computer program 703, it implements the steps in the various method embodiments described above. Alternatively, when the processor 701 executes the computer program 703, it implements the functions of each module / unit in the various device embodiments described above.

[0139] Electronic device 7 can be a desktop computer, laptop, handheld computer, cloud server, or other electronic device. Electronic device 7 may include, but is not limited to, processor 701 and memory 702. Those skilled in the art will understand that... Figure 7 This is merely an example of electronic device 7 and does not constitute a limitation on electronic device 7. It may include more or fewer components than shown, or different components.

[0140] The processor 701 can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.

[0141] The memory 702 can be an internal storage unit of the electronic device 7, such as a hard disk or RAM of the electronic device 7. The memory 702 can also be an external storage device of the electronic device 7, such as a plug-in hard disk, Smart Media Card (SMC), Secure Digital (SD) card, Flash Card, etc., equipped on the electronic device 7. The memory 702 can also include both internal and external storage units of the electronic device 7. The memory 702 is used to store computer programs and other programs and data required by the electronic device.

[0142] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0143] If integrated modules / units are implemented as software functional units and sold or used as independent products, they can be stored in a readable storage medium (e.g., a computer-readable storage medium). Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program may include computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. A computer-readable storage medium may include: any entity or device capable of carrying computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc.

[0144] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A method of automatically matching a verification procedure, characterized by, The method comprises the following steps: obtaining a message frame set sent by a controller group currently mounted on a test bench, wherein the controller group comprises at least two different target controllers, and the message frame set comprises at least two first message frames, one first message frame corresponding to one target controller; determining, for each first message frame corresponding to a target controller, a first signal bit and a first check bit of the first message frame, wherein the first signal bit comprises a first effective signal segment and a first redundant segment; finding a first check program set matched with the first redundant segment from a first check program library, wherein the first check program set comprises at least one first check program, and the first check program library comprises check programs corresponding to various different controllers for mounting a test bench test; determining, based on the first signal bit, a first check result corresponding to each first check program; determining, as a candidate check program, a first check program in the first check program set whose first check result is consistent with the first check bit; if the number of candidate check programs is at least two, then grouping at least two candidate check programs to form a second check program set; obtaining a second message frame sent by the target controller; determining a second signal bit and a second check bit of the second message frame, wherein the second signal bit comprises a second effective signal segment and a second redundant segment, and the second redundant segment is different from the first redundant segment; determining, based on the second signal bit, a second check result corresponding to each candidate check program in the second check program set; based on the second check bit and the second check result, screening a target check program matched with the check mode of the target controller from the second check program set.

2. The method of claim 1, wherein, The method for determining the first signal bit and the first check bit of the first message frame comprises the following steps: reading a message analysis file; based on the message analysis file, identifying and field dividing the first message frame to determine the first signal bit and the first check bit of the first message frame.

3. The method of claim 1, wherein, The method for finding a first check program set matched with the first redundant segment from a first check program library comprises the following steps: obtaining classification mark information corresponding to each check program in the first check program library; based on the classification mark information and the first redundant segment, screening at least one first check program from the first check program library to form a first check program set.

4. The method of claim 1, wherein, After determining, as a candidate check program, a first check program in the first check program set whose first check result is consistent with the first check bit, the method further comprises the following steps: if the number of candidate check programs is one, then determining the candidate check program as a target check program matched with the check mode of the target controller.

5. The method of claim 1, wherein, After determining, as a candidate check program, a first check program in the first check program set whose first check result is consistent with the first check bit, the method further comprises the following steps: if the number of candidate check programs is zero, then sending a refresh request to a server to make the server, based on the refresh request, refresh the first check program library to obtain a second check program library; finding a third check program set matching the first redundant segment from the second check program library, wherein the third check program set comprises at least one third check program; determining a third check result corresponding to each of the third check programs based on the first signal bit; screening a target check program matching the check mode of the target controller from the third check program set based on the first check bit and the third check result.

6. The method of claim 1, wherein, The method further comprises: obtaining a control signal value input by the test bench; generating a control message frame based on the target check program and the control signal value; sending the control message frame to the target ECU.

7. An apparatus for automatically matching a verification procedure, characterized by comprises: an obtaining module configured to obtain a message frame set sent by a controller group currently carried by a test bench, wherein the controller group comprises at least two different target controllers, and the message frame set comprises at least two first message frames, one first message frame corresponding to one target controller; a first determining module configured to determine a first signal bit and a first check bit of each first message frame corresponding to each of the target controllers, wherein the first signal bit comprises a first effective signal segment and a first redundant segment; a finding module configured to find a first check program set matching the first redundant segment from a first check program library, wherein the first check program set comprises at least one first check program, and the first check program library comprises check programs corresponding to various different controllers for bench test; a second determining module configured to determine a first check result corresponding to each of the first check programs based on the first signal bit; a screening module configured to determine, as a candidate check program, a first check program in the first check program set whose first check result is consistent with the first check bit; if the number of the candidate check programs is at least two, to form a second check program set by at least two of the candidate check programs; to obtain a second message frame sent by the target controller; to determine a second signal bit and a second check bit of the second message frame, wherein the second signal bit comprises a second effective signal segment and a second redundant segment, and the second redundant segment is different from the first redundant segment; to determine a second check result corresponding to each of the candidate check programs in the second check program set based on the second signal bit; and to screen a target check program matching the check mode of the target controller from the second check program set based on the second check bit and the second check result.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, The processor executes the computer program to implement the steps of the method according to any one of claims 1 to 6.

9. A readable storage medium, the readable storage medium storing a computer program, characterized in that, The computer program is executed by the processor to implement the steps of the method according to any one of claims 1 to 6.

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