Chip embedding structure of hybrid integrated circuit and preparation method thereof

Abstract

The present invention provides a chip embedding structure for a hybrid integrated circuit and a preparation method thereof. The structure comprises a packaging substrate (1), a embedding groove (11) and a BGA solder ball (2) provided on the packaging substrate (1), a multi-layer chip interconnection component (3) connected in the embedding groove (11), an AlN substrate (5) connected on the multi-layer chip interconnection component (3), a thermally conductive insulating adhesive (6) filled in the embedding groove (11), and the AlN substrate (5) electrically connected to the conductor of the packaging substrate by gold wire ball bonding. The preparation method provided by the present invention adopts a multi-layer chip interconnection component embedded structure, significantly improving the integration efficiency, functional density and heat dissipation capacity of the chip embedding circuit, fully utilizing the internal structural space, and improving the high-density integration level and packaging reliability.

Description

Technical Field

[0001] The present invention belongs to the technical field of hybrid integrated circuits, and in particular relates to a hybrid integrated circuit chip and a preparation method thereof. Background Art

[0002] High-density hybrid integrated circuits (HIICs) require both a high-density multilayer wiring substrate and high-density assembly and interconnection of components, typically chips. Typically, these components are assembled and interconnected on the surface of the circuit substrate. However, as users and systems demand ever-increasing miniaturization and integration of HICs, the industry is increasingly adopting the method of embedding chips and other components within the substrate to achieve even higher-density integration, particularly in the field of system integration.

[0003] Currently, embedding chips within a packaging substrate typically involves embedding a single layer of chips at the embedding location, and lacks specific heat dissipation considerations. For example, prior art methods for reducing the positional deviation between chip embedding and photolithographic patterning (CN110517961A) and a substrate structure with an embedded chip and a light-emitting device using the same (CN11208645A) both involve chip embedding, but are targeted at embedding a single chip rather than 3D stacked chips. This hinders full utilization of the internal structural space of a multi-layer wiring substrate, hinders further improvement in the integration level and functional density of circuits and systems, and lacks effective countermeasures when heat dissipation issues become prominent, hindering performance and reliability improvements in hybrid integrated packaging. Summary of the Invention

[0004] The present invention aims to overcome the deficiencies in the prior art and provides a chip embedding structure for a hybrid integrated circuit and a preparation method thereof.

[0005] This application provides the following technical solutions:

[0006] A method for preparing a chip embedded structure of a hybrid integrated circuit, characterized in that it comprises the following steps:

[0007] S1, taking a ceramic packaging substrate, on which a buried groove is provided;

[0008] S2. A group of BGA solder balls are evenly distributed on the bottom surface of the package substrate;

[0009] S3. A group of heat dissipation holes are evenly distributed on the bottom surface of the buried groove. The heat dissipation holes are filled with heat dissipation metal pillars and are also used for electrical connection between the front and back sides of the packaging substrate. A conductive metal layer covering the heat dissipation holes is provided on the bottom surface of the buried groove;

[0010] S4. A multi-layer chip interconnection assembly is provided on the metal layer, the multi-layer chip interconnection assembly including a top chip, a plurality of stacked chips and a bottom chip distributed vertically from top to bottom, a PAD welding area is provided on the upper surface of the stacked chip, a group of first conductive bumps corresponding to the PAD welding area are distributed on the lower surface of the top chip and the stacked chip, a group of through-silicon vias are provided on the stacked chip and the bottom chip, a group of blind vias opening downward are provided on the top chip, the through-silicon vias and the blind vias are filled with conductive metal, one end of the conductive metal is electrically connected to the corresponding first conductive bump, and the other end is electrically connected to the PAD welding area, and then a group of second conductive bumps are provided on the bottom surface of the bottom chip, one end of the conductive metal in the bottom chip is electrically connected to the corresponding second conductive bump, and the other end is electrically connected to the PAD welding area;

[0011] S5. A graphene composite thermally conductive film is placed between the top chip and the topmost stacked chip, between each layer of stacked chips, and between the bottommost stacked chip and the bottom chip. The graphene composite thermally conductive film is provided with clearance holes distributed corresponding to the first conductive bumps. The additives compounded with graphene in the graphene composite thermally conductive film include fluorinated graphene and polyimide. An insulating adhesive layer is provided on the graphene composite thermally conductive film. An insulating adhesive layer is also provided on the hole walls of the clearance holes. The insulating adhesive layer is doped with amorphous polytetrafluoroethylene and nano-aluminum nitride powder. The adjacent chips are connected to each other by first welding using nano-silver paste, and the upper and lower surfaces of the adjacent chips are connected by the graphene thermally conductive film adhesive layer, thereby forming a multi-layer chip interconnection component.

[0012] S6, coating the metal layer with nano silver paste, and then placing the multi-layer chip interconnection assembly so that the second conductive bump contacts the nano silver paste, completing the nano silver paste welding interconnection between the chip interconnection assembly and the metal layer;

[0013] S7. Fill the buried trench with thermally conductive insulating adhesive, which is made of the same material as the epoxy adhesive layer. Fill the gaps between the multi-layer chip interconnect assembly and the buried trench wall, and between the multi-layer chip interconnect assembly and the bottom surface of the buried trench, until the thermally conductive insulating adhesive is flush with the top surface of the top chip. Then, cure the thermally conductive insulating adhesive according to the applicable temperature and time. The thermally conductive insulating adhesive is made of the same material as the insulating adhesive layer.

[0014] S8, bonding an AlN substrate with multi-layer wiring to the upper surface of the top chip using nano silver paste;

[0015] S9. Use gold wire ball bonding to achieve electrical connection between the PAD area of ​​the AlN substrate and the conductor of the packaging substrate.

[0016] On the basis of the above technical solutions, the following technical solutions can also be adopted:

[0017] During the first welding in step S5, the welding temperature is greater than the temperature during the eutectic welding of the chip interconnect component and the metal layer in step S6.

[0018] The heat dissipation metal column in S3 is silver or silver alloy.

[0019] The metal layers in S3 and S6 are gold conductors.

[0020] In S5 , nano silver paste is coated on the surface of the PAD soldering area, and the total height of the graphene composite thermal conductive film and the insulating adhesive layer is greater than the height of the first conductive bump and less than the sum of the height of the first conductive bump and the coating thickness of the nano silver paste.

[0021] A chip embedding structure for a hybrid integrated circuit manufactured by a method for embedding a chip of a hybrid integrated circuit comprises: a packaging substrate, a embedding groove provided on the packaging substrate, and is characterized in that: a group of BGA solder balls are provided on the bottom surface of the packaging substrate; a multi-layer chip interconnection assembly is provided in the embedding groove, the embedding groove is filled with thermally conductive insulating adhesive, an AlN substrate with multi-layer wiring is provided on the upper surface of the multi-layer chip interconnection assembly, and an electrical connection is formed between the AlN substrate and the packaging substrate through gold wire.

[0022] The multi-layer chip interconnection assembly includes a plurality of stacked chips distributed vertically from top to bottom, a top chip, and a bottom chip. The upper surface of the stacked chips is provided with a PAD welding area, and a group of first conductive bumps corresponding to the PAD welding area are distributed on the lower surface of the stacked chips. A group of through-silicon vias are provided on the stacked chips and the bottom chip. A group of blind vias with downward openings is provided on the top chip. The through-silicon vias and the blind vias are filled with conductive metal, one end of the conductive metal is electrically connected to the corresponding first conductive bump, and the other end is electrically connected to the PAD welding area. Then, a group of second conductive bumps are provided on the bottom surface of the bottom chip, one end of the conductive metal in the bottom chip is electrically connected to the corresponding second conductive bump, and the other end is electrically connected to the PAD welding area.

[0023] A graphene composite thermally conductive film is placed between the top chip and the uppermost stacked chip, between each layer of stacked chips, and between the bottommost stacked chip and the bottom chip. The graphene composite thermally conductive film is provided with clearance holes corresponding to the first conductive bumps, an insulating adhesive layer is provided on the graphene composite thermally conductive film, and an insulating adhesive layer is also provided on the hole walls of the clearance holes. The first welding interconnection between adjacent chips is completed by nano silver paste, and the connection between the upper surface and the lower surface of adjacent chips is achieved through the graphene thermally conductive film adhesive layer, thereby forming a multi-layer chip interconnection component.

[0024] The volume of the second conductive bump is larger than that of the first conductive bump.

[0025] A group of heat dissipation holes are evenly distributed on the bottom surface of the buried groove, and heat dissipation metal columns made of silver are filled in the heat dissipation holes. A conductive metal layer covering the heat dissipation holes is provided on the bottom surface of the buried groove.

[0026] Advantages of the invention:

[0027] The fabrication method provided by the present invention utilizes a TSV-based embedded multi-layer chip interconnect assembly structure. Furthermore, this embedded multi-layer chip interconnect assembly incorporates a specialized packaging design, significantly improving the integration efficiency, functional density, and heat dissipation capabilities of the embedded chip circuits. This fully utilizes the internal structural space, thereby enhancing the overall high-density integration level and packaging reliability of the system-level hybrid integrated package. Specifically, a graphene composite thermally conductive film is used between adjacent chips in the multi-layer chip interconnect assembly, providing superior heat dissipation compared to thermally conductive adhesives. The additives composited with graphene in the thermal conductive film include fluorinated graphene and polyimide (PI), which improve the flexibility, electrical insulation, thermal conductivity and flame retardancy of the thermal conductive film; a layer of insulating adhesive is coated on the surface of the film, and the adhesive layer is doped with amorphous polytetrafluoroethylene and nano-aluminum nitride powder, which can improve the thermal conductivity and high-frequency performance of the adhesive layer, and ensure the high-performance thermal conductivity of the graphene composite film; the upper and lower surfaces of the film and the inner surface of the hole are coated with insulating adhesive, while ensuring electrical insulation between the bumps and between the upper and lower surfaces of adjacent chips; the thickness of the entire film (including the surface adhesive layer) is greater than the bump height and less than the sum of the bump height and the nano-silver paste coating thickness, which can ensure that the adhesive surface of the film is in full contact and bonding with the chip, and that the first conductive bump is in full contact and bonding with the nano-silver paste, while meeting the chip heat dissipation and bump connection requirements. The thermally conductive insulating adhesive in the buried trench is the same adhesive as the adhesive on the surface of the thermally conductive film, thus also improving the thermal conductivity and high-frequency performance of the colloid filling. Since the filling adhesive and adhesive are the same, thermal compatibility between the two is maximized, minimizing the thermal stress impact on the multi-layer chip interconnect assembly. The top chip in the multi-layer chip interconnect assembly is provided with a semi-through hole, with no opening on the chip's top surface. The hole is filled with conductive metal, which can achieve both thermal conductivity and electrical connection of the chip. The entire top surface of the top chip is assembled with a multi-layer aluminum nitride substrate using nanosilver paste. The aluminum nitride surface has a metallized layer, which not only provides sufficient heat dissipation for the interconnected component chip, but also achieves three-dimensional electrical interconnection with the packaging substrate through bonding. The conductive metal is filled in the chip's silicon through-hole via, which not only provides electrical conductivity on the top and bottom of the chip, but also serves as a heat dissipation channel. The thermal conductive pillars on the bottom of the packaging substrate not only provide heat dissipation but also serve as electrical interconnection between the inside and outside of the buried trench of the packaging substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 This is a schematic diagram of a chip embedding structure of a hybrid integrated circuit manufactured by adopting a preparation method for embedding a chip of a hybrid integrated circuit provided by the invention;

[0029] Figure 2 yes Figure 1 A-axis enlarged view. DETAILED DESCRIPTION

[0030] like Figure 1 and 2 As shown, a method for preparing a chip embedded structure of a hybrid integrated circuit comprises the following steps:

[0031] S1 . Take a ceramic package substrate 1 for a chip, on which a buried groove 11 is provided.

[0032] S2. A group of BGA solder balls 2 are evenly prepared on the bottom surface 1 of the package substrate.

[0033] S3. A group of heat dissipation holes 12 are evenly distributed on the bottom surface of the buried groove 11. The heat dissipation metal columns 13 made of silver are filled in the heat dissipation holes 12, which are also used for electrical connection between the front and back sides of the packaging substrate. A conductive metal layer 14 covering the heat dissipation holes 12 is provided on the bottom surface of the buried groove 1. The metal layer 14 is a gold conductor.

[0034] S4. A multi-layer chip interconnection assembly 3 is provided on the metal layer 13. The multi-layer chip interconnection assembly 3 includes a top chip 3a, a plurality of stacked chips 3b and a bottom chip 3e located at the bottom layer, which are vertically distributed from top to bottom.

[0035] Each stacked chip 3b has a PAD pad on its top surface and a set of first conductive bumps 3c distributed uniformly on its bottom surface, corresponding to the PAD pads. A set of through-silicon vias 3h is provided on each stacked chip 3b, and a set of downward-facing blind vias 3k is provided on the top chip 3a. Both the through-silicon vias 3h and the blind vias 3k are filled with conductive metal 3d, a copper columnar structure.

[0036] One end of the conductive metal 3d contacts the corresponding first conductive bump 3c, and the other end contacts the PAD pad, so that the first conductive bump 3c and the PAD pad are electrically connected to each other through the conductive metal 3d.

[0037] A set of second conductive bumps 4 are provided on the bottom surface of the bottom chip 3e. The volume of the second conductive bumps 4 is larger than that of the first conductive bumps 3c. One end of the conductive metal 3d in the bottom chip 3e is electrically connected to the corresponding second conductive bump 4, and the other end is electrically connected to the PAD pad.

[0038] S5. A graphene composite thermally conductive film 3g is placed between the top chip and the topmost stacked chip, between each stacked chip, and between the bottommost stacked chip 3b and the bottom chip 3e. The graphene-composite additives in the film include fluorinated graphene and polyimide (PI). The graphene composite thermally conductive film 3g is provided with clearance holes corresponding to the first conductive bumps 3c. An epoxy adhesive layer 13g is also applied to the surface of the graphene composite thermally conductive film 3g and the inner walls of the clearance holes. The epoxy adhesive layer 13g is also doped with amorphous polytetrafluoroethylene and nano-aluminum nitride powder.

[0039] A nanosilver paste solder layer 3j is also placed between the first conductive bump 3c and the underlying chip 3e. Assuming the height of the chip's first conductive bump 3c is d1 and the thickness of the nanosilver paste solder layer 3j is d2, the thickness of the entire graphene composite thermally conductive film plus the epoxy adhesive layer 13g is between d1 and d1 + d2. Adjacent chips 3a are interconnected by a primary soldering connection using the nanosilver paste, while the graphene composite thermally conductive film 3g provides an adhesive and heat dissipating connection between adjacent chips, thereby forming a multi-layer chip interconnect assembly 3.

[0040] S6. Nanosilver paste is applied to the metal layer 14. The multilayer chip interconnect assembly 3 is then placed into the buried groove 11 so that the second conductive bump 4 contacts the nanosilver paste. The chip interconnect assembly 3 and the metal layer 14 are then soldered together using the nanosilver paste in a eutectic soldering furnace under vacuum. The soldering temperature used in this eutectic soldering is 30°C-40°C lower than the first soldering temperature in step S5.

[0041] S7. Fill the perimeter of the multi-layer chip interconnect assembly 3 within the embedded trench 11 with thermally conductive insulating adhesive 6, ensuring that the adhesive fills the gaps between the chips on different layers of the multi-layer chip interconnect assembly 3 and between the adhesive and the walls of the embedded trench 11 until the adhesive is flush with the top surface of the top chip 3a. The adhesive is then cured at the appropriate temperature and for the appropriate time. The adhesive 6 is made of the same material (composition) as the epoxy adhesive layer 13g, ensuring that their coefficients of thermal expansion are consistent and preventing any issues arising from differences in their contact coefficients.

[0042] S8. The AlN substrate 5 with multi-layer wiring is bonded to the upper surface of the top stacked chip 3b via the nano silver paste 8.

[0043] S9. Using gold wire ball bonding, the PAD area on the AlN substrate is electrically connected to the conductor on the package substrate 1 through the gold wire 7, thereby obtaining a chip embedded structure of a hybrid integrated circuit.

[0044] A chip embedding structure for a hybrid integrated circuit comprises a ceramic packaging substrate 1 for the chip, an embedding groove 11 is provided on the packaging substrate 1, and a group of BGA solder balls 2 are arranged on the bottom surface 1 of the packaging substrate.

[0045] A group of heat dissipation holes 12 are evenly distributed on the bottom surface of the buried groove 11 . The heat dissipation holes 12 are filled with silver heat dissipation metal columns 13 . A conductive metal layer 14 covering the heat dissipation holes 12 is provided on the bottom surface of the buried groove 11 .

[0046] A multi-layer chip interconnection component 3 is connected to the metal layer 14, and the multi-layer chip interconnection component 3 includes a top chip 3a, a plurality of stacked chips 3b and a bottom chip 3e distributed vertically from top to bottom. The upper surface of the stacked chip 3b is provided with a PAD welding area, and a group of first conductive bumps 3c corresponding to the PAD welding area are distributed on the lower surface of the top chip 3a and the stacked chip 3b. A group of through-silicon vias 3h are provided on the stacked chip 3b and the bottom chip 3e. A group of blind vias 3k opening downward is provided on the top chip 3a. The through-silicon vias 3h and the blind vias 3k are filled with conductive metal 3d. One end of the conductive metal 3d is electrically connected to the corresponding first conductive bump 3c, and the other end is electrically connected to the PAD welding area. Then, a group of second conductive bumps 4 are provided on the bottom surface of the bottom chip 3e. One end of the conductive metal 3d in the bottom chip 3e is electrically connected to the corresponding second conductive bump 4, and the other end is electrically connected to the PAD welding area.

[0047] A graphene composite thermal conductive film 3g is placed between the top chip 3a and the topmost stacked chip 3b, between each layer of stacked chips, and between the bottommost stacked chip 3b and the bottom chip 3e. The graphene composite thermal conductive film 3g is provided with clearance holes (not shown in the figure) distributed corresponding to the first conductive bumps 3c.

[0048] An insulating adhesive layer 13g is applied to the graphene composite thermally conductive film 3g, and an insulating adhesive layer is also applied to the walls of the clearance holes. Adjacent chips are connected by a nanosilver paste for a first soldering connection, and the graphene thermally conductive film adhesive layer connects the top and bottom surfaces of adjacent chips, thereby forming a multi-layer chip interconnect assembly 3.

[0049] The buried groove 11 is filled with thermally conductive insulating adhesive 6, and a multi-layer wiring AlN substrate 5 is bonded to the upper surface of the multi-layer chip interconnection component 3. An electrical connection is formed between the AlN substrate 5 and the conductor on the packaging substrate 1 through a gold wire 7.

Claims

1. A method for preparing a chip embedded structure of a hybrid integrated circuit, characterized in that: It includes the following steps: S1, taking a ceramic packaging substrate (1), and providing an embedded groove (11) on the packaging substrate (1); S2, a group of BGA solder balls (2) are evenly distributed on the bottom surface of the packaging substrate (1); S3. A group of heat dissipation holes (12) are evenly distributed on the bottom surface of the buried groove (11), and heat dissipation metal columns (13) are filled in the heat dissipation holes (12). The heat dissipation holes (12) are also used for electrical connection between the front and back sides of the packaging substrate. A conductive metal layer (14) covering the heat dissipation holes (12) is provided on the bottom surface of the buried groove (11); S4. A multi-layer chip interconnection component (3) is provided on the metal layer (14). The multi-layer chip interconnection component (3) includes a top chip (3a), a plurality of stacked chips (3b) and a bottom chip (3e) distributed longitudinally from top to bottom. The top surface of the stacked chip (3b) is provided with a PAD welding area. A group of first conductive bumps (3c) distributed corresponding to the PAD welding area are distributed on the bottom surface of the top chip (3a) and the stacked chip (3b). A group of through-silicon vias (3h) are provided on the stacked chip (3b) and the bottom chip (3e). A group of blind holes (3k) opening downward are provided on the top chip (3a). The through-silicon vias (3h) and the blind holes (3k) are filled with conductive metal (3d). One end of the conductive metal (3d) is electrically connected to the corresponding first conductive bump (3c), and the other end is electrically connected to the PAD welding area. Then, a group of second conductive bumps (4) are provided on the bottom surface of the bottom chip (3e). One end of the conductive metal (3d) in the bottom chip (3e) is electrically connected to the corresponding second conductive bump (4), and the other end is electrically connected to the PAD welding area; S5, a graphene composite thermal conductive film is placed between the top chip (3a) and the topmost stacked chip (3b), between each stacked chip (3b), and between the bottommost stacked chip (3b) and the bottom chip (3e); a clearance hole corresponding to the first conductive bump (3c) is provided on the graphene composite thermal conductive film (3g); an additive compounded with graphene in the graphene composite thermal conductive film (3g) includes fluorinated graphene and polyimide; an insulating adhesive layer (13g) is provided on the graphene composite thermal conductive film; an insulating adhesive layer (13g) is also provided on the hole wall of the clearance hole; amorphous polytetrafluoroethylene and nano-aluminum nitride powder are doped in the insulating adhesive layer (13g); adjacent chips are connected to each other by first welding through nano silver paste, and the upper surface and lower surface of adjacent chips are connected by the graphene thermal conductive film adhesive layer, thereby forming a multi-layer chip interconnection component (3); S6, coating the metal layer (14) with nano silver paste, and then placing the multi-layer chip interconnection component (3) so that the second conductive bump (4) is in contact with the nano silver paste, completing the nano silver paste welding interconnection between the chip interconnection component (3) and the metal layer (14); S7, filling the embedded groove (11) with a thermally conductive insulating adhesive (6), the thermally conductive insulating adhesive (6) filling the gap between the multi-layer chip interconnection component (3) and the embedded groove (11) wall, and the gap between the multi-layer chip interconnection component (3) and the inner bottom surface of the embedded groove (11), until the thermally conductive insulating adhesive (6) is flush with the upper surface of the top chip (3a), and then the thermally conductive insulating adhesive (6) is cured according to the applicable temperature and time, and the thermally conductive insulating adhesive (6) and the insulating adhesive layer (13g) are made of the same material; S8, bonding an AlN substrate (5) having a multilayer wiring layer to the upper surface of the top chip (3a) by using a nano silver paste; S9. Use gold wire ball bonding to achieve electrical connection between the PAD area of ​​the AlN substrate and the conductor of the packaging substrate.

2. The method for preparing a chip embedded structure of a hybrid integrated circuit according to claim 1, characterized in that: During the first welding in step S5, the welding temperature is greater than the temperature during the eutectic welding of the chip interconnection component (3) and the metal layer (14) in step S6.

3. The method for preparing a chip embedded structure of a hybrid integrated circuit according to claim 1, characterized in that: The heat dissipation metal column (13) in S3 is silver or a silver alloy.

4. The method for preparing a chip embedded structure of a hybrid integrated circuit according to claim 1, characterized in that: The metal layer (14) in S3 and S6 is a gold conductor.

5. The method for preparing a chip embedded structure of a hybrid integrated circuit according to claim 1, characterized in that: Nano silver paste is coated on the surface of the PAD soldering area in S5, and the total height of the graphene composite thermal conductive film (3g) and the insulating adhesive layer (13g) is greater than the height of the first conductive bump (3c) and less than the sum of the height of the first conductive bump (3c) and the coating thickness of the nano silver paste.

6. A chip-embedded structure for a hybrid integrated circuit manufactured by the method for embedding a chip for a hybrid integrated circuit according to claim 1, comprising: A packaging substrate (1) is provided with an embedded groove (11) on the packaging substrate (1), characterized in that: a group of BGA solder balls (2) are evenly provided on the bottom surface (1) of the packaging substrate; a multi-layer chip interconnection component (3) is provided in the embedded groove (11), the embedded groove (11) is filled with a thermally conductive insulating adhesive (6), an AlN substrate (5) with multi-layer wiring is provided on the upper surface of the multi-layer chip interconnection component (3), and an electrical connection is formed between the AlN substrate (5) and the packaging substrate (1) through a gold wire (7).

7. A chip embedding structure for a hybrid integrated circuit according to claim 6, characterized in that: The multi-layer chip interconnection component (3) includes a top chip (3a), a plurality of stacked chips (3b) and a bottom chip (3e) distributed longitudinally from top to bottom, the top surface of the stacked chip (3b) is provided with a PAD welding area, a group of first conductive bumps (3c) distributed corresponding to the PAD welding area are distributed on the bottom surface of the top chip (3a) and the stacked chip (3b), a group of through-silicon vias (3h) are provided on the stacked chip (3b) and the bottom chip (3e), a group of blind holes (3k) with downward openings are provided on the top chip (3a), and the through-silicon vias (3h) and the blind holes (3k) are filled with conductive metal (3d), one end of the conductive metal (3d) is electrically connected to the corresponding first conductive bump (3c), and the other end is electrically connected to the PAD welding area, and then a group of second conductive bumps (4) are provided on the bottom surface of the bottom chip (3e). One end of the conductive metal (3d) in the bottom chip (3e) is electrically connected to the corresponding second conductive bump (4), and the other end is electrically connected to the PAD welding area; A graphene composite thermal conductive film (3g) is placed between the top chip (3a) and the topmost stacked chip (3b), between each stacked chip layer, and between the bottommost stacked chip (3b) and the bottom chip (3e). The graphene composite thermal conductive film (3g) is provided with a clearance hole distributed corresponding to the first conductive bump (3c). An insulating adhesive layer (13g) is provided on the graphene composite thermal conductive film (3g), and an insulating adhesive layer (13g) is also provided on the hole wall of the clearance hole. The first welding interconnection between adjacent chips is completed by nano silver paste, and the connection between the upper surface and the lower surface of adjacent chips is achieved by the graphene thermal conductive film adhesive layer, thereby forming a multi-layer chip interconnection component (3).

8. A chip embedding structure for a hybrid integrated circuit according to claim 7, characterized in that: The volume of the second conductive bump (4) is larger than that of the first conductive bump (3c).

9. A chip embedding structure for a hybrid integrated circuit according to claim 7, characterized in that: A group of heat dissipation holes (12) are evenly distributed on the bottom surface of the embedded groove (11), the heat dissipation holes (12) are filled with silver heat dissipation metal columns (13), and a conductive metal layer (14) covering the heat dissipation holes (12) is provided on the bottom surface of the embedded groove (11).

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