Method for producing semiconductor element using carrier wafer and semiconductor element

By applying the carrier wafer using the cofferdam filling method step in the semiconductor component manufacturing process, the problems of large substrate tension and difficult processing are solved, and mechanical stability of the wafer and efficient manufacturing of semiconductor components are achieved.

CN119560435APending Publication Date: 2025-03-04ROBERT BOSCH GMBH
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Patent Information

Application Number
CN202411234376.9
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Priority Date
2023-09-04
Filing Date
2024-09-04
Publication Date
2025-03-04

AI Technical Summary

Technical Problem

When manufacturing semiconductor components, especially power semiconductor components, in the prior art, the substrate tension is high due to extremely thinning of materials or multiple bonding, resulting in fragile substrates, making it difficult to further process or difficult to process.

Method used

Through the cofferdam filling method step, the carrier wafer is applied to the wafer surface, providing a stable carrier layer, and the thickness and tension of the substrate are reduced by the application of the carrier wafer and subsequent thinning process.

Benefits of technology

Mechanical stability of the wafer in subsequent method steps is achieved, simplifying the processing and handling of the wafer, reducing the risk of the wafer bow, and improving the manufacturability and testing speed of semiconductor components.

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Abstract

The invention relates to a method for producing a semiconductor element, in particular a power semiconductor element, from a wafer, comprising the following steps:-providing a wafer substrate (101),-treating a structured wafer surface (102),-applying a carrier wafer (103) to the wafer substrate (101), and-reducing the thickness of the wafer substrate (101) by wafer thinning, characterized in that the wafer substrate (101) is provided with a substrate surface (102), and the substrate surface (102) is provided with a substrate surface (102). The carrier wafer (103) is applied to the wafer surface (102) by a cofferdam filling method step. The invention also relates to a corresponding semiconductor component.
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Description

Technical Field

[0001] The invention relates to a method for producing semiconductor components from wafers by using a carrier wafer, in particular a carrier wafer which has been applied by means of a dam-and-fill method step. Background Art

[0002] In order to produce power semiconductors or semiconductor chips, wafers made of materials such as silicon (Si), silicon carbide or sapphire with a diameter of, for example, 150 mm, 200 mm or 300 mm are usually processed via a plurality of individual steps. It is known that substrates are bonded to wafers in order to produce products in the field of MEMS and power semiconductor technology, for example, in order to support the grinding of very thin wafers for execution reasons during the manufacturing process. In this case, the provision of a temporary carrier wafer made of a strong material such as quartz or silicon carbide is also used to mechanically stabilize the wafer during the processing and to simplify handling. In addition, wafer bending or so-called wafer bowing can be minimized. In particular, wafers with deep groove structures or thick passivation and metallization layers (which are the cause of wafer bowing) can hardly be processed without a carrier wafer when the chip thickness is less than 150 μm.

[0003] A disadvantage of the known methods is that due to the extreme thinning or multiple bonding (wafer stacking) of wafers and substrates of different materials, the extreme tensions that arise, in particular in connection with thick layers such as metal layers, passivation layers and the deep trenches that are common in power semiconductor technology, cause the substrate to become brittle, so that it can no longer be processed or can only be processed further with great effort. Summary of the invention

[0004] The invention relates to a method for producing semiconductor components, in particular power semiconductor components, from a wafer, comprising the following steps:

[0005] - providing a wafer substrate,

[0006] - processing of structured wafer surfaces,

[0007] - applying a carrier wafer to the wafer substrate, and

[0008] - Reducing the thickness of the wafer substrate by wafer thinning, wherein, according to the invention, a carrier wafer is applied to the wafer surface by a dam filling method step.

[0009] Advantageous developments of the method according to the invention for producing a plurality of semiconductor components from a wafer are listed below.

[0010] By applying the carrier wafer to the wafer surface by the dam filling method step or dam filling process according to the invention, a carrier layer that stabilizes the wafer can be applied to the front side of the finished wafer in an effective manner, and the wafer is mechanically stabilized in subsequent method steps, in particular in the wafer thinning process for reducing the substrate thickness. In addition to the simple coating method, the provision of the carrier wafer according to the invention also compensates for tension in the system. Here, compared with a pure additive manufacturing carrier layer, a significantly higher filled layer thickness can be applied, which provides clear advantages in terms of shrinkage behavior during curing and possible CTE mismatch between the carrier system and the wafer. The printed carrier layer also serves as an insulator at the same time, so that the flashover risk is reduced in the case of breakdown voltages of up to about 1600V during electrical testing, so that multiple test heads can be used for higher test speeds. In addition, the carrier can remain on the wafer until the final method step of wafer cutting or dividing the wafer into individual semiconductor components, thereby significantly simplifying the handling of thin wafers in the final process, improving manufacturability and reducing error costs. Therefore, the method according to the invention makes it possible to optimize process control and manufacture semiconductor components more reliably.

[0011] The steps of the weir filling method advantageously include applying at least one delimiting frame structure or edge structure in the form of a weir with a predefined height surrounding a volume by means of digital printing techniques known per se, and filling the volume created here or delimited by the frame structure with a filling material, preferably by means of a glue dispensing or glue dispensing step known per se. The frame structure and the filling can be cured individually or together in a manner known per se, for example by means of UV or heat.

[0012] In this case, the application of ink for providing the weir or frame structure can be carried out in a manner known per se by means of a corresponding print head which is arranged to be movable relative to the wafer surface or the working surface supporting the wafer. This step advantageously comprises the application of an organic or inorganic ink and subsequent curing. In this case, an organic, for example polymer-based ink or an inorganic ink is advantageously printed onto the finished structured wafer surface with a layer thickness of preferably 5 to 25 μm. The ink can advantageously have organic and / or inorganic, for example mineral or ceramic, fillers to improve the thermal or mechanical properties.

[0013] Advantageously, a filling material preferably having a small coefficient of shrinkage and thermal expansion or CTE is filled as a carrier layer into the volume bounded by the frame structure by means of a dispensing step known per se. The filling material can then be leveled and / or cured by a leveling process such as vibration or ultrasound.

[0014] The carrier wafer produced in this way serves as a mechanical carrier during the backside thinning and backside metallization and during the handling process therebetween and does not deform during this time, is highly vacuum-compatible and thermally stable. Before or during the wafer separation process, the carrier wafer can be removed with a wafer saw or a laser. For example, the carrier wafer can be stripped in a water bath or solvent bath and / or by adding additives. Alternatively, the carrier wafer can be stripped by thermal or optical stimulation.

[0015] Applying the carrier wafer can include a plurality of dam filling method steps for applying a plurality of layers stacked one above the other, which are applied sequentially and in each case with subsequent curing. Coating is advantageously performed in such a way that a carrier wafer having a layer thickness of 5 to 500 μm is provided.

[0016] The weir filling method step can advantageously include applying at least one frame structure around the metallized surface of the wafer surface for providing an opening in the filling material. In this case, an additional inner frame structure around the corresponding metallized surface can be applied or printed on as a weir within the outer frame structure, after which the volume between these frame structures is filled in the weir filling process. As a result, the corresponding metallized surface is not covered by the carrier wafer, so that the wafer can be electrically contacted and tested during the further method. As a result, the wafer can continue to be tested not only after the back side thinning but also after the back side metallization is sprayed on.

[0017] It is further advantageous that the openings provided in the filling material of the carrier wafer can be filled or printed with a separate, removable filling or supporting material, preferably during the dam filling method step and with the aid of digital printing technology. The contour definition of the carrier wafer in the region of the opening can thereby be improved, so that smaller openings can be achieved, especially in the case of higher layer thicknesses. The supporting material can be removed again after the carrier wafer has been applied, for example in a water bath or solvent bath or with the aid of thermal actuation.

[0018] Furthermore, the method advantageously comprises selective stripping of the filling material, in which the metallized surface arranged on the wafer surface is exposed from the carrier wafer filling material arranged on the metallized surface. For example, the filling material applied in the region of the metallized surface can be selectively removed by means of laser exposure in such a way that the metallized surface can be electrically contacted and tested during the further method.

[0019] The method can advantageously also include a leveling step after the printed carrier wafer has been applied, in which a predefined and preferably uniform carrier wafer layer thickness is produced or achieved on the wafer surface. This can be done, for example, by means of a scraper. In particular, in this case, excess ink can also be removed or the surface of the applied layer or layers can be smoothed.

[0020] Advantageously, in the dam filling method step, the frame structure and / or the filling material is applied in the outer circular region of the wafer substrate in such a way that this circular region is compensated and in particular flush with the surface of the wafer substrate. Thus, the circular portion arranged in the edge region can be compensated and the flat carrier wafer can be coated closer to the edge region. In particular, the risk of fractures during the backside thinning process can be avoided, since otherwise no back pressure can be applied in these regions by the carrier wafer.

[0021] Advantageously, before applying the filling material of the carrier wafer, the method can also include applying a water-soluble support layer to the wafer surface, which is preferably laterally bounded by the previously applied frame structure. The support layer can be dissolved or stripped off by the process liquid during the singulation process, thus making it possible to simplify the stripping of the singulated carrier wafer layer from the individual semiconductor components.

[0022] Further advantageously, the method can also include applying a grinding film on the carrier wafer, which in particular covers the openings arranged therein. Thus, premature dissolution of the support layer can be prevented during wafer thinning or during a backside thinning process, in which a process liquid is also used.

[0023] According to the invention, the step of applying the carrier wafer is carried out before a wafer thinning or backside thinning process of the wafer, in which the wafer is reduced from its original wafer thickness to the desired or necessary component thickness for the subsequent semiconductor component or chip application. This can be carried out, for example, by means of grinding, chemical mechanical polishing (CMP) or by etching, depending on the specific requirements of the manufacturing process and the desired wafer thickness. In a preferred embodiment, the wafer is backside thinned to a thickness of less than 300 μm, preferably less than 200 μm, further preferably less than 150 μm.

[0024] The present invention further relates to a semiconductor component, in particular a power semiconductor component, which is manufactured or can be manufactured according to the above method.

[0025] Further advantages and details of the invention result from the following description of preferred embodiments of the invention and with reference to the drawings, which are shown only schematically. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1a -1e shows the method steps of a first preferred embodiment of the method according to the invention with the aid of a schematic side view of a wafer,

[0027] Figure 2a -2c shows the method steps of another preferred embodiment of the method in the case of applying a separate, soluble support layer,

[0028] Figure 3a -3c shows a detailed view of applying a carrier wafer onto the edge region of the wafer. DETAILED DESCRIPTION

[0029] In the figures, identical elements or elements having the same function are provided with the same reference numerals.

[0030] like Figure 1a As shown, a wafer substrate 101, for example made of silicon (Si), silicon carbide (SiC) or gallium nitride (GaN), is first provided as a basis for processing the semiconductor components to be formed on the wafer. Then, in a manner known per se, desired layers and structures 102, or those predetermined during the processing, are formed on the surface of the wafer substrate for manufacturing semiconductor components such as transistors, diodes or integrated circuits.

[0031] like Figure 1b As shown in FIG. 1 and FIG. 1c, in the next step, a carrier wafer 103 is applied to the wafer substrate 101 by means of a dam filling method step. Here, firstly, preferably by means of digital printing technology or inkjet technology, a dam or frame structure 103a, 103b is printed in a structured manner on the finished wafer surface, which dam or frame structure is composed of an organic or inorganic ink with a typical layer thickness of 5-25 μm and preferably a wall thickness of 50 to several 100 μm. During or after the printing of the layer, the ink is cured or sintered (for example by means of UV or heat).

[0032] After printing, a leveling step can optionally be carried out, for example using a doctor blade, in order to produce a layer that is as flat as possible. In order to be able to achieve larger layer thicknesses, for example in the range of 50-500 μm, this process is repeated several times, similar to the 3D printing based on inkjet known per se. Optionally, after printing the corresponding layer, a final curing or sintering step is also carried out in order to achieve complete crosslinking and improve the mechanical properties. The ink preferably contains organic and / or inorganic, for example mineral or ceramic fillers, in order to improve the thermal properties.

[0033] Next, the volume 104 bounded by the frame structure is filled with a highly filled filling material 105 by means of dispensing. The filling material can be a bottom filling material or be configured as a spherical top (Globe Top) and advantageously has a small shrinkage and a small coefficient of thermal expansion or CTE. The filling material can then be flattened by a flattening process such as vibration or ultrasound.

[0034] The filling material 105 is preferably introduced in such a way that openings 107 remain free for the metallized areas 106 of the wafer. For this purpose, the applied frame structure preferably comprises an inner frame structure 103 b which surrounds one or more metallized areas 106 of the structured wafer surface 102 .

[0035] Optionally, a removable filling material or supporting material 108 is applied, in particular printed, in parallel with the application of the carrier wafer 103 in the region of the opening 107 . Figure 1b 107. This improves the contour sharpness of the carrier wafer 103 in the region of the opening 107, so that smaller openings can be realized, especially in the case of higher layer thicknesses. After printing the carrier wafer 103, the support material 108 can be removed again, for example, in a water bath, a solvent bath or by means of thermal stimulation.

[0036] like Figure 1d As shown, prior to the backside thinning process of the wafer substrate 101 , a grinding film 111 may be optionally applied to the front side of the wafer.

[0037] like Figure 1e As shown, the method comprises a further step of backside thinning or wafer thinning, in which the wafer substrate 101 is reduced to a predefined thickness. Backside thinning can be performed, for example, by grinding with a suitable grinding medium 112. In a preferred embodiment, the wafer is back-thinned to a thickness of less than 300 μm, preferably less than 200 μm, further preferably less than 150 μm. After the backside thinning process, the optionally applied grinding film 111 can be removed and the backside metal contact of the wafer can be applied.

[0038] In a subsequent production step (not shown), the wafer substrate 101 can be separated or divided into individual semiconductor components.

[0039] As an alternative to the previously described embodiment, the method can include the full coverage of the wafer surface 102 with the filling material 105 within the printed frame structure 103a, wherein the wafer thinning or backside thinning step is performed after coating the carrier wafer 103. By means of selective removal, for example by means of a laser, openings 107 can be produced in the carrier wafer 103 in such a way that one or more metallized surfaces 106 arranged on the wafer surface are exposed from the filling material of the carrier wafer 103 arranged on the metallized surface for contacting for wafer testing.

[0040] Figure 2a 2c shows another preferred embodiment of the method. Figure 1a -1e method is different in that, when dealing with Figure 1a After the structured wafer surface 102 is shown, a soluble, in particular water-soluble, support layer 110 is preferably printed onto the wafer surface by means of digital printing technology. This can be done by means of printing technology during the application of the frame structure 103a. In this case, the frame structure 103a preferably surrounds the support layer 110 on the sides. The carrier wafer 103 is then applied and structured by means of a dam filling method step, such as Figure 2c Shown schematically.

[0041] In the subsequent wafer separation step, the support layer 110 can be dissolved or peeled off by the process liquid. As a result, the carrier wafer layer after separation is also peeled off. By means of the frame structure 103a arranged at the side, the support layer 110 is also protected in the back thinning process, which also uses process liquid, so that the support layer 110 does not dissolve too early. In addition, an optional grinding film 111 (see Figure 1d ) is used to protect the support layer 110 from contact with the process liquid.

[0042] Figure 3a -3c shows the edge region 109 of the wafer substrate 101. This edge region is rounded in the first 100 to 300 μm region, which increases the risk of fractures during thinning of the wafer substrate back side. Advantageously, in the method according to the invention, during application of the carrier wafer 103, the frame structure 103a is applied or printed in such a way that this rounded region is compensated, in particular flush with the surface 113 of the wafer substrate. This can be done by means of a multilayer construction or printed frame structure 103a, as in Figure 3a 3 c . By flattening in the circular edge region 109 of the wafer 101 , the carrier wafer 103 can be placed closer to the outer wafer edge.

Claims

1. A method for producing semiconductor components, in particular power semiconductor components, from a wafer, comprising the following steps: - providing a wafer substrate (101), - processing the structured wafer surface (102), - applying a carrier wafer (103) onto said wafer substrate (101), and - reducing the thickness of the wafer substrate (101) by wafer thinning, It is characterized in that The carrier wafer (103) is applied to the wafer surface (102) by a dam and fill method step.

2. The method according to claim 1, characterized in that The dam filling method steps include applying at least one frame structure (103a, 103b) on the wafer surface (102) by means of digital printing technology and filling the volume (104) bounded by the frame structure (103a, 103b) with a filling material (105) by means of dispensing.

3. The method according to claim 1 or 2, characterized in that: The dam and fill method steps include applying a frame structure (103b) around at least one metallized face (106) of the wafer surface (102) for providing an opening (107) in a fill material (105).

4. The method according to claim 3, characterized in that The openings (107) in the filling material (105) of the carrier wafer (103) are filled with a separate, removable filling material (108), preferably with the aid of digital printing technology.

5. The method according to any one of the preceding claims, characterized in that The method comprises selectively removing the filling material, preferably by means of a laser, during which at least one metallization surface (106) arranged on the wafer surface (102) is exposed from the filling material (105) of the carrier wafer (103) arranged on the metallization surface.

6. The method according to any one of the preceding claims, characterized in that The application of the carrier wafer (103) comprises coating with an organic or inorganic ink and subsequent curing.

7. The method according to any one of the preceding claims, characterized in that The application of the carrier wafer (103) comprises a plurality of dam filling method steps for applying a plurality of layers stacked one above the other, which layers are applied sequentially and are each followed by curing.

8. The method according to any one of the preceding claims, characterized in that During the dam filling method step, a frame structure and / or a filling material is applied to the outer circular area (109) of the wafer substrate (101) in such a way that the circular area is compensated and, in particular, leveled with the surface (113) of the wafer substrate (102).

9. The method according to any one of the preceding claims, characterized in that The method comprises, before applying the filling material (105) of the carrier wafer (103), applying a water-soluble supporting layer (110) on the wafer surface (102), preferably by means of digital printing technology, and preferably bounded laterally by a frame structure (103a).

10. The method according to claim 9, characterized in that The method comprises applying a grinding film (111) on the carrier wafer (103), the grinding film in particular covering openings (107) arranged in the carrier wafer.

11. Semiconductor component produced by a method according to any of the preceding claims.