Image acquisition system, control method and storage medium

Abstract

The invention relates to an image acquisition system, a control method and a storage medium. The system includes: a DVP device configured to generate DVP image data, a pixel clock signal, a row reference signal, and a frame synchronization signal; a data channel selector configured to switch between the DVP image data and the external memory controller data; an external storage device configured to store the DVP image data; and the micro-control unit is configured to control the DVP equipment, the data channel selector and the external storage equipment, and the micro-control unit counts the number of line synchronization signals of an image output by the DVP equipment. According to the image acquisition system provided by the invention, interface limitation is solved, a part of MCUs which are not provided with DVP interfaces but are provided with EXMC interfaces can execute DVP image acquisition tasks, the use scenes of the MCUs are expanded, and the development threshold of image acquisition and processing is reduced.

Description

Technical Field

[0001] The present invention relates to the field of image acquisition technology, and in particular to an image acquisition system, a control method and a storage medium. Background Art

[0002] In existing image acquisition systems, whether the image data is used for display devices or image processing systems, the acquisition device or display device is required to have an image data transmission control interface. For example, the image data such as MIPI, LVDS, DVP, etc. output from the image sensor requires the receiver to have the corresponding mobile industry processor interface (MIPI), digital video port (DVP) and low voltage differential signal (LVDS) interface before image acquisition can be performed. This type of system structure is usually as follows: Figure 1 shown.

[0003] Existing image acquisition systems often have limitations, that is, MIPI devices are only applicable to storage devices or display devices with MIPI interfaces, and DVP devices are also only applicable to storage devices or display devices with DVP interfaces. A device without MIPI interfaces, LVDS interfaces, and DVP interfaces cannot directly acquire image data for display or processing. For example, a screen with a two-wire serial bus (Inter-Integrated Circuit, abbreviated as I2C or IIC) interface cannot be directly used to display DVP image data; if the microcontroller unit (MCU) chip does not have a DVP interface, it cannot receive and process DVP image data input by the processor. When performing image processing, requiring the image processing device to have a large-capacity random access memory (Random-Access Memory, RAM) is also a limitation of existing image acquisition systems. Summary of the invention

[0004] In view of some or all of the problems in the prior art, the present invention provides an image acquisition system, which includes:

[0005] A DVP device, the DVP device being configured to generate DVP image data, a pixel clock signal, a line reference signal, and a frame synchronization signal;

[0006] a data channel selector configured to switch DVP image data and external memory controller data;

[0007] an external storage device configured to store DVP image data; and

[0008] A micro control unit is configured to control the DVP device, the data channel selector and the external storage device, and the micro control unit counts the number of line synchronization signals of the image output by the DVP device.

[0009] Further, the micro control unit outputs a reference clock signal to an XCLK port of the DVP device;

[0010] The IIC interface of the microcontroller unit is connected to the serial camera control bus interface of the DVP device so that the microcontroller unit can control the DVP device;

[0011] The row reference signal of the DVP device is input to the counter input port of the micro control unit so that the counter counts the number of row synchronization signals of the image output by the DVP device.

[0012] Further, the data line of the DVP device is connected in parallel to the first input terminal of the data channel selector, and the 8-bit DVP image data is expanded to 16-bit first input terminal data;

[0013] The pixel clock signal of the DVP device is connected to the clock input terminal of the external storage device to form a synchronization signal; the pixel clock signal of the DVP device is simultaneously input to the input terminal of the binary frequency division module of the external storage device; the row reference signal of the DVP device is connected in parallel to the enable terminal of the binary frequency division module.

[0014] Further, the external storage device interface of the microcontroller is connected to the second input terminal of the data channel selector and the ADD terminal of the external storage device, so that the microcontroller controls the external storage device and accesses the data of the external storage device; the universal input and output of the microcontroller is connected to the control terminal of the data channel selector, so that the microcontroller switches the data path inside the data channel selector by setting the level of the universal input and output;

[0015] The output end of the data channel selector is connected to the data end of the external storage device so that the data channel selector performs data storage on the external storage device.

[0016] The present invention also provides a control method for the image acquisition system, the control method comprising:

[0017] The microcontroller unit is connected to the external storage device, and the DVP device is disconnected from the external storage device;

[0018] The micro control unit configures the working mode of the external storage device through its external storage device interface;

[0019] The microcontroller unit configures the counter to be in input capture mode to count the number of line synchronization signals of the image data output by the DVP device;

[0020] The micro control unit configures the DVP device through its IIC interface so that the DVP device outputs image data;

[0021] The micro control unit is in communication with the external storage device via its external storage device interface;

[0022] The micro control unit sets the external storage device address through its external storage device interface;

[0023] The DVP device is in communication with the external storage device;

[0024] The DVP device outputs image data; at the same time, the counter in the micro control unit receives and counts the number of line synchronization signals; if the number of line synchronization signals reaches a set value, this step is completed; if the number of line synchronization signals does not reach the set value, the DVP device and the external storage device are reconnected;

[0025] The external storage device is connected to the micro control unit, and the external storage device is disconnected from the DVP device;

[0026] The micro control unit sets the external memory storage device to an asynchronous working mode;

[0027] The micro control unit controls the DVP device to stop outputting data through its IIC interface; and

[0028] The micro control unit reads out image data stored in an external storage device through its external storage device interface and performs processing.

[0029] Furthermore, the micro control unit configures the working mode of the external storage device through its external storage device interface including:

[0030] The microcontroller unit configures the external storage device through its external storage device interface, and configures the external storage device to a mode in which the address is automatically incremented when storing data; in the mode in which the address is automatically incremented, when the DVP subsequently outputs data, the data is stored in the external storage device in an address incrementing manner, and when the pixel data of the same row is continuously stored, there is no need to continuously configure the address of the external storage device from the outside.

[0031] Furthermore, the micro control unit configures the DVP device through its IIC interface so that the DVP device outputs image data including:

[0032] The microcontroller configures the DVP device through its IIC interface, and configures its resolution, pixel size, line blank, frame blank and image format; after the microcontroller completes the configuration of the DVP device, the DVP device outputs the pixel data and pixel clock signal of the image.

[0033] Furthermore, the micro control unit sets the external storage device address through its external storage device interface, including:

[0034] The micro control unit sets an external storage device through its external storage device interface and sets the storage address of the DVP image data.

[0035] Furthermore, the DVP device outputs image data including:

[0036] At the falling edge of the pixel clock signal of the DVP device, the DVP device outputs pixel data of the image;

[0037] At the rising edge of the pixel clock signal of the DVP device, the pixel data is stored in the storage address of the external storage device;

[0038] The transmission and storage of one frame of pixel data of the output image of the DVP device are completed in sequence.

[0039] The present invention also provides a computer-readable storage medium on which machine-readable instructions are stored. When the machine-readable instructions are executed by a processor, the steps of the control method of the image acquisition system are executed.

[0040] Compared with the prior art, the present invention has the following beneficial effects:

[0041] 1. The image acquisition system provided by the present invention solves the interface limitation, so that some MCUs without DVP interface but with EXMC (External Memory Controller) interface can perform DVP image acquisition tasks, which expands the use scenarios of MCU and lowers the development threshold of image acquisition and processing.

[0042] 2. The image acquisition system provided by the present invention adopts an external larger RAM to store images, which solves the limitation that the memory capacity of the traditional MCU is too small to cope with the image processing operation which requires a larger space.

[0043] 3. The image acquisition system and control method provided by the present invention realize the row data transmission by the coordinated work of software and hardware, and finally realize the acquisition, transmission and storage of a frame of data. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] To further illustrate the above and other advantages and features of various embodiments of the present invention, a more specific description of various embodiments of the present invention will be presented with reference to the accompanying drawings. It will be understood that these drawings only depict typical embodiments of the present invention and are therefore not to be considered as limiting the scope thereof. In the accompanying drawings, for clarity, identical or corresponding parts will be represented by identical or similar reference numerals.

[0045] Figure 1 It is a structural schematic diagram of an existing image acquisition system;

[0046] Figure 2 A simplified structural block diagram of an image acquisition system according to an embodiment of the present invention;

[0047] Figure 3 is a structural block diagram of an image acquisition system according to another embodiment of the present invention;

[0048] Figure 4 A schematic diagram of an overview of control timing of an image acquisition system according to an embodiment of the present invention;

[0049] Figure 5 A schematic diagram of an idle state timing sequence of an image acquisition system according to an embodiment of the present invention;

[0050] Figure 6 A schematic flow chart of a control method of an image acquisition system according to an embodiment of the present invention;

[0051] Figure 7 A schematic diagram of a timing sequence of system configuration of an image acquisition system according to an embodiment of the present invention;

[0052] Figure 8 A schematic diagram of the row transmission control timing of an image acquisition system according to an embodiment of the present invention;

[0053] Fig. 9 A schematic diagram of frame transmission control timing of an image acquisition system according to an embodiment of the present invention; and

[0054] Fig.10 The figure is a schematic diagram of the frame end control timing of the image acquisition system according to an embodiment of the present invention. DETAILED DESCRIPTION

[0055] In the following description, the present invention is described with reference to various embodiments. However, those skilled in the art will recognize that various embodiments may be implemented without one or more specific details or with other replacement and / or additional methods or components. In other cases, well-known structures or operations are not shown or described in detail to avoid obscuring the inventive point of the present invention. Similarly, for the purpose of explanation, specific numbers and configurations are set forth to provide a comprehensive understanding of embodiments of the present invention. However, the present invention is not limited to these specific details.

[0056] In this specification, reference to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present invention. The phrase "in one embodiment" appearing in various places in this specification does not necessarily all refer to the same embodiment.

[0057] It should be noted that the embodiments of the present invention describe the method steps in a specific order, but this is only for the purpose of illustrating the specific embodiment, rather than limiting the order of the steps. On the contrary, in different embodiments of the present invention, the order of the steps can be adjusted according to actual needs.

[0058] The present invention provides an image acquisition system and control method. Based on a microcontroller unit (MCU) for execution control, the DVP image data storage timing is simulated to realize the MCU to collect DVP image data without a DVP interface; the DVP image data is received by an external external memory controller (EXMC) storage device, thereby solving the problem that the traditional MCU has a small memory and is difficult to accommodate image data. The EXMC storage device is referred to as an external storage device. In addition, the collected image data can also be sent to the receiving interface of a display device through internal processing of the MCU, so that the image data from the DVP interface can be displayed on the screen of any interface.

[0059] The technical solutions in the embodiments of the present invention are described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0060] Figure 2 FIG. 1 is a simplified structural block diagram of an image acquisition system according to an embodiment of the present invention. Figure 2 As shown, the image acquisition system includes a DVP device, a MUX, an EXMC storage device and an MCU. The DVP device is configured to generate signals such as DVP image data, a pixel clock (Pixel Clock, PCLK) signal, a horizontal reference (Horizontal Reference, HREF) signal and a vertical synchronization (Vertical Synchronization, VSYNC) signal. MUX (Multiplexer) is a data channel selector, and the data channel selector is configured to switch DVP image data and external memory controller data. EXMC storage device is an external storage device, and the external storage device is configured to store DVP image data. MCU is a micro control unit, and the micro control unit is configured to control the DVP device, the data channel selector and the external storage device, and the micro control unit counts the number of line synchronization signals of the image output by the DVP device.

[0061] The PCLK signal is used to synchronously transmit pixel information, and 1 Byte of pixels is transmitted in each clock cycle. Because there are 8 signal lines D[7:0] for transmitting pixel lines, 1 Byte of pixels is transmitted in each PCLK cycle. PCLK is connected in parallel to the trigger IN terminal of the EXMC storage device to alternately generate signals of Q=0 and Q#=0. When Q=0, the driver LB# is valid, and the EXMC memory stores DATA[7:0] in DATA[15:0]; when Q#=0, the driver UB# is valid, and the EXMC memory stores DATA[15:8] in DATA[15:0]. PCLK is connected in parallel to the trigger CLK terminal of the EXMC storage device, and is the signal that drives the EXMC memory to work synchronously.

[0062] The HREF signal is an indication signal that the pixel row is valid. All pixels are valid during the high level of HREF. Similar to this signal is the horizontal synchronization signal (HSYNC), which indicates the start of pixel row transmission. HREF is the valid part of the HSYNC signal. The HREF signal is connected to the EXMC storage device and the MCU in parallel. The role of this signal in the system is: the HREF connected in parallel to the EXMC storage device is used to select the trigger in the EXMC storage device to control the Q and Q# signals therein; the HREF connected in parallel to the MCU is used to count the number of rows that have been transmitted.

[0063] The VSYNC signal is a frame synchronization signal, which indicates the start of a frame of image transmission. After receiving this signal, the receiving device is ready to receive image information. The VSYNC signal is used to select the EXMC storage device.

[0064] Figure 3 FIG. 1 is a structural block diagram of an image acquisition system according to another embodiment of the present invention. Figure 3 , the structure of the image acquisition system is explained in more detail. Figure 3 Only the connection relationship of the main signals is listed. Figure 3 As shown, the DVP device model is OV7670, MUX is a data selector composed of multiple Quad 2-Channel Analog Multiplexers, the MCU model is HC32F4A0, and the EXMC storage device is composed of PSRAM (Pseudo Static Random Access Memory) and a clock processing circuit, where the PSRAM model is IS66 series.

[0065] The connection relationship between the DVP device and the MCU is as follows: the clock output from the MCU MCO (Microcontroller Clock Output) is sent to the XCLK port of the DVP device, providing a reference clock for the DVP device. The IIC interface of the MCU is connected to the SCCB (Serial Cameral Control Bus) interface of the DVP device to enable the MCU to configure the DVP device. The HREF signal of the DVP is input to the TIMER (counter) capture input port of the MCU so that the TIMER can count the number of line synchronization signals in the DVP data, that is, the number of lines in a frame of data.

[0066] The connection relationship between the DVP device and the MUX is as follows: the data line D[7:0] of the DVP is connected in parallel to the first input terminals IN0[7:0] and IN0[15:8] of the MUX, that is, D[0] is connected to IN0[0] and IN0[8], D[1] is connected to IN0[1] and IN0[9], ..., and D[7] is connected to IN0[7] and IN0

[15] . The purpose of the parallel connection is to expand the 8-bit DVP[7:0] to the 16-bit IN0[15:0]. The high 8 bits and the low 8 bits of the expanded 16-bit data are equal. The purpose of this data width expansion is to ensure that the 16-bit EXMC storage device can be combined with EXMC_LB# / EXMC_UB# to store in bytes.

[0067] The connection relationship between the DVP device and the EXMC storage device is as follows: the pixel clock signal PCLK of the DVP device is directly connected to the clock input terminal CLK of the EXMC storage device to form a synchronization signal, so that the DVP data OUT[15:0] (OUT[15:8] is D[7:0], OUT[7:0] is D[7:0]) output from the MUX forms a synchronization relationship with the clock signal CLK of the EXMC. The clock signal output by the DVP is simultaneously input to the IN terminal of the 2-division module of the EXMC device, and its output 2-division signal Q is connected to the LB# terminal of the PSRAM, and the 2-division inverted output signal Q# is connected to the UB# terminal of the PSRAM; the HREF output of the DVP device is also connected in parallel to the enable port of the above-mentioned 2-division module to control the 2-division module to output valid Q (LB#) and Q# (UB#) signals only when the HREF signal is valid.

[0068] The connection relationship between MUX and MCU is as follows: the EXMC interface data line of MCU is connected to the second input terminal IN1[15:0] of MUX and the ADD terminal of EXMC storage device, so that MCU can control EXMC storage device and access data of EXMC storage device. The control terminal SW of MUX is connected to a general-purpose input / output (GPIO) pin of MCU, so that MCU can switch the data path inside MUX by setting the high and low levels of GPIO. When GPIO_SW=0, the data line of EXMC storage device is disconnected from the DVP data line and connected to the EXMC interface of MCU; when GPIO_SW=1, the data line of EXMC storage device is connected to the DVP data line and disconnected from the EXMC interface of MCU.

[0069] The connection relationship between the MUX and the EXMC storage device is: the output OUT[15:0] of the MUX is connected to DATA[15:0] of the EXMC storage device, so that the MUX stores data on the EXMC storage device.

[0070] In one embodiment of the present invention, based on the image acquisition system framework of the present invention, the system composition can be reduced by selecting different devices in actual applications. For example, by selecting a device with configurable port status, the data channel selector MUX can be omitted; when the LB# / UB# of the EXMC storage device is configurable, the 2-divider of the EXMC storage device can also be omitted; in terms of the use of the MCU interface, when a high-frequency GPIO port appears, the EXMC interface of this system may be replaced by GPIO.

[0071] Figure 4 FIG. 1 is a schematic diagram of a control timing overview of an image acquisition system according to an embodiment of the present invention. Figure 4 As shown in the figure, four groups of control signals are listed: IIC, EXMC, DVP and SW (switching control signal). The shaded part in the figure indicates that the group of control signals is in the flip state, that is, the working state, and the signal is valid at this time; the constant level in the figure indicates that the group of control signals is in the invalid state in the corresponding time period. idle ~t conf During this phase, the system is in an idle state. conf ~t start In this stage, the MCU configures the working mode of the EXMC storage device through the EXMC interface. start ~t 0 In the stage, the DVP device is configured. The MCU configures the image format, resolution, frame rate and other parameters output by the DVP device through the IIC interface. conf ~t start Phase and t start ~t 0 The two phases are collectively called the configuration phase.0 ~t h During the DVP data collection phase, the MCU continuously operates the EXMC to store the DVP data in the EXMC storage device. 0 Indicates the start time of the first row, t h Indicates the end time of the hth row (the beginning of the h+1th row). h ~t stop In this stage, the MCU configures the DVP device to stop working through the IIC interface, and can also decide to continue collecting images or stop the DVP device according to the actual usage scenario. Figure 4 Each group of control timing can be further decomposed into a single signal line or a signal group (address or data signal line). For example, the IIC signal can be decomposed into IIC_SCL, IIC_SDA; the EXMC signal can be decomposed into EXMC_UB#, EXMC_LB#, EXMC_ADD[15:0], EXMC_DATA[15:0], etc.; the DVP signal can be decomposed into DVP_D[7:0], DVP_VSYNC, DVP_HREF, DVP_PCLK, etc.; the SW signal can be decomposed into GPIO_SW signal.

[0072] Figure 5 FIG. 1 is a timing diagram of an idle state of an image acquisition system according to an embodiment of the present invention. Figure 5 As shown in the figure, before operating the image acquisition system, the control signals of each module are in the initial / invalid state in the idle state. The GPIO_SW signal is high level valid, and the other signals are low level valid.

[0073] Figure 6 The figure is a flow chart of a control method of an image acquisition system according to an embodiment of the present invention. Figure 6 The starting state in Figure 5 The idle state shown below Figure 6 , explaining the control method of the image acquisition system.

[0074] First, the microcontroller unit is connected to the external storage device, and the DVP device is disconnected from the external storage device, so that the MCU can configure the working mode of the EXMC storage device.

[0075] Next, the microcontroller unit configures the working mode of the external storage device through its external storage device interface, configures its write speed and working mode so that the DVP image data is synchronized with the EXMC clock, and automatically stores each line of image data in pixels (bytes) to the EXMC storage device.

[0076] Next, the microcontroller configures the counter to input capture mode to count the number of line synchronization signals of the DVP device output image data. When the TIMER counts to the set number, it indicates the end of the frame and triggers an interrupt signal for the MCU to make subsequent judgments and processing.

[0077] Next, the microcontroller unit configures the DVP device through its IIC interface, configures its data format, resolution, and pixel color depth, so that the DVP device outputs image data.

[0078] The above steps correspond to the configuration phase. Figure 7 FIG. 1 is a schematic diagram of the system configuration timing of an image acquisition system according to an embodiment of the present invention. Figure 7 As shown, at t conf ~t start In the stage, the MCU configures the EXMC storage device through its EXMC interface, and configures the external storage device to store data in an address self-incrementing mode; in the address self-incrementing mode, when the DVP outputs data later, the data is stored in the EXMC storage device in an address incrementing manner, and the address of the EXMC storage device does not need to be continuously configured from the outside when the same row of pixel data is stored continuously. start ~t 0 In this stage, the MCU configures the DVP device through its IIC interface, and configures its resolution, pixel size, horizontal blanking (HBLANK), vertical blanking (VBLANK), and image format. HBLANK is the time from the end of the current row of data transmission to the beginning of the next row of data transmission. The MCU configures the address of the EXMC device during the HBLANK period. In order to ensure that the MCU has enough time to configure the EXMC storage device, the size of the HBLANK should be considered in combination with the operating frequency of the MCU, the program execution instruction cycle and other factors. When the operating frequency of the MCU is high and the program instruction execution cycle is short, a smaller HBLANK can be configured; when the operating frequency of the MCU is low and the program instruction execution cycle is long, a larger HBLANK can be configured. t 0 After that, the MCU completes the configuration of the DVP device and DVP_PCLK starts to output.

[0079] Next, the micro control unit communicates with the external storage device through its external storage device interface.

[0080] Next, the microcontroller unit sets the external storage device address through its external storage device interface.

[0081] Next, the DVP device communicates with the external storage device.

[0082] Next, the DVP device outputs image data; at the same time, the counter in the micro control unit receives and counts the number of line synchronization signals; if the number of line synchronization signals reaches the set value, this step is completed; if the number of line synchronization signals does not reach the set value, the DVP device and the external storage device are reconnected.

[0083] Figure 8 FIG. 1 is a schematic diagram of the row transmission control timing of an image acquisition system according to an embodiment of the present invention. Figure 8 As shown in the figure, the storage of DVP image data is in units of lines, and the effective part of the line data transmission is indicated by the low level of HREF. When the TIMER counts to the set number of image lines h, the reception of a frame of data is completed. H is the height component of the image resolution. If the image resolution is 320*240, then h=240. Before the start of each line data transmission, the storage address needs to be set by software, and the address setting is performed by the MCU during HBLANK. No software intervention is required during the line data transmission process, and the pixel values ​​that make up the line data are controlled and stored by the EXMC_UB# and EXMC_LB# signals.

[0084] Take the data transmission of the first row as an example. 0 / t 0_sw0 ~t 0_add0 In this stage, the MCU connects the EXMC storage device data channel to the EXMC interface of the MCU by setting GPIO_SW = 0, and the EXMC storage device data channel is disconnected from the DVP data line. 0_add0 ~t 0_add1 In the first stage, the MCU operates the EXMC storage device through the EXMC interface and pre-sets the storage address of the first row of DVP data. 0_add1 ~t 0_sw1 In this stage, the MCU controls GPIO_SW = 1 to connect the data channel EXMC_DATA[15:0] of the EXMC storage device to DVP_D[7:0], and disconnect the EXMC_DATA[15:0] of the EXMC storage device from the EXMC interface of the MCU, so that the DVP data can be directly transmitted to the EXMC storage device. Here, the DVP_D[7:0] signal is the same as the expanded signal MUX_OUT[15:0], and MUX_OUT[15:0] is connected to EXMC_DATA[15:0]. 0_sw1 ~t 0_0During the effective period of DVP_VSYNC, DVP_HREF and DVP_D[7:0] will output valid signals. The length of DVP_VSYNC time depends on the MCU execution time, HBLANK, and VBLANK size. The HBLANK size needs to be reasonably set according to the MCU main frequency and program instruction execution time. For MCUs with lower main frequency and longer execution time, the HBLANK value can be appropriately increased to leave enough time for the MCU to configure the EXMC storage device address and switch GPIO_SW. 0_0 ~t 0_1 In the stage, DVP_PCLK falls and HREF falls, EXMC_LB# outputs a valid signal, and at the same time DVP_D[7:0] outputs valid data, where the valid data is the first pixel value. At the rising edge of DVP_PCLK, the pixel value is stored in the low address of the storage unit of the pre-set address of the EXMC storage device. 0_1 ~t 0_2 In the first stage, at the falling edge of DVP_PCLK, EXMC_UB# outputs a valid signal, and the DVP device outputs the second pixel value. At the rising edge of DVP_PCLK, the pixel value is stored in the high address of the storage unit of the EXMC storage device. The subsequent transmission of the 3rd, 4th, ..., w-1, w pixels is the same as the 1st and 2nd pixels. The storage of these pixels is completed by hardware timing without software intervention. 0_w-1 ~t 0_w In the stage, at the falling edge of DVP_PCLK, the DVP device outputs the wth pixel value, and at the rising edge of DVP_PCLK, the pixel value is stored in the storage unit of the EXMC storage device. When the image resolution is 320*240, w=320. So far, the storage of the first row of DVP image data is completed.

[0085] t 0_w / t 1_sw0 ~t 1_add0 In the first stage, HREF rises, MCU sets GPIO_SW = 0, EXMC_DATA[15:0] is connected to the EXMC interface of MCU, and EXMC_DATA[15:0] is disconnected from DVP_D[7:0]. 0_add0 ~t 0_add1 In the stage, the MCU operates the EXMC storage device through the EXMC interface and pre-sets the storage address of the DVP data in row 2. The control timing of the subsequent rows 2 to v is basically the same as that of row 1, except that the storage address of the EXMC storage device is set differently.

[0086] This process is repeated to set the storage address of the row data until the transmission of one frame of data is completed. Fig. 9 The figure is a schematic diagram of the frame transmission control timing of an image acquisition system according to an embodiment of the present invention. Fig. 9 In, t 0 ,t 1 ,t h They are the timing nodes of the DVP data transmission of the 1st row, the 2nd row, and the hth row respectively. h is the vertical component of the image resolution. When the image resolution is 320*240, h=240.

[0087] Next, the external storage device is connected to the micro control unit, and the external storage device is disconnected from the DVP device.

[0088] Next, the micro control unit sets the external storage device to an asynchronous working mode.

[0089] Next, the micro control unit controls the DVP device to stop outputting data through its IIC interface.

[0090] Finally, the micro control unit reads out the image data stored in the external storage device through its external storage device interface and performs processing.

[0091] The above steps correspond to the frame end stage. The HREF signal is input to the MCU's TIMER as the trigger signal of the counter to count the number of rows transmitted. When the counter counts to h, it indicates that a frame of data transmission is completed. You can choose the subsequent operation according to the actual application scenario, and choose to continue receiving or stop the DVP device output. Fig.10 FIG. 1 is a schematic diagram of the frame end control timing of an image acquisition system according to an embodiment of the present invention. stop_sw0 The corresponding h-row data transmission ends at time t h .t h / t stop_sw0 ~t stop_conf In the hth HREF rising edge, the MCU's built-in module TIMER counts to h. The MCU's internal program recognizes that a frame of data transmission of the DVP device is completed. The MCU controls GPIO_SW = 0, and the EXMC storage device data channel EXMC_DATA[15:0] is connected to the MCU's EXMC interface and disconnected from the DVP device's data line DVP_D[7:0]. stop_conf ~t stop_act In this stage, the MCU configures the EXMC storage device to asynchronous mode so that it can continue to work after EXMC_CLK is cut off. stop_act ~t stop_end In this stage, the MCU controls the DVP device to stop transmitting data through the IIC interface. stop_end ~t rd_startIn this stage, the DVP device stops outputting data DVP_D[7:0] and clock DVP_PCLK, and the clock signal of EXMC_CLK is cut off. So far, the DVP data has been collected into the EXMC storage device. rd_start ~t rd_stop In this stage, the MCU reads the DVP image data stored in the EXMC device through the EXMC interface for subsequent processing.

[0092] The image acquisition system provided by the present invention solves the interface limitation, so that some MCUs without DVP interface but with EXMC interface can perform DVP image acquisition tasks, expands the application scenarios of MCU, and lowers the development threshold of image acquisition and processing; adopts an external larger RAM to store images, which solves the limitation that the traditional MCU memory capacity is too small to cope with the image processing operation requiring a larger space; software and hardware work together to realize line data transmission, and finally realize the acquisition, transmission and storage of one frame of data.

[0093] In one embodiment of the present invention, the present invention further provides a computer-readable storage medium having machine-readable instructions stored thereon, wherein the machine-readable instructions implement the following processing steps when executed by a processor: the microcontroller unit is connected to an external storage device, and the DVP device is disconnected from the external storage device; the microcontroller unit configures the working mode of the external storage device through its external storage device interface; the microcontroller unit configures the counter to an input capture mode to count the number of line synchronization signals of the DVP device outputting image data; the microcontroller unit configures the DVP device through its IIC interface to enable the DVP device to output image data; the microcontroller unit is connected to the external storage device through its external storage device interface; the microcontroller unit sets the external storage through its external storage device interface device address; the DVP device is connected with the external storage device; the DVP device outputs image data; at the same time, the counter in the micro control unit receives and counts the number of line synchronization signals; if the number of line synchronization signals reaches the set value, this step is completed; if the number of line synchronization signals does not reach the set value, the DVP device and the external storage device are reconnected; the external storage device is connected with the micro control unit, and the external storage device is disconnected from the DVP device; the micro control unit sets the external storage device to an asynchronous working mode; the micro control unit controls the DVP device to stop outputting data through its IIC interface; and the micro control unit reads out the image data stored in the external storage device through its external storage device interface to perform processing.

[0094] The readable storage medium includes: a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and other media that can store machine-readable instructions.

[0095] Although various embodiments of the present invention are described above, it should be understood that they are presented as examples only and not as limitations. It is obvious to those skilled in the relevant art that various combinations, modifications and changes can be made thereto without departing from the spirit and scope of the present invention. Therefore, the breadth and scope of the present invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should only be defined according to the attached claims and their equivalents.

Claims

1. An image acquisition system, characterized in that: include: A DVP device, the DVP device being configured to generate DVP image data, a pixel clock signal, a line reference signal, and a frame synchronization signal; a data channel selector configured to switch DVP image data and external memory controller data; an external storage device configured to store DVP image data; as well as A micro control unit is configured to control the DVP device, the data channel selector and the external storage device, and the micro control unit counts the number of line synchronization signals of the image output by the DVP device.

2. The image acquisition system according to claim 1, characterized in that: The micro control unit outputs a reference clock signal to an XCLK port of the DVP device; The IIC interface of the microcontroller unit is connected to the serial camera control bus interface of the DVP device so that the microcontroller unit can control the DVP device; The row reference signal of the DVP device is input to the counter input port of the micro control unit so that the counter counts the number of row synchronization signals of the image output by the DVP device.

3. The image acquisition system according to claim 1, characterized in that: The data line of the DVP device is connected in parallel to the first input terminal of the data channel selector, and the 8-bit DVP image data is expanded to 16-bit first input terminal data; The pixel clock signal of the DVP device is connected to the clock input terminal of the external storage device to form a synchronization signal; the pixel clock signal of the DVP device is simultaneously input to the input terminal of the binary frequency division module of the external storage device; the row reference signal of the DVP device is connected in parallel to the enable terminal of the binary frequency division module.

4. The image acquisition system according to claim 1, characterized in that: The external storage device interface of the micro control unit is connected to the second input terminal of the data channel selector and the ADD terminal of the external storage device, so that the micro control unit controls the external storage device and accesses the external storage device data; The universal input and output of the microcontroller are connected to the control end of the data channel selector, so that the microcontroller switches the data path inside the data channel selector by setting the level of the universal input and output; The output end of the data channel selector is connected to the data end of the external storage device so that the data channel selector performs data storage on the external storage device.

5. A control method for an image acquisition system according to any one of claims 1 to 4, characterized in that: include: The microcontroller unit is connected to the external storage device, and the DVP device is disconnected from the external storage device; The micro control unit configures the working mode of the external storage device through its external storage device interface; The microcontroller unit configures the counter to be in input capture mode to count the number of line synchronization signals of the image data output by the DVP device; The micro control unit configures the DVP device through its IIC interface so that the DVP device outputs image data; The micro control unit is in communication with the external storage device via its external storage device interface; The micro control unit sets the external storage device address through its external storage device interface; The DVP device is in communication with the external storage device; The DVP device outputs image data; at the same time, the counter in the micro control unit receives and counts the number of line synchronization signals; if the number of line synchronization signals reaches a set value, this step is completed; if the number of line synchronization signals does not reach the set value, the DVP device and the external storage device are reconnected; The external storage device is connected to the micro control unit, and the external storage device is disconnected from the DVP device; The micro control unit sets the external memory storage device to an asynchronous working mode; The micro control unit controls the DVP device to stop outputting data through its IIC interface; and The micro control unit reads out image data stored in an external storage device through its external storage device interface and performs processing.

6. The control method of the image acquisition system according to claim 5, characterized in that: The microcontroller unit configures the working mode of the external storage device through its external storage device interface including: The microcontroller unit configures the external storage device through its external storage device interface, and configures the external storage device to a mode in which the address is automatically incremented when storing data; in the mode in which the address is automatically incremented, when the DVP subsequently outputs data, the data is stored in the external storage device in an address incrementing manner, and when the pixel data of the same row is continuously stored, there is no need to continuously configure the address of the external storage device from the outside.

7. The control method of the image acquisition system according to claim 5, characterized in that: The microcontroller unit configures the DVP device through its IIC interface so that the DVP device outputs image data including: The microcontroller configures the DVP device through its IIC interface, and configures its resolution, pixel size, line blank, frame blank and image format; after the microcontroller completes the configuration of the DVP device, the DVP device outputs the pixel data and pixel clock signal of the image.

8. The control method of the image acquisition system according to claim 5, characterized in that: The microcontroller unit sets the external storage device address through its external storage device interface, including: The micro control unit sets an external storage device through its external storage device interface and sets the storage address of the DVP image data.

9. The control method of the image acquisition system according to claim 5, characterized in that: The DVP device outputs image data including: At the falling edge of the pixel clock signal of the DVP device, the DVP device outputs pixel data of the image; At the rising edge of the pixel clock signal of the DVP device, the pixel data is stored in the storage address of the external storage device; The transmission and storage of one frame of pixel data of the output image of the DVP device are completed in sequence.

10. A computer-readable storage medium, characterized in that: Machine readable instructions are stored thereon, and when the machine readable instructions are executed by a processor, the steps of the method according to any one of claims 5 to 9 are performed.

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