Method, circuit, equipment and medium for improving signal reliability

Abstract

The invention discloses a method, a circuit, equipment and a medium for improving signal reliability, and relates to the technical field of aviation computers.The method comprises the steps that whether first data information written into a relay enable register by a CPU is effectively written or not is judged; if yes, activating a first relay and a second relay in a peripheral output driving circuit; acquiring second data information written into a master switch enable register by the CPU, and judging whether the second data information is consistent with preset control information or not; and if yes, a preset time sequence pulse generated by the CPLD pulse generation module is used as a target signal to be sent to a receiver, and the pulse signal is used for replacing high and low levels to serve as an effective signal. According to the method, false triggering caused by wire crosstalk, interference or software runaway can be avoided, and then the reliability of signal transmission is improved.

Description

Technical Field

[0001] The present disclosure generally relates to the field of aviation computer technology, and more particularly to a method, circuit, device, and medium for improving signal reliability. Background Art

[0002] Discrete signals play a vital role in aviation because they are transmitted in digital form and can provide stable and reliable signals for controlling and monitoring various systems and functions of the aircraft.

[0003] At the same time, discrete quantity signals are commonly used digital signals on board. The receiving end determines whether an event is valid through high and low levels and pre-agreed meanings. This method has a simple circuit and low circuit cost, and is widely used in communications within devices or between devices.

[0004] Generally, discrete quantities are sent or received through 1-bit data. Due to mutual coupling between transmission lines or external interference, it is obviously not very reliable to judge whether an event is valid by a single signal, especially for critical and important signals involving personnel safety or mission safety. Therefore, there is an urgent need for a method to improve signal reliability to ensure the safety and reliability of discrete quantity signals. Summary of the invention

[0005] In view of the above-mentioned defects or deficiencies in the prior art, it is desirable to provide a method, circuit, device and medium for improving signal reliability.

[0006] In a first aspect, the present application provides a method for improving signal reliability, comprising: responding to a transmission request of a target signal; Determine whether the first data information written by the CPU to the relay enable register is valid; If yes, activating the first relay and the second relay in the peripheral output drive circuit; Acquire the second data information written by the CPU to the main switch enable register, and determine whether the second data information is consistent with the preset control information; If yes, the preset timing pulse generated by the CPLD pulse generation module is sent to the receiver through the first relay and the second relay as the target signal.

[0007] According to the technical solution provided by the present application, before determining whether the first data information written by the CPU to the relay enable register is validly written, the method further includes: The CPU reads back the first calibration information written to the data verification register through the bus, and if the read information is consistent with the written first calibration information, it is confirmed that the bus is normal; According to the technical solution provided by the present application, after confirming that the bus is normal and before determining whether the first data information written by the CPU to the relay enable register is validly written, it also includes: The second calibration information written by the CPU to the identity recognition register is obtained, and if the second calibration information is consistent with the second preset calibration information, it is confirmed that the CPU writes normally. According to the technical solution provided by the present application, the relay enable register includes: two independently controlled first relay enable registers and second relay enable registers; the first data information includes: two sub-data information written into the first relay enable register and the second relay enable register respectively; Determining whether the first data information written by the CPU to the relay enable register is validly written specifically includes: Acquire the sub-data information written into the first relay enable register and the second relay enable register; When the two sub-data information are consistent with the corresponding preset enable information, it is confirmed that the first data information written by the CPU to the relay enable register is effectively written.

[0008] According to the technical solution provided by the present application, activating the first relay and the second relay in the peripheral output drive circuit specifically includes: An enable signal is sent to a peripheral output drive circuit to control the peripheral drive circuit to provide current to the first relay and the second relay, so that the first relay and the second relay are attracted and enter an activated state.

[0009] According to the technical solution provided by the present application, the CPLD pulse generation module generates a first pulse sequence and a second pulse sequence; The preset timing pulse generated by the CPLD pulse generation module is sent to the receiver as the target signal, specifically including: The first pulse sequence and the second pulse sequence are sent according to a preset timing; the first pulse sequence and the second pulse sequence have different pulse widths and periods.

[0010] In a second aspect, the present application provides a circuit for improving signal reliability, which is applied with the above-mentioned method for improving signal reliability, and the circuit includes: CPU unit and CPLD unit that communicate with each other; The CPLD unit at least comprises an interface communication module, a CPLD pulse generation module, a credibility authentication module, and an output control enabling module that can be realized through internal logic; An output drive circuit includes: a target signal transmission branch, an independently controlled first relay drive branch and a second relay drive branch.

[0011] According to the technical solution provided by the present application, the target signal transmission branch includes: the first relay and the second relay connected in series with the CPLD unit in sequence, and used to transmit the target signal to the receiver; One end of the first relay driving branch is connected to the CPLD unit, and the other end is connected to the first relay; one end of the second relay driving branch is connected to the CPLD unit, and the other end is connected to the second relay; The first relay driving branch and the second relay driving branch are used to activate the first relay and the second relay respectively.

[0012] In a third aspect, the present application provides a terminal device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of a method for improving signal reliability as described above when executing the computer program.

[0013] In a fourth aspect, the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and wherein when the computer program is executed by a processor, the steps of a method for improving signal reliability as described above are implemented.

[0014] In summary, the technical solution specifically discloses a method, circuit, device and medium for improving signal reliability. The method includes: determining whether the first data information written by the CPU to the relay enable register is valid; if so, activating the first relay and the second relay in the peripheral output drive circuit; obtaining the second data information written by the CPU to the main switch enable register, and determining whether the second data information is consistent with the preset control information; if so, sending the preset timing pulse generated by the CPLD pulse generation module as the target signal to the receiver.

[0015] Existing discrete quantities are generally sent or received through 1-bit data. Due to mutual coupling between transmission lines or external interference, it is obviously not very reliable to judge whether an event is valid through a single signal, especially for critical and important signals involving personnel safety or task safety. The present application can activate the external electromagnetic relay physical switch through the effective writing of the CPU to the relay enable register, and can control the internal logical main switch and two logical sub-switches of the CPLD through the specific writing of the CPU to the main switch enable register. These three logical switches are combined through a strict timing relationship to ensure that the output target signal is issued within the normal controllable range, thereby improving the output reliability of key signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings: Figure 1 A flow chart of a method for improving signal reliability is shown.

[0017] Figure 2 A circuit structure for improving signal reliability.

[0018] Figure 3 The figure is a functional block diagram of a terminal device.

[0019] Numbers in the figure: 1, CPU unit; 2, CPLD unit; 3, output drive circuit; 31, first relay drive branch; 32, second relay drive branch; 4, first relay; 5, second relay; 500, terminal device; 502, ROM; 503, RAM; 504, bus; 505, I / O interface; 506, input part; 507, output part; 508, storage part; 509, communication part; 510, drive; 511, removable medium. DETAILED DESCRIPTION

[0020] The present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the relevant invention, rather than to limit the invention. It is also necessary to explain that, for ease of description, only the parts related to the invention are shown in the accompanying drawings.

[0021] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0022] Example 1 In order to make the technical solution of the embodiment of the present application clearer and easier to understand, the application background of the embodiment of the present application is introduced below.

[0023] Discrete signals play a vital role in the aviation field because they are transmitted in digital form and can provide stable and reliable signals for controlling and monitoring various systems and functions of aircraft. In avionics systems, discrete signals are often used to indicate switch states, system startup, fault detection, warnings, and many other critical operations.

[0024] For example, in the aircraft control system, navigation system or engine control system, discrete signals are relied upon to perform specific operations or instructions. These signals ensure the coordinated operation of various parts of the aircraft. Discrete signals are also used in communications inside and outside the aircraft to transmit short information, such as status reports, command confirmations, etc. In fault diagnosis and monitoring systems, discrete signals can be used to detect system faults and abnormal conditions, and timely warnings can be issued to help maintenance personnel diagnose problems.

[0025] In summary, discrete signals play a central role in the aviation field and are essential to the safe, reliable and efficient operation of aircraft. Therefore, ensuring the accurate transmission and processing of these signals is an important aspect in the design of aviation computer systems.

[0026] In view of this, an embodiment of the present application proposes a method for improving the reliability of key signals. The method uses dual redundant pulse signals and strict timing authentication methods to reliably transmit key signals. Compared with the traditional method of using 0 / 1 levels to transmit key signals, the method has higher reliability and can effectively prevent the main program from running away or the external circuit from being interfered with and erroneously triggering the key signal, causing serious consequences.

[0027] Specifically, the method includes: determining whether the first data information written by the CPU to the relay enable register is a valid write; if so, activating the first relay and the second relay in the peripheral output drive circuit; obtaining the second data information written by the CPU to the main switch enable register, and determining whether the second data information is consistent with the preset control information; if so, sending the preset timing pulse generated by the CPLD pulse generation module as the target signal to the receiver.

[0028] It can be seen that this method can activate the physical switch of the external electromagnetic relay through the effective writing of the CPU (Central Processing Unit) to the relay enable register, and can control the closing of the internal logic main switch of the CPLD (Complex Programming Logic Device) through the specific writing of the CPU to the main switch enable register. Based on the combination of these three logical switches through a strict timing relationship, it is ensured that the output target signal (key signal) is issued within the normal controllable range, rather than being interfered with or the program running away and erroneously triggering the output of the key signal.

[0029] In order to make the technical solution of the present application clearer and easier to understand, the method is explained below by taking the coordination between the CPU unit, the CPLD unit and the output drive circuit as an example.

[0030] First, the CPU unit 1 calculates and controls the circuit to complete logical operations, arithmetic operations and timing control, decides whether to output the target signal, and completes the communication with the CPLD unit 2; in the present invention, LocalBus is used to realize data transmission between the CPU unit 1 and the CPLD unit 2, but there is no specific limitation, and it can also be an SPI interface, UART interface, PCIe interface, etc.

[0031] At the same time, the CPLD unit 2 has at least an interface communication module, a pulse generation module, a credibility authentication module, and an output control enable module that can be realized through internal logic; among them, the CPLD pulse generation module is responsible for generating pulses with configurable period and duty cycle, and the credibility authentication module includes setting up various data verification registers to perform strict timing and data verification to authenticate whether the output behavior of this key signal is legal; the output control enable module controls external relays and internal electronic switches to ensure that all conditions meet the requirements before outputting key signals.

[0032] The output drive circuit includes two sets of independent relays connected to the CPLD unit 2. The two sets of relays are connected in series to complete the signal control with the CPLD unit 2 and the CPU unit 1. In this method, only when the two sets of relays are operated at the same time can the discrete quantity signal or pulse signal be output.

[0033] like Figure 2 As shown, the figure is a flow chart of a method for improving signal reliability provided by an embodiment of the present application, including: S200, CPLD unit 2 responds to the transmission request of the target signal; When the CPLD unit 2 needs to execute the transmission task of the target signal, the CPU unit 1 needs to make the transmission decision of the target signal.

[0034] S201, CPU unit 1 writes first calibration information to a data check register via a bus; The CPU unit 1 verifies whether the data transmission on the bus is correct based on a specific data pattern and a data check register in the internal logic circuit of the CPLD unit 2 to avoid transmission errors on the bus.

[0035] S202 , the CPU unit 1 reads back the written first calibration information. If the read-back information is consistent with the written first calibration information, it is confirmed that the bus is normal.

[0036] If the information read back by the CPU unit 1 is consistent with the written first preset calibration information, it proves that the bus transmission is stable and the risk of interference with the key signal transmission is eliminated.

[0037] Specifically, in the embodiment of the present application, the set first calibration information may be 0xaa55, but its specific form is not limited.

[0038] S203, CPU unit 1 writes second calibration information to the identity register; The identity register in the internal logic circuit of CPLD unit 2 is a special register used to store information or identifiers about the program status. The CPU performs a self-test or system initialization process by writing second calibration information to the identity register. It is also used to complete the operations used to identify and synchronize each processor in a multi-processor system to ensure that each processor can identify and distinguish its own status, which helps prevent conflicts and confusion between processors.

[0039] S204, the CPLD unit 2 obtains the second calibration information written by the CPU unit 1, and if the second calibration information is consistent with the second preset calibration information, it is confirmed that the CPU writing is valid; If the second calibration information read by the CPLD unit 2 in the identity recognition register is consistent with the pre-agreed second preset calibration information, it is confirmed that the CPU write is normal.

[0040] Specifically, in the embodiment of the present application, the second preset calibration information is set to 0x1234, but its specific form is not limited.

[0041] S205, CPU unit 1 writes first data information to the relay enable register; In the embodiment of the present application, the relay enable register includes: two independently controlled first relay enable registers and second relay enable registers; accordingly, the first data information includes: two sub-data information written into the first relay enable register and the second relay enable register respectively; In the embodiment of the present application, the first relay enable register and the second relay enable register correspond to two independently controlled first relays 4 and second relays 5, respectively, but in fact, there is no limitation on the number of relays, which can be adjusted according to actual conditions; the signal control is completed in series with the relay contact switches, so that the CPU unit 1 must write effectively to the first relay enable register and the second relay enable register to trigger the output of subsequent target signals. In this way, false triggering caused by wire crosstalk, interference or software running away can be further effectively prevented.

[0042] S206, the CPLD unit 2 determines whether the first data information written by the CPU is validly written, and if so, activates the first relay and the second relay in the peripheral output drive circuit; CPLD unit 2 first obtains the sub-data information written into the first relay enable register and the second relay enable register, and compares it with the preset enable information. Only when the two sub-data information are consistent with the corresponding preset enable information, it is confirmed that the first data information written by the CPU to the relay enable register is valid, and an enable signal is sent to the peripheral output drive circuit.

[0043] Furthermore, the output drive circuit receives the enable signal and can provide current to the first relay and the second relay, so that the first relay and the second relay are attracted and enter an activated state, that is, the first relay and the second relay are closed.

[0044] Specifically, in the embodiment of the present application, the preset enable information set for the first relay enable register and the second relay enable register is 0x0001, but the specific form thereof is not limited.

[0045] S207, CPU unit 1 writes second data information to the main switch enable register; After the peripheral output drive circuit drives two electromagnetic relays to close, the CPLD pulse generation module does not output a pulse at this time, but needs to further judge the write status of CPU unit 1 to the main switch enable register (or, the main logic switch enable register), which is equivalent to the closure of the first relay and the second relay belonging to the closure of the sub-switch, and further logic of the main switch is required. Only when all three switches are closed can the key signal be output.

[0046] S208, the CPLD unit 2 obtains the second data information written by the CPU, and determines whether the second data information is consistent with the preset control information. If yes, the preset timing pulse generated by the CPLD pulse generation module is sent to the receiver through the first relay and the second relay as the target signal; CPLD unit 2 obtains the second data information and judges the second data information based on the preset control information. If the second data information is consistent with the preset control information, then all three switches are in a closed state. The CPLD pulse generation module can then send the generated preset timing pulse as the target signal to the receiver, thereby completing the transmission of the key signal.

[0047] Specifically, in the embodiment of the present application, the preset control information is also set to 0x0001, but its specific form is not limited.

[0048] Furthermore, the CPLD pulse generation module sends the first pulse sequence and the second pulse sequence according to a preset timing; the first pulse sequence and the second pulse sequence have different pulse widths and periods.

[0049] In the embodiment of the present application, two pulse sequences with different periods and duty cycles are used; among them, pulse sequence 1 is a pulse with a pulse width of 1us and a period of 1ms, and is set to send 8 cycles; pulse sequence 2 is a pulse with a pulse width of 10us and a period of 2ms, and is sent for 8 cycles; finally, pulse sequence 1 is sent first and then pulse sequence 2.

[0050] By sending two pulse signals with different periods and pulse widths in a certain sequence to replace the 0 / 1 discrete signal, when the receiver receives the pulse, it can also detect whether the period and pulse width of the pulse signal match the set pulse sequence 1 and pulse sequence 2, and make another judgment. If they match, the signal is determined to be valid, otherwise, it is determined to be an interference signal, which can further prevent false triggering caused by wire crosstalk, interference or software running away.

[0051] Based on the above description, it can be seen that the present application proposes a method for improving signal reliability for transmitting target signals or key signals. Specifically, before determining whether the CPU is effectively written, the method preferentially confirms whether the bus transmission is normal and whether the CPU itself can execute the write task, thereby providing a good pre-environment for the subsequent CPU and CPLD interaction; subsequently, by judging whether the first data information written by the CPU to the relay enable register is effectively written and whether the second data information written by the CPU to the main switch enable register is valid, and other multiple logical judgments are made, as a condition for triggering the preset timing pulse generated by the CPLD pulse generation module to be sent to the receiver as the target signal, the signal transmission reliability is greatly improved to a certain extent. At the same time, in this method, a pulse signal is used to replace a 0 / 1 discrete signal. When receiving the pulse, the receiver can also match and judge the received pulse signal with a preset pulse sequence, thereby further improving the isolation of false trigger signals.

[0052] Example 2 Combination Figure 2 As shown, based on a method for improving signal reliability shown in Example 1, an embodiment of the present application provides a circuit for improving signal reliability, the circuit comprising: A CPU unit 1 and a CPLD unit 2 that communicate with each other; The CPLD unit 2 at least has an interface communication module, a CPLD pulse generation module, a credibility authentication module, and an output control enabling module that can be realized through internal logic; The output driving circuit 3 includes: a target signal transmission branch, a first relay driving branch 31 and a second relay driving branch 32 which are independently controlled.

[0053] Combined with the introduction of the foregoing content, in the embodiment of the present application, the CPU unit 1 calculates and controls the circuit to complete logical operations, arithmetic operations and timing control, decides whether to output the target signal, and completes communication with the CPLD unit 2 at the same time; the CPU unit 1 and the CPLD unit 2 jointly complete the read and write timing control, the CPLD completes the address decoding and read and write timing control internally, the CPU accesses the input information collected by the CPLD through the LocalBus, completes the parameter register configuration and external timing control, etc.; in the present invention, LocalBus is used to realize data transmission between the CPU unit 1 and the CPLD unit 2, but it is not specifically limited, and it can also be an SPI interface, a UART interface, a PCIe interface, etc.

[0054] The CPLD unit 2 has at least an interface communication module, a pulse generation module, a credibility authentication module, and an output control enable module that can be realized through internal logic; among them, the CPLD pulse generation module is responsible for generating pulses with configurable period and duty cycle, and the credibility authentication module includes setting up various data verification registers to perform strict timing and data verification to authenticate whether the output behavior of this key signal is legal; the output control enable module controls external relays and internal electronic switches to ensure that all conditions meet the requirements before outputting key signals.

[0055] The target signal transmission branch in the output drive circuit 3 is used to transmit the target signal to the receiver, while the first relay drive branch 31 and the second relay drive branch 32 are used to control the first relay 4 and the second relay 5 connected thereto to close respectively after the output drive circuit 3 receives the enable signal.

[0056] In a preferred embodiment, the target signal transmission branch includes: a first relay 4 and a second relay 5 connected in series with the CPLD unit 2, for transmitting the target signal to the receiving party; One end of the first relay driving branch 31 is connected to the CPLD unit 2, and the other end is connected to the first relay 4; one end of the second relay driving branch 32 is connected to the CPLD unit 2, and the other end is connected to the second relay 5; The first relay driving branch 31 and the second relay driving branch 32 are used to activate the first relay 4 and the second relay 5 respectively.

[0057] After the output drive circuit 3 receives the enable signal and controls the first relay 4 and the second relay 5 to close respectively, it is also necessary to meet the condition that the second data information written by the CPU unit 1 to the main switch enable register is consistent with the preset control information, that is, the main logic switch is also closed. Then, after the first relay 4 and the second relay 5 arranged in series are closed, the preset timing pulse generated by the CPLD pulse generation module in the CPLD unit 2 is sent to the receiver through the input end connected to the first relay 4 or the second relay 5, and then a discrete quantity signal or a pulse signal is output.

[0058] Since the first relay 4 and the second relay 5 are essentially for distinguishing the schemes, they are distinguished in the form of "first" and "second". In essence, there is no difference between the two relays, so the input end connected to an output end of the CPLD unit 2 can be connected to the first relay 4 or the second relay 5. Since the first relay 4 and the second relay 5 are in series, the operation of transmitting signals outward can be realized when the two relays are closed.

[0059] Example 3 A terminal device comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of a method for improving signal reliability as described in Example 1 when executing the computer program.

[0060] In this embodiment, if Figure 3 As shown, the terminal device 500 includes a CPU unit 1, which can perform various appropriate actions and processes according to the program stored in the ROM (read only memory) 502 or the program loaded from the storage part to the RAM (random access memory) 503. In the RAM 503, various programs and data required for system operation are also stored. The CPU unit 1, ROM 502 and RAM 503 are connected to each other through a bus 504. An I / O (input / output) interface 505 is also connected to the bus 504.

[0061] The following components are connected to the I / O interface 505: an input section 506 including a keyboard, a mouse, etc.; an output section 507 including a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 508 including a hard disk, etc.; and a communication section 509 including a network interface card such as a LAN card, a modem, etc. The communication section 509 performs communication processing via a network such as the Internet. A drive is also connected to the I / O interface 505 as needed. A removable medium 511, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 510 as needed, so that a computer program read therefrom is installed into the storage section 508 as needed.

[0062] In particular, according to an embodiment of the present invention, the above reference process diagram Figure 1 The described process can be implemented as a computer software program. For example, embodiment 1 of the present invention includes a computer program product, which includes a computer program carried on a computer readable medium, and the computer program contains program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through a communication part, and / or installed from a removable medium. When the computer program is executed by the CPU unit 1, the above-mentioned functions defined in the system of the present invention are performed.

[0063] It should be noted that the computer-readable medium shown in the present invention may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM) 503, a read-only memory (ROM) 502, an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present invention, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in combination with an instruction execution system, device or device. In the present invention, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, which carries a computer-readable program code. This propagated data signal may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Computer-readable signal media may also be any computer-readable medium other than computer-readable storage media, which may send, propagate or transmit a program for use by or in conjunction with an instruction execution system, apparatus or device. The program code contained on the computer-readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wire, optical cable, RF, etc., or any suitable combination of the above.

[0064] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present invention. In this regard, each box in the flow chart or block diagram can represent a module, a program segment, or a part of a code, and the above-mentioned module, program segment, or a part of a code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flow chart, and the combination of the boxes in the block diagram or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0065] The units involved in the embodiments of the present invention may be implemented by software or hardware, and the units described may also be arranged in a processor. The names of these units do not, in some cases, constitute limitations on the units themselves. The units or modules described may also be arranged in a processor, for example, they may be described as: a processor includes a first generation module, an acquisition module, a search module, a second generation module, and a merging module. The names of these units or modules do not, in some cases, constitute limitations on the units or modules themselves, for example, the acquisition module may also be described as "an acquisition module for acquiring multiple instances to be detected in the basic table."

[0066] Example 4 The present invention also provides a computer-readable medium, which may be included in the electronic device described in the above embodiment; or may exist independently without being assembled into the electronic device. The above computer-readable medium carries one or more programs, and when the above one or more programs are executed by an electronic device, the electronic device implements a method for improving signal reliability as described in the above embodiment.

[0067] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with (but not limited to) technical features with similar functions disclosed in the present application.

Claims

1. A method for improving signal reliability, characterized in that: include: responding to a transmission request of a target signal; Determine whether the first data information written by the CPU to the relay enable register is valid; If yes, activating the first relay and the second relay in the peripheral output drive circuit; Acquire the second data information written by the CPU to the main switch enable register, and determine whether the second data information is consistent with the preset control information; If yes, the preset timing pulse generated by the CPLD pulse generation module is sent to the receiver through the first relay and the second relay as the target signal.

2. A method for improving signal reliability according to claim 1, characterized in that: Before determining whether the first data information written by the CPU to the relay enable register is validly written, the method further includes: The CPU reads back the first calibration information written to the data verification register through the bus. If the read information is consistent with the written first calibration information, it is confirmed that the bus is normal.

3. A method for improving signal reliability according to claim 2, characterized in that: After confirming that the bus is normal and before determining whether the first data information written by the CPU to the relay enable register is validly written, the method further includes: The second calibration information written by the CPU to the identity recognition register is obtained, and if the second calibration information is consistent with the second preset calibration information, it is confirmed that the CPU writes normally.

4. A method for improving signal reliability according to claim 1, characterized in that: The relay enable register includes: a first relay enable register and a second relay enable register which are independently controlled; the first data information includes: two sub-data information which are written into the first relay enable register and the second relay enable register respectively; Determining whether the first data information written by the CPU to the relay enable register is validly written specifically includes: Acquire the sub-data information written into the first relay enable register and the second relay enable register; When the two sub-data information are consistent with the corresponding preset enable information, it is confirmed that the first data information written by the CPU to the relay enable register is effectively written.

5. A method for improving signal reliability according to claim 4, characterized in that: Activating a first relay and a second relay in a peripheral output drive circuit includes: An enable signal is sent to a peripheral output drive circuit to control the peripheral drive circuit to provide current to the first relay and the second relay, so that the first relay and the second relay are attracted and enter an activated state.

6. A method for improving signal reliability according to claim 1, characterized in that: The CPLD pulse generation module generates a first pulse sequence and a second pulse sequence; The preset timing pulse generated by the CPLD pulse generation module is sent to the receiver as the target signal, specifically including: Sending the first pulse sequence and the second pulse sequence according to a preset timing; The first pulse train and the second pulse train have different pulse widths and periods.

7. A circuit for improving signal reliability, characterized in that: A method for improving signal reliability according to any one of claims 1 to 6 is applied, wherein the circuit comprises: A CPU unit (1) and a CPLD unit (2) communicating with each other; The CPLD unit (2) at least comprises an interface communication module, a CPLD pulse generation module, a credibility authentication module, and an output control enabling module that can be realized through internal logic; An output drive circuit (3), the output drive circuit (3) comprising: a target signal transmission branch, an independently controlled first relay drive branch (31) and a second relay drive branch (32).

8. A circuit for improving signal reliability according to claim 7, characterized in that: The target signal transmission branch comprises: the first relay (4) and the second relay (5) which are sequentially connected in series with the CPLD unit (2) and are used to transmit the target signal to the receiving party; One end of the first relay drive branch (31) is connected to the CPLD unit (2), and the other end is connected to the first relay (4); one end of the second relay drive branch (32) is connected to the CPLD unit (2), and the other end is connected to the second relay (5); The first relay driving branch (31) and the second relay driving branch (32) are used to activate the first relay (4) and the second relay (5) respectively.

9. A terminal device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of a method for improving signal reliability as claimed in any one of claims 1 to 6 are implemented.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of a method for improving signal reliability as described in any one of claims 1 to 6 are implemented.

Images