Signal processing method, device and system

Abstract

The invention discloses a signal processing method, device and system, and relates to the technical field of communication. In the method, a signal to be transmitted is encoded to obtain a plurality of code blocks, and the plurality of code blocks not only comprise a first data signal and / or a first control signal, but also comprise a management signal, so that the signal types included in the plurality of code blocks are rich. In addition, according to the method, a plurality of code blocks are transmitted through one serial channel, and the number of pins of the serial channel can be small. In addition, the method can adopt a serial channel realized based on the MII, so that the method can be applied to the scene of the MII.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a signal processing method, device and system. Background Art

[0002] In the field of communication technology, a signal transmitting end may process a signal and transmit the obtained processing result to a signal receiving end, and the signal receiving end may restore the signal based on the received processing result. Summary of the invention

[0003] The present application proposes a signal processing method, device and system for processing a signal.

[0004] In a first aspect, a signal processing method is provided, the method comprising: encoding a signal to be transmitted to obtain a plurality of code blocks, the plurality of code blocks including a first data signal and / or a first control signal, and the plurality of code blocks also including a management signal; and sending the plurality of code blocks through a serial channel. In the method, since the plurality of code blocks include a management signal, as well as a first data signal and / or a first control signal, the plurality of code blocks can include the contents of more types of signals. When the plurality of code blocks are transmitted through a serial channel, only a few pins need to be set to implement the serial channel, and then the transmission of the first data signal, the first control signal, and the management signal is implemented based on the serial channel.

[0005] In a possible implementation, a first code block among the multiple code blocks includes a first part and a second part, the first part includes a first data signal and / or a first control signal, and the second part includes a management signal. That is, the same first code block can carry a management signal, and can also carry a first data signal and / or a first control signal, and the types of signals carried by the first code block are relatively rich and flexible.

[0006] In a possible implementation, there are multiple first code blocks, and the management signal appears periodically in the multiple first code blocks. Therefore, the position of the management signal in the first code block can be determined relatively quickly based on the regularity of the periodic appearance of the management signal in the multiple first code blocks, and the efficiency of obtaining the management signal from the first code block is relatively high.

[0007] In a possible implementation, the plurality of code blocks include a management code block, and the management code block includes a management signal. That is, in addition to the method of carrying the management signal through the first code block, the management signal can also be carried through the management code block, and the carrying method of the management signal is relatively flexible. Furthermore, when the management code block includes a management signal of multiple bits, the management signal is transmitted by transmitting the management code block, and the transmission efficiency of the management signal is relatively high.

[0008] In one possible implementation, the serial channel is used to connect the media access control (MAC) layer and the physical layer (PHY). In this case, the serial channel can be called a serial channel implemented based on a media independent interface (MII), so the method can be applied to the MII scenario.

[0009] In a possible implementation, the serial channel is implemented by one pin or a group of pins, so that the number of pins used to implement the serial channel can be relatively small.

[0010] In a possible implementation, the signal to be transmitted is related to an Ethernet frame, so the method can be applied to the Ethernet scenario.

[0011] In a possible implementation, the management signal includes a first management data input output (MDIO) signal corresponding to the read operation; the method further includes: receiving a second MDIO signal, the second MDIO signal being used to provide feedback on the read operation. Thus, the method can implement interaction of management signals by transmitting the first MDIO signal and the second MDIO signal.

[0012] In a possible implementation, the serial channel for receiving the second MDIO signal is different from the serial channel for sending the plurality of code blocks. In this case, it is possible to determine whether the transmitted MDIO signal is the first MDIO signal or the second MDIO signal based on the serial channel, thereby avoiding confusion between a read operation and feedback of a read operation, or between feedback of a read operation and a read operation.

[0013] In a possible implementation, the method is applied to a PHY function module, and the plurality of code blocks further include a physical layer channel state indication. Thus, the method can realize the transmission of the physical layer channel state indication.

[0014] In a second aspect, a signal processing method is provided, the method comprising: receiving a plurality of code blocks through a serial channel, the plurality of code blocks including a first data signal and / or a first control signal, and the plurality of code blocks also including a management signal; obtaining a management signal, and the first data signal and / or the first control signal from the plurality of code blocks. In the method, since the plurality of code blocks include a management signal, and the first data signal and / or the first control signal, the plurality of code blocks can include the content of more types of signals. When the plurality of code blocks are transmitted through a serial channel, only a few pins need to be set to realize the serial channel, and then the transmission of the first data signal, the first control signal and the management signal is realized based on the serial channel.

[0015] In a possible implementation, a first code block among multiple code blocks includes a first part and a second part, the first part includes a first data signal and / or a first control signal, and the second part includes a management signal; obtaining the management signal, as well as the first data signal and / or the first control signal from the multiple code blocks includes: obtaining the first data signal and / or the first control signal from the first part of the first code block; obtaining the management signal from the second part of the first code block. In this method, the same first code block can carry the management signal, and can also carry the first data signal and / or the first control signal, and the types of signals carried by the first code block are relatively rich and flexible, so that multiple signals can be obtained based on the first code block.

[0016] In a possible implementation, there are multiple first code blocks, and the second part appears periodically in the multiple first code blocks; obtaining the management signal from the second part of the first code block includes: obtaining the periodically appearing second part from the multiple first code blocks; obtaining the management signal from the second part. In this method, according to the regularity of the periodic appearance of the second part in the multiple first code blocks, the position of the management signal in the first code block can be determined relatively quickly, so that the efficiency of obtaining the management signal from the first code block is relatively high.

[0017] In a possible implementation, the multiple code blocks include a management code block, and the management code block includes a management signal; obtaining the management signal from the multiple code blocks includes: obtaining the management signal from the management code block. That is, in addition to the method of carrying the management signal through the first code block, the management signal can also be carried through the management code block, and the carrying method of the management signal is more flexible. Furthermore, in the case where the management code block includes a management signal of multiple bits, the management signal is transmitted by transmitting the management code block, and the transmission efficiency of the management signal is higher.

[0018] In a possible implementation, the serial channel is used to connect the MAC layer and the PHY. In this case, the serial channel can be called a serial channel implemented based on MII, so the method can be applied to the MII scenario.

[0019] In a possible implementation, the serial channel is implemented by one pin or a group of pins, so that the number of pins used to implement the serial channel can be relatively small.

[0020] In a possible implementation, the management signal includes a first MDIO signal corresponding to the read operation; the method further includes: sending a second MDIO signal, the second MDIO signal being used to provide feedback on the read operation. Thus, the method can implement interaction of management signals by transmitting the first MDIO signal and the second MDIO signal.

[0021] In a possible implementation, the serial channel for sending the second MDIO signal is different from the serial channel for receiving the plurality of code blocks. In this case, it is possible to determine whether the transmitted MDIO signal is the first MDIO signal or the second MDIO signal based on the serial channel, thereby avoiding confusion between a read operation and feedback of a read operation, or between feedback of a read operation and a read operation.

[0022] In a possible implementation, the method is applied to a MAC function module, the multiple code blocks also include a physical layer channel state indication; the method further includes: obtaining the physical layer channel state indication from the multiple code blocks. Thus, the method can realize the transmission of the physical layer channel state indication.

[0023] In a third aspect, a signal processing device is provided, which includes: a transceiver module for performing operations related to receiving and / or sending in the first aspect and any corresponding possible implementation method; a processing module for performing other operations other than the operations related to receiving and / or sending in the first aspect and any corresponding possible implementation method.

[0024] In a fourth aspect, a signal processing device is provided, which includes: a transceiver module for performing operations related to receiving and / or sending in the second aspect and any corresponding possible implementation method; a processing module for performing other operations other than the operations related to receiving and / or sending in the second aspect and any corresponding possible implementation method.

[0025] In a fifth aspect, a chip is provided, comprising: a MAC layer circuit, wherein the MAC layer circuit is used to execute any signal processing method in the first aspect and / or the second aspect.

[0026] In a sixth aspect, another chip is provided, the chip comprising: a PHY circuit, the PHY circuit is used to execute any signal processing method in the first aspect and / or the second aspect.

[0027] In the seventh aspect, a communication system is provided, which includes a MAC layer circuit and a PHY circuit, the MAC layer circuit is used to execute the signal processing method in the first aspect, and the PHY circuit is used to execute the signal processing method in the second aspect; or, the PHY circuit is used to execute the signal processing method in the first aspect, and the MAC layer circuit is used to execute the signal processing method in the second aspect.

[0028] It should be understood that the beneficial effects achieved by the technical solutions of the third to seventh aspects of the present application and the corresponding possible implementation methods can be referred to the technical effects of the technical solutions of the first to second aspects and their corresponding possible implementation methods, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a pin diagram of MII in the related art;

[0030] Figure 2 This is a pin diagram of RMII in the related art;

[0031] Figure 3 is a schematic diagram of a host, SPI and MACPHY chip in a related art;

[0032] Figure 4 It is a schematic diagram of SGMII compatible with a transmission rate of 100Mbps in a related art;

[0033] Figure 5 It is a schematic diagram of a signal transmitted by a MII interface in a related art;

[0034] Figure 6 is a schematic diagram of transmitting management signals in a related art;

[0035] Figure 7 It is a schematic diagram of an implementation environment provided by an embodiment of the present application;

[0036] Figure 8 is a flow chart of a signal processing method provided by an embodiment of the present application;

[0037] Fig. 9 It is a schematic diagram of the format of a management frame provided in an embodiment of the present application;

[0038] Fig.10 is a schematic diagram of the format of another management frame provided in an embodiment of the present application;

[0039] Fig.11 is a schematic diagram of multiple first code blocks provided in an embodiment of the present application;

[0040] Fig.12 is a schematic diagram of another plurality of first code blocks provided in an embodiment of the present application;

[0041] Fig.13 is a schematic diagram of another type of multiple first code blocks provided in an embodiment of the present application;

[0042] Fig.14 is a schematic diagram of another type of multiple first code blocks provided in an embodiment of the present application;

[0043] Fig.15 is a schematic diagram of another type of multiple first code blocks provided in an embodiment of the present application;

[0044] Fig.16 is a schematic diagram of a management code block provided in an embodiment of the present application;

[0045] Fig.17 is a schematic diagram of a code block provided in an embodiment of the present application;

[0046] Fig.18 is a schematic diagram of a second code block provided in an embodiment of the present application;

[0047] Fig.19 is a schematic diagram of a third code block provided in an embodiment of the present application;

[0048] Fig. 20 is a schematic diagram of a first code block provided in an embodiment of the present application;

[0049] Fig.21 It is a transmission schematic diagram of an Ethernet frame provided in an embodiment of the present application;

[0050] Fig. 22 is a schematic diagram of misidentification provided by an embodiment of the present application;

[0051] Fig.23 It is a schematic diagram of a process of transmitting multiple code blocks provided by an embodiment of the present application;

[0052] Fig.24 This is a schematic diagram of a process of transmitting a first code block provided by an embodiment of the present application;

[0053] Fig.25 is another schematic diagram of a process for transmitting a first code block provided in an embodiment of the present application;

[0054] Fig.26 It is a schematic diagram of a process of transmitting a management code block provided by an embodiment of the present application;

[0055] Fig. 27 is a schematic diagram of another code block provided in an embodiment of the present application;

[0056] Fig.28 It is a schematic diagram of a process of transmitting an H.sig code block provided in an embodiment of the present application;

[0057] Fig.29 It is a schematic diagram of another process of transmitting H.sig code blocks provided in an embodiment of the present application;

[0058] Fig.30 This is another schematic diagram of a process for transmitting an H.sig code block provided in an embodiment of the present application;

[0059] Fig.31 is a schematic diagram of another first code block provided in an embodiment of the present application;

[0060] Fig.32 is another schematic diagram of a process for transmitting multiple first code blocks provided in an embodiment of the present application;

[0061] Fig.33 is a schematic diagram of a newly added code table provided in an embodiment of the present application;

[0062] Fig.34 is a schematic diagram of a physical layer signal indicator code provided in an embodiment of the present application;

[0063] Fig.35 is a flowchart of another signal processing method provided by an embodiment of the present application;

[0064] Fig.36 It is a schematic diagram of a process of inputting multiple code blocks into RS provided by an embodiment of the present application;

[0065] Fig.37 It is a schematic diagram of a synchronization process of a management channel provided in an embodiment of the present application;

[0066] Fig.38 It is a schematic diagram of a synchronization process of a data channel provided in an embodiment of the present application;

[0067] Fig.39 is a structural schematic diagram of a signal processing device provided in an embodiment of the present application;

[0068] Fig.40 is a structural schematic diagram of another signal processing device provided in an embodiment of the present application;

[0069] Fig.41 is a schematic diagram of the structure of a computer system provided in an embodiment of the present application;

[0070] Fig.42 It is a structural diagram of another computer system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0071] The terms used in the implementation method of this application are only used to explain the embodiments of this application, and are not intended to limit this application. The embodiments of this application are described below in conjunction with the accompanying drawings.

[0072] In the field of communication technology, a signal transmitting end can process a signal to be transmitted to obtain a processing result, and send the processing result to a signal receiving end. Among them, the signal transmitting end can encode the signal, and the processing result includes multiple code blocks obtained by encoding. The signal receiving end can decode the multiple code blocks to restore the signal. In the related art, only a data signal or a control signal is encoded to obtain multiple code blocks. Since the types of signals obtained by encoding multiple code blocks are small, the multiple code blocks only carry information of the data signal or the control signal, and the types of information carried by the multiple code blocks are small.

[0073] In addition, in the field of communication technology, the media access control (MAC) chip and the physical layer (PHY) chip can transmit signals through the media independent interface (MII). For example, in scenarios such as industrial IoT, the IoT terminal includes a PHY chip and a microcontroller (MCU), and the MCU includes a MAC chip. The PHY chip and the MAC chip transmit signals through the MII. For another example, in a scenario where a switch is used, the switch includes a PHY chip and a MAC chip, and the PHY chip and the MAC chip transmit signals through the MII.

[0074] In the related art, MII is a parallel interface, and MII includes pins for transmitting data signals, pins for transmitting control signals, and pins for transmitting management signals. Figure 1 This is a pin diagram of MII in related technology, such as Figure 1 As shown in the figure, MII is used to realize signal transmission between MAC chip and PHY chip. MII includes 18 pins, and the signals transmitted by these 18 pins are as follows: 1 pin is used to transmit the transmit enable signal (transmit enable, TX_EN), 1 pin is used to transmit the transmit data error prompt signal (transmit error, TX_ER), 4 pins are used to transmit the transmit data signal (transmitdata, TXD), Figure 1 In the figure, these four pins are represented as TXD<3:0>, one pin is used to transmit the transmit data reference clock (transmit clock, TX_CLK), one pin is used to transmit the receive data error prompt signal (receive error, RX_ER), one pin is used to transmit the receive data valid signal (receive data valid, RX_DV), and four pins are used to transmit the receive data signal (receive data, RXD). Figure 1 The four pins used to transmit RXD are represented as RXD<3:0>, one pin is used to transmit the receive data reference clock (receive clock, RX_CLK), one pin is used to transmit the collision detection (collision detected, COL) signal, one pin is used to transmit the carrier sense (carrier sense, CRS) signal, one pin is used to transmit the management data clock (management data clock, MDC), and one pin is used to transmit the management data input and output (management data input output, MDIO) signal.

[0075] However, in scenarios such as industrial IoT, since the chip packaging cost increases with the number of chip pins, the number of chip pins needs to be controlled. In the case where the number of pins that a chip can provide is relatively limited, it is necessary to reduce the number of MII pins so that the MCU can allocate more pins to provide other functions. In the scenario of using a switch, the MAC chip can be included in the switching chip. Since the switching chip usually needs to connect more Ethernet chips to support more Ethernet interfaces, it is necessary to reduce the number of MII pins of the MAC chip so that the switching chip can support more Ethernet interfaces.

[0076] In a related technology, a reduced media independent interface (RMII) is obtained based on the MII, and signals between a MAC chip and a PHY chip are transmitted through the RMII. Figure 2 This is a pin diagram of RMII in the related art, such as Figure 2 As shown in the figure, RMII is used to realize signal transmission between MAC chip and PHY chip. RMII includes 9 pins, and the signals transmitted by these 9 pins are as follows: 1 pin is used to transmit TX_EN, 2 pins are used to transmit TXD, Figure 2 In the example, these two pins are represented as TXD<1:0>, one pin is used to transmit RX_ER, and two pins are used to transmit RXD. Figure 2 The two pins used to transmit RXD are represented as RXD<1:0>, one pin is used to transmit the carrier sense data valid (CRS_DV) signal, one pin is used to transmit the MDC signal, and one pin is used to transmit the MDIO signal. However, the number of RMII pins is still large.

[0077] In another related technology, a MAC chip and a PHY chip are integrated into a media access control physical layer (MACPHY) chip, and the MCU may include the MACPHY chip, and the MACPHY chip is communicatively connected with a host via a serial peripheral interface (SPI). Figure 3 This is a schematic diagram of a host, SPI and MACPHY chip in a related art. Figure 3As shown in FIG. 1 , the host and the MACPHY chip transmit serial clock signals (serial clock, SCK), master output slave input (master output slave input, MOSI), n chip selects (chip select, CS), master input slave output (master input slave output, MISO) and n interrupt requests (interrupt request, IRQ), where n is a positive integer and n CS is transmitted through Figure 3 CSn shown in the figure indicates that n IRQs are connected through Figure 3 The IRQn shown in the figure indicates that the MACPHY chip can also transmit signals to other chips, such as Figure 3 As shown, the MACPHY chip is connected with signal line 1 and signal line 2, and signal line 1 and signal line 2 can be used to transmit differential signals to other chips. However, the SPI in the related art is not suitable for a transmission rate of 100 megabit per second (Mbps), resulting in a relatively limited scope of application.

[0078] In another related technology, signal transmission between a MAC chip and a PHY chip is implemented through a serial gigabit media independent interface (SGMII). The bit width of SGMII is 8 bits and supports a transmission rate of 1000 megabits per second (Mbps). SGMII is backward compatible with transmission rates of 10Mbps and 100Mbps. In the case of SGMII being compatible with a transmission rate of 10Mbps, the data is copied 100 times and then the copied data is transmitted. In the case of SGMII being compatible with a transmission rate of 100Mbps, the data is copied 10 times and then the copied data is transmitted. Figure 4 The figure is a schematic diagram of SGMII compatible with 100Mbps transmission rate in related technology. Figure 4 As shown in FIG. 1 , the data to be transmitted at a transmission rate of 100 Mbps include d0, d1, and d2. For each data to be transmitted at a transmission rate of 100 Mbps, each data is copied 10 times, and then the copied data can be transmitted through SGMII, so that SGMII is compatible with a transmission rate of 100 Mbps. However, the method of copying data multiple times to be compatible with a lower transmission rate results in higher transmission costs and power consumption.

[0079] Furthermore, since the data width of SGMII is 8 bits and the data width of MII is 4 bits, if SGMII is used to replace MII, the difference in data width will lead to the problem of data width mismatch. Figure 5 It is a schematic diagram of the signal transmitted by the MII interface in the related art, such as Figure 5 As shown, RX_DV indicates that 4 bits of 0101, D1, D2, / F / and D4 to D7 are valid data, RX_ER indicates that / F / is error data, and D1, D2, D4 to D7 are all non-error data. Among them, D1, D2, / F / and D4 to D7 are all 4 bits. For the error data / F / transmitted by MII, if SGMII is used to replace MII, the data transmitted by SGMII to replace the error data / F / will meet the requirement that the data width of SGMII is 8 bits by occupying D2 or D4. In other words, the 8-bit data width of SGMII cannot match the 4-bit data width of MII.

[0080] In another related technology, the management signal is transmitted through an independent channel. For example, Figure 6 The switch chip includes a MAC chip, and see Figure 6 , the switching chip is connected to multiple PHY chips, and the switching chip is also connected to a complex programmable logic device (CPLD) or MCU. The switching chip establishes channels for transmitting management signals with N PHY chips through CPLD or MCU, where N is a positive integer. That is to say, the switching chip transmits management signals with N PHY chips through CPLD or MCU, and the management signals include MDIO signals. However, the method of establishing channels for transmitting management signals through CPLD or MCU has a high equipment cost for transmitting management signals and a large development workload.

[0081] The embodiment of the present application provides a signal processing method for encoding and decoding a signal to be transmitted to realize signal processing. The method can be applied to a scenario where a signal is transmitted via MII, that is, the signal to be transmitted is a signal transmitted by MII. The method can also be applied to other scenarios besides MII. Figure 7 is a schematic diagram of an implementation environment provided by an embodiment of the present application, and the method can be applied to Figure 7 The implementation environment shown, wherein Figure 7 The implementation environment shown is an example of the MII scenario. The method can also be applied to other implementation environments. For example, the implementation environment in which the method is applied includes chip 1 and chip 2, and chip 1 and chip 2 are connected, and the method can be applied to chip 1 or chip 2.

[0082] See also Figure 7 , the implementation environment includes a switch 701 and an IoT terminal 702. The switch 701 includes a MAC function module 7011 and a PHY function module 7012, and the MAC function module 7011 and each PHY function module 7012 transmit signals through the MII. The IoT terminal 702 includes a MAC function module 70211 and a PHY function module 7022, and the MAC function module 70211 and the PHY function module 7022 transmit signals through the MII. Signals can be transmitted between the PHY function module 7012 and the PHY function module 7022. In some embodiments, the IoT terminal 702 includes an MCU 7021 and a PHY function module 7022, and the MCU 7021 includes a MAC function module 70211. In some embodiments, one or more of the MAC function module 7011, the PHY function module 7012, the MAC function module 70211, and the PHY function module 7022 can be located in a separate chip, or in a separate die, or in one or more cores of a multi-core chip. The signal processing method provided in the embodiment of the present application can be applied to signal transmission between the MAC function module 7011 and the PHY function module 7012 , and can also be applied to signal transmission between the MAC function module 70211 and the PHY function module 7022 . Figure 7 The number of switches 701, the number of MAC function modules 7011, the number of PHY function modules 7012, the number of IoT terminals 702, the number of MCUs 7021, the number of MAC function modules 70211, and the number of PHY function modules 7022 shown are only examples, and the embodiments of the present application are not limited thereto. Exemplarily, the switches 701 and IoT terminals 702 may be single pair Ethernet (SPE) devices or advanced physical layer (APL) devices.

[0083] The signal processing method provided in the embodiment of the present application can be as follows Figure 8 As shown, next, combined with Figure 7 The method is described in the implementation environment shown. The method can be applied to Figure 7 The MAC functional module or PHY functional module shown. Figure 8 As shown, the method includes but is not limited to S801 and S802.

[0084] S801, encode a signal to be transmitted to obtain a plurality of code blocks, wherein the plurality of code blocks include a first data signal and / or a first control signal, and the plurality of code blocks also include a management signal.

[0085] In one possible implementation, the signal to be transmitted includes at least one of a first data signal and / or a first control signal, and the signal to be transmitted also includes a management signal. The signal type included in the multiple code blocks is determined based on the signal type included in the signal to be transmitted. Thus, in the case where the signal to be transmitted includes the first data signal, the multiple code blocks include the first data signal; in the case where the signal to be transmitted includes the first control signal, the multiple code blocks include the first control signal; in the case where the signal to be transmitted includes the management signal, the multiple code blocks include the management signal. In an embodiment of the present application, the first data signal may be a signal for transmitting data, the first control signal may be a signal for controlling the transmission of data, and the management signal may be a signal other than the first data signal and the first control signal.

[0086] Taking the example that the signal to be transmitted includes a signal transmitted through the MII, the management signal includes an MDIO signal. For example, the method is applied to a MAC functional module, and the MAC functional module includes a management entity (station management entity, STA). In this case, the management signal includes an MDIO signal driven by the STA. For another example, the method is applied to a PHY functional module. In this case, the management signal includes an MDIO signal driven by the PHY functional module. The way in which STA drives the MDIO signal can refer to the way in which STA drives the MDIO signal in the Institute of Electrical and Electronics Engineers (IEEE) 802.3 standard, and the way in which the PHY functional module drives the MDIO signal can refer to the way in which the PHY functional module drives the MDIO signal in the IEEE 802.3 standard, which will not be further described here.

[0087] In one possible implementation, the MDIO signal is related to a management frame, for example, each bit of the MDIO signal is used to form a management frame. The management frame includes an operation (OP) field, and the operation type indicated by the operation field includes any one of a write operation, a read operation, or a read feedback operation. For example, when the method is applied to a MAC function module, the operation type indicated by the operation field is a write operation or a read operation; when the method is applied to a PHY function module, the operation type indicated by the operation field is a read feedback operation. The management frame may also include other fields besides the operation field. Fig. 9 is a schematic diagram of the format of a management frame provided in an embodiment of the present application, such as Fig. 9As shown, the management frame includes a start field, an operation field, a physical layer address field, a register address field, a reserved field, and a register data field. The start field is used to indicate the start of the management frame transmission, the physical layer address field is used to indicate the address of the PHY function module where the register to be operated is located, the register address field is used to indicate the address of the register, the register data field is used to indicate the data for performing the operation, and the reserved field can be a preset value. Fig. 9 As shown, the length of the start field is 2 bits, the length of the operation field is 2 bits, the length of the physical layer address field is 5 bits, the length of the register address field is 5 bits, the length of the reserved field is 2 bits, and the length of the register data field is 16 bits.

[0088] Fig.10 is a schematic diagram of another management frame format provided by an embodiment of the present application. Fig.10 , when the method is applied to the MAC function module and data needs to be written to a register of the PHY function module, the operation type indicated by the operation field is a write operation, and the value of the operation field can be 01; the physical layer address field is used to indicate the address of the PHY function module, the register address field is used to indicate the address of the register, and the value of the reserved field is the first preset value, Fig.10 Where xx may represent a first preset value; the register data field is used to indicate the data that needs to be written into the register.

[0089] In the case where the method is applied to the MAC function module and the value of a register of the PHY function module needs to be read, the operation type indicated by the operation field is a read operation, and the value of the operation field can be 10; the physical layer address field is used to indicate the address of the PHY function module, the register address field is used to indicate the address of the register, and the value of the reserved field is a first preset value; since the first processor is not used to write data to the register, the value of the register data field can be a second preset value, Fig.10 Where xxxxx may represent a second preset value.

[0090] In the case where the method is applied to a PHY function module and the data of a register of the PHY function module needs to be fed back to the MAC function module, the operation type indicated by the operation field is a read feedback operation, and the value of the operation field can be 10; the physical layer address field is used to indicate the address of the PHY function module, the register address field is used to indicate the address of the register, the value of the reserved field is a first preset value, and the value of the register data field is used to indicate the data read in the register. Exemplarily, since the read operation and the read feedback operation are for the same register, such as Fig.10 As shown, the value of the physical layer address field corresponding to the read operation and the read feedback operation is the same, and the value of the register address field is the same.

[0091] The values ​​of the above-mentioned operation fields, the values ​​of the reserved fields, and the values ​​of the register data fields when the operation type is a read operation are only used for illustration. Those skilled in the art can set them according to experience or actual needs, and the embodiments of the present application do not limit this. In a possible implementation, whether the method is applied to a MAC functional module or a PHY functional module, the management signal is obtained based on the management frame and idle (idle), and the idle can be before or after the management frame. For example, see Fig. 9 ,Except for management frames, there are idle periods before and after management frames. Management frames and idle periods are used to obtain management signals.

[0092] Still taking the example of the signal to be transmitted including the signal transmitted through MII, when the method is applied to the MAC function module, both the first data signal and the first control signal can be transmitted through Figure 1 TX_EN, TX_ER and TXD are shown as a whole. That is, the validity and invalidity of TX_EN and the validity and invalidity of TX_ER indicate whether the signal transmitted by TXD is a data signal or a control signal. Among them, the data signal includes but is not limited to the data (data) included in the Ethernet frame, and the control signal includes but is not limited to the preamble (preamble), low power idle (low power idle, LPI) and end-of-frame delimiter (end-of-frame delimiter, EFD) during Ethernet frame transmission. In the case where the method is applied to the PHY function module, the first data signal and the first control signal can be passed Figure 1 The RX_DV, RX_ER and RXD are shown as a whole. That is, the validity and invalidity of RX_DV and the validity and invalidity of RX_ER indicate whether the signal transmitted by RXD is a data signal or a control signal.

[0093] In one possible implementation, the signal to be transmitted is related to the Ethernet frame. That is, the method can be applied in an Ethernet scenario. Exemplarily, the signal to be transmitted includes a first data signal and / or a first control signal, and the first data signal and / or the first control signal are generated based on the Ethernet frame to be transmitted. The signal to be transmitted also includes a management signal, and the management signal can be used to manage the transmission of the Ethernet frame. Exemplarily, when the method is applied to the MAC function module for execution, the MAC function module converts the Ethernet frame to be transmitted into a parallel signal transmitted through the MII, and obtains the signal to be transmitted based on the parallel signal transmitted through the MII. Among them, the parallel signal transmitted through the MII refers to the signal transmitted through the MII. Figure 1 The signals transmitted by the multiple pins of the MII are shown. Exemplarily, part or all of the data signals transmitted by the MII are used as the first data signal, and part or all of the control signals transmitted by the MII are used as the first control signal.

[0094] Alternatively, both the first data signal and the first control signal may be generated based on an Ethernet frame. For example, when the method is applied to a MAC function module, the MAC function module obtains an Ethernet frame and generates a first data signal based on the Ethernet frame. For another example, when the method is applied to a MAC function module, the MAC function module obtains an Ethernet frame and generates a first sub-signal of a first control signal based on the Ethernet frame. In some embodiments, the first processor may also generate a second sub-signal of the first control signal. Among them, the first sub-signal may be a signal obtained based on the content of the Ethernet frame, for example, the first sub-signal is a control signal of MII transmission obtained based on the Ethernet frame; the second sub-signal may be an error signal for transmitting error information. For example, an error signal is generated when the transmission of the Ethernet frame needs to be interrupted. For another example, after the transmission of the Ethernet frame is completed, if the channel needs to be occupied continuously, an error signal is generated. The embodiment of the present application does not limit the format of the error signal. That is, if the signal to be transmitted includes a first data signal, the first data signal is obtained based on an Ethernet frame; if the signal to be transmitted includes a first control signal, the first control signal includes at least one of the first sub-signal obtained based on the Ethernet frame or the second sub-signal generated.

[0095] In a possible implementation, when the Ethernet frame carries data, the signal to be transmitted includes a first data signal generated based on the carried data; when the Ethernet frame does not carry data, the signal to be transmitted does not include the first data signal. Exemplarily, the first sub-signal of the first control signal is obtained based on other parts of the Ethernet frame except the start of the Ethernet frame, or based on other parts of the Ethernet frame except the start of the Ethernet frame and the end of the Ethernet frame. In an embodiment of the present application, the Ethernet frame can also be used to obtain a second control signal, or to obtain a second control signal and a third control signal. For example, a second control signal is generated based on the Ethernet frame start of the Ethernet frame, or a second control signal is generated based on the Ethernet frame start of the Ethernet frame, and a third control signal is generated based on the Ethernet frame end of the Ethernet frame. In the case where the second control signal is obtained, the signal to be transmitted may include the second control signal. In the case where the second control signal and the third control signal are obtained, the signal to be transmitted may include the second control signal and the third control signal.

[0096] In the case of obtaining the signal to be transmitted, the signal to be transmitted can be encoded to obtain multiple code blocks. In a possible implementation, the first code block in the multiple code blocks includes a first part and a second part, the first part includes a first data signal and / or a first control signal, and the second part includes a management signal. For example, the first part is obtained by encoding the first data bit group of the first data signal and / or the first control bit group of the first control signal, and the second part is obtained based on the management signal. In an embodiment of the present application, the first data bit group of the first data signal may include some bits or all bits of the first data signal, and the first control bit group of the first control signal may include some bits or all bits of the first control signal. The first part may include at least one code block, and the second part may include at least one code block or at least one bit that has not been encoded. Among them, at least one code block included in the second part is obtained by encoding the bits of the management signal, and the embodiment of the present application does not limit the number of bits of a code block obtained by encoding. In an embodiment of the present application, the position of the bit obtained based on the first data signal can be called a data channel, the position of the bit obtained based on the first control signal can be called a control channel, and the position of the bit obtained based on the management signal can be called a management channel.

[0097] In a possible implementation, the code block included in the first part is obtained based on any one of 4B / 5B encoding, 8B / 9B encoding, 8B / 10B encoding, 64B / 65B encoding, 64B / 66B encoding, and 80B / 81B encoding. In some embodiments, if the second part includes at least one bit that has not been encoded, the at least one bit included in the second part may be a transformed bit or an untransformed bit. The embodiment of the present application does not limit the transformation method. For example, the transformation method includes sequential transformation, and the second part includes multiple bits that have been sequentially transformed. If the second part includes at least one code block obtained by encoding, the code block included in the second part is obtained based on any one of 4B / 5B encoding, 8B / 9B encoding, 8B / 10B encoding, 64B / 65B encoding, 64B / 66B encoding, or 80B / 81B encoding. In some embodiments, when the first part and the second part of the first code block both include encoded code blocks, the encoding method of the code blocks in the first part and the encoding method of the code blocks in the second part may be the same or different, so that the encoding method of the code blocks in the first part and the encoding method of the code blocks in the second part are more flexible.

[0098] Exemplarily, when there are multiple first code blocks, the management signal appears periodically in the multiple first code blocks. Fig.11 is a schematic diagram of a plurality of first code blocks provided in an embodiment of the present application, see Fig.11 , each first code block includes a first part and a second part, and the first part and the second part appear alternately in multiple first code blocks, so that the management signal appears periodically in multiple first code blocks.

[0099] In a possible implementation, the encoding result of the first part is used to indicate that the first part is obtained by encoding the first data bit group of the first data signal, or by encoding the first control bit group of the first control signal, or by encoding the first data bit group of the first data signal and the first control bit group of the first control signal. For example, the first part includes at least one code block obtained based on 4B / 5B encoding, and for any one of the at least one code block, the overall encoding condition of the any one code block is used to indicate that the code block is obtained by encoding the first data bit group of the first data signal, or by encoding the first control bit group of the first control signal.

[0100] For another example, the first part includes at least one code block obtained based on 8B / 10B encoding. For any one of the at least one code block, the overall encoding status of the any one code block is used to indicate that the code block is obtained by encoding the first data bit group of the first data signal, or by encoding the first control bit group of the first control signal, or by encoding the first data bit group of the first data signal and the first control bit group of the first control signal. Whether the code block of the first part is obtained by 4B / 5B encoding or 8B / 10B encoding, the method of indicating the source of the bits of the code block as a whole can refer to the relevant content of indicating the source of the bits of the code block as a whole obtained by 4B / 5B encoding and 8B / 10B encoding in the IEEE 802.3 standard, which will not be described in detail here.

[0101] In another possible implementation, part of the content in the first part is used to indicate the bit source of the first part. For example, the first part includes a type identification field, and the type identification field is used to indicate that the first part is obtained by encoding the first data bit group of the first data signal, or by encoding the first control bit group of the first control signal, or by encoding the first data bit group of the first data signal and the first control bit group of the first control signal. In the embodiment of the present application, the signal type obtained by obtaining the first part can be referred to as the bit source of the first part.

[0102] Exemplarily, the first part includes at least one code block, each code block includes a type identification field, and the type identification field is used to indicate the type of any code block. The type of a code block corresponds to a bit source, so that for any code block, the type identification field of any code block can indicate the bit source of any code block. For code blocks obtained by different encoding methods, the type identification field of the code block can refer to the field used to identify the type in the code block obtained by the encoding method in the IEEE 802.3 standard. For example, when any code block is obtained based on any encoding method of 8B / 9B encoding, 64B / 65B encoding or 80B / 81B encoding, the type identification field is the bit position of the highest bit of the code block. For another example, when any code block is obtained based on 64B / 66B encoding, the type identification field includes the first 2 bit positions of the code block.

[0103] In some embodiments, the type identification field indicates that the first part is obtained by encoding the first data bit group of the first data signal, and the other parts of the first part except the type identification field can be called the data field. In some embodiments, the type identification field indicates that the first part is obtained by encoding the first control bit group of the first control signal, or by encoding the first data bit group of the first data signal and the first control bit group of the first control signal, and the other parts of the first part except the type identification field can be called the control field.

[0104] Fig.12 is a schematic diagram of another plurality of first code blocks provided in an embodiment of the present application. Fig.12 As shown, for any first code block, the first part of the first code block is obtained based on at least one of the first data bit group of the first data signal or the first control bit group of the first control signal, and the second part of the first code block includes bits of the management signal. Fig.12 In the first code block shown, the first part of the first code block is obtained based on 8B / 9B encoding, the first part includes 9 bits, and the most significant bit position of the 9 bits is used as a type identification field. The second part of the first code block includes 1 bit.

[0105] Fig.13 FIG. 1 is another schematic diagram of multiple first code blocks provided in an embodiment of the present application. Fig.13 As shown, for any first code block, the first part of the first code block is obtained based on at least one of the first data bit group of the first data signal or the first control bit group of the first control signal, and the second part of the first code block includes bits of the management signal. Fig.13 In the first code block shown, the first part of the first code block is obtained based on 64B / 65B encoding, the first part includes 65 bits, and the most significant bit position of the 65 bits is used as a type identification field. The second part of the first code block includes 1 bit.

[0106] The embodiment of the present application does not limit the way in which the type identification field indicates the source of the bits of the first part. For example, if the type identification field includes 1 bit, the value of this bit is the first value, and the first part is obtained by encoding the first data bit group of the first data signal, that is, the first part includes the type identification field and the data field, and the content of the data field is obtained by encoding the first data bit group of the first data signal. If the value of this bit is the second value, the first part is obtained by encoding the first control bit group of the first control signal, or by encoding the first data bit group of the first data signal or the first control bit group of the first control signal. That is, the first part includes the type identification field and the control field. The content of the control field is obtained by encoding the first control bit group of the first control signal, or by encoding the first data bit group of the first data signal and the first control bit group of the first control signal. Exemplarily, the first value is 0 and the second value is 1.

[0107] In a possible implementation, the control field includes a first subfield and a second subfield. The content of the first subfield is obtained by encoding a first data bit group of a first data signal, and the content of the second subfield is obtained by encoding a first control bit group of a first control signal. Alternatively, the content of the first subfield and the content of the second subfield are both obtained by encoding a first control bit group of a first control signal, and the first bit used to obtain the content of the first subfield is different from the first bit used to obtain the content of the second subfield.

[0108] Fig.14 FIG. 1 is another schematic diagram of multiple first code blocks provided in an embodiment of the present application. Fig.14 As shown, the type identification field of the first part of a first code block includes 1 bit, the value of this bit is 0, indicating that the other parts of the first part except the type identification field are data fields, the data field includes 8 bits, and the second part of this first code block includes 1 bit of management signal. The type identification field of the first part of another first code block includes 1 bit, the value of this bit is 1, indicating that the other parts of the first part except the type identification field are control fields, and the control field includes 8 bits. Among them, the control field includes a first subfield and a second subfield, and the first subfield and the second subfield each include 4 bits. The content of the second subfield can be indicated by the content based on the first subfield, for example, the first subfield is a first control code, in which case the second subfield is an extended control code corresponding to the first control code; or, the first subfield is a second control code, in which case the second subfield carries half-byte data. In the case where the second subfield is an extended control code, the content of the second subfield is obtained by encoding the first control bit group of the first control signal; in the case where the second subfield carries half-byte data, the content of the second subfield is obtained by encoding the first data bit group of the first data signal.

[0109] Fig.14 The lengths of the first subfield and the second subfield shown are only examples, and the lengths of the first subfield and the second subfield may also be other cases, for example, the first subfield includes 2 bits and the second subfield includes 6 bits. Fig.14 The second part of the first code block shown includes 1 bit of the management signal, and the second parts of the two first code blocks are used to carry the management signal.

[0110] In a possible implementation, at least one of the first data bit group of the first data signal or the first control bit group of the first control signal is encoded to obtain a first part of each first code block, and a second part of each first code block is inserted between the plurality of first parts, thereby obtaining each first code block. The second part includes but is not limited to at least one code block obtained based on the management signal or at least one bit of the management signal that has not been encoded.

[0111] Fig.15 FIG. 1 is another schematic diagram of multiple first code blocks provided in an embodiment of the present application. Fig.15 As shown, at least one of the first data bit group of the first data signal or the first control bit group of the first control signal is encoded to obtain a coding sequence, and the first part of each first code block is obtained based on the coding sequence, and then the second part of each first code block is inserted to obtain each first code block. In an embodiment of the present application, a coding symbol can be a code block. Inserting the second part may cause an interruption in the coding sequence. After obtaining multiple first code blocks, multiple code blocks used to identify the boundary of the coding sequence may be located in the first part of the same first code block or in the first part of multiple first code blocks. Thus, when it is necessary to identify the boundary of the coding sequence later, the boundary of the coding sequence can be identified based on the first part of the same first code block, or it can be identified based on the first part of multiple first code blocks.

[0112] In a possible implementation, the first part of the first code block also carries the uncoded second data bit group of the first data signal and / or the uncoded second control bit group of the first control signal. For example, the first part of the first code block carries at least one code block obtained by encoding the first data bit group of the first data signal, and also carries the uncoded second data bit group. Alternatively, the first part of the first code block carries at least one code block obtained by encoding the first control bit group of the first control signal, and also carries the uncoded second control bit group. Alternatively, the first part of the first code block carries at least one code block obtained by encoding the first control bit group of the first control signal, and also carries the uncoded second data bit group. The second data bit group may include some or all of the bits in the first data signal except the first data bit group, and the second control bit group may include some or all of the bits in the first control signal except the first control bit group. In the first data signal, which bits are used as bits of the first data bit group and which bits are used as bits of the second data bit group can be set according to experience or actual needs; in the first control signal, which bits are used as bits of the first control bit group and which bits are used as bits of the second control bit group can also be set according to experience or actual needs, and the embodiments of the present application are not limited. Since the first part may include only the encoded code blocks, or include the encoded code blocks and unencoded bits, the manner in which the first part carries the first data signal or the first control signal is relatively flexible.

[0113] In some embodiments, the plurality of code blocks further include a management code block, and the management code block includes a management signal. That is, the management signal and the first data signal and / or the first control signal are carried in different code blocks. Exemplarily, the management code block includes a third control code and the management signal, and the third control code is used to indicate that the code block is a management code block. Fig.16 is a schematic diagram of a management code block provided in an embodiment of the present application, such as Fig.16 As shown, the third control code is 00011, and the bit position for carrying the management signal is represented by "O". The management code block can also be called a PHY operation administration and maintenance (OAM) code block. The bit position for carrying the management signal can also be set at other bit positions based on experience or needs.

[0114] In some embodiments, the method is applied to a PHY functional module, and the multiple code blocks further include a physical layer channel state indication, which includes but is not limited to part or all of COL and CRS. Fig.17 is a schematic diagram of a code block provided in an embodiment of the present application, such as Fig.17 As shown, the code block includes a fourth control code and a physical layer channel status indication, wherein the fourth control code is 00100, the physical layer channel status indication includes COL and CRS, and the code block also includes an error indication (error, ERR). The code block can also be used to carry management signals, such as Fig.17 The bit position where the "O" is shown is used to carry the management signal. That is, the physical layer signal status indication and the management signal can be encoded into the same code block. The bit position used to carry the management signal, ERR, COL and CRS can also be set at other bit positions based on experience or needs.

[0115] In some embodiments, the signal to be transmitted includes other signals except the management signal, the first data signal and the first control signal. When other signals are included, the other signals are encoded to obtain at least one code block. For example, if the signal to be transmitted includes a second control signal, the second control signal is encoded to obtain a second code block, wherein the second control signal is obtained based on the Ethernet frame start of the Ethernet frame. Thus, the multiple code blocks for encoding the signal to be transmitted include the second code block. Fig.18 is a schematic diagram of a second code block provided in an embodiment of the present application, such as Fig.18 As shown, the second code block includes the / J / code and the / K / code obtained by 4B / 5B encoding in the IEEE 802.3 standard, and the second code block can be used to indicate a start of stream delimiter (SSD).

[0116] If the signal to be transmitted includes a third control signal, the third control signal is encoded to obtain a third code block, wherein the third control signal is obtained based on the Ethernet frame end of the Ethernet frame. Thus, the multiple code blocks obtained by encoding the signal to be transmitted include the third code block. Fig.19is a schematic diagram of a third code block provided in an embodiment of the present application, such as Fig.19 As shown, the third code block includes the / T / code and the / R / code obtained by 4B / 5B encoding in the IEEE 802.3 standard, and the third code block can be used to indicate an end of stream delimiter (ESD). Since the multiple code blocks also include the second code block and the third code block, the types of the multiple code blocks are relatively rich, and the method for encoding the transmission signal is relatively flexible.

[0117] Next, taking the first part of the first code block obtained based on 4B / 5B encoding as an example, the obtained multiple code blocks are described.

[0118] The 4B / 5B encoding method specified in the IEEE 802.3 standard is to encode bits based on half-byte width, and the encoded symbols obtained are used to represent data codes and control codes. The encoding efficiency of 4B / 5B encoding is 4 / 5*100%=80%. Fig. 20 is a schematic diagram of a first code block provided in an embodiment of the present application. Fig. 20 , the first code block includes a first part and a second part, wherein the first part includes a code block obtained based on 4B / 5B encoding and 4 uncoded bits, and the second part includes 1 bit. The bits used to obtain the code block can be the first data bit group of the first data signal or the first control bit group of the first control signal. In the case where the code block is obtained based on the first data bit group, the uncoded bits can be obtained based on the second data bit group. In the case where the code block is obtained based on the first control bit group, the uncoded bits can be obtained based on the second data bit group or the second control bit group.

[0119] Exemplarily, the code block included in the first part is obtained by using the 4B / 5B encoding method specified in the IEEE 802.3 standard, and the encoded code block can be a data code or a control code. In the first part, the specific type of the uncoded 4 bits can be indicated by the type of the code block in the first part. For example, if the code block is a data code, the uncoded 4 bits are the second data bit group of the first data signal. If the code block is a control code, the uncoded 4 bits are the second control bit group of the first control signal or the second data bit group of the first data signal. If the code block is a control code, the second part can be determined according to the type of the control code of the code block.

[0120] In some embodiments, the situation for obtaining the bits of the first part can be indicated by TX_EN and TX_ER of the MII transmission. Fig. 20TX_EN and TX_ER can indicate that the bits of the first half byte are the first data bit group of the first data signal or the first control bit group of the first control signal, and can also indicate that the bits of the second half byte are the second data bit group of the first data signal or the second control bit group of the first control signal. The bits of the first half byte are used to obtain the code block in the first part, and the bits of the second half byte are used to obtain the uncoded bits in the first part.

[0121] The bits of the management signal are used to obtain the second part of the first code block. Fig. 20 As shown, the second part includes one bit of the management signal, which is marked as "0". Fig. 20 As shown, the second part may be located between the code block included in the first part and the uncoded bit, or between the uncoded bits or before or after the first part, which is not limited in the embodiment of the present application. The second part may also include four bits of the second half byte, which may be the second data bit group of the first data signal or the second control bit group of the first control signal.

[0122] In a possible implementation, the uncoded 4 bits are the unchanged second data bit group or the second control bit group, or are the changed second data bit group or the second control bit group. The embodiment of the present application does not limit the manner of changing the second data bit group and the second control bit group. For example, the order of the bits in the second data bit group or the second control bit group is changed. Fig. 20 For the first code block shown, if the first part is obtained based on 8 bits of the first data signal, or based on 8 bits of the first control signal, or based on 4 bits of the first data signal and 4 bits of the first control signal, the coding efficiency of the first code block is 8 / 10*100%=80%.

[0123] In the embodiment of the present application, continuous / J / codes and / K / codes are used for stream synchronization and to indicate SSD. When continuous / J / codes and / K / codes are identified, it is determined that the Ethernet frame starts to be transmitted. Continuous / T / codes and / R / codes are used to indicate ESD. Thus, when continuous / T / codes and / R / codes are identified, it is determined that the Ethernet frame transmission ends. Fig.21 Schematic diagram of the transmission of an Ethernet frame provided in an embodiment of the present application. Fig.21As shown, the Ethernet frame is represented by TX_EN, TX_ER and TXD transmitted by the MII, and the Ethernet frame includes the Ethernet frame start, the Ethernet frame end and the part of the Ethernet frame other than the Ethernet frame start and the Ethernet frame end. The signal representing the Ethernet frame start of the Ethernet frame is encoded to obtain a second code block, the second code block includes a / J / code and a / K / code, the signal representing the Ethernet frame end of the Ethernet frame is encoded to obtain a third code block, the third code block includes a / T / code and a / R / code, and the signal representing the part of the Ethernet frame other than the Ethernet frame start and the Ethernet frame end is encoded to obtain multiple first code blocks. Exemplarily, if the number of bits included in the Ethernet frame is not an integer multiple of a byte, the first part of the last first code block in the multiple first code blocks is encoded based on the first control bit group of the first control signal, and as shown Fig.21 As shown, the first part of the first code block also includes a second data bit group of the first data signal.

[0124] In a possible implementation, by using continuous / J / and / K / codes to represent SSD, it is possible to avoid the content of the first code block being recognized as a / J / code or a / K / code, and continuous / J / and / K / codes can also be represented as / J / K / codes. By using continuous / T / and / R / codes to represent ESD, it is possible to avoid the content of the first code block being recognized as a / R / code, and continuous / T / and / R / codes can also be represented as / T / R / codes.

[0125] Fig. 22 is a schematic diagram of misidentification provided by an embodiment of the present application. Fig. 22 As shown, if the / J / code and the / K / code are not used continuously, the content of the first code block may be identified as the / J / code and the / K / code, causing the first code block to be regarded as the second code block. The content of the previous first code block may be identified as the / J / code, and the content of the next first code block may be identified as the / K / code, causing the content belonging to the two first code blocks to be regarded as a second code block. If the / T / code and the / R / code are not used continuously, the content of the first code block may be identified as the / T / code and the / R / code, causing the first code block to be identified as the third code block. The above three situations will all lead to the misidentification of the first code block, that is, the bits of the management signal are mistaken for the bits of the first control signal. Therefore, in an embodiment of the present application, the / J / code and the / K / code need to be used continuously, and the / T / code and the / R / code need to be used continuously, so as to avoid the first code block from being misidentified as the second code block or the third code block. In this case, a code block including consecutive / J / codes and / K / codes is the second code block, and a code block including consecutive / T / codes and / R / codes is the third code block.

[0126] Exemplarily, the second code block includes 1100010001, where 11000 represents / J / code, 10001 represents / K / code, and the second code block is used to represent SSD. The third code block includes 0110100111, where 01101 represents / T / code, 00111 represents / R / code, and the third code block is used to represent ESD. The content included in the first code block can be shown in Table 1 below, where the first code block includes a first sub-block and a second sub-block, the first sub-block includes 5 bits encoded in the first part, and the second sub-block includes 4 bits not encoded in the second part and the first part. The value of the position represented by O can be 1, and the value of the position represented by x can be 0 or 1.

[0127] Table 1

[0128]

[0129] In some embodiments, if the last 5 bits of the R code are other parts of Oxxxx except Ox1xx, the first code block is a control type code block and indicates reset extension (reset extend). If the last 5 bits of the H code are O ERR 1CRSCOL, the first code block is a control type code block and indicates a physical layer channel state indication. In this case, the first code block can be called an H.sig code. If the last 5 bits of the S code are O1110, the first code block is a control type code block and indicates PHY-level collision avoidance (PLCA) BEACON (a signal type). If the last 5 bits of the S code are O1101, the first code block is a control type code block and indicates PLCA COMMIT (a signal type). If the last 5 bits of the S code are other parts of Oxxxx except O1110 and O1101, the first code block is a control type code block and indicates set extension (set extend). In other cases where the first code block is other than the case shown in Table 1, the first code block is a control type code block and indicates reserved. Exemplarily, the reserved first code block is used to expand a new Ethernet function, which is not limited in the embodiment of the present application.

[0130] S802, sending multiple code blocks through a serial channel.

[0131] In one possible implementation, a serial channel is used to connect the MAC layer and the PHY. For example, the serial channel is used to connect the reconciliation sublayer (RS) and the physical coding sublayer (PCS). For another example, the serial channel is used to connect the RS and the physical layer signaling sublayer (PLS). Exemplarily, the serial channel is used to implement data transmission between the MAC sublayer and the PHY, or to implement data transmission between the STA and the PHY. The serial channel may also be referred to as a serial channel implemented based on the MII. Exemplarily, the serial channel is implemented by a pin or a group of pins. Thus, if the serial channel is implemented by a pin, the pin is used to send multiple code blocks. If the serial channel is implemented by multiple pins, the differential signal transmitted through multiple pins can be obtained based on multiple code blocks, and then the differential signal can be transmitted through multiple pins to implement sending multiple code blocks through one serial channel. Thus, by using one serial channel to send multiple code blocks, only fewer pins need to be set to implement the serial channel, and then the transmission of data signals, control signals and management signals based on the serial channel can be implemented.

[0132] Fig.23 1 is a schematic diagram of a process of transmitting multiple code blocks provided by an embodiment of the present application. The method can be applied to a MAC function module or a PHY function module. If the method is applied to a MAC function module, the method can transmit multiple code blocks to a PHY function module via a serial channel. The transmission process can correspond to Fig.23 If the method is applied to the PHY function module, the method can transmit multiple code blocks to the MAC function module through the serial channel. The transmission process can correspond to Fig.23 shows the RX serial transfer.

[0133] In an embodiment of the present application, when transmitting multiple code blocks through a serial channel, the obtained multiple code blocks can be directly transmitted, or the multiple code blocks can be processed first and then the processed multiple code blocks can be transmitted. The processing of the multiple code blocks includes at least one of encoding or scrambling, and the encoding includes non-return-to-zero-invert (NRZI) encoding or non-return-to-zero (NRZ) encoding.

[0134] Fig.24 Schematic diagram of a process of transmitting a first code block provided by an embodiment of the present application. Fig.24As shown, the signal to be transmitted includes a management signal, a first data signal and a first control signal transmitted in parallel by MII, and the signal to be transmitted is encoded to obtain a first code block. Among them, the first part of the first code block is obtained by encoding at least one of the four first bits of the first data signal or the four first bits of the first control signal, the first part also includes the four second bits of the first data signal or the four second bits of the first control signal, the second part includes one bit of the management signal, and the first code block includes 10 bits. After obtaining the first code block, the first code block is transmitted serially through MII. And, as Fig.24 As shown, when transmitting the first code block, multiple bits of the first code block can be transmitted in a descending order of bit positions. In some embodiments, multiple bits of the first code block can also be transmitted in a descending order of bit positions.

[0135] Fig.25 FIG. 1 is another schematic diagram of a process for transmitting a first code block provided by an embodiment of the present application. Fig.25 As shown, the bit positions corresponding to the first part of the plurality of first code blocks are used as data and control channels, and the bit positions corresponding to the second part of the plurality of first code blocks are used as management channels. Fig.25 As shown, the bits of the management signal included in the plurality of second parts can be used to compose an MDIO signal. Fig.26 Schematic diagram of a process of transmitting a management code block provided by an embodiment of the present application. Fig.26 As shown, when there is no need to transmit a data signal, that is, when the data channel is idle, a management code block is encoded, and the management code block can include multiple bits of the management signal. Fig.26 , each management code block includes four bits of the management signal, and the four bits of the management signal are represented by “0”. In this case, compared with the case where the second part of the first code block includes only one bit of the management signal, the transmission efficiency of the management signal is higher.

[0136] Fig. 27 is a schematic diagram of another code block provided in an embodiment of the present application. For example, when the code block includes a physical layer status indication, the code block may be as follows: Fig. 27 As shown, the code block can be called an H.sig code block, where: Fig. 27 The x shown can be 0 or 1. Fig.28 FIG. 1 is a schematic diagram of a process of transmitting an H.sig code block provided by an embodiment of the present application. Fig.28As shown, in the case where the method is applied to the PHY function module and multiple code blocks are transmitted to the MAC function module, if the MAC function module is in the sending mode, that is, the MAC function module sends the code block to the PHY function module, the PHY function module can transmit the H.sig code block to the MAC function module through the receiving channel of the MAC function module. Among them, the sending channel of the MAC function module can be a channel established by the MAC function module based on MII for transmitting code blocks to the PHY function module, and the receiving channel of the MAC function module can be a channel established by the MAC function module based on MII for receiving code blocks transmitted by the PHY function module.

[0137] If the method is applied to a PHY functional module and multiple code blocks are transmitted to a MAC functional module, if the MAC functional module is in a receiving mode, that is, the MAC functional module receives the code blocks sent by the PHY functional module, the PHY functional module can transmit the H.sig code blocks to the MAC functional module through the receiving channel of the MAC functional module.

[0138] Fig.29 FIG. 1 is another schematic diagram of a process for transmitting an H.sig code block provided in an embodiment of the present application. Fig.29 As shown, the MAC function module receives data through the receiving channel, and the data is obtained based on the Ethernet frame. For example, the data obtained based on the Ethernet frame includes Fig.29 The / data / shown. Fig.29 As shown, the PHY function module also transmits the / J / K / code for indicating SSD and the / T / R / code for indicating ESD to the MAC function module. In the case that there is no abnormality in the data, the MAC function module can obtain the physical layer status indication based on the received Ethernet frame. The MAC function module can also receive the H.sig code block sent by the PHY function module through the receiving channel. The H.sig code block includes a physical layer status indication, and the physical layer status indication included in the H.sig code block can indicate the virtual CRS occupancy.

[0139] When the method is applied to the PHY functional module and the code block is transmitted to the MAC functional module, if the MAC functional module is in the receiving mode and the data sent by the PHY functional module to the MAC functional module is abnormal, the H.sig code block can be used to replace the abnormal data for transmission. Fig.30 FIG. 1 is another schematic diagram of a process for transmitting an H.sig code block provided in an embodiment of the present application. Fig.30 As shown, the MAC function module receives data through the receiving channel, and the data is obtained based on the Ethernet frame. For example, the data obtained based on the Ethernet frame includes Fig.30 The / data / shown. Fig.30As shown, the PHY function module also transmits the / J / K / code used to represent SSD to the MAC function module. The MAC function module also receives the H.sig code block through the receiving channel. The H.sig code block includes a physical layer status indication. The H.sig code block is obtained by replacing abnormal data. Fig.30 As shown, the PHY function module can also transmit an idle code block to the MAC function module, and the idle code block is the first code block indicating idleness. Figures 28 to 30 In the present invention, the process of transmitting the H.sig code block by the PHY functional module is implemented in a half-duplex scenario.

[0140] The above description is made by taking the method of obtaining the first part of the first code block based on 4B / 5Bb encoding as an example. Next, the description is made by taking the method of obtaining the first part of the first code block based on 64B / 65B encoding as an example.

[0141] Fig.31 is a schematic diagram of another first code block provided in an embodiment of the present application. Fig.31 Since the bit width of the TXD of the MII is 4 bits, it is necessary to obtain the first part of the first code block based on the bit encoding of the TXD of 16 cycles, and the second part of the first code block includes one bit of the management signal. Fig.32 FIG. 1 is another schematic diagram of a process for transmitting multiple first code blocks provided by an embodiment of the present application. Fig.32 As shown, the management signal can be transmitted by transmitting the second part of the plurality of first code blocks, where the management signal includes the MDIO signal.

[0142] Exemplarily, in the 64B / 65B encoding of the IEEE 802.3 standard, the frame start position of the Ethernet frame is indicated by the / S / code, and the / S / code can only be located at the first byte and the fifth byte in the 64-bit block. In the method provided in the embodiment of the present application, the Ethernet frame is transmitted through the MII. If the first part of the first code block is obtained by 64B / 65B encoding, the frame start position needs to be able to be located at any byte in the 64 bits of the first part, so it is necessary to add a code table that can indicate that the / S / code is located at any byte in the encoding table of the IEEE 802.3 standard. Since the 64B / 65B encoding table of the IEEE 802.3 standard already contains the code tables of S0 and S4, the method provided in the embodiment of the present application can expand the code tables indicating S1, S2, and S3 based on S0, and expand the code tables indicating S5, S6, and S7 based on S4. Fig.33 is a schematic diagram of a newly added code table provided in an embodiment of the present application, such as Fig.33As shown, the type (type) of the S0 code is 0x78, which can be indicated by modifying the value of the second hexadecimal bit, that is, 0x7i, where i is a variable value, and setting the type value to 0x7i1, 0x7i2, 0x7i3, respectively indicating S1, S2, S3. The type of the S4 code is 0x33, which can be indicated by modifying the value of the second hexadecimal bit, that is, 0x3i, where i is a variable value, and setting the type value to 0x3i5, 0x3i6, 0x3i7, respectively indicating S5, S6, S7. Among them, i1 to i7 all represent the value of i. Fig.33 For other parts not described in the specification, please refer to the 64B / 65B encoding table in the IEEE 802.3 standard, which will not be described in detail here.

[0143] Exemplarily, the bit width of the control code / C / in the 64B / 65B encoding of the IEEE 802.3 standard is 7 bits. The method provided in the embodiment of the present application can expand the first code block representing half-byte data, the first code block representing the physical layer channel state indication, etc. on the basis of the control code of the IEEE 802.3 standard. The first code block representing half-byte data can be called a half-byte representation code, and the first code block representing the physical layer channel state indication can be called a physical layer signal indication code. Table 2 is a control code table of 64B / 65B encoding in the IEEE 802.3 standard, and the half-byte representation code can be obtained based on the reserved code expansion in the control code table. As shown in Table 2, the reserved code includes reserved code 0 to reserved code 5. Taking the half-byte representation code obtained based on reserved code 5 as an example, the half-byte representation code can be 0x7h, wherein 0x7 represents the control code type, and the h part is 4 bits, representing the half-byte data. The physical layer signal indication code can be obtained by expanding the error code 0x1E in Table 2. For example, the physical layer signal indication code is 0x1u, where 0x1 indicates the control code type, and the u part is 4 bits, indicating the physical layer channel status indication. The physical layer indication code can also be obtained by expanding the reserved code in Table 2, which will not be repeated here.

[0144] Table 2

[0145] name symbol Control Code Idle / I / 0x00 Low power idle (LPI) / LI / 0x06 Start / S / Encoding by block type field terminate / T / Encoding by block type field Error / E / 0x1E Reserved code: 0 - 0x2D Reserved code 1 - 0x33 Reserved code 2 - 0x4B Reserved code 3 - 0x55 Reserved code 4 - 0x66 Reserved code 5 - 0x78

[0146] Fig.34 is a schematic diagram of a physical layer signal indicator code provided in an embodiment of the present application. Fig.34 , the value of x can be 0 or 1. For example, see Fig.34 , when the bit position is 0 for valid and 1 for invalid, if both COL and CRS are invalid and x is 1, the physical layer channel indicator code is the same as the original error code.

[0147] In a possible implementation, the management signal includes a first MDIO signal corresponding to a read operation, and the method further includes: receiving a second MDIO signal, the second MDIO signal being used to provide feedback on the read operation. Exemplarily, the serial channel for receiving the second MDIO signal is different from the serial channel for sending multiple code blocks. That is, the first MDIO signal corresponding to the read operation and the second MDIO signal corresponding to the read feedback operation are transmitted through two serial channels. Exemplarily, the serial channel for transmitting the second MDIO signal is also used to connect the MAC layer and the PHY, and the serial channel can be implemented by one pin or by a group of pins. The second MDIO signal can also be encoded into a code block, and then the second MDIO signal is transmitted by transmitting the code block. For example, the method is applied to a MAC function module, and the MAC function module receives a code block transmitted by a PHY function module, and the code block includes a second MDIO signal. For another example, the method is applied to a PHY function module, and the PHY function module receives a code block transmitted by a MAC function module, and the code block includes a second MDIO signal. The method for encoding a code block including a second MDIO signal is the same as the method for encoding a code block including a first MDIO signal, and will not be repeated here.

[0148] The above text describes the information processing method provided by the embodiment of the present application from the perspective of encoding. Next, the method is described from the perspective of decoding. The method can be as follows: Fig.35 This method can be applied to Figure 7 The MAC functional module or the PHY functional module shown in the figure can be located in the same chip or in different chips. Fig.35 As shown, the method includes but is not limited to S3501 and S3502.

[0149] S3501, receiving a plurality of code blocks through a serial channel, the plurality of code blocks including a first data signal and / or a first control signal, and the plurality of code blocks also including a management signal.

[0150] In one possible implementation, a serial channel is used to connect the MAC layer and the PHY, and the serial channel can be referred to as a channel implemented based on the MII. Exemplarily, the serial channel is implemented by one pin or by a group of pins. Thus, if the serial channel is implemented by one pin, the pin is used to receive multiple code blocks. If the serial channel is implemented by multiple pins, differential signals obtained based on multiple code blocks can be received through multiple pins, and multiple code blocks can be obtained based on the differential signals. Thus, by using one serial channel to receive multiple code blocks, the serial channel can be implemented by setting fewer pins, and then the transmission of data signals, control signals and management signals can be implemented based on the serial channel. For the content related to the encoding of multiple code blocks, please refer to the content in the encoding method, which will not be repeated here.

[0151] S3502, obtain a management signal, a first data signal and / or a first control signal from multiple code blocks.

[0152] For example, see above Fig.24 , after receiving multiple first code blocks through MII, the multiple first code blocks are decoded to obtain signals to be transmitted, that is, management signals, and first data signals and / or first control signals. Wherein, each first code block includes 10 bits. Exemplarily, if the first code block among the multiple code blocks includes a first part and a second part, the first part includes a first data signal and / or a first control signal, and the second part includes a management signal; obtaining the management signal, and the first data signal and / or the first control signal from the multiple code blocks includes: obtaining the first data signal and / or the first control signal from the first part of the first code block; obtaining the management signal from the second part of the first code block. For example, in the case where the first part includes at least one code block obtained by encoding the first data bit group of the first data signal and / or the first control bit group of the first control signal, at least one first code block is decoded according to the encoding method of at least one code block to obtain the first data bit group of the first data signal and / or the first control bit group of the first control signal. If the first part also includes the second data bit group of the first data signal and / or the second control bit group of the first control signal, the second data bit group and / or the second control bit group of the first data signal are obtained from the first part. Bits of the management signal are obtained from the second portion of the first code block.

[0153] Exemplarily, if there are multiple first code blocks, the second part appears periodically in the multiple first code blocks; obtaining the management signal from the second part of the first code block includes: obtaining the second part that appears periodically from the multiple first code blocks; obtaining the management signal from the second part. Exemplarily, the multiple code blocks include a management code block, and the management code block includes a management signal; obtaining the management signal from the multiple code blocks includes: obtaining the management signal from the management code block. For example, the management signal is obtained from the management code block in a manner based on the management signal. Fig.16 Taking the management code block shown as an example, the bits of the management signal are obtained from the position indicated by "O" in the management code block.

[0154] In a possible implementation, the method is applied to a MAC functional module, and the plurality of code blocks further include a physical layer channel state indication. Thus, the method further includes: obtaining the physical layer channel state indication from the plurality of code blocks. For example, in a manner of obtaining a code block including the physical layer channel state indication based on the physical layer channel state indication, obtaining the physical layer channel state indication from the code block. Fig.17 Taking the code block shown as an example, the physical layer channel state indication is obtained from the positions indicated by "COL" and "CRS".

[0155] In one possible implementation, the management signal includes a first MDIO signal corresponding to the read operation; the method further includes: sending a second MDIO signal, the second MDIO signal being used to provide feedback on the read operation. Exemplarily, the serial channel for sending the second MDIO signal is different from the serial channel for receiving the plurality of code blocks. The manner of sending the second MDIO signal is the same as the manner of sending the first MDIO signal in principle, and the relevant contents of the first MDIO signal in S801 and S802 may be referred to, which will not be repeated here.

[0156] Exemplarily, if the multiple code blocks further include a second code block, a second control signal is obtained based on the second code block, and the second control signal is used to obtain the Ethernet frame start of the Ethernet frame. Exemplarily, if the multiple code blocks further include a third code block, a third control signal is obtained based on the third code block, and the third control signal is used to obtain the Ethernet frame end of the Ethernet frame.

[0157] In some embodiments, if the method is applied to a PHY functional module, obtaining a management signal, a first data signal and / or a first control signal from a plurality of code blocks includes: inputting a plurality of code blocks into a coordination sublayer (RS), and executing in the RS to obtain a management signal, a first data signal and / or a first control signal from a plurality of code blocks. By executing in the RS to obtain a management signal, a first data signal and / or a first control signal from a plurality of code blocks, the method can directly convert the management signal, the first data signal and / or the first control signal into a signal that can be processed in the PLS in the RS, without first converting the management signal, the first data signal and / or the first control signal into a parallel signal for MII transmission in the IEEE 802.3 standard, and then converting the parallel signal into a signal processed by the PLS, and the efficiency of obtaining the signal processed by the PLS is higher.

[0158] Fig.36 FIG. 1 is a schematic diagram of a process of inputting multiple code blocks into RS provided by an embodiment of the present application. Fig.36 As shown, multiple code blocks received through the serial channel enter the RS, and the RS performs acquisition of management signals, first data signals and / or first control signals from the multiple code blocks. The RS also converts the management signals, the first data signals and / or the first control signals into signals processed by PLS, for example, the signals processed by PLS include Fig.36 The PLS service primitives shown in FIG. 1 are shown in FIG. 1 . The multiple code blocks include control type code blocks and data type code blocks. The type of the code block is determined according to the content of the code block obtained by encoding. The control type code block can be called a control code block. Fig.36 The code block represented by C shown in the figure may be a control code block; the code block of the data type may be called a data code block, Fig.36 The code block represented by D shown may be a data code block.

[0159] like Fig.36 As shown, the RS can separate the control code block and the data code block, and perform operations on the separated data code block and the control code block. The operations performed are as follows: Fig.36 As shown in C1 and C2 in FIG. 1 , the present embodiment does not limit the type of operation. The PLS service primitives include but are not limited to Fig.36 PLS control request, PLS data request, PLS signal indication, PLS carrier indication, PLS data indication and PLS control indication are shown.

[0160] In a possible implementation, after receiving multiple code blocks, it is necessary to identify the boundaries of the multiple code blocks to achieve synchronization of the multiple code blocks. The synchronization of the multiple code blocks includes but is not limited to synchronization of management channels and synchronization of data channels. The interaction of management signals can be ensured by synchronizing the management channels, and the interaction of data signals and control signals can be ensured by synchronizing the data channels.

[0161] Fig.37 This is a schematic diagram of a synchronization process of a management channel provided in an embodiment of the present application, see Fig.37 , when the first part of the first code block is obtained based on the first control bit group and the second control bit group of the first control signal, the first part of the first code block includes the / I / code and the second control bit group, the / I / code is also the idle code, and the / I / code can be uniquely identified. In the case where the management signal does not include the MDIO signal, the value of the bit of the management signal is 1. In the case where the management signal includes the MDIO signal and the MDIO signal starts to be transmitted, multiple bits of the management signal will have a "101" jump, which can indicate the start field. Therefore, synchronization of the management channel can be achieved by identifying the start field. Fig.37 For other information about the management signals shown, please refer to the previous Fig. 9 and Fig.10 The relevant description will not be repeated here. Fig.37 A0 to a4 shown are only used to illustrate the value of the physical layer address field, and r0 to r4 are only used to illustrate the value of the register address field, and are not used to limit the values ​​of these two fields.

[0162] In a possible implementation, data channel synchronization is achieved by identifying the SSD of the Ethernet frame. That is, by identifying consecutive / J / codes and / K / codes, it can be determined that the Ethernet frame starts to be transmitted, thereby achieving data channel synchronization. Fig.38 Schematic diagram of a data channel synchronization process provided by an embodiment of the present application. Fig.38 As shown, a first code block is first identified, and the first code block is a control type code block and indicates idle, for example Fig.38 The first code block shown is 11111x1111, Fig.38 The x shown may represent 0 or 1. Then the second code block is identified, and the second code block includes a / J / code and a / K / code, so that after the second code block is identified, it can be determined that the Ethernet frame starts to be transmitted, and the synchronization of the data channel is achieved. In a possible implementation, when the synchronization of the data channel is achieved, since the position of the bits of the management channel in the first code block is fixed, when the synchronization of the data channel is achieved, the position of the bits of the management channel can be directly located, so that the synchronization of the management channel can be achieved by identifying the start field of the management signal.

[0163] In the signal processing method provided in the embodiment of the present application, since the multiple code blocks include the management signal, the first data signal and / or the first control signal, the multiple code blocks can include the content of more types of signals. In the case of transmitting the multiple code blocks through a serial channel, only a few pins need to be set to implement the serial channel, and then the transmission of the data signal, the control signal and the management signal is implemented based on the serial channel.

[0164] The embodiment of the present application also provides a signal processing device. Fig.39 1 is a schematic diagram of a signal processing device provided in an embodiment of the present application. The device is applied to a MAC function module or a PHY function module, based on Fig.39 The multiple modules shown in the figure can perform Figure 7 It should be understood that the device may include more additional modules than the modules shown or omit some of the modules shown therein, and the embodiments of the present application are not limited to this. Fig.39 As shown, the device includes a coding module 3901 and a sending module 3902.

[0165] The encoding module 3901 is used to encode the transmission signal to obtain multiple code blocks, which include a first data signal and / or a first control signal, and the multiple code blocks also include a management signal; the sending module 3902 is used to send multiple code blocks through a serial channel.

[0166] In some embodiments, a first code block among the plurality of code blocks includes a first portion and a second portion, the first portion includes a first data signal and / or a first control signal, and the second portion includes a management signal.

[0167] In some embodiments, there are multiple first code blocks, and the management signal appears periodically in the multiple first code blocks.

[0168] In some embodiments, the plurality of code blocks include a management code block, and the management code block includes a management signal.

[0169] In some embodiments, a serial channel is used to connect the MAC layer and the PHY.

[0170] In some embodiments, the serial channel is implemented by one pin or by a group of pins.

[0171] In some embodiments, the signal to be transmitted is associated with an Ethernet frame.

[0172] In some embodiments, the management signal includes a first MDIO signal corresponding to the read operation; the device further includes: a receiving module, configured to receive a second MDIO signal, wherein the second MDIO signal is used to provide feedback on the read operation.

[0173] In some embodiments, the serial channel for receiving the second MDIO signal is different from the serial channel for sending the plurality of code blocks.

[0174] In some embodiments, if the apparatus is applied to a PHY function module, the plurality of code blocks further include a physical layer channel state indication.

[0175] In the device provided in the embodiment of the present application, since the multiple code blocks include management signals, first data signals and / or first control signals, the multiple code blocks can include the contents of more types of signals. When the multiple code blocks are transmitted through a serial channel, only a few pins need to be set to implement the serial channel, and then the transmission of data signals, control signals and management signals is implemented based on the serial channel.

[0176] The embodiment of the present application also provides another signal processing device. Fig.40 1 is a schematic diagram of the structure of another signal processing device provided in an embodiment of the present application. The device is applied to a MAC function module or a PHY function module, based on Fig.40 The multiple modules shown in the figure can perform Fig.35 It should be understood that the device may include more additional modules than the modules shown or omit some of the modules shown, and the embodiments of the present application are not limited to this. Fig.40 As shown, the device includes a receiving module 4001 and an acquiring module 4002.

[0177] The receiving module 4001 is used to receive multiple code blocks through a serial channel, where the multiple code blocks include a first data signal and / or a first control signal, and the multiple code blocks also include a management signal; the acquiring module 4002 is used to acquire the management signal, as well as the first data signal and / or the first control signal from the multiple code blocks.

[0178] In some embodiments, the first code block among multiple code blocks includes a first part and a second part, the first part includes a first data signal and / or a first control signal, and the second part includes a management signal; the acquisition module 4002 is used to acquire the first data signal and / or the first control signal from the first part of the first code block; and acquire the management signal from the second part of the first code block.

[0179] In some embodiments, there are multiple first code blocks, and the second part appears periodically in the multiple first code blocks; the acquisition module 4002 is used to acquire the periodically appearing second part from the multiple first code blocks; and acquire the management signal from the second part.

[0180] In some embodiments, the plurality of code blocks include a management code block, and the management code block includes a management signal; the acquisition module 4002 is used to acquire the management signal from the management code block.

[0181] In some embodiments, a serial channel is used to connect the MAC layer and the PHY.

[0182] In some embodiments, the serial channel is implemented by one pin or by a group of pins.

[0183] In some embodiments, the management signal includes a first MDIO signal corresponding to the read operation; the device further includes: a sending module, configured to send a second MDIO signal, wherein the second MDIO signal is used to provide feedback on the read operation.

[0184] In some embodiments, the serial channel for sending the second MDIO signal is different from the serial channel for receiving the plurality of code blocks.

[0185] In some embodiments, if the method is applied to a MAC function module, the multiple code blocks also include a physical layer channel status indication; the acquisition module 4002 is further used to acquire the physical layer channel status indication from the multiple code blocks.

[0186] In the device provided in the embodiment of the present application, since the multiple code blocks include management signals, first data signals and / or first control signals, the multiple code blocks can include the contents of more types of signals. When the multiple code blocks are transmitted through a serial channel, only a few pins need to be set to implement the serial channel, and then the transmission of data signals, control signals and management signals is implemented based on the serial channel.

[0187] It should be understood that the above Fig.39 and Fig.40 When the device provided realizes its functions, only the division of the above-mentioned functional modules is used as an example for illustration. In practical applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. In addition, the device and method embodiments provided in the above embodiments belong to the same concept, and their specific implementation process is detailed in the method embodiment, which will not be repeated here.

[0188] See also Fig.41 , Fig.41 The following is a schematic diagram of the structure of a computer system provided in an embodiment of the present application. Fig.41 As shown, the computer system is a computer system 2000. The computer system 2000 may be a network device, a routing device or a switching device. Fig.41 The computer system 2000 shown is used to execute the above Figure 8 or Fig.35 The operations in the signal processing method shown. The computer system 2000 is, for example, a server, etc. The computer system 2000 can be implemented by a general bus architecture.

[0189] like Fig.41 As shown, the computer system 2000 includes at least one processor 2001 , a memory 2003 , and at least one communication interface 2004 .

[0190] Processor 2001 is a central processing unit (CPU), a digital signal processor (DSP), a network processor (NP), a graphics processing unit (GPU), a neural-network processing unit (NPU), a data processing unit (DPU), a microprocessor or one or more integrated circuits for implementing the method provided in the embodiment of the present application. For example, processor 2001 includes an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. PLD is, for example, a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination of the above three. Processor 2001 can be a combination of various logic boxes, modules and circuits described in conjunction with the disclosure of the embodiment of the present application, or a combination of computing functions, such as a combination of one or more microprocessors, a combination of DSP and microprocessors, and the like.

[0191] Optionally, the computer system 2000 further includes a bus. The bus is used to transmit information between the components of the computer system 2000. The bus may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Fig.41 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0192] The memory 2003 is, for example, a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, or a random access memory (RAM) or other types of dynamic storage devices that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory 2003 is, for example, independent and connected to the processor 2001 via a bus. The memory 2003 can also be integrated with the processor 2001.

[0193] The communication interface 2004 uses any transceiver-like device to communicate with other devices or communication networks, and the communication network can be Ethernet, radio access network (RAN) or wireless local area network (WLAN), etc. The communication interface 2004 can include a wired communication interface and can also include a wireless communication interface. Specifically, the communication interface 2004 can be an Ethernet interface, a fast Ethernet (FE) interface, a gigabit Ethernet (GE) interface, an asynchronous transfer mode (ATM) interface, a WLAN interface, a cellular network communication interface or a combination thereof. The Ethernet interface can be an optical interface, an electrical interface or a combination thereof. In an embodiment of the present application, the communication interface 2004 can be used for the computer system 2000 to communicate with other devices.

[0194] In a specific implementation, as an embodiment, the processor 2001 may include one or more CPUs, such as Fig.41 0 and CPU1 shown in FIG. Each of these processors may be a single-CPU processor or a multi-CPU processor. A processor herein may refer to one or more devices, circuits, and / or processing cores for processing data (e.g., computer program instructions).

[0195] In a specific implementation, as an embodiment, the computer system 2000 may include multiple processors, such as Fig.41 2001 and processor 2005 are shown in FIG. Each of these processors may be a single-core processor (single-CPU) or a multi-core processor (multi-CPU). A processor herein may refer to one or more devices, circuits, and / or processing cores for processing data (such as computer program instructions).

[0196] In a specific implementation, as an embodiment, the computer system 2000 may also include an output device and an input device. The output device communicates with the processor 2001 and can display information in a variety of ways. For example, the output device may be a liquid crystal display (LCD), a light emitting diode (LED) display device, a cathode ray tube (CRT) display device, or a projector. The input device communicates with the processor 2001 and can receive user input in a variety of ways. For example, the input device may be a mouse, a keyboard, a touch screen device, or a sensor device.

[0197] In some embodiments, the memory 2003 is used to store program code 2010, and the processor 2001 can execute the program code 2010 stored in the memory 2003. The program code 2010 may include one or more software modules. Optionally, the processor 2001 itself may also store program code or instructions.

[0198] In a specific embodiment, the computer system 2000 of the embodiment of the present application may include the MAC functional module and / or PHY functional module in the above-mentioned method embodiments, and the MAC functional module and / or PHY functional module may be implemented by the processor 2001 in the computer system 2000.

[0199] The computer system 2000 may also correspond to the above Fig.39 and Fig.40 The device shown, Fig.39 or Fig.40 Each functional module in the illustrated apparatus may be implemented by a circuit in the processor 2000 .

[0200] in, Figure 8 and Fig.35 Each step of the signal processing method shown is completed by the hardware integrated logic circuit in the processor of the computer system 2000. The steps of the method disclosed in the embodiment of the present application can be directly embodied as being executed by the hardware processor.

[0201] Fig.42 is a schematic diagram of the structure of another computer system provided in an embodiment of the present application, the computer system is used to execute the above Figure 8 and Fig.35 The operations in the signal processing method shown. Exemplarily, the computer system is a server, and the server may have relatively large differences due to different configurations or performances. The computer system may include one or more processors 4201, and the one or more processors 4201 are used to implement the MAC function module and / or PHY function module in the method embodiment. Fig.42 As shown, the computer system may further include one or more memories 4202, wherein at least one computer program is stored in the one or more memories 4202, and the at least one computer program is loaded and executed by one or more processors 4201. Exemplarily, the processor 4201 is a CPU. Of course, the computer system may also have components such as a wired or wireless network interface, a keyboard, and an input and output interface for input and output, and the computer system may also include other components for realizing device functions, which will not be described in detail here.

[0202] The present application also provides a communication device, which includes: a transceiver module for executing Figure 8 The receiving and / or sending related operations in the signal processing method shown; the processing module is used to perform Figure 8 The signal processing method shown in the figure has other operations other than the operations related to receiving and / or sending. The embodiment of the present application also provides another communication device, which includes: a transceiver module, which is used to perform Fig.35 The receiving and / or sending related operations in the signal processing method shown; the processing module is used to perform Fig.35 The signal processing method shown includes other operations except the operations related to receiving and / or sending.

[0203] The present application provides a chip, which includes: a MAC layer circuit, the MAC layer circuit is used to execute Figure 8 and / or Fig.35 The present application also provides another chip, which includes: a PHY circuit, the PHY circuit is used to execute Figure 8 and / or Fig.35 The signal processing method shown.

[0204] The embodiment of the present application also provides a communication system, the communication system includes a MAC layer circuit and a PHY circuit; the MAC layer circuit is used to perform Figure 8 The signal processing method shown in the figure is used by the PHY circuit to perform Fig.35 The signal processing method shown; or, the PHY circuit is used to perform Figure 8The signal processing method shown in the figure, the MAC layer circuit is used to perform Fig.35 The signal processing method shown.

[0205] It should be understood that the processor may be a CPU, or other general-purpose processors, DSPs, ASICs, FPGAs or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc. It is worth noting that the processor may be a processor supporting an advanced RISC machines (ARM) architecture.

[0206] Further, in an optional embodiment, if one or more of the above-mentioned computer system, communication device, chip or communication system also includes a memory, the memory may include a read-only memory and a random access memory, and provide instructions and data to the processor. The memory may also include a non-volatile random access memory. For example, the memory may also store information about the device type.

[0207] The memory may be a volatile memory or a nonvolatile memory, or may include both volatile and nonvolatile memory. Among them, the nonvolatile memory may be a ROM, a programmable read-only memory (programmable ROM, PROM), an erasable programmable read-only memory (erasable PROM, EPROM), an electrically erasable programmable read-only memory (electrically EPROM, EEPROM) or a flash memory. The volatile memory may be a RAM, which is used as an external cache. By way of example but not limitation, many forms of RAM are available. For example, static random access memory (static RAM, SRAM), dynamic random access memory (dynamic random access memory, DRAM), synchronous dynamic random access memory (synchronous DRAM, SDRAM), double data rate synchronous dynamic random access memory (double data rate SDRAM, DDR SDRAM), enhanced synchronous dynamic random access memory (enhanced SDRAM, ESDRAM), synchronous connection dynamic random access memory (synchlink DRAM, SLDRAM) and direct memory bus random access memory (direct rambus RAM, DR RAM).

[0208] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program or a computer program product. A computer program or a computer program product includes one or more computer instructions. When loading and executing a computer program instruction on a computer, a process or function according to the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. Computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, a computer instruction can be transmitted from a website site, a computer, a server or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. A computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server, a data center, etc. that contains one or more available media integrated. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a digital video disc (DVD)), or a semiconductor medium (eg, a solid state disk (SSD)).

[0209] In order to clearly illustrate the interchangeability of hardware and software, the steps and components of each embodiment have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. A person of ordinary skill in the art may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0210] The computer program code for realizing the method for the embodiment of the present application can be written in one or more programming languages. These computer program codes can be provided to the processor of the storage device of general-purpose computer, special-purpose computer or other programmable annotation content, so that the program code, when being executed by the storage device of computer or other programmable annotation content, causes the function / operation specified in the flow chart and / or block diagram to be implemented. The program code can be executed completely on the computer, partially on the computer, as an independent software package, partially on the computer and partially on the remote computer or completely on the remote computer or server.

[0211] In the context of the embodiments of the present application, computer program codes or related data may be carried by any appropriate carrier to enable a device, apparatus or processor to perform the various processes and operations described above. Examples of carriers include signals, computer readable media, etc. Examples of signals may include electrical, optical, radio, acoustic or other forms of propagation signals, such as carrier waves, infrared signals, etc.

[0212] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and modules described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0213] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the module is only a logical function division. There may be other division methods in actual implementation, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or modules, or it can be an electrical, mechanical or other form of connection.

[0214] The modules described as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical modules, that is, they may be located in one place or distributed on multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the embodiments of the present application.

[0215] In addition, each functional module in each embodiment of the present application can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The above integrated modules can be implemented in the form of hardware or software functional modules.

[0216] In this application, the terms "first", "second", etc. are used to distinguish between identical or similar items with substantially the same effects and functions. It should be understood that there is no logical or temporal dependency between "first", "second", and "nth", nor is the quantity and execution order limited. It should also be understood that although the following description uses the terms first, second, etc. to describe various elements, these elements should not be limited by the terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of various examples, the first figure can be referred to as the second figure, and similarly, the second figure can be referred to as the first figure.

[0217] It should also be understood that in the various embodiments of the present application, the size of the serial number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0218] The term "at least one" in this application means one or more, and the term "multiple" in this application means two or more, for example, multiple range locks means two or more range locks. The terms "system" and "network" are often used interchangeably herein.

[0219] It should be understood that the terms used in the description of various examples herein are only for describing specific examples and are not intended to be limiting. As used in the description of various examples and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0220] It should also be understood that the term “comprise” (also known as “includes,” “including,” “comprises” and / or “comprising”) when used in this specification specifies the presence of stated features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0221] It should also be understood that, depending on the context, the phrase “if it is determined that…” or “if [stated condition or event] is detected” may be interpreted to mean “upon determining that…” or “in response to determining that…” or “upon detecting [stated condition or event]” or “in response to detecting [stated condition or event]”.

[0222] It should be understood that determining B based on A does not mean determining B only based on A. B can also be determined based on A and / or other information.

[0223] It should also be understood that the references to "one embodiment", "an embodiment", or "a possible implementation" throughout the specification mean that specific features, structures, or characteristics related to the embodiment or implementation are included in at least one embodiment of the present application. Therefore, the references to "in one embodiment" or "in an embodiment", or "a possible implementation" throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0224] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the principles of the present application should be included in the protection scope of the present application.

Claims

1. A signal processing method, characterized in that: The method comprises: Encoding the signal to be transmitted to obtain a plurality of code blocks, wherein the plurality of code blocks include a first data signal and / or a first control signal, and the plurality of code blocks also include a management signal; The plurality of code blocks are transmitted through a serial channel.

2. The method according to claim 1, characterized in that A first code block among the plurality of code blocks includes a first part and a second part, the first part includes the first data signal and / or the first control signal, and the second part includes the management signal.

3. The method according to claim 2, characterized in that There are multiple first code blocks, and the management signal appears periodically in the multiple first code blocks.

4. The method according to any one of claims 1 to 3, characterized in that: The plurality of code blocks include a management code block, and the management code block includes the management signal.

5. The method according to any one of claims 1 to 4, characterized in that: The serial channel is used to connect the media access control MAC layer and the physical layer PHY.

6. The method according to any one of claims 1 to 5, characterized in that: The serial channel is implemented by one pin or by a group of pins.

7. The method according to any one of claims 1 to 6, characterized in that: The signal to be transmitted is related to an Ethernet frame.

8. The method according to any one of claims 1 to 7, characterized in that: The management signal includes a first management data input and output MDIO signal corresponding to the read operation; the method further includes: A second MDIO signal is received, where the second MDIO signal is used to provide feedback on the read operation.

9. The method according to claim 8, characterized in that A serial channel for receiving the second MDIO signal is different from a serial channel for sending the plurality of code blocks.

10. The method according to any one of claims 1 to 9, characterized in that: The method is applied to a physical layer PHY function module, and the multiple code blocks also include a physical layer channel status indication.

11. A signal processing method, characterized in that: The method comprises: receiving a plurality of code blocks through a serial channel, the plurality of code blocks including a first data signal and / or a first control signal, the plurality of code blocks also including a management signal; The management signal, and the first data signal and / or the first control signal are obtained from the multiple code blocks.

12. The method according to claim 11, characterized in that A first code block among the plurality of code blocks comprises a first part and a second part, the first part comprises the first data signal and / or the first control signal, and the second part comprises the management signal; The acquiring the management signal, the first data signal and / or the first control signal from the multiple code blocks includes: Acquire the first data signal and / or the first control signal from a first part of the first code block; The management signal is obtained from a second portion of the first code block.

13. The method according to claim 12, characterized in that There are multiple first code blocks, and the second part appears periodically in the multiple first code blocks; and obtaining the management signal from the second part of the first code block includes: Acquire a periodically occurring second portion from the plurality of first code blocks; The management signal is obtained from the second portion.

14. The method according to any one of claims 11 to 13, characterized in that: The multiple code blocks include a management code block, and the management code block includes the management signal; and obtaining the management signal from the multiple code blocks includes: The management signal is obtained from the management code block.

15. The method according to any one of claims 11 to 14, characterized in that: The serial channel is used to connect the media access control MAC layer and the physical layer PHY.

16. The method according to any one of claims 11 to 15, characterized in that: The serial channel is implemented by one pin or by a group of pins.

17. The method according to any one of claims 11 to 16, characterized in that: The management signal includes a first management data input and output MDIO signal corresponding to the read operation; the method further includes: A second MDIO signal is sent, where the second MDIO signal is used to provide feedback on the read operation.

18. The method according to claim 17, characterized in that A serial channel for sending the second MDIO signal is different from a serial channel for receiving the plurality of code blocks.

19. The method according to any one of claims 11 to 18, characterized in that: The method is applied to a media access control (MAC) function module, wherein the multiple code blocks further include a physical layer channel state indication; the method further includes: The physical layer channel state indication is obtained from the multiple code blocks.

20. A signal processing device, characterized in that: The signal processing device comprises: A transceiver module, used to perform operations related to receiving and / or sending in any of the methods described in claims 1-10; A processing module, used to perform other operations in the method described in any one of claims 1-10 except the operations related to receiving and / or sending.

21. A signal processing device, characterized in that: The signal processing device comprises: A transceiver module, used to perform the operations related to receiving and / or sending in any of the methods described in claims 11-19; A processing module, used to perform other operations in the method described in any one of claims 11-19 except for operations related to receiving and / or sending.

22. A chip, characterized in that: The chip comprises: a media access control MAC layer circuit, and the MAC layer circuit is used to execute the signal processing method as described in any one of claims 1-9 and 11-19.

23. A chip, characterized in that: The chip comprises: a physical layer PHY circuit, and the PHY circuit is used to execute the signal processing method as described in any one of claims 1-10 and 11-18.

24. A signal processing system, characterized in that: The signal processing system comprises a media access control MAC layer circuit and a physical layer PHY circuit; the MAC layer circuit is used to execute the signal processing method according to any one of claims 1 to 9, and the PHY circuit is used to execute the signal processing method according to any one of claims 11 to 19; Alternatively, the PHY circuit is used to execute the signal processing method as described in any one of claims 1-10, and the MAC layer circuit is used to execute the signal processing method as described in any one of claims 11-18.

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