Semiconductor device and method of manufacturing the same

Abstract

Embodiments relate to a semiconductor device and a method of manufacturing the same. The semiconductor device includes: a first electrode; a second electrode; a first semiconductor layer containing a first impurity that serves as a donor and protons, and having a first position within which the concentration of the first impurity is maximum; a second semiconductor layer that is disposed on a first direction side from the first electrode toward the second electrode with respect to the first semiconductor layer, contains the first impurity and protons, and has a higher concentration of the protons than the first impurity; and a third semiconductor layer that is disposed on the first direction side of the second semiconductor layer and contains the first impurity, the concentration of the first impurity being higher than the concentration of the protons. In at least a portion of the first semiconductor layer on the second semiconductor layer side, the concentration of the first impurity is higher than the concentration of the protons. A second position at which the concentration of the protons in the first direction is maximized is located on the opposite side of the first direction from the first position.

Description

[0001] Related Application

[0002] This application claims the priority of Japanese Patent Application No. 2023-144803 (filing date: September 6, 2023) as a basic application. The present application incorporates the entire contents of the basic application by reference. Technical Field

[0003] Embodiments relate to a semiconductor device and a method for manufacturing the same. Background Art

[0004] Semiconductor devices for power control are required to have a certain short-circuit tolerance so that the semiconductor device does not break down during the period from when a load is short-circuited to when a protection circuit operates. Summary of the invention

[0005] The semiconductor device of the embodiment comprises: a first electrode; a second electrode; a first semiconductor layer of n-type conductivity, which contains a first impurity and protons that serve as donors and has a first position inside where the concentration of the first impurity takes a maximum value; a second semiconductor layer of n-type conductivity, which is arranged on the first direction side from the first electrode toward the second electrode relative to the first semiconductor layer, contains the first impurity and protons, and the concentration of the protons is higher than the concentration of the first impurity; and a third semiconductor layer of n-type conductivity, which is arranged on the first direction side of the second semiconductor layer, contains the first impurity, and the concentration of the first impurity is higher than the concentration of the protons. In at least a portion of the first semiconductor layer on the second semiconductor layer side, the concentration of the first impurity is higher than the concentration of the protons. The second position where the concentration of the protons in the first direction takes a maximum value is located on the opposite side of the first direction compared to the first position.

[0006] The manufacturing method of a semiconductor device of an embodiment comprises: a step of injecting a first impurity serving as a donor into a semiconductor component having an n-type conductivity from a first surface side of the semiconductor component along a first direction to form a first position where the concentration of the first impurity takes a maximum value inside the semiconductor component; a step of disposing an absorber on the first surface side of the semiconductor component; a step of injecting protons into the semiconductor component via the absorber along the first direction to make a second position where the concentration of the protons takes a maximum value be located on the opposite side of the first direction compared to the first position; and a step of removing the absorber.

[0007] According to the embodiment, a semiconductor device with high short-circuit tolerance and a method for manufacturing the same can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1(a) is a top view showing the semiconductor device of the first embodiment, Figure 1 (b) is its cross-sectional view.

[0009] Figure 2 This is a graph showing the concentration curve of each impurity along the Z direction in the first embodiment, with the position in the Z direction being represented on the horizontal axis and the concentration of each impurity being represented on the vertical axis.

[0010] Figure 3 It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0011] Figure 4 It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0012] Figure 5 It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0013] Figure 6 It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0014] Figure 7 It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0015] Figure 8 It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0016] Fig. 9 It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0017] Fig.10 This is a graph showing the concentration curve along the Z direction of each impurity in the first modification of the first embodiment, with the position in the Z direction being represented on the horizontal axis and the concentration of each impurity being represented on the vertical axis.

[0018] Fig.11 This is a graph showing the concentration curve along the Z direction of each impurity in the second modification of the first embodiment, with the position in the Z direction being represented on the horizontal axis and the concentration of each impurity being represented on the vertical axis.

[0019] Fig.12 It is a cross-sectional view showing a semiconductor device according to a second embodiment.

[0020] Fig.13 This is a graph showing the concentration curve of each impurity along the Z direction in the second embodiment, with the position in the Z direction being represented on the horizontal axis and the concentration of each impurity being represented on the vertical axis.

[0021] Fig.14This is a graph showing a concentration curve along the Z direction of each impurity in a modification of the second embodiment, with the position in the Z direction being represented on the horizontal axis and the concentration of each impurity being represented on the vertical axis.

[0022] Fig.15 The graph shows the influence of the proton curve on the short-circuit withstand capacity by taking the position where the proton concentration in the Z direction is the maximum value on the horizontal axis and taking the result of the short-circuit withstand capacity test on the vertical axis.

[0023] Fig.16 This is a graph showing the concentration curve along the Z direction of each impurity in the test example, with the position in the Z direction being represented on the horizontal axis and the concentration of each impurity being represented on the vertical axis. DETAILED DESCRIPTION

[0024] <First embodiment>

[0025] (Semiconductor Device)

[0026] Figure 1 (a) is a top view showing the semiconductor device of this embodiment. Figure 1 (b) is its cross-sectional view.

[0027] exist Figure 1 In (a), an emitter electrode and an insulating member described later are omitted, and the upper surface of the semiconductor portion is shown.

[0028] The semiconductor device 1 of the present embodiment is, for example, a power semiconductor for power control, such as an IGBT (Insulated Gate Bipolar Transistor).

[0029] like Figure 1 As shown in (a) and (b) of FIG. 1 , a semiconductor portion 10 is provided in a semiconductor device 1. The semiconductor portion 10 is made of a semiconductor material, for example, single crystal silicon (Si). Impurities that become donors or acceptors are introduced into each part of the semiconductor portion 10, and the conductivity type of each part is set to n-type or p-type.

[0030] The semiconductor device 1 is provided with a collector electrode 31, an emitter electrode 32, a gate electrode 33, and a dummy gate electrode 34. The collector electrode 31 and the emitter electrode 32 are each provided with one. The gate electrode 33 and the dummy gate electrode 34 are provided in plurality. The collector electrode 31 is in contact with the lower surface 10a of the semiconductor portion 10, and the emitter electrode 32 is in contact with the upper surface 10b of the semiconductor portion 10. The gate electrode 33 and the dummy gate electrode 34 are arranged in the semiconductor portion 10 and extend in one direction.

[0031] Hereinafter, in this specification, for the convenience of explanation, an XYZ orthogonal coordinate system is used. The direction from the collector electrode 31 toward the emitter electrode 32 is set as the "Z direction" (first direction), the direction in which the gate electrode 33 and the dummy gate electrode 34 extend is set as the "Y direction", and the direction orthogonal to the Z direction and the Y direction is set as the "X direction". In addition, the Z direction is also called "up", and the opposite direction (-Z direction) is also called "down", but this expression is also for convenience and has nothing to do with the direction of gravity.

[0032] In the semiconductor portion 10, there is a p + The collector electrode layer 11 (the fourth semiconductor layer), the thin n-type buffer layer 12 (the first semiconductor layer), the thick n-type buffer layer 13 (the second semiconductor layer), the n - type base layer 14 (third semiconductor layer), n-type barrier layer 15, p-type base layer 16 (fifth semiconductor layer), p + Type diffusion layer 17, n + type emitter layer 18 (sixth semiconductor layer) and p + Type contact layer 19.

[0033] p + The collector electrode layer 11 forms the lower surface 10a of the semiconductor portion 10. + The collector electrode layer 11 is disposed on the collector electrode 31 and is in contact with the collector electrode 31. + type collector electrode layer 11, thin n-type buffer layer 12, thick n-type buffer layer 13, n - The n-type base layer 14, the n-type barrier layer 15, and the p-type base layer 16 are stacked in this order along the Z direction and are connected to each other. In this specification, "connected" means electrically connected.

[0034] n + Type emitter layer 18 and p + The p-type contact layer 19 is disposed on the p-type base layer 16 and extends along the X direction. + Type emitter layer 18 and p + The type contact layers 19 are arranged alternately along the Y direction. + Type emitter layer 18 and p + The type contact layer 19 constitutes the upper surface 10 b of the semiconductor portion 10 .

[0035] p + The p-type diffusion layer 17 is disposed between the p-type base layer 16 and the n-type + between the p-type emitter layer 18 and between the p-type base layer 16 and the p + The dummy gate electrode 34 is located near the type contact layer 19 and extends along the Y direction.

[0036] In n +The emitter layer 18 and the p + An emitter electrode 32 is arranged on the type contact layer 19. + Type emitter layer 18 and p + The type contact layer 19 is connected to the emitter electrode 32 .

[0037] The gate electrode 33 and the dummy gate electrode 34 extend from the upper surface 10b side of the semiconductor portion 10, that is, the emitter electrode 32 side, toward the lower side, that is, the collector electrode 31 side. + The upper surface of the emitter layer 18 and the p + The upper surface of the p-type contact layer 19 passes through the sides of the p-type base layer 16 and the n-type barrier layer 15 and reaches the n-type - The dummy gate electrode 34 is also provided through the p + The gate electrodes 33 and the dummy gate electrodes 34 may be arranged alternately one by one along the X direction, one dummy gate electrode 34 may be arranged for a plurality of gate electrodes 33, or one gate electrode 33 may be arranged for a plurality of dummy gate electrodes 34. In addition, the dummy gate electrode 34 may not be provided.

[0038] The semiconductor device 1 is provided with a gate insulating film 21, a dummy gate insulating film 22, a gate insulating member 23, and a dummy gate insulating member 24. The gate insulating film 21 is disposed between the gate electrode 33 and the semiconductor portion 10 to insulate the gate electrode 33 from the semiconductor portion 10. The dummy gate insulating film 22 is disposed between the dummy gate electrode 34 and the semiconductor portion 10 to insulate the dummy gate electrode 34 from the semiconductor portion 10.

[0039] The gate insulating member 23 and the dummy gate insulating member 24 are arranged on the semiconductor portion 10. The gate insulating member 23 is arranged between the gate electrode 33 and the emitter electrode 32 to insulate the gate electrode 33 from the emitter electrode 32. The dummy gate insulating member 24 is arranged to cover the upper end of the dummy gate insulating film 22 to protect the upper end of the dummy gate insulating film 22. A portion of the emitter electrode 22 is arranged between the dummy gate insulating members 24 and connected to the dummy gate electrode 34. Therefore, an emitter potential is applied to the dummy gate electrode 34.

[0040] (Impurity concentration profile on the collector electrode side of the semiconductor part)

[0041] Next, the collector electrode side portion of the semiconductor portion 10, that is, the p + type collector electrode layer 11, thin n-type buffer layer 12, thick n-type buffer layer 13 and n - The impurity concentration profile of the type base layer 14 along the Z direction will be described.

[0042] The semiconductor portion 10 contains phosphorus (P) and protons (H + ), contains boron (B) as an acceptor impurity. Proton is a cation of hydrogen, which is called proton. In addition, impurities other than protons that become donors are not limited to phosphorus, but may also be other impurities such as arsenic (As) or antimony (Sb). In addition, impurities that become acceptors are not limited to boron, but may also be other impurities such as gallium (Ga) or indium (In).

[0043] Figure 2 This is a graph showing the concentration curve of each impurity along the Z direction in the present embodiment, with the position in the Z direction being represented on the horizontal axis and the concentration of each impurity being represented on the vertical axis.

[0044] also, Figure 2 This is a conceptual diagram that qualitatively shows the characteristics of each concentration curve. The actual measurement results will be described in the examples described later. Figure 2 The vertical axis is logarithmic.

[0045] First, the overview of each layer is described.

[0046] like Figure 1 (b) and Figure 2 As shown, the thickness of the thick n-type buffer layer 13, that is, the length in the Z direction, is thicker than the thickness of the thin n-type buffer layer 12. In addition, the average value of the carrier concentration of the thick n-type buffer layer 13 is lower than the average value of the carrier concentration of the thin n-type buffer layer 12. - The thickness of the n-type base layer 14 is thicker than the thickness of the n-type buffer layer 13. - The average value of the carrier concentration of the thick n-type base layer 14 is lower than the average value of the carrier concentration of the thick n-type buffer layer 13. The thickness of the n-type barrier layer 15 is greater than that of the n-type base layer 14. - The thickness of the n-type base layer 14 is thin. In addition, the average value of the carrier concentration of the n-type barrier layer 15 is smaller than that of the n-type base layer 14. - The average value of the carrier concentration of the type base layer 14 is high.

[0047] Next, the concentration profile of each impurity will be described.

[0048] like Figure 2 As shown, the boron concentration curve starts from the lower surface 10a of the semiconductor portion 10 and increases toward the +Z direction. + The collector electrode layer 11 has a peak value P1. Figure 2 In the range shown, the boron concentration reaches a maximum value at the peak P1. Therefore, the position 41 where the boron concentration reaches a maximum value in the Z direction coincides with the position of the peak P1. + In the type collector electrode layer 11, the concentration of boron is higher than the total value of the concentration of phosphorus and the concentration of protons.

[0049] The phosphorus concentration curve starts from the lower surface 10a of the semiconductor portion 10 and increases toward the +Z direction, and has a peak value P2 in the thin n-type buffer layer 12. The phosphorus concentration takes a maximum value at the peak value P2. + The concentration of impurities decreases monotonically from the peak P2 in the +Z direction or in the -Z direction in the n-type collector electrode layer 11, the thin n-type buffer layer 12, and the thick n-type buffer layer 13. In addition, "monotonically decreases" means that the actual concentration of impurities decreases in one direction, without considering the slight increase or decrease caused by the measurement noise.

[0050] In n - The concentration of phosphorus in the base layer 14 is approximately constant. Figure 2 In the range shown, the position 42 where the phosphorus concentration in the Z direction reaches the maximum value coincides with the position of the peak P2. - In the type base layer 14 , the total value of the phosphorus concentration and the proton concentration is higher than the boron concentration.

[0051] The proton concentration curve starts from the lower surface 10a of the semiconductor portion 10, increases as it goes toward the +Z direction, and has a peak value P3 in the thin n-type buffer layer 12. The proton concentration takes a maximum value at the peak value P3, and decreases monotonically from the peak value P3 in both the +Z direction and the -Z direction. Therefore, the position 43 where the proton concentration takes a maximum value in the Z direction coincides with the position of the peak value P3. In the Z direction, the position 43 where the proton concentration takes a maximum value is located on the -Z direction side, that is, on the lower surface 10a side of the semiconductor portion 10, compared to the position 42 where the phosphorus concentration takes a maximum value.

[0052] Next, the relationship between the impurity concentrations of each layer will be described with attention paid.

[0053] In p + In the collector electrode layer 11, the concentration of boron is higher than the sum of the concentration of phosphorus and the concentration of protons. The peak value P1 of boron is at p + Type collector electrode layer 11.

[0054] In the thin n-type buffer layer 12, the total value of the phosphorus concentration and the proton concentration is higher than the boron concentration. In addition, in at least the portion of the thin n-type buffer layer 12 on the thick n-type buffer layer 13 side, the phosphorus concentration is higher than the proton concentration. The peak P2 of phosphorus and the peak P3 of protons are in the thin n-type buffer layer 12. The peak P3 of protons is located on the -Z direction side compared to the peak P2 of phosphorus. + The interface between the n-type collector electrode layer 11 and the thin n-type buffer layer 12 is a position where the magnitude relationship between the concentration of the impurity that becomes an acceptor and the concentration of the impurity that becomes a donor is reversed. +In the n-type collector electrode layer 11, the concentration of impurities that serve as acceptors is higher than the concentration of impurities that serve as donors, and in the thin n-type buffer layer 12, the concentration of impurities that serve as donors is higher than the concentration of impurities that serve as acceptors.

[0055] In the thick n-type buffer layer 13, the total value of the concentration of phosphorus and the concentration of protons is higher than the concentration of boron, and the concentration of protons is higher than the concentration of phosphorus. The interface between the thin n-type buffer layer 12 and the thick n-type buffer layer 13 is a position where the magnitude relationship between the concentration of phosphorus and the concentration of protons is reversed. In at least the portion of the thin n-type buffer layer 12 on the thick n-type buffer layer 13 side, the concentration of phosphorus is higher than the concentration of protons, and in the thick n-type buffer layer 13, the concentration of protons is higher than the concentration of phosphorus. As described above, the overall carrier concentration of the thick n-type buffer layer 13 is lower than the carrier concentration of the thin n-type buffer layer 12. There is no peak in the impurity concentration in the thick n-type buffer layer 13, and the concentration of each impurity decreases monotonically toward the +Z direction.

[0056] In n - In the type base layer 14, the total value of the concentration of phosphorus and the concentration of protons is higher than the concentration of boron, and the concentration of phosphorus is higher than the concentration of protons. - The overall carrier concentration of the n-type base layer 14 is lower than the carrier concentration of the thick n-type buffer layer 13. - There is no peak of impurity concentration in the type base layer 14, and the carrier concentration is approximately constant in the Z direction. In addition, "carrier concentration" refers to the concentration of effective impurities that contribute to the conductivity of the semiconductor material. When a certain part contains both impurities that become donors and impurities that become acceptors, it refers to the difference concentration excluding the offset amount.

[0057] (Manufacturing method)

[0058] Next, a method for manufacturing the semiconductor device according to the present embodiment will be described.

[0059] Figure 3 to Figure 9 It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the present embodiment.

[0060] First, if Figure 3 As shown in FIG. 1 , a semiconductor wafer 10 w is prepared. The semiconductor wafer 10 w is made of, for example, single crystal silicon and contains impurities that serve as donors, such as phosphorus, uniformly throughout the wafer. The conductivity type of the semiconductor wafer 10 w is n - type.

[0061] Next, if Figure 4 As shown in FIG. 1 , an n-type barrier layer 15 is formed by ion implanting impurities into the upper surface 10b of the semiconductor wafer 10w. The portion of the semiconductor wafer 10w into which the impurities are not ion implanted becomes an n-type barrier layer. - Type base layer 14.

[0062] Next, a gate trench 36 and a dummy gate trench 37 are formed from the upper surface 10b side of the semiconductor wafer 10w. Next, a gate insulating film 21 is formed on the inner surface of the gate trench 36, and a dummy gate insulating film 22 is formed on the inner surface of the dummy gate trench 37 by performing a thermal oxidation process. Next, a conductive material such as polysilicon is deposited on the entire surface to form a gate electrode 33 in the gate trench 36, and a dummy gate electrode 34 is formed in the dummy gate trench 37. Next, the conductive material deposited on the upper surface 10b of the semiconductor wafer 10w is removed.

[0063] Next, if Figure 5 As shown, by sequentially ion-implanting impurities into the upper surface 10b of the semiconductor wafer 10w, a p-type base layer 16, a p-type base layer 17, and a p-type base layer 18 are formed. + Type diffusion layer 17, p + Type contact layer 19 (refer to Figure 1 (a)), n + The type emitter layer 18 is formed. Next, silicon oxide is selectively formed on the upper surface 10b of the semiconductor wafer 10w to form the gate insulating member 23 and the dummy gate insulating member 24. In this way, the upper structure of the IGBT is formed on the upper part of the semiconductor wafer 10w.

[0064] Next, if Figure 6 As shown in FIG. 1 , the semiconductor wafer 10 w is ground from the lower surface side to be thinned.

[0065] Next, if Figure 7 As shown, phosphorus is ion-implanted from the lower surface 10a side of the semiconductor wafer 10w. At this time, the phosphorus concentration curve has a peak value P2 in the semiconductor wafer 10w (refer to Figure 2 ). Thus, a thin n-type buffer layer 12 is formed.

[0066] Next, if Figure 8 As shown, boron is ion-implanted from the lower surface 10a side of the semiconductor wafer 10w. At this time, the boron concentration curve has a peak P1 at a position closer to the -Z direction side than the peak P2 in the semiconductor wafer 10w (see Figure 2 ). Thus, p + Type collector electrode layer 11.

[0067] Next, if Fig. 9As shown, an absorbent 90 is arranged on the lower surface 10a of the semiconductor wafer 10w. The absorbent 90 is formed by, for example, stacking aluminum foils. Then, protons, i.e., positive ions of hydrogen, are injected into the semiconductor wafer 10w along the Z direction through the absorbent 90 by, for example, a cyclotron. Since protons are smaller than phosphorus, they reach a deeper position in the semiconductor wafer 10w. On the other hand, since protons are injected through the absorbent 90, a part of the protons stays in the absorbent 90. As a result, the peak value P3 of the protons (see Figure 2 ) is located on the -Z direction side compared to the peak P2 of phosphorus. Thus, a thick n-type buffer layer 13 is formed. For silicon constituting the thick n-type buffer layer 13, protons are defects and impurities that serve as donors.

[0068] In one example, the proton implantation conditions are set so that the peak P3 of the proton concentration curve is located at the lower surface 10a of the semiconductor wafer 10w. However, the actual position of the peak P3 may be offset from the lower surface 10a in the +Z direction or the -Z direction. Figure 2 The example in which the peak P3 is shifted to the +Z direction side, that is, the inside of the semiconductor wafer 10w, compared with the lower surface 10a is shown. As a result, the peak P3 of the proton is located in the thin n-type buffer layer 12 and is located to the -Z direction side compared with the peak P2 of phosphorus. Then, the getter 90 is removed.

[0069] Next, heat treatment is performed to activate the implanted impurities. The implanted protons are activated by heat treatment to form an n-type defect layer that is a lattice defect and functions as a donor. The n-type defect layer functions as an n-type conductive layer and thus forms a thick n-type buffer layer 13 .

[0070] Next, if Figure 1 As shown in (a) and (b) of FIG. 1 , the collector electrode 31 and the emitter electrode 32 are formed. Next, the semiconductor wafer 10 w is diced and divided into individual pieces. Thus, the semiconductor device 1 is manufactured.

[0071] (Effect)

[0072] Next, the effects of this embodiment will be described.

[0073] In the semiconductor device 1 of the present embodiment, in addition to the thin n-type buffer layer 12, a thick n-type buffer layer 13 is provided. As a result, the extension of the depletion layer when the semiconductor device 1 is turned off can be suppressed. Therefore, by allowing the depletion layer to reach the thin n-type buffer layer 12 and quickly discharging carriers, the LC resonance between the capacitance (C) of the depletion layer inside the device and the parasitic inductance (L) outside the device can be suppressed. As a result, the vibration of the voltage associated with switching can be suppressed.

[0074] In the present embodiment, the position 43 where the proton concentration reaches the maximum value is located on the -Z direction side, that is, on the collector electrode 31 side, relative to the position 42 where the phosphorus concentration reaches the maximum value. This can improve the short-circuit tolerance of the semiconductor device 1 .

[0075] When the semiconductor device 1 is in the on state, if the load connected to the semiconductor device 1 is short-circuited for some reason, a large current flows in the semiconductor device 1. Usually, in such a case, although the external protection circuit will work and cut off the current flowing into the semiconductor device 1, it takes time from the load short circuit to the protection circuit working. It is hoped that the semiconductor device 1 will not be destroyed during this time. Short-circuit tolerance refers to the level at which the semiconductor device 1 will not be destroyed under such a situation.

[0076] In this embodiment, since the position 43 where the proton concentration takes the maximum value is located on the -Z direction side compared to the position 42 where the phosphorus concentration takes the maximum value, the transport efficiency near the lower surface 10a of the semiconductor portion 10 is increased, and more holes are injected. As a result, the electric field near the lower surface 10a is reduced, and the short-circuit tolerance is increased.

[0077] Furthermore, if the position 43 where the proton concentration takes the maximum value is the same as or more than the position 42 where the phosphorus concentration takes the maximum value, in the +Z direction, that is, on the emitter electrode 32 side, the transport efficiency near the lower surface 10a decreases, the hole injection decreases, and the electric field near the lower surface 10a increases. As a result, the short-circuit tolerance decreases.

[0078] <First Modification of First Embodiment>

[0079] Fig.10 The graph shows the concentration curve of each impurity along the Z direction in the present modification example, with the position in the Z direction being represented on the horizontal axis and the concentration of each impurity being represented on the vertical axis.

[0080] like Fig.10 As shown, in this modification, the peak value P3 of the proton is at p + The proton concentration in the Z direction takes a maximum value at position 43 located in the p-type collector electrode layer 11. + The collector electrode layer 11 is formed in the type collector electrode layer 11. Thus, the same effects as those of the above-mentioned embodiment can be obtained. The structure, operation and effects other than those described above in this modification are the same as those of the first embodiment.

[0081] <Second Modification of First Embodiment>

[0082] Fig.11 The graph shows the concentration curve of each impurity along the Z direction in the present modification example, with the position in the Z direction being represented on the horizontal axis and the concentration of each impurity being represented on the vertical axis.

[0083] like Fig.11 As shown, in this modification, there is no peak on the proton concentration curve, and the proton concentration takes a maximum value at the lower surface 10a of the semiconductor portion 10, and decreases monotonically as it moves in the Z direction. Therefore, in the semiconductor portion 10, the position 43 where the proton concentration takes a maximum value coincides with the lower surface 10a of the semiconductor portion 10.

[0084] Such a curve is obtained by Fig. 9 In the process shown, protons are injected into the semiconductor portion 10 via the getter 90 in such a manner that the peak value P3 of the proton concentration is located at the lower surface 10a of the semiconductor portion 10 or in the getter 90, and then the getter 90 is removed. Thus, the same effect as in the above-mentioned embodiment can be obtained. The structure, operation and effect other than the above in this modification are the same as those in the first embodiment.

[0085] <Second embodiment>

[0086] Fig.12 is a cross-sectional view showing a semiconductor device according to this embodiment.

[0087] Fig.13 This is a graph showing the concentration curve of each impurity along the Z direction in the present embodiment, with the position in the Z direction being represented on the horizontal axis and the concentration of each impurity being represented on the vertical axis.

[0088] like Fig.12 As shown, the semiconductor device 2 of this embodiment is a pn diode. The semiconductor device 2 includes a semiconductor portion 60, an anode electrode 61, and a cathode electrode 62. The semiconductor portion 60 includes a p-type portion 65 and an n-type portion 66, the anode electrode 61 is connected to the p-type portion 65, and the cathode electrode 62 is connected to the n-type portion 66.

[0089] The n-type portion 66 includes n + n-type contact layer 51, thin n-type buffer layer 12, thick n-type buffer layer 13 and n - Type base layer 14. - The p-type base layer 14 is in contact with the p-type portion 65, and the thin n-type buffer layer 12 is in contact with the cathode electrode 62. + Type collector electrode layer 11.

[0090] like Fig.13 As shown, in the present embodiment, there is no peak on the proton concentration curve, and the position 43 where the proton concentration takes the maximum value in the Z direction coincides with the lower surface 60 a of the semiconductor portion 60 .

[0091] Such a curve, as in Fig. 9As described in the above, the peak value P3 of the proton concentration is located in the getter 90 or on the lower surface 60a when the thick n-type buffer layer 13 is formed by disposing the getter 90 on the lower surface 60a of the semiconductor portion 60 and injecting protons through the getter 90. After the protons are injected, the getter 90 is removed, so the peak value P3 of the proton concentration does not remain in the semiconductor portion 60.

[0092] In the present embodiment, the position 43 is located closer to the cathode electrode 62 than the position 42, so that the short-circuit resistance can be improved. The structure, operation, and effects other than the above in the present embodiment are the same as those of the first embodiment described above.

[0093] <Modification of Second Embodiment>

[0094] Fig.14 The graph shows the concentration curve of each impurity along the Z direction in the present modification example, with the position in the Z direction being represented on the horizontal axis and the concentration of each impurity being represented on the vertical axis.

[0095] like Fig.14 As shown, in this modification, the position 43 of the peak value P3 of the proton concentration is located on the cathode electrode 62 side compared to the position 42 of the peak value P2 of the phosphorus concentration in the thin n-type buffer layer 12. Thus, the short-circuit tolerance can be improved. The structure, operation and effect other than the above in this modification are the same as those of the second embodiment described above.

[0096] <Test example>

[0097] Fig.15 The graph shows the influence of the proton curve on the short-circuit withstand capacity by taking the position where the proton concentration in the Z direction is the maximum value on the horizontal axis and taking the result of the short-circuit withstand capacity test on the vertical axis.

[0098] Fig.15 The coordinates of the horizontal axis are based on the position of the lower surface 10a of the semiconductor portion 10. That is, "0" on the horizontal axis corresponds to the position of the lower surface 10a, negative values ​​correspond to the outside of the semiconductor portion 10, specifically, the inside of the absorbent 90, and positive values ​​correspond to the inside of the semiconductor portion 10. The position 42 where the phosphorus concentration takes the maximum value exists near +4μm.

[0099] In this test example, a plurality of semiconductor devices 1 of the first embodiment were manufactured. In the plurality of manufactured semiconductor devices 1, the positions 43 where the proton concentration takes the maximum value are different from each other. In addition, the short-circuit withstand capability of each semiconductor device 1 was evaluated. A semiconductor device that did not undergo destruction under a predetermined condition was defined as "non-destructive", and a semiconductor device that underwent destruction was defined as "destructive".

[0100] like Fig.15As shown, the semiconductor device where the position 43 where the proton concentration takes the maximum value is located on the -Z direction side compared to the position 42 where the phosphorus concentration takes the maximum value is "non-destructed". On the other hand, the semiconductor device where the position 43 is located on the +Z direction side compared to the position 42 is "destructed". In the destroyed semiconductor device, the semiconductor portion 10 is melted.

[0101] Next, an example of measuring the impurity concentration curve of an actual product is shown.

[0102] Fig.16 This is a graph showing the concentration curve of each impurity along the Z direction in this test example, with the position in the Z direction on the horizontal axis and the concentration of each impurity on the vertical axis.

[0103] The concentration of each impurity was measured by SIMS (Secondary Ionization Mass Spectrometer).

[0104] Fig.16 The coordinates of the horizontal axis are based on the position of the lower surface 10a of the semiconductor portion 10. Fig.16 In the figure, region R is excluded from the following consideration because it is a region where the influence of surface adsorbents appears.

[0105] like Fig.16 As shown in FIG. 4 , in this measurement example, the position 43 of the peak value P3 of the proton concentration is also located on the −Z direction side compared to the position 42 of the peak value P2 of the phosphorus concentration. Fig.15 This device was evaluated in the same manner as the test example shown, and the short-circuit withstand capability was good.

[0106] According to the above-described embodiments, a semiconductor device with high short-circuit tolerance and a method for manufacturing the same can be realized.

[0107] Some embodiments of the present invention have been described above, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the main purpose of the invention. These embodiments and their variations are included in the scope and main purpose of the invention, and are included in the scope of the invention and its equivalents recorded in the claims. In addition, the aforementioned embodiments and their variations can be combined with each other for implementation.

[0108] The present invention includes the following aspects.

[0109] (Note 1)

[0110] A semiconductor device comprising:

[0111] a first electrode;

[0112] a second electrode;

[0113] A first semiconductor layer of n-type conductivity, including a first impurity serving as a donor and protons, and having a first position in the layer where the concentration of the first impurity takes a maximum value;

[0114] a second semiconductor layer of n-type conductivity, arranged on the first direction side from the first electrode toward the second electrode relative to the first semiconductor layer, and containing the first impurity and protons, wherein the concentration of the protons is higher than the concentration of the first impurity; and

[0115] a third semiconductor layer of n-type conductivity, disposed on the first direction side of the second semiconductor layer, and containing the first impurity, wherein the concentration of the first impurity is higher than the concentration of the protons;

[0116] In at least a portion of the first semiconductor layer on the second semiconductor layer side, the concentration of the first impurity is higher than the concentration of the protons,

[0117] A second position where the concentration of the protons in the first direction takes a maximum value is located on the opposite side of the first position in the first direction.

[0118] (Note 2)

[0119] The semiconductor device according to Supplementary Note 1, wherein:

[0120] The second position is located in the first semiconductor layer.

[0121] (Note 3)

[0122] The semiconductor device according to Supplementary Note 1, wherein:

[0123] The second position is located on a surface of the first semiconductor layer on the first electrode side.

[0124] (Note 4)

[0125] The semiconductor device according to any one of Supplementary Notes 1 to 3, wherein:

[0126] The semiconductor device further includes a fourth semiconductor layer having a p-type conductivity.

[0127] The first semiconductor layer is located on the first direction side of the fourth semiconductor layer.

[0128] (Note 5)

[0129] The semiconductor device according to Supplementary Note 4, wherein:

[0130] The second position is located in the fourth semiconductor layer.

[0131] (Note 6)

[0132] The semiconductor device according to Supplementary Note 4, wherein:

[0133] The second position is located on a surface of the fourth semiconductor layer opposite to the first semiconductor layer.

[0134] (Note 7)

[0135] The semiconductor device according to any one of Supplementary Notes 4 to 6, wherein:

[0136] The semiconductor device further includes a fifth semiconductor layer which is arranged on the first direction side of the third semiconductor layer and has a p-type conductivity type.

[0137] (Note 8)

[0138] The semiconductor device according to Supplementary Note 7, further comprising:

[0139] A sixth semiconductor layer, which is disposed on the first direction side of the fifth semiconductor layer and has an n-type conductivity;

[0140] a gate electrode, which is opposite to the fifth semiconductor layer; and

[0141] a gate insulating film disposed between the fifth semiconductor layer and the gate electrode;

[0142] The first electrode is a collector electrode connected to the fourth semiconductor layer,

[0143] The second electrode is an emitter electrode connected to the sixth semiconductor layer.

[0144] (Note 9)

[0145] The semiconductor device according to any one of Supplementary Notes 1 to 8, wherein:

[0146] The first impurity is phosphorus.

[0147] (Note 10)

[0148] A method for manufacturing a semiconductor device, comprising:

[0149] A step of implanting a first impurity serving as a donor into a semiconductor component having an n-type conductivity from a first surface side of the semiconductor component along a first direction to form a first position where the concentration of the first impurity takes a maximum value inside the semiconductor component;

[0150] a step of disposing a getter on the first surface side of the semiconductor component;

[0151] a step of injecting protons into the semiconductor component along the first direction via the getter so that a second position where the proton concentration takes a maximum value is located on the opposite side of the first position in the first direction; and

[0152] A step of removing the absorbent.

[0153] (Note 11)

[0154] The method for manufacturing a semiconductor device according to Supplementary Note 10, wherein:

[0155] In the step of implanting protons, a target position of the second position is set to the first surface.

[0156] Description of Reference Numerals

[0157] 1.2 Semiconductor devices

[0158] 10Semiconductor

[0159] 10a Lower surface

[0160] 10b Upper surface

[0161] 10w semiconductor wafer

[0162] 11p + Type collector electrode layer

[0163] 12Thin n-type buffer layer

[0164] 13 thick n-type buffer layer

[0165] 14n - Base layer

[0166] 15n-type barrier layer

[0167] 16p type base layer

[0168] 17p + Diffusion layer

[0169] 18n + Type emitter layer

[0170] 19p + Contact layer

[0171] 21Gate insulating film

[0172] 22Dummy gate insulating film

[0173] 23. Gate insulation parts

[0174] 24Dummy gate insulation component

[0175] 31 Collector electrode

[0176] 32 emitter electrode

[0177] 33 Gate electrode

[0178] 34Dummy gate electrode

[0179] 36Gate trench

[0180] 37Dummy gate trench

[0181] 41 Location where the boron concentration reaches its maximum value

[0182] 42 The location where the phosphorus concentration reaches its maximum value

[0183] 43 The position where the proton concentration reaches its maximum

[0184] 51n + Contact layer

[0185] 60 Semiconductor Part

[0186] 60a lower surface

[0187] 61 Anode electrode

[0188] 62 cathode electrode

[0189] 65p type part

[0190] 66n type part

[0191] 90 Absorbent

[0192] P1 boron peak

[0193] P2 phosphorus peak

[0194] Peak value of P3 proton

Claims

1. A semiconductor device, characterized in that: have: a first electrode; a second electrode; A first semiconductor layer of n-type conductivity, including a first impurity serving as a donor and protons, and having a first position in the layer where the concentration of the first impurity takes a maximum value; a second semiconductor layer of n-type conductivity, arranged on the first direction side from the first electrode toward the second electrode relative to the first semiconductor layer, and containing the first impurity and protons, wherein the concentration of the protons is higher than the concentration of the first impurity; as well as a third semiconductor layer of n-type conductivity, disposed on the first direction side of the second semiconductor layer, and containing the first impurity, wherein the concentration of the first impurity is higher than the concentration of the protons; In at least a portion of the first semiconductor layer on the second semiconductor layer side, the concentration of the first impurity is higher than the concentration of the protons, A second position where the concentration of the protons in the first direction takes a maximum value is located on the opposite side of the first position in the first direction.

2. The semiconductor device according to claim 1, wherein: The second position is located in the first semiconductor layer.

3. The semiconductor device according to claim 1, wherein: The second position is located on a surface of the first semiconductor layer on the first electrode side.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that The semiconductor device further includes a fourth semiconductor layer having a p-type conductivity. The first semiconductor layer is located on the first direction side of the fourth semiconductor layer.

5. The semiconductor device according to claim 4, wherein: The second position is located in the fourth semiconductor layer.

6. The semiconductor device according to claim 4, wherein: The second position is located on a surface of the fourth semiconductor layer opposite to the first semiconductor layer.

7. The semiconductor device according to claim 4, wherein: The semiconductor device further includes a fifth semiconductor layer which is arranged on the first direction side of the third semiconductor layer and has a p-type conductivity type.

8. The semiconductor device according to claim 7, wherein: Also available: a sixth semiconductor layer of n-type conductivity, disposed on the first direction side of the fifth semiconductor layer; a gate electrode, which is opposite to the fifth semiconductor layer; as well as a gate insulating film disposed between the fifth semiconductor layer and the gate electrode; The first electrode is a collector electrode connected to the fourth semiconductor layer, The second electrode is an emitter electrode connected to the sixth semiconductor layer.

9. The semiconductor device according to claim 1, wherein: The first impurity is phosphorus.

10. A method for manufacturing a semiconductor device, characterized in that: The following processes are available: Into a semiconductor component containing a first impurity serving as a donor and having an n-type conductivity, the first impurity is implanted from a first surface side of the semiconductor component along a first direction to form a first position where the concentration of the first impurity takes a maximum value inside the semiconductor component; disposing an absorbent on the first surface side of the semiconductor component; injecting protons into the semiconductor component via the getter along the first direction, so that a second position where the proton concentration takes a maximum value is located on the opposite side of the first direction compared to the first position; as well as The absorbent is removed.

11. The method for manufacturing a semiconductor device according to claim 10, wherein: In the step of implanting protons, a target position of the second position is set to the first surface.

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