Display panel and display device

Abstract

The invention relates to a display panel and a display device, and the display panel comprises a plurality of pixel groups which are arranged along a first direction; wherein each pixel group comprises N sub-pixel columns; a plurality of data signal lines; wherein each sub-pixel column is correspondingly connected with M data signal lines, at least part of sub-pixels of the same sub-pixel column are connected with different data signal lines, N is greater than or equal to 2, and M is greater than or equal to 2; a plurality of multiplexing circuits, wherein each multiplexing circuit respectively comprises M multiplexing units; the multiplexing unit comprises a signal input end, N signal output ends and N shunt control ends, and the shunt control ends are respectively used for receiving shunt control signals; the i-th data signal line corresponding to each sub-pixel column in the same pixel group is connected with each signal output end in the i-th multiplexing unit in the corresponding multiplexing circuit, and i is greater than or equal to 1 and less than or equal to M. The display panel provided by the invention has relatively good display performance.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] As an important part of the information industry, display technology has played an important role in the development of information technology. With the development of display technology, organic light emitting diode display panels and other types of display panels have been widely used.

[0003] However, the display performance of the display panel in the related art is insufficient. Summary of the invention

[0004] Based on this, it is necessary to provide a display panel and a display device, aiming to improve the display performance of the display panel.

[0005] In a first aspect, the present application provides a display panel, comprising:

[0006] A plurality of pixel groups, wherein the plurality of pixel groups are arranged along a first direction; wherein each pixel group includes N sub-pixel columns;

[0007] A plurality of data signal lines; wherein each of the sub-pixel columns is connected to M data signal lines respectively, and at least some of the sub-pixels in the same sub-pixel column are connected to different data signal lines, N≥2, M≥2;

[0008] A plurality of multiplexing circuits, each of the multiplexing circuits comprises M multiplexing units; the multiplexing unit comprises a signal input terminal, N signal output terminals, and N branch control terminals; in the same multiplexing unit, each branch control terminal is used to receive different branch control signals; wherein the i-th data signal line corresponding to each sub-pixel column in the same pixel group is connected to each signal output terminal of the i-th multiplexing unit in the corresponding multiplexing circuit, and the display panel further comprises a plurality of fan-out lines, the signal input terminal of each multiplexing unit is connected to a different fan-out line, 1≤i≤M.

[0009] In one embodiment, the display panel further includes:

[0010] A plurality of scanning signal lines, each of which is connected to a sub-pixel row;

[0011] The display panel has a plurality of driving stages, each of which includes: N charging stages and a scanning stage, and the charging stages do not overlap; wherein, in the jth charging stage of the N charging stages, the branch control signal received by the jth branch control terminal in the multiplexing unit is at an effective level, 1≤j≤N, and in the scanning stage, the scanning signals received by the adjacent M rows of sub-pixels are all at an effective level;

[0012] In one of the embodiments, the pixel group includes at least one sub-pixel unit, and the sub-pixel unit includes three sub-pixel columns.

[0013] In one embodiment, each of the sub-pixel columns comprises a plurality of light-emitting elements, the light-emitting elements in the same sub-pixel column emit the same light-emitting color, and the light-emitting colors of the sub-pixel columns in the sub-pixel unit are different from each other.

[0014] In one embodiment, the sub-pixel columns corresponding to the last charging stage in each of the driving stages emit the same light color.

[0015] In one embodiment, the multiplexing unit further includes N switching transistors, the first pole of each switching transistor is the signal input end, the second pole of each switching transistor is the signal output end, and the gate of each switching transistor is the branch control end.

[0016] In one embodiment, the pixel group includes a first sub-pixel column, a second sub-pixel column and a third sub-pixel column; each of the multiplexing circuits includes a first multiplexing unit and a second multiplexing unit.

[0017] In one embodiment, the first multiplexing unit and the second multiplexing unit each include three switch transistors.

[0018] In one embodiment, the first sub-pixel column, the second sub-pixel column and the third sub-pixel column are respectively connected to two data signal lines, which are the first data signal line and the second data signal line respectively; the sub-pixels in the Ath row of the sub-pixel columns are connected to the first data signal line, and the sub-pixels in the A+1th row are connected to the second data signal line, and A≥1.

[0019] Among them, the first data signal line corresponding to the first sub-pixel column, the first data signal line corresponding to the second sub-pixel column, and the first data signal line corresponding to the third sub-pixel column are respectively connected to the second electrodes of the three switching transistors of the first multiplexing unit, and the second data signal line corresponding to the first sub-pixel column, the second data signal line corresponding to the second sub-pixel column, and the second data signal line corresponding to the third sub-pixel column are respectively connected to the second electrodes of the three switching transistors of the second multiplexing unit.

[0020] In one embodiment, each of the sub-pixel columns includes a plurality of light-emitting elements, and the light-emitting colors of the light-emitting elements in the same sub-pixel column are the same, and the light-emitting colors of the light-emitting elements included in the first sub-pixel column, the second sub-pixel column, and the third sub-pixel column are different.

[0021] In one embodiment, the scanning signal received by the sub-pixels in the Ath row of the sub-pixel column is synchronized with the scanning signal received by the sub-pixels in the A+1th row.

[0022] In one embodiment, each driving stage includes: a first charging stage, a second charging stage, a third charging stage and a scanning stage; wherein the first charging stage, the second charging stage and the third charging stage have no overlap, and the overlapping time of the third charging stage and the scanning stage is less than or equal to a preset time threshold;

[0023] In one embodiment, the display panel has multiple driving stages. In the first charging stage, the first multiplexing unit is used to provide a data signal to the first data signal line of the first sub-pixel column, and the second multiplexing unit is used to provide a data signal to the second data signal line of the first sub-pixel column; in the second charging stage, the first multiplexing unit is used to provide a data signal to the first data signal line of the second sub-pixel column, and the second multiplexing unit is used to provide a data signal to the second data signal line of the second sub-pixel column; in the third charging stage, the first multiplexing unit is used to provide a data signal to the first data signal line of the third sub-pixel column, and the second multiplexing unit is used to provide a data signal to the second data signal line of the third sub-pixel column.

[0024] In one embodiment, each of the pixel groups includes a fourth sub-pixel column, a fifth sub-pixel column, a sixth sub-pixel column, a seventh sub-pixel column, an eighth sub-pixel column and a ninth sub-pixel column; each of the multiplexing circuits includes a third multiplexing unit, a fourth multiplexing unit and a fifth multiplexing unit.

[0025] In one embodiment, the third multiplexing unit, the fourth multiplexing unit and the fifth multiplexing unit each include six switch transistors.

[0026] In one embodiment, each of the sub-pixel columns includes a plurality of light-emitting elements, and the light-emitting elements in the same sub-pixel column have the same light-emitting color. The light-emitting elements included in the fourth sub-pixel column, the fifth sub-pixel column, and the sixth sub-pixel column have different light-emitting colors. The light-emitting elements included in the fourth sub-pixel column and the seventh sub-pixel column have the same light-emitting color. The light-emitting elements included in the fifth sub-pixel column and the eighth sub-pixel column have the same light-emitting color. The light-emitting elements included in the sixth sub-pixel column and the ninth sub-pixel column have the same light-emitting color.

[0027] In one embodiment, each of the sub-pixel columns is connected to three data signal lines, which are the third data signal line, the fourth data signal line and the fifth data signal line respectively. The sub-pixels in the Ath row of the sub-pixel columns are connected to the third data signal line, the sub-pixels in the A+1th row are connected to the fourth data signal line, and the sub-pixels in the A+2th row are connected to the fourth data signal line, and A≥1.

[0028] In one embodiment, the scanning signals received by the sub-pixels in the Ath row, the scanning signals received by the sub-pixels in the A+1th row, and the scanning signals received by the sub-pixels in the A+2th row in the sub-pixel column are synchronized.

[0029] In a second aspect, the present application provides a display device, comprising the display panel of the first aspect.

[0030] The display panel provided by the embodiment of the present application includes multiple pixel groups arranged along a first direction, multiple data signal lines, multiple multiplexing circuits and multiple fan-out lines, wherein each pixel group includes N sub-pixel columns, each multiplexing circuit includes M multiplexing units, and each multiplexing unit includes a signal input terminal, N signal output terminals, and N branch control terminals. In the present application, each sub-pixel column is respectively connected to M data signal lines, at least some sub-pixels in the same sub-pixel column are connected to different data signal lines, and the i-th data signal line corresponding to each sub-pixel column in the same pixel group is connected to each signal output end in the i-th multiplexing unit in the corresponding multiplexing circuit, each branch control end is used to receive different branch control signals, and the signal input end of each multiplexing unit is connected to a different fan-out line, so that the signal input end of each multiplexing unit receives different data signals, and then under the action of the branch control signal received by the branch control end, each signal input end in the multiplexing circuit is controlled to provide a corresponding data signal to the corresponding signal output end, so as to charge the corresponding data signal line, thereby realizing that the multiplexing circuit cooperates with multiple data signal lines to charge multiple sub-pixels in a sub-pixel column, thereby improving the charging time of the sub-pixels and thus improving the display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 A schematic diagram of a planar structure of a display panel provided in an embodiment of the present application;

[0032] Figure 2 A schematic diagram of a planar structure of another display panel provided in an embodiment of the present application;

[0033] Figure 3 A schematic diagram of a planar structure of another display panel provided in an embodiment of the present application;

[0034] Figure 4 A schematic diagram of a planar structure of another display panel provided in an embodiment of the present application;

[0035] Figure 5 A driving timing diagram of a display panel provided in an embodiment of the present application;

[0036] Figure 6 A schematic diagram of a planar structure of another display panel provided in an embodiment of the present application;

[0037] Figure 7 A driving timing diagram of another display panel provided in an embodiment of the present application;

[0038] Figure 8 A schematic diagram of the structure of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0039] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present application more thorough and comprehensive.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0041] When describing positional relationships, unless otherwise specified, when an element such as a layer, film, or substrate is referred to as being "on" another element, it can be directly on the other element or there may be intervening elements. Further, when a layer is referred to as being "under" another layer, it can be directly under or there may be one or more intervening elements. It is also understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or there may be one or more intervening elements.

[0042] In the case of using “including”, “having”, and “comprising” described herein, another component may be added unless a clear limiting term such as “only”, “consisting of”, etc. is used. Unless mentioned otherwise, a term in the singular form may include a plural form and should not be understood as being one in number.

[0043] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present application.

[0044] It should also be understood that when interpreting an element, even if not explicitly described, the element is interpreted as including a range of error, which should be within the acceptable deviation range of the specific value determined by those skilled in the art. For example, "approximately", "approximately" or "substantially" can mean within one or more standard deviations, which are not limited here.

[0045] Furthermore, in the specification, the phrase “planar distribution schematic diagram” refers to a drawing when a target portion is viewed from above, and the phrase “cross-sectional schematic diagram” refers to a drawing when a section taken by vertically cutting the target portion is viewed from the side.

[0046] In addition, the drawings are not drawn to a 1:1 scale, and the relative sizes of the elements in the drawings are drawn only as examples and not necessarily according to the true scale.

[0047] As mentioned in the background technology section, the refresh rate and resolution of the display panel are key indicators for measuring the quality of the display panel. With the continuous improvement of user demand, high refresh rate and high resolution have become the industry trend. With the increase of refresh rate and resolution, the pixel charging time of the display panel will be shortened, which will lead to insufficient pixel charging time, so that each pixel cannot be fully charged, and the display effect cannot be guaranteed at low grayscale, affecting the display effect of the display device, such as the problem of poor display uniformity.

[0048] To solve the above technical problems, please refer to Figure 1 The present application proposes a display panel, characterized in that it includes: a plurality of pixel groups 10, a plurality of data signal lines 20 and a plurality of multiplexing circuits 30.

[0049] Among them, multiple pixel groups 10 are arranged along a first direction, the first direction is the X-axis direction shown in the figure, each pixel group 10 includes N sub-pixel columns PL, each sub-pixel column PL corresponds to M data signal lines 20, and at least some sub-pixels P of the same sub-pixel column PL are connected to different data signal lines 20, N≥2, M≥2.

[0050] The multiplexing circuit 30 includes M multiplexing units 301, and the multiplexing unit 301 includes a signal input terminal, N signal output terminals, and N branch control terminals, and each branch control terminal is used to receive a branch control signal Demux; wherein, the i-th data signal line corresponding to each sub-pixel column PL in the same pixel group 10 is connected to each signal output terminal of the i-th multiplexing unit in the corresponding multiplexing circuit, and the display panel also includes multiple fan-out lines (not shown in the figure), and the signal input terminal of each multiplexing unit 301 is connected to a different fan-out line, so that the signal input terminal of each multiplexing unit 301 receives a different data signal source, 1≤i≤M.

[0051] In this example, see Figure 1 The display panel provided in the present application includes a plurality of pixel groups 10 arranged along a first direction, each pixel group 10 includes a plurality of sub-pixel columns PL, each sub-pixel column PL includes a plurality of sub-pixels P arranged along a second direction, and the second direction is the Y-axis direction shown in the figure. In an example, the luminous colors of the sub-pixels P in a sub-pixel column PL are the same, and the luminous colors of the sub-pixels P in adjacent sub-pixel columns PL are different.

[0052] A multiplexing circuit 30 provides a data signal for each sub-pixel P in a pixel group 10, that is, the number of multiplexing circuits 30 in the display panel of the present application is the same as the number of pixel groups 10. Among them, a multiplexing circuit 30 may include M multiplexing units 301, and the number of multiplexing units 301 in a multiplexing circuit 30 is the same as the number of data signal lines corresponding to a sub-pixel column. A multiplexing unit 301 may have a signal input terminal, N signal output terminals and N branch control terminals, each branch control terminal is used to receive a different branch control signal, and the branch control signals received by the branch control terminals in different multiplexing units 301 may be the same. Under the action of the branch control signal Demux received by each branch control terminal, the signal input terminal transmits the received data signal source to the corresponding signal output terminal, thereby charging the corresponding data signal line. Exemplarily, under the action of the kth branch control signal Demux, the signal input end of each multiplexing unit 301 in the same multiplexing circuit 30 can respectively transmit each data signal to the corresponding signal output end of each multiplexing unit 301, thereby charging each data signal line corresponding to the kth sub-pixel column in the pixel group, thereby realizing the multiplexing unit cooperating with multiple data signal lines to charge multiple sub-pixels in a sub-pixel column, thereby improving the charging time of the sub-pixels, and thereby improving the display effect of the display panel.

[0053] In the application, the pixel group includes at least one sub-pixel unit, the sub-pixel unit includes three sub-pixel columns, each sub-pixel column includes a plurality of light-emitting elements, the light-emitting colors of the light-emitting elements in the same sub-pixel column are the same, and the light-emitting colors of the sub-pixel columns in the sub-pixel unit are different. In an example, see Figure 1A pixel group 10 may include a sub-pixel unit, and the sub-pixel unit includes three sub-pixel columns PL, wherein the luminous colors of the three sub-pixel columns PL may be different, for example, the luminous color of a sub-pixel column PL is red, the luminous color of a sub-pixel column PL is green, and the luminous color of a sub-pixel column PL is blue. Each sub-pixel column PL is respectively connected to two data signal lines 20 (data signal line 20-1 and data signal line 20-2), and the multiplexing circuit 30 includes two multiplexing units 301 (multiplexing unit 301-1 and multiplexing unit 301-2), and the multiplexing unit 301-1 and the multiplexing unit 301-2 respectively include a signal input terminal, three signal output terminals and three branch control terminals, and the signal input terminal of the multiplexing unit 301-1 is used to receive the data signal source-1, and the signal input terminal of the multiplexing unit 301-2 is used to receive the data signal source-2. Under the action of the branch control signal Demux-1 received by the first branch control end, the signal input end of the multiplexing unit 301-1 can transmit the data signal source-1 to the data signal line 20-1 corresponding to the first sub-pixel column in the corresponding pixel group 10, and the signal input end of the multiplexing unit 301-2 can transmit the data signal source-2 to the data signal line 20-2 corresponding to the first sub-pixel column in the corresponding pixel group 10; under the action of the branch control signal Demux-2 received by the second branch control end, the signal input end of the multiplexing unit 301-1 can transmit the data signal source-1 to the data signal line 20-2 corresponding to the first sub-pixel column in the corresponding pixel group 10. The signal input end of the multiplexing unit 301-2 can transmit the data signal source-2 to the data signal line 20-2 corresponding to the second sub-pixel column in the corresponding pixel group 10; under the action of the branch control signal Demux-3 received by the third branch control end, the signal input end of the multiplexing unit 301-1 can transmit the data signal source-1 to the data signal line 20-1 corresponding to the third sub-pixel column in the corresponding pixel group 10, and the signal input end of the multiplexing unit 301-2 can transmit the data signal source-2 to the data signal line 20-2 corresponding to the third sub-pixel column in the corresponding pixel group 10. In this way, the two data signal lines corresponding to each sub-pixel column can charge each sub-pixel P in the sub-pixel column PL at the same time, thereby improving the charging time of the sub-pixel and thus improving the display effect of the display panel.

[0054] The display panel provided by the embodiment of the present application includes multiple pixel groups arranged along a first direction, multiple data signal lines, multiple multiplexing circuits and multiple fan-out lines, wherein each pixel group includes N sub-pixel columns, each multiplexing circuit includes M multiplexing units, and each multiplexing unit includes a signal input terminal, N signal output terminals, and N branch control terminals. In the present application, each sub-pixel column is respectively connected to M data signal lines, at least some sub-pixels in the same sub-pixel column are connected to different data signal lines, and the i-th data signal line corresponding to each sub-pixel column in the same pixel group is connected to each signal output end in the i-th multiplexing unit in the corresponding multiplexing circuit, each branch control end is used to receive different branch control signals, and the signal input end of each multiplexing unit is connected to a different fan-out line, so that the signal input end of each multiplexing unit receives a different data signal, and then under the action of the branch control signal received by the branch control end, each signal input end in the multiplexing circuit is controlled to provide a corresponding data signal to the corresponding signal output end, so as to charge the corresponding data signal line, thereby realizing that the multiplexing unit cooperates with multiple data signal lines to charge multiple sub-pixels in a sub-pixel column, thereby improving the charging time of the sub-pixels and thus improving the display effect of the display panel.

[0055] In an exemplary embodiment, see Figure 2 The display panel further includes a plurality of scanning signal lines 40, each scanning signal line 40 being connected to a sub-pixel row.

[0056] The display panel includes multiple driving stages, each driving stage includes: N charging stages and a scanning stage, and there is no overlap between the charging stages. The overlapping time of the scanning stage and the Nth charging stage is less than or equal to a preset time threshold. In the jth charging stage of the N charging stages, the branch control signal received by the jth branch control terminal in the multiplexing unit is a valid level, 1≤j≤N, and in the scanning stage, the scanning signals received by adjacent M rows of sub-pixels are all valid levels.

[0057] In the application, the scanning signal line 40 is used to provide a scanning control signal Scan to the corresponding sub-pixel row to control the data writing process of the sub-pixel in the corresponding sub-pixel row. Before data writing, each multiplexing unit 301 needs to charge the corresponding data signal line, that is, in the first charging stage, the first branch control terminal in the multiplexing circuit receives the branch control signal as an effective level, and each multiplexing unit 301 charges each data signal line corresponding to the first sub-pixel column in the pixel group; in the second charging stage, the second branch control terminal in the multiplexing circuit receives the branch control signal as an effective level, and each multiplexing unit 301 charges each data signal line corresponding to the second sub-pixel column in the pixel group; ...; in the Nth charging stage, the Nth branch control terminal in the multiplexing circuit receives the branch control signal as an effective level, and each multiplexing unit 301 charges each data signal line corresponding to the Nth sub-pixel column in the pixel group. Finally, in the scanning stage, each data signal line charges the data signal into the corresponding sub-pixel.

[0058] In the present application, the pixel arrangement of the display panel can be a real RGB arrangement, which means that the square pixel is evenly divided into three sub-pixels, which are respectively given red (R), green (G), and blue (B). The three colors of red, green, and blue are independent of each other and cannot be produced by mixing other colors. Almost all other colors in nature can be obtained by combining the three primary colors of red, green, and blue in different proportions, thereby ensuring that each pixel can accurately present the three primary colors of red, green, and blue, so that the display panel can achieve full-color display. The pixel group of the present application may include at least one sub-pixel unit, and a sub-pixel unit refers to a combination of an R sub-pixel column, a G sub-pixel column, and a B sub-pixel column.

[0059] It can be understood that when the charging phase and the scanning phase do not overlap, the data signal is first charged to the corresponding data signal line, and when the scanning phase is turned on, the corresponding sub-pixel is charged by the data signal line, that is, pre-charging. When the charging phase and the scanning phase overlap, the data signal is directly charged into the corresponding sub-pixel, that is, direct charging. When the data signal size is the same, the gate potential of the driving transistor in the sub-pixel using the direct charging method is higher than the gate potential of the driving transistor in the sub-pixel using the pre-charging method.

[0060] Since the present application adopts the real RGB pixel arrangement method, the color of the last sub-pixel column of each pixel group can be made the same, that is, the luminous color of the sub-pixel column corresponding to the last charging stage in each driving stage is the same. Since there is no time overlap between the charging stages in the driving stage of the present application, the overlapping time of the Nth charging stage and the scanning stage is less than or equal to the preset time threshold, it can be ensured that the sizes of data signals written to different sub-pixel columns are different, and at least the sub-pixel columns corresponding to the first N-1 charging stages all adopt a pre-charging method. When the Nth charging stage does not overlap with the scanning stage, the last sub-pixel column of each pixel group corresponding to the Nth charging stage adopts a pre-charging method. When the Nth charging stage overlaps with the scanning stage, it can be ensured that the charging method of sub-pixel columns of the same color is the same, so as to ensure the display uniformity of the display panel.

[0061] In addition, in the present application, the adjacent M rows of sub-pixels in each pixel column are connected to different data signal lines to ensure that different data signals are written to the adjacent M rows of sub-pixels, and then the adjacent M rows of sub-pixels can be controlled to receive synchronized scanning signals, that is, to achieve simultaneous control of the adjacent M rows of sub-pixels, so that the duration of the driving phase of the present application is M 1H, where 1H is the ratio of one frame time of the display panel to the number of rows of all sub-pixel rows in the display panel, that is, 1H is the interval duration of the scanning signal of the pixel circuit in the current sub-pixel row and the scanning signal of the pixel circuit in the next sub-pixel row. By achieving simultaneous control of multiple rows of sub-pixels, the duration of the driving phase can be increased, and then the duration of each charging phase can be increased, the charging time of each sub-pixel can be increased, and the display effect of the display panel can be improved.

[0062] In an exemplary embodiment, see Figure 3 The multiplexing unit 301 also includes N switch transistors T, the first electrodes of each switch transistor T are the signal input terminals, the second electrodes of each switch transistor are the corresponding signal output terminals, and the gates of each switch transistor are the branch control terminals.

[0063] In this embodiment, in a multiplexing circuit 30, the first electrode of the qth switch transistor T in each multiplexing unit 301 is respectively connected to the corresponding fan-out line to receive the data signal; the second electrode of the qth switch transistor T in each multiplexing unit 301 is respectively connected to the data signal line of the qth sub-pixel column in the pixel group, and the gate of the qth switch transistor T in each multiplexing unit 301 is connected to the same branch control terminal. Then, under the action of the branch control terminal receiving the branch control signal Demux, the qth switch transistor T in each multiplexing unit 301 is turned on at the same time to charge the data signal line of the qth sub-pixel column in the pixel group through each signal input terminal and the corresponding signal output terminal. Among them, the switch transistor T can be a P-type transistor or an N-type transistor.

[0064] In an exemplary embodiment, see Figure 4 The pixel group 10 includes a first sub-pixel column PL1, a second sub-pixel column PL2 and a third sub-pixel column PL3, each sub-pixel column PL includes a plurality of light-emitting elements, the light-emitting colors of the light-emitting elements in a sub-pixel column PL are the same, the light-emitting colors of the light-emitting elements included in the first sub-pixel column PL1, the second sub-pixel column PL2 and the third sub-pixel column PL3 are different, exemplarily, the light-emitting color of the light-emitting elements included in the first sub-pixel column PL1 is red, the light-emitting color of the light-emitting elements included in the second sub-pixel column PL2 is green, and the light-emitting color of the light-emitting elements included in the third sub-pixel column PL3 is blue.

[0065] Each sub-pixel column PL is respectively connected to two data signal lines 20: a first data signal line 21 and a second data signal line 22. Specifically, the first sub-pixel column PL1 is respectively connected to the first data signal line 21a and the second data signal line 22a, the second sub-pixel column PL2 is respectively connected to the first data signal line 21b and the second data signal line 22b, and the third sub-pixel column PL3 is respectively connected to the first data signal line 21c and the second data signal line 22c, and the data signal lines 20 connected to two adjacent rows of sub-pixels in the sub-pixel column are different. For example, see Figure 4 , Figure 4 The black circular pattern in each sub-pixel represents the connection relationship between the sub-pixel and the data signal line. It can be seen that in each sub-pixel column, the sub-pixels in the first row are connected to the first data signal line 21, the sub-pixels in the second row are connected to the second data signal line 22, the sub-pixels in the third row are connected to the first data signal line 21, the sub-pixels in the fourth row are connected to the second data signal line 22….

[0066] The multiplexing circuit 30 includes a first multiplexing unit 31 and a second multiplexing unit 32. The first multiplexing unit 31 and the second multiplexing unit 32 respectively include three switch transistors; wherein the gate of each switch transistor is respectively three branch control terminals, the first terminals of the three switch transistors are respectively signal input terminals, and the second terminals of the three switch transistors are respectively three signal output terminals. The first data signal line 21a corresponding to the first sub-pixel column PL1, the first data signal line 21b corresponding to the second sub-pixel column PL2, and the first data signal line 21c corresponding to the third sub-pixel column PL3 are respectively connected to the second terminals of the three switch transistors in the first multiplexing unit 31; the second data signal line 22a corresponding to the first sub-pixel column PL1, the second data signal line 22b corresponding to the second sub-pixel column PL2, and the second data signal line 22c corresponding to the third sub-pixel column PL3 are respectively connected to the second terminals of the three switch transistors in the second multiplexing unit 32.

[0067] Specifically, the first multiplexing unit 31 includes three switching transistors (switching transistor T1, switching transistor T2 and switching transistor T3), wherein the first electrodes of the switching transistors T1, T2 and T3 are connected to the same fan-out line to receive the data signal source1, the second electrode of the switching transistor T1 is connected to the first data signal line 21a, the second electrode of the switching transistor T2 is connected to the first data signal line 21b, the second electrode of the switching transistor T3 is connected to the first data signal line 21c, the gate of the switching transistor T1 is used to receive the branch control signal Demux1, the gate of the switching transistor T2 is used to receive the branch control signal Demux2, and the gate of the switching transistor T3 is used to receive the branch control signal Demux3. The second multiplexing unit 32 includes three switching transistors (switch transistor T4, switch transistor T5 and switch transistor T6), wherein the first electrodes of the switch transistors T4, T5 and T6 are commonly connected to another fan-out line to receive the data signal source2, the second electrode of the switch transistor T4 is connected to the second data signal line 22a, the second electrode of the switch transistor T5 is connected to the second data signal line 22b, the second electrode of the switch transistor T6 is connected to the second data signal line 22c, the gate of the switch transistor T4 is used to receive the branch control signal Demux1, the gate of the switch transistor T5 is used to receive the branch control signal Demux2, and the gate of the switch transistor T6 is used to receive the branch control signal Demux3.

[0068] In the application, the scanning signal received by the sub-pixel in the Ath row of the sub-pixel column is synchronized with the scanning signal received by the sub-pixel in the A+1th row. Figure 4 The scanning signal line 40 includes a plurality of scanning signal lines, such as a scanning signal line 41, a scanning signal line 42, a scanning signal line 43, and a scanning signal line 44, wherein the scanning signal line 41 is used to provide a scanning signal scan1 for the first row of sub-pixels, the scanning signal line 42 is used to provide a scanning signal scan2 for the second row of sub-pixels, the scanning signal line 43 is used to provide a scanning signal scan3 for the third row of sub-pixels, and the scanning signal line 44 is used to provide a scanning signal scan4 for the fourth row of sub-pixels, .... Among them, the scanning signal scan1 is synchronized with the scanning signal scan2, the scanning signal scan3 is synchronized with the scanning signal scan4, ....

[0069] In this example, see Figure 5The display panel of the present application has multiple driving stages, and the driving stages include a first charging stage t1, a second charging stage t2, a third charging stage t3 and a scanning stage t4; wherein the first charging stage t1, the second charging stage t2 and the third charging stage t3 do not overlap, and the overlapping time of the third charging stage t3 and the scanning stage t4 is less than a preset time threshold. In the first charging stage, the first multiplexing unit is used to provide a data signal to the first data signal line of the first sub-pixel column, and the second multiplexing unit is used to provide a data signal to the second data signal line of the first sub-pixel column; in the second charging stage, the first multiplexing unit is used to provide a data signal to the first data signal line of the second sub-pixel column, and the second multiplexing unit is used to provide a data signal to the second data signal line of the second sub-pixel column; in the third charging stage, the first multiplexing unit is used to provide a data signal to the first data signal line of the third sub-pixel column, and the second multiplexing unit is used to provide a data signal to the second data signal line of the third sub-pixel column.

[0070] Please refer to Figure 4 and Figure 5In this example, the duration of the driving phase is 2H. In order to increase the charging time of the sub-pixels in this application, two adjacent rows of sub-pixels are set to be charged simultaneously and receive different data signals. For example, in the first charging phase t1, the gate of the switch transistor T1 and the gate of the switch transistor T4 simultaneously receive the low-level shunt control signal Demux1. Under the action of the shunt control signal Demux1, the switch transistor T1 and the switch transistor T4 are turned on, and then the data signal source1 charges the first data signal line 21a, and the data signal source2 charges the second data signal line 22a; then the first charging phase t1 ends and enters the second charging phase t2, the gate of the switch transistor T2 and the gate of the switch transistor T5 simultaneously receive the low-level shunt control signal Demux2, under the action of the shunt control signal Demux2 Under the condition that the switching transistor T2 and the switching transistor T5 are turned on, the data signal source1 charges the first data signal line 21b, and the data signal source2 charges the second data signal line 22b; then the second charging stage t2 ends and enters the third charging stage t3, the gate of the switching transistor T3 and the gate of the switching transistor T6 simultaneously receive the low-level branch control signal Demux3, under the action of the branch control signal Demux3, the switching transistor T3 and the switching transistor T6 are turned on, and the data signal source1 charges the first data signal line 21c, and the data signal source2 charges the second data signal line 22c. The third charging stage t3 may overlap with the scanning stage t4. In the scanning stage t4, the first data signal line 21a and the second data signal line 22a charge the corresponding sub-pixels in the first sub-pixel column, the first data signal line 21b and the second data signal line 22b charge the corresponding sub-pixels in the second sub-pixel column, and the first data signal line 21c, the second data signal line 22c and the two signal input terminals charge the corresponding sub-pixels in the third sub-pixel column. Since the light emitting colors of the third sub-pixel columns in each pixel group are the same, that is, blue, the present application can ensure that the sub-pixel columns of the same color are charged in the same manner to ensure the uniformity of the display panel.

[0071] At the same time, since the first data signal line and the second data signal line corresponding to two adjacent rows of sub-pixels in the sub-pixel column are charged synchronously and the received data signals are different, the present application can synchronously control the pixel circuits of two adjacent rows. For example, for the first row of sub-pixels and the second row of sub-pixels in the first sub-pixel column, in the first charging stage, the first data signal line 21a corresponding to the first row of sub-pixels in the first sub-pixel column receives the data signal source1, and the second data signal line 22a corresponding to the second row of sub-pixels in the first sub-pixel column receives the data signal source2. Therefore, in the scanning stage, the scanning signal scan1 and the scanning signal scan2 can be controlled to be both low-level valid signals, so that the data signal source1 and the data signal source2 are simultaneously written into the first row of sub-pixels and the second row of sub-pixels in the first sub-pixel column, respectively, and the charging time of the sub-pixels is increased by simultaneously controlling multiple rows of sub-pixels.

[0072] It can be understood that at the same time, the size of the data signal received by the signal input end of the first multiplexing unit may be different from the size of the data signal received by the signal input end of the second multiplexing unit. In addition, in different charging stages, the size of the data signal received by the signal input end of the first multiplexing unit may be different, and the size of the data signal received by the signal input end of the second multiplexing unit may also be different.

[0073] In an exemplary embodiment, see Figure 6 , each pixel group 30 includes a fourth sub-pixel column PL4, a fifth sub-pixel column PL5, a sixth sub-pixel column PL6, a seventh sub-pixel column PL7, an eighth sub-pixel column PL8 and a ninth sub-pixel column PL9. The light-emitting colors of the light-emitting elements in a sub-pixel column PL are the same, the light-emitting colors of the light-emitting elements included in the fourth sub-pixel column PL4, the fifth sub-pixel column PL5 and the sixth sub-pixel column PL6 are different, the light-emitting colors of the light-emitting elements included in the fourth sub-pixel column PL4 and the seventh sub-pixel column PL7 are the same, the light-emitting colors of the light-emitting elements included in the fifth sub-pixel column PL5 and the eighth sub-pixel column PL8 are the same, and the light-emitting colors of the light-emitting elements included in the sixth sub-pixel column PL6 and the ninth sub-pixel column PL9 are the same. Exemplarily, the light-emitting colors of the light-emitting elements included in the fourth sub-pixel column PL4 and the seventh sub-pixel column PL7 are red, the light-emitting colors of the light-emitting elements included in the fifth sub-pixel column PL5 and the eighth sub-pixel column PL8 are green, and the light-emitting colors of the light-emitting elements included in the sixth sub-pixel column PL6 and the ninth sub-pixel column PL9 are blue.

[0074] Each sub-pixel column PL is respectively connected to three data signal lines 20: a third data signal line 23, a fourth data signal line 24 and a fifth data signal line 25. Specifically, the fourth sub-pixel column PL4 is respectively connected to the third data signal line 23a, the fourth data signal line 24a and the fifth data signal line 25a, the fifth sub-pixel column PL5 is respectively connected to the third data signal line 23b, the fourth data signal line 24b and the fifth data signal line 25b, the sixth sub-pixel column PL6 is respectively connected to the third data signal line 23c, the fourth data signal line 24c and the fifth data signal line 25c, the seventh sub-pixel column PL7 is respectively connected to the third data signal line 23d, the fourth data signal line 24d and the fifth data signal line 25d, the eighth sub-pixel column PL8 is respectively connected to the third data signal line 23e, the fourth data signal line 24e and the fifth data signal line 25e, and the ninth sub-pixel column PL9 is respectively connected to the third data signal line 23f, the fourth data signal line 24f and the fifth data signal line 25f. The data signal lines 20 connected to the three adjacent rows of sub-pixels in the sub-pixel column are different. Figure 6 , Figure 6 The black circular pattern in each sub-pixel represents the connection relationship between the sub-pixel and the data signal line. It can be seen that in each sub-pixel column, the sub-pixels in the first row are connected to the third data signal line 23, the sub-pixels in the second row are connected to the fourth data signal line 24, the sub-pixels in the third row are connected to the fifth data signal line 25, the sub-pixels in the fourth row are connected to the third data signal line 23, the sub-pixels in the fifth row are connected to the fourth data signal line 24, and the sub-pixels in the sixth row are connected to the fifth data signal line 25.

[0075] The multiplexing circuit 30 includes a third multiplexing unit 33, a fourth multiplexing unit 34 and a fifth multiplexing unit 35. The third multiplexing unit 33, the fourth multiplexing unit 34 and the fifth multiplexing unit 35 include six switch transistors respectively; wherein the gates of the six switch transistors are six branch control terminals respectively, the first terminals of the six switch transistors are signal input terminals, and the second terminals of the six switch transistors are six signal output terminals respectively.

[0076] In this embodiment, the third multiplexing unit 33 is the first multiplexing unit in the multiplexing circuit 30, the fourth multiplexing unit 34 is the second multiplexing unit in the multiplexing circuit 30, and the fifth multiplexing unit 35 is the third multiplexing unit in the multiplexing circuit 30. The third data signal line 23 is the first data signal line corresponding to the sub-pixel column, the fourth data signal line 24 is the second data signal line corresponding to the sub-pixel column, and the fifth data signal line 25 is the third data signal line corresponding to the sub-pixel column.

[0077] The third data signal line 23a corresponding to the fourth sub-pixel column PL4, the third data signal line 23b corresponding to the fifth sub-pixel column PL5, the third data signal line 23c corresponding to the sixth sub-pixel column PL6, the third data signal line 23d corresponding to the seventh sub-pixel column PL7, the third data signal line 23e corresponding to the eighth sub-pixel column PL8 and the third data signal line 23f corresponding to the ninth sub-pixel column PL9 are respectively connected to the second electrodes of the six switching transistors of the third multiplexing unit 33; the fourth data signal line 24a corresponding to the fourth sub-pixel column PL4, the fourth data signal line 24b corresponding to the fifth sub-pixel column PL5, the fourth data signal line 24c corresponding to the sixth sub-pixel column PL6, the third data signal line 23d corresponding to the seventh sub-pixel column PL7 The fourth data signal line 24d, the fourth data signal line 24e connected to the eighth sub-pixel column PL8 and the fourth data signal line 24f connected to the ninth sub-pixel column PL9 are respectively connected to the second electrodes of the six switching transistors of the fourth multiplexing unit 34; the fifth data signal line 25a connected to the fourth sub-pixel column PL4, the fifth data signal line 25b connected to the fifth sub-pixel column PL5, the fifth data signal line 25c connected to the sixth sub-pixel column PL6, the fifth data signal line 25d connected to the seventh sub-pixel column PL7, the fifth data signal line 25e connected to the eighth sub-pixel column PL8 and the fifth data signal line 25f connected to the ninth sub-pixel column PL9 are respectively connected to the second electrodes of the six switching transistors of the fifth multiplexing unit 35.

[0078] Specifically, the third multiplexing unit 33 includes six switching transistors (switching transistor T7, switching transistor T8, switching transistor T9, switching transistor T10, switching transistor T11 and switching transistor T12), wherein the first electrodes of the switching transistors T7, T8, T9, T10, T11 and T12 are connected to the same fan-out line to receive the data signal source3, the second electrode of the switching transistor T7 is connected to the third data signal line 23a, the second electrode of the switching transistor T8 is connected to the third data signal line 23b, the second electrode of the switching transistor T9 is connected to the third data signal line 23c, and the switching transistors T The second electrode of the switch transistor 10 is connected to the third data signal line 23d, the second electrode of the switch transistor T11 is connected to the third data signal line 23e, the second electrode of the switch transistor T12 is connected to the third data signal line 23f, the gate of the switch transistor T7 is used to receive the shunt control signal Demux4, the gate of the switch transistor T8 is used to receive the shunt control signal Demux5, the gate of the switch transistor T9 is used to receive the shunt control signal Demux6, the gate of the switch transistor T10 is used to receive the shunt control signal Demux7, the gate of the switch transistor T11 is used to receive the shunt control signal Demux8, and the gate of the switch transistor T12 is used to receive the shunt control signal Demux9.

[0079] The fourth multiplexing unit 34 includes six switching transistors (switching transistor T13, switching transistor T14, switching transistor T15, switching transistor T16, switching transistor T17 and switching transistor T18), wherein the first electrodes of the switching transistors T13, switching transistor T14, switching transistor T15, switching transistor T16, switching transistor T17 and switching transistor T18 are commonly connected to another fan-out line to receive the data signal source4, the second electrode of the switching transistor T13 is connected to the fourth data signal line 24a, the second electrode of the switching transistor T14 is connected to the fourth data signal line 24b, the second electrode of the switching transistor T15 is connected to the fourth data signal line 24c, and the switching transistors The second electrode of the switch transistor T16 is connected to the fourth data signal line 24d, the second electrode of the switch transistor T17 is connected to the fourth data signal line 24e, the second electrode of the switch transistor T18 is connected to the fourth data signal line 24f, the gate of the switch transistor T13 is used to receive the branch control signal Demux4, the gate of the switch transistor T14 is used to receive the branch control signal Demux5, the gate of the switch transistor T15 is used to receive the branch control signal Demux6, the gate of the switch transistor T16 is used to receive the branch control signal Demux7, the gate of the switch transistor T17 is used to receive the branch control signal Demux8, and the gate of the switch transistor T18 is used to receive the branch control signal Demux9.

[0080] The fifth multiplexing unit 35 includes six switch transistors (switch transistor T19, switch transistor T20, switch transistor T21, switch transistor T22, switch transistor T23 and switch transistor T24), wherein the first electrodes of the switch transistors T19, T20, T21, T22, T23 and T24 are commonly connected to another fan-out line to receive the data signal source5, the second electrode of the switch transistor T19 is connected to the fifth data signal line 25a, the second electrode of the switch transistor T20 is connected to the fifth data signal line 25b, the second electrode of the switch transistor T21 is connected to the fifth data signal line 25c, and the switch transistors The second electrode of the body transistor T22 is connected to the fifth data signal line 25d, the second electrode of the switching transistor T23 is connected to the fifth data signal line 25e, the second electrode of the switching transistor T24 is connected to the fifth data signal line 25f, the gate of the switching transistor T19 is used to receive the branch control signal Demux4, the gate of the switching transistor T20 is used to receive the branch control signal Demux5, the gate of the switching transistor T21 is used to receive the branch control signal Demux6, the gate of the switching transistor T22 is used to receive the branch control signal Demux7, the gate of the switching transistor T23 is used to receive the branch control signal Demux8, and the gate of the switching transistor T24 is used to receive the branch control signal Demux9.

[0081] In the application, the scanning signal received by the sub-pixel in the Ath row, the scanning signal received by the sub-pixel in the A+1th row, and the scanning signal received by the sub-pixel in the A+2th row are synchronized. Figure 6 , the scanning signal line 40 includes a plurality of scanning signal lines, such as scanning signal line 41, scanning signal line 42, scanning signal line 43, scanning signal line 44, scanning signal line 45, scanning signal line 46, etc., wherein the scanning signal line 41 is used to provide a scanning signal scan1 for the first row of sub-pixels, the scanning signal line 42 is used to provide a scanning signal scan2 for the second row of sub-pixels, the scanning signal line 43 is used to provide a scanning signal scan3 for the third row of sub-pixels, the scanning signal line 44 is used to provide a scanning signal scan4 for the fourth row of sub-pixels, the scanning signal line 45 is used to provide a scanning signal scan5 for the fifth row of sub-pixels, and the scanning signal line 46 is used to provide a scanning signal scan6 for the sixth row of sub-pixels, .... Among them, the scanning signals scan1, scan2 and scan3 are the same, the scanning signals scan4 and scan5 are the same as the scanning signal scan6, ....

[0082] In this example, see Figure 7The driving stages of the display panel of the present application include a fourth charging stage t5, a fifth charging stage t6, a sixth charging stage t7, a seventh charging stage t8, an eighth charging stage t9, a ninth charging stage t10 and a scanning stage t11; there is no overlap between the fourth charging stage t5, the fifth charging stage t6, the sixth charging stage t7, the seventh charging stage t8, the eighth charging stage t9 and the ninth charging stage t10, and the overlapping time of the ninth charging stage t10 and the scanning stage t11 is less than a preset time threshold.

[0083] In the fourth charging stage, the third multiplexing unit 33 is used to provide a data signal for the third data signal line of the fourth sub-pixel column PL4, the fourth multiplexing unit 34 is used to provide a data signal for the fourth data signal line of the fourth sub-pixel column, and the fifth multiplexing unit 35 is used to provide a data signal for the fifth data signal line of the fourth sub-pixel column; in the fifth charging stage, the third multiplexing unit 33 is used to provide a data signal for the third data signal line of the fifth sub-pixel column PL5, the fourth multiplexing unit 34 is used to provide a data signal for the fourth data signal line of the fifth sub-pixel column PL5, and the fifth multiplexing unit 35 is used to provide a data signal for the fifth data signal line of the fifth sub-pixel column PL5; in the sixth charging stage, the third multiplexing unit 33 is used to provide a data signal for the third data signal line of the sixth sub-pixel column PL6, the fourth multiplexing unit 34 is used to provide a data signal for the fourth data signal line of the sixth sub-pixel column PL6, and the fifth multiplexing unit 35 is used to provide a data signal for the fifth data signal line of the sixth sub-pixel column PL6; In the charging stage, the third multiplexing unit 33 is used to provide a data signal for the third data signal line of the seventh sub-pixel column PL7, the fourth multiplexing unit 34 is used to provide a data signal for the fourth data signal line of the seventh sub-pixel column PL7, and the fifth multiplexing unit 35 is used to provide a data signal for the fifth data signal line of the seventh sub-pixel column PL7; in the eighth charging stage, the third multiplexing unit 33 is used to provide a data signal for the third data signal line of the eighth sub-pixel column PL8, the fourth multiplexing unit 34 is used to provide a data signal for the fourth data signal line of the eighth sub-pixel column PL8, and the fifth multiplexing unit 35 is used to provide a data signal for the fifth data signal line of the eighth sub-pixel column PL8; in the ninth charging stage, the third multiplexing unit 33 is used to provide a data signal for the third data signal line of the ninth sub-pixel column PL9, the fourth multiplexing unit 34 is used to provide a data signal for the fourth data signal line of the ninth sub-pixel column PL9, and the fifth multiplexing unit 35 is used to provide a data signal for the fifth data signal line of the ninth sub-pixel column PL9;

[0084] Please refer to Figure 6 and Figure 7In this example, the duration of the driving phase is 3 hours. In order to increase the charging time of the sub-pixels in this application, three adjacent rows of sub-pixels are charged simultaneously and receive different data signals. For example, in the fourth charging phase t5, the gate of the switch transistor T7, the gate of the switch transistor T13, and the gate of the switch transistor T19 simultaneously receive the low-level shunt control signal Demux4. Under the action of the shunt control signal Demux4, the switch transistor T7, the switch transistor T13, and the switch transistor T19 are turned on, and then the data signal source3 charges the third data signal line 23a, the data signal source4 charges the fourth data signal line 24a, and the data signal source5 charges the fifth data signal line 25a; then the fourth charging phase At the end of t5, the fifth charging stage t6 is entered. The gates of the switch transistors T8, T14 and T20 simultaneously receive the low-level branch control signal Demux5. Under the action of the branch control signal Demux5, the switch transistors T8, T14 and T20 are turned on, and then the data signal source3 charges the third data signal line 23b, the data signal source4 charges the fourth data signal line 24b, and the data signal source5 charges the fifth data signal line 25b. After that, the fifth charging stage t6 is entered. Phase t6 ends and enters the sixth charging phase t7. The gates of the switch transistors T9, T15 and T21 simultaneously receive the low-level branch control signal Demux6. Under the action of the branch control signal Demux6, the switch transistors T9, T15 and T21 are turned on, and then the data signal source3 charges the third data signal line 23c, the data signal source4 charges the fourth data signal line 24c, and the data signal source5 charges the fifth data signal line 25c. After that, the sixth charging phase t7 is completed. The charging stage t7 ends and enters the seventh charging stage t8. The gates of the switch transistor T10, the switch transistor T16 and the switch transistor T22 simultaneously receive the low-level shunt control signal Demux7. Under the action of the shunt control signal Demux7, the switch transistor T10, the switch transistor T16 and the switch transistor T22 are turned on, and then the data signal source3 charges the third data signal line 23d, the data signal source4 charges the fourth data signal line 24d, and the data signal source5 charges the fifth data signal line 25d.Then the seventh charging stage t8 ends and enters the eighth charging stage t9, the gate of the switch transistor T11, the gate of the switch transistor T17 and the gate of the switch transistor T23 simultaneously receive the low-level shunt control signal Demux8, under the action of the shunt control signal Demux8, the switch transistor T11, the switch transistor T17 and the switch transistor T23 are turned on, and then the data signal source3 charges the third data signal line 23e, the data signal source4 charges the fourth data signal line 24e, and the data signal source5 charges the fifth data signal line 25e; then the eighth charging stage t9 ends and enters the ninth charging stage t10, the gate of the switch transistor T12, the gate of the switch transistor T18 and the gate of the switch transistor T24 simultaneously receive the low-level shunt control signal Demux9, under the action of the shunt control signal Demux98, the switch transistor T12, the switch transistor T18 and the switch transistor T24 are turned on, and then the data signal source3 charges the third data signal line 23f, the data signal source4 charges the fourth data signal line 24e, and the data signal source5 charges the fifth data signal line 25e. The data signal source5 charges the fifth data signal line 25f; in the scanning stage t11, the third data signal line 23a, the fourth data signal line 24a and the fifth data signal line 25a charge the corresponding sub-pixels in the fourth sub-pixel column PL4 respectively; the third data signal line 23b, the fourth data signal line 24b and the fifth data signal line 25b charge the corresponding sub-pixels in the fifth sub-pixel column PL5 respectively; the third data signal line 23c, the fourth data signal line 24c and the fifth data signal line 25c charge the corresponding sub-pixels in the sixth sub-pixel column PL6 respectively. The corresponding sub-pixels in the sub-pixel column PL6 are charged; the third data signal line 23d, the fourth data signal line 24d and the fifth data signal line 25d are charged for the corresponding sub-pixels in the seventh sub-pixel column PL7; the third data signal line 23e, the fourth data signal line 24e and the fifth data signal line 25e are charged for the corresponding sub-pixels in the eighth sub-pixel column PL8; the third data signal line 23f, the fourth data signal line 24f and the fifth data signal line 25f and the three signal input terminals are charged for the corresponding sub-pixels in the ninth sub-pixel column PL9. Since the luminous color of the ninth sub-pixel column PL9 in each pixel group is the same, which is blue, the present application can ensure that at least some of the sub-pixel columns of the same color are charged in the same way to ensure the uniformity of the display panel. ;

[0085] At the same time, since the third data signal line, the fourth data signal line and the fifth data signal line corresponding to the three adjacent rows of sub-pixels in the sub-pixel column are charged synchronously and the received data signals are different, the present application can synchronously control the three adjacent rows of pixel circuits. For example, for the first row of sub-pixels, the second row of sub-pixels and the third sub-pixel in the fourth sub-pixel column, in the fourth charging stage, the third data signal line 23a corresponding to the first row of sub-pixels in the fourth sub-pixel column PL4 receives the data signal source3, the fourth data signal line 24a corresponding to the second row of sub-pixels in the fourth sub-pixel column PL4 receives the data signal source4, and the fifth data signal line 25a corresponding to the third row of sub-pixels in the fourth sub-pixel column PL4 receives the data signal source5. Therefore, in the scanning stage, the scanning signal scan1, the scanning signal scan2 and the scanning signal scan3 can be controlled to be valid signals of low level, and the data signal source3, the data signal source4 and the data signal source5 are simultaneously written into the first row of sub-pixels, the second row of sub-pixels and the third row of sub-pixels in the fourth sub-pixel column PL4, so as to increase the charging time of the sub-pixels by simultaneously controlling multiple rows of sub-pixels.

[0086] It can be understood that at the same time, the size of the data signal received by the signal input end of the third multiplexing unit, the size of the data signal received by the signal input end of the fourth multiplexing unit, and the size of the data signal received by the signal input end of the fifth multiplexing unit can be different. And in different charging stages, the size of the data signal received by the signal input end of the third multiplexing unit can be different, the size of the data signal received by the signal input end of the fourth multiplexing unit can be different, and the size of the data signal received by the signal input end of the fifth multiplexing unit can be different.

[0087] Based on the same application concept, an embodiment of the present application also provides a display device. Figure 8 A schematic diagram of the structure of a display device 200 provided in an embodiment of the present application is shown in FIG. Figure 8 As shown, the display device 200 includes the display panel 100 in any of the above embodiments. Figure 8 As shown, the display device 200 includes a display panel 100. Therefore, the display device 200 also has the beneficial effects of the display panel 100 in the above embodiment, and the similarities can be understood by referring to the above explanation of the display panel 100, which will not be repeated below.

[0088] The display device 200 provided in the embodiment of the present application can be Figure 8The mobile phone shown can also be any electronic product with a display function, including but not limited to the following categories: televisions, laptops, desktop displays, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, industrial control equipment, medical display screens, touch interactive terminals, etc. The embodiments of the present application do not specifically limit this.

[0089] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0090] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A display panel, characterized in that: include: A plurality of pixel groups, wherein the plurality of pixel groups are arranged along a first direction; wherein each pixel group includes N sub-pixel columns; A plurality of data signal lines; wherein each of the sub-pixel columns is connected to M data signal lines respectively, and at least some of the sub-pixels in the same sub-pixel column are connected to different data signal lines, N≥2, M≥2; A plurality of multiplexing circuits, each of the multiplexing circuits comprises M multiplexing units; the multiplexing unit comprises a signal input terminal, N signal output terminals, and N branch control terminals; in the same multiplexing unit, each branch control terminal is used to receive different branch control signals; wherein the i-th data signal line corresponding to each sub-pixel column in the same pixel group is connected to each signal output terminal of the i-th multiplexing unit in the corresponding multiplexing circuit, and the display panel further comprises a plurality of fan-out lines, the signal input terminal of each multiplexing unit is connected to a different fan-out line, 1≤i≤M.

2. The display panel according to claim 1, characterized in that: The display panel further includes: A plurality of scanning signal lines, each of which is connected to a sub-pixel row; The display panel has a plurality of driving stages, each of which includes: N charging stages and a scanning stage, and the charging stages do not overlap; wherein, in the jth charging stage of the N charging stages, the branch control signal received by the jth branch control terminal in the multiplexing unit is at an effective level, 1≤j≤N, and in the scanning stage, the scanning signals received by the adjacent M rows of sub-pixels are all at an effective level; Optionally, the pixel group includes at least one sub-pixel unit, and the sub-pixel unit includes three sub-pixel columns; Optionally, each of the sub-pixel columns comprises a plurality of light-emitting elements, the light-emitting elements in the same sub-pixel column emit the same light-emitting color, and the light-emitting colors of the sub-pixel columns in the sub-pixel unit are different from each other; Optionally, the luminous colors of the sub-pixel columns corresponding to the last charging stage in each of the driving stages are the same.

3. The display panel according to claim 1, characterized in that: The multiplexing unit also includes N switching transistors, the first pole of each switching transistor is the signal input end, the second pole of each switching transistor is the signal output end, and the gate of each switching transistor is the branch control end.

4. The display panel according to claim 3, characterized in that: The pixel group includes a first sub-pixel column, a second sub-pixel column and a third sub-pixel column; each of the multiplexing circuits includes a first multiplexing unit and a second multiplexing unit respectively; Optionally, the first multiplexing unit and the second multiplexing unit each include three switching transistors.

5. The display panel according to claim 4, characterized in that: The first sub-pixel column, the second sub-pixel column and the third sub-pixel column are respectively connected to two data signal lines, which are the first data signal line and the second data signal line respectively; the sub-pixels in the Ath row of the sub-pixel columns are connected to the first data signal line, and the sub-pixels in the A+1th row are connected to the second data signal line, where A≥1; Among them, the first data signal line corresponding to the first sub-pixel column, the first data signal line corresponding to the second sub-pixel column, and the first data signal line corresponding to the third sub-pixel column are respectively connected to the second electrodes of the three switching transistors of the first multiplexing unit, and the second data signal line corresponding to the first sub-pixel column, the second data signal line corresponding to the second sub-pixel column, and the second data signal line corresponding to the third sub-pixel column are respectively connected to the second electrodes of the three switching transistors of the second multiplexing unit.

6. The display panel according to claim 4, characterized in that: Each of the sub-pixel columns comprises a plurality of light-emitting elements, the light-emitting elements in the same sub-pixel column emit the same light color, and the light-emitting elements in the first sub-pixel column, the second sub-pixel column and the third sub-pixel column emit different light colors; Optionally, the scanning signal received by the sub-pixels in the Ath row in the sub-pixel column is synchronized with the scanning signal received by the sub-pixels in the A+1th row.

7. The display panel according to claim 5, characterized in that: The display panel has multiple driving stages, each of which includes: a first charging stage, a second charging stage, a third charging stage and a scanning stage; wherein the first charging stage, the second charging stage and the third charging stage have no overlap, and the overlapping time of the third charging stage and the scanning stage is less than or equal to a preset time threshold; Optionally, in the first charging stage, the first multiplexing unit is used to transmit a data signal to the first data signal line of the first sub-pixel column, and the second multiplexing unit is used to transmit a data signal to the second data signal line of the first sub-pixel column; in the second charging stage, the first multiplexing unit is used to transmit a data signal to the first data signal line of the second sub-pixel column, and the second multiplexing unit is used to transmit a data signal to the second data signal line of the second sub-pixel column; in the third charging stage, the first multiplexing unit is used to transmit a data signal to the first data signal line of the third sub-pixel column, and the second multiplexing unit is used to transmit a data signal to the second data signal line of the third sub-pixel column.

8. The display panel according to claim 3, characterized in that: Each of the pixel groups includes a fourth sub-pixel column, a fifth sub-pixel column, a sixth sub-pixel column, a seventh sub-pixel column, an eighth sub-pixel column and a ninth sub-pixel column; each of the multiplexing circuits includes a third multiplexing unit, a fourth multiplexing unit and a fifth multiplexing unit respectively; Optionally, the third multiplexing unit, the fourth multiplexing unit and the fifth multiplexing unit each include six switch transistors.

9. The display panel according to claim 8, characterized in that: Each of the sub-pixel columns includes a plurality of light-emitting elements, and the light-emitting elements in the same sub-pixel column have the same light-emitting color. The light-emitting elements included in the fourth sub-pixel column, the fifth sub-pixel column, and the sixth sub-pixel column have different light-emitting colors. The light-emitting elements included in the fourth sub-pixel column and the seventh sub-pixel column have the same light-emitting color. The light-emitting elements included in the fifth sub-pixel column and the eighth sub-pixel column have the same light-emitting color. The light-emitting elements included in the sixth sub-pixel column and the ninth sub-pixel column have the same light-emitting color. Optionally, each of the sub-pixel columns is connected to three data signal lines, which are respectively a third data signal line, a fourth data signal line and a fifth data signal line, the sub-pixels in the Ath row of the sub-pixel column are connected to the third data signal line, the sub-pixels in the A+1th row are connected to the fourth data signal line, and the sub-pixels in the A+2th row are connected to the fourth data signal line, and A≥1; The scanning signals received by the sub-pixels in the Ath row, the scanning signals received by the sub-pixels in the A+1th row, and the scanning signals received by the sub-pixels in the A+2th row in the sub-pixel column are synchronized.

10. A display device, characterized in that: The invention comprises the display panel as claimed in any one of claims 1 to 9.

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