Display device and method of manufacturing same

Abstract

A display device and a method of manufacturing the same are provided. The display device includes: a substrate including a display area and a driving circuit area; a first transistor in the display area and including a first active layer on the substrate and a first gate electrode on the first active layer; a first gate insulating layer between the first active layer and the first gate electrode and entirely covering the first active layer; a second transistor in the driving circuit region and including a second active layer on the substrate and a second gate electrode on the second active layer; a second gate insulating layer between the second active layer and the second gate electrode, covering a portion of the second active layer overlapping the second gate electrode, and exposing other portions of the second active layer; and a first oxide semiconductor layer between the first gate insulating layer and the first gate electrode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0121486 filed in the Korean Intellectual Property Office on September 13, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments relate to a display device and a method of manufacturing the display device. Background Art

[0004] As multimedia technology develops, the importance of display devices has steadily increased. Therefore, various types of display devices such as liquid crystal display devices or light emitting display devices have been developed. Summary of the invention

[0005] Aspects of the present disclosure provide a display device capable of optimizing operation characteristics of a first transistor disposed in a display region and a second transistor disposed in a driving circuit region, and a method of manufacturing the display device.

[0006] However, aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0007] According to aspects of the present disclosure, a display device is provided, which includes: a substrate including a display area and a driving circuit area; a first transistor arranged in the display area and including a first active layer arranged on the substrate and a first gate electrode arranged on the first active layer; a first gate insulating layer arranged between the first active layer and the first gate electrode and entirely covering the first active layer; a second transistor arranged in the driving circuit area and including a second active layer arranged on the substrate and a second gate electrode arranged on the second active layer; a second gate insulating layer arranged between the second active layer and the second gate electrode, covering a portion of the second active layer overlapping with the second gate electrode and exposing other portions of the second active layer; and a first oxide semiconductor layer arranged between the first gate insulating layer and the first gate electrode.

[0008] In an embodiment, the display device may further include a second oxide semiconductor layer disposed between the second gate insulating layer and the second gate electrode.

[0009] In an embodiment, the first oxide semiconductor layer and the second oxide semiconductor layer may include the same oxide semiconductor.

[0010] In an embodiment, the second gate electrode may be disposed directly on the second gate insulating layer.

[0011] In an embodiment, the first gate insulating layer may be entirely disposed in the display area.

[0012] In embodiments, the first gate insulating layer may have a shape and size corresponding to those of the first active layer, and may be an island-shaped insulating pattern layer covering an upper surface and side surfaces of the first active layer.

[0013] In an embodiment, the second gate insulating layer may be an island-shaped insulating pattern layer having a shape and size corresponding to those of the second gate electrode.

[0014] In an embodiment, the first active layer and the second active layer may be disposed at the same layer on the substrate and include the same oxide semiconductor.

[0015] In an embodiment, the first transistor and the second transistor may be N-type oxide transistors, and electron mobility of the second transistor may be higher than electron mobility of the first transistor.

[0016] In an embodiment, the display device may further include an interlayer insulating layer entirely covering the first and second active layers, the first and second gate insulating layers, the first oxide semiconductor layer, and the first and second gate electrodes.

[0017] In an embodiment, the first transistor may further include at least one of a first source electrode and a first drain electrode disposed on the interlayer insulating layer and connected to different portions of the first active layer.

[0018] In an embodiment, the display device may further include a buffer layer arranged between the substrate and the semiconductor layer including the first active layer and the second active layer, and the first transistor may further include a first bottom gate electrode arranged between the substrate and the buffer layer and overlapping the first gate electrode when the first active layer is arranged between the first bottom gate electrode and the first gate electrode.

[0019] In an embodiment, the first bottom gate electrode may be connected to the first source electrode.

[0020] In an embodiment, the second transistor may further include at least one of a second source electrode and a second drain electrode disposed on the interlayer insulating layer and connected to different portions of the second active layer.

[0021] In an embodiment, the display device may further include a buffer layer arranged between the substrate and the semiconductor layer including the first active layer and the second active layer, and the second transistor may further include a second bottom gate electrode arranged between the substrate and the buffer layer and overlapping the second gate electrode when the second active layer is arranged between the second bottom gate electrode and the second gate electrode.

[0022] In embodiments, the second bottom gate electrode may be connected to the second gate electrode.

[0023] In an embodiment, the display device may further include a pixel arranged in the display area and including a first transistor, and a driving circuit arranged in the driving circuit area and including a second transistor.

[0024] According to aspects of the present disclosure, a method for manufacturing a display device is provided, which includes: preparing a substrate including a display area and a driving circuit area, forming a first active layer and a second active layer in the display area and the driving circuit area on the substrate, respectively, sequentially forming a gate insulating layer covering the first active layer and the second active layer and an oxide semiconductor layer covering the gate insulating layer on the substrate, forming a first gate electrode overlapping with a portion of the first active layer and a second gate electrode overlapping with a portion of the second active layer on the oxide semiconductor layer, patterning the gate insulating layer into a first gate insulating layer that entirely covers the first active layer and a second gate insulating layer that partially covers the second active layer by etching the gate insulating layer, and forming an interlayer insulating layer covering the first active layer, the second active layer, the first gate insulating layer, the second gate insulating layer, the first gate electrode, and the second gate electrode in the display area and the driving circuit area.

[0025] In an embodiment, the method may further include: before patterning the gate insulating layer into the first gate insulating layer and the second gate insulating layer, forming a first oxide semiconductor layer having a shape and size corresponding to the shape and size of the first gate electrode under the first gate electrode by etching the oxide semiconductor layer.

[0026] In an embodiment, the method may further include: before forming the first gate electrode and the second gate electrode, forming a first oxide semiconductor layer on a portion of the first active layer by etching the oxide semiconductor layer.

[0027] According to the display device and the method for manufacturing the display device according to the embodiment, the operating characteristics of the first transistor and the second transistor can be differentiated and / or optimized. In an embodiment, the first gate insulating layer that entirely or comprehensively covers the first active layer of the first transistor is arranged on the first active layer, so that the threshold voltage and the driving range of the first transistor can be properly ensured, and the operating characteristics of the first transistor can be stabilized. In an embodiment, the second gate insulating layer that partially covers the second active layer of the second transistor and exposes the other part of the second active layer is arranged on the second active layer, so that the on-current of the second transistor can be increased and the output characteristics of the second transistor can be improved.

[0028] In addition, according to the display device and the method of manufacturing the display device according to the embodiment, the first oxide semiconductor layer may be disposed between the first gate insulating layer and the first gate electrode. Therefore, the operation characteristics of the first transistor may be stably ensured.

[0029] However, the effects according to the embodiment are not limited to the above effects, and various other effects are incorporated herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other aspects and features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0031] Figure 1 is a schematic plan view showing a display device according to an embodiment;

[0032] Figure 2 It is shown Figure 1 A schematic plan view of a display panel;

[0033] Figure 3 is a schematic diagram of an equivalent circuit of a pixel according to an embodiment;

[0034] Figure 4 is a schematic diagram showing a driving circuit of a first driver according to an embodiment;

[0035] Figure 5 is a schematic diagram of an equivalent circuit of a stage of a driving circuit according to an embodiment;

[0036] Figure 6 is a schematic cross-sectional view showing a display panel according to an embodiment;

[0037] Figure 7 is a schematic cross-sectional view showing a display panel according to an embodiment;

[0038] Figure 8 is a schematic cross-sectional view showing a display panel according to an embodiment;

[0039] Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 and Fig.16 is a schematic cross-sectional view illustrating a method of manufacturing a display device according to an embodiment; and

[0040] Fig.17 , Fig.18 and Fig.19 is a schematic cross-sectional view illustrating a method of manufacturing a display device according to an embodiment. DETAILED DESCRIPTION

[0041] In the following description, for the purpose of explanation, many specific details are set forth in order to provide a thorough understanding of various embodiments or implementations of the present invention. As used herein, "embodiment" and "implementation" are interchangeable words, which are non-limiting examples of the device or method disclosed herein. However, it is apparent that various embodiments may be practiced without these specific details or in the case of one or more equivalent arrangements. Here, various embodiments do not have to be exclusive, nor do they limit the present disclosure. For example, the specific shape, configuration, and characteristics of an embodiment may be used or implemented in another embodiment.

[0042] Unless otherwise specified, the illustrated embodiments will be understood to provide features of the present invention. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects of the various embodiments, etc. (hereinafter, individually or collectively referred to as "elements") may be combined, separated, interchanged and / or rearranged in other ways without departing from the scope of the present invention.

[0043] The use of cross hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Thus, unless otherwise specified, the presence or absence of cross hatching or shading does not convey or indicate any preference or requirement for a particular material, material performance, size, ratio, commonality between the elements shown, and / or any other characteristics, attributes, performances, etc. of the elements. In addition, in the drawings, the size and relative size of the elements may be exaggerated for clarity and / or descriptive purposes. When the embodiment can be implemented differently, the specific process sequence can be performed differently from the order described. For example, two processes described in succession can be performed substantially simultaneously or in an order opposite to the order described. Moreover, similar reference numerals represent similar elements.

[0044] When an element or layer is referred to as being "on", "connected to" or "coupled to" another element or layer, it may be directly on, directly connected to or directly coupled to another element or layer, or there may be an intervening element or layer. However, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to" or "directly coupled to" another element or layer, there is no intervening element or layer. For this reason, the term "connection" may refer to a physical, electrical and / or fluid connection with or without an intervening element. In addition, the axis of the first direction D1, the axis of the second direction D2, and the axis of the third direction D3 are not limited to the three axes of a rectangular coordinate system, such as the X-axis, the Y-axis, and the Z-axis, and may be interpreted in a broader sense. For example, the axis of the first direction D1, the axis of the second direction D2, and the axis of the third direction D3 may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purpose of this disclosure, "at least one of A and B" may be understood to mean only A, only B, or any combination of A and B. Furthermore, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as any combination of only X, only Y, only Z, or two or more of X, Y, and Z. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0045] Although the terms "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0046] Spatially relative terms, such as "below," "beneath," "below," "above," "up," "above," "higher," "side" (e.g., as in "sidewall"), etc., may be used herein for descriptive purposes and thereby describe the relationship of one element to another element(s) as shown in the accompanying drawings. In addition to the orientations depicted in the accompanying drawings, spatially relative terms are intended to cover different orientations of the device in use, operation, and / or manufacture. For example, if the device in the accompanying drawings is turned over, an element described as being "below" or "beneath" other elements or features will subsequently be oriented to be "above" the other elements or features. Thus, the term "below" is able to cover both the above and below orientations. In addition, the device may be oriented in other ways (e.g., rotated 90 degrees or at other orientations), and thus, the spatially relative descriptors used herein are interpreted accordingly.

[0047] The terms used herein are for the purpose of describing a particular embodiment, and are not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms "one", "an" and "the" are also intended to include plural forms. In addition, the terms "include", "include", "comprise" and / or "comprise" when used in this specification specify the existence of stated features, integral bodies, steps, operations, elements, parts and / or its groups, but do not exclude the existence or increase of one or more other features, integral bodies, steps, operations, elements, parts and / or its groups. It should also be noted that, as used herein, the terms "substantially", "about" and other similar terms are used as approximate terms and are not used as terms of degree, and thus, are used to explain the inherent deviations in the measured values, calculated values ​​and / or provided values ​​recognized by those of ordinary skill in the art.

[0048] Various embodiments are described herein with reference to cross-sectional illustrations and / or exploded illustrations as schematic illustrations of embodiments and / or intermediate structures. Thus, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, the embodiments disclosed herein should not necessarily be construed as limited to the shapes of the particular illustrations of the regions, but rather are to include deviations in shape due to, for example, manufacturing. In this manner, the regions illustrated in the drawings may be schematic in nature and the shapes of these regions may not reflect the actual shapes of the regions of the device, and thus, are not necessarily intended to be limiting.

[0049] As is customary in the art, some embodiments are described in terms of functional blocks, units and / or modules and are shown in the accompanying drawings. It will be appreciated by those skilled in the art that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, etc.) that can be formed using semiconductor-based preparation techniques or other manufacturing techniques. In the case where blocks, units and / or modules are implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and optionally, can be driven by firmware and / or software. It is also contemplated that each block, unit and / or module can be implemented by dedicated hardware, or implemented as a combination of dedicated hardware that performs some functions and processors (e.g., one or more programmed microprocessors and associated circuits) that perform other functions. Moreover, without departing from the scope of the present invention, each block, unit and / or module of some embodiments can be physically separated into two or more interacting and discrete blocks, units and / or modules. Furthermore, the blocks, units and / or modules of some embodiments may be physically combined into more complex blocks, units and / or modules without departing from the scope of the invention.

[0050] Figure 1is a schematic plan view showing a display device 100 according to an embodiment. Figure 2 It is shown Figure 1 Schematic plan view of the display panel 110.

[0051] Reference Figure 1 and Figure 2 , the display device 100 may be a device for displaying a moving image or a still image. The display device 100 may be used as a display screen of various devices such as a television, a laptop computer, a monitor, a billboard, and an Internet of Things (IOT) device, and portable electronic devices such as a mobile phone, a smart phone, a tablet personal computer (PC), a smart watch, a watch phone, a mobile communication terminal, an electronic notepad, an electronic book, a portable multimedia player (PMP), a navigation device, and an ultra mobile PC (UMPC). These are examples, and the display device 100 may be applied to various other types of electronic devices.

[0052] In an embodiment, the display device 100 may be a light-emitting display device, such as an organic light-emitting display device including an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, or an ultra-small light-emitting display using an ultra-small light-emitting diode such as a micro or nano light-emitting diode (micro-LED or nano-LED), but the embodiment is not limited thereto. For example, the display device 100 may be another type of display device other than the light-emitting display device. Hereinafter, an embodiment in which the display device 100 is an organic light-emitting display device will be disclosed.

[0053] The display device 100 may include a display panel 110 including pixels PX, and a first driver 120 and a second driver 130 for supplying a driving signal to the pixels PX. The display device 100 may further include additional components. For example, the display device 100 may further include a power supply unit for supplying a power supply voltage to the pixels PX, the first driver 120 and the second driver 130, and a timing controller for controlling the operation of the first driver 120 and the second driver 130.

[0054] The display panel 110 may include a display area DA and a non-display area NDA (also referred to as a "frame area"). The display area DA may be an area including pixels PX for displaying an image. The non-display area NDA may be an area other than the display area DA, and an image may not be displayed in the non-display area NDA. In an embodiment, the non-display area NDA may be positioned around the display area DA and may surround the display area DA.

[0055] exist Figure 1 and Figure 2In the embodiment, a first direction D1, a second direction D2 and a third direction D3 are defined. In an embodiment, the first direction D1 and the second direction D2 may be perpendicular to each other, the first direction D1 and the third direction D3 may be perpendicular to each other, and the second direction D2 and the third direction D3 may be perpendicular to each other. For example, the first direction D1 may be a horizontal direction of the display panel 110 (e.g., a row direction or an X-axis direction), and the second direction D2 may be a vertical direction of the display panel 110 (e.g., a column direction or a Y-axis direction). The third direction D3 may be a thickness direction of the display panel 110 (e.g., a height direction or a Z-axis direction).

[0056] In an embodiment, the display panel 110 may have a rectangular shape in a plan view. For example, the display panel 110 may include two first sides extending in a first direction D1 and two second sides extending in a second direction D2 intersecting the first direction D1. Figure 1 and Figure 2 The display panel 110 is shown in which the first side in the horizontal direction is longer than the second side in the vertical direction, but the shape of the display panel 110 is not limited thereto. For example, the display panel 110 may have a shape in which the second side in the vertical direction is longer than the first side in the horizontal direction, or the length of the first side is substantially the same as the length of the second side.

[0057] In an embodiment, the display panel 110 may include an angled corner portion at a portion where the first side intersects the second side, but the embodiment is not limited thereto. For example, the display panel 110 may include a rounded corner portion at a portion where the first side intersects the second side.

[0058] The planar shape of the display panel 110 is not limited to the rectangular shape shown, and it may be applied in other shapes. For example, the display panel 110 may have a square shape, a non-quadrilateral polygonal shape, a circular shape, an elliptical shape, an atypical shape, or other shapes in a plan view.

[0059] In an embodiment, the display panel 110 may be substantially flat on a plane defined by the first direction D1 and the second direction D2, and may have a uniform thickness in the third direction D3. In another embodiment, the display panel 110 may be provided in a three-dimensional shape having a bent surface or the like.

[0060] The display panel 110 may be provided as a panel having a rigid property so as not to be substantially deformed, or as a panel having a flexible property capable of being transformed into at least partially folded, bent, or rolled. The display panel 110 may be provided to the display device 100 without being bent, or may be provided to the display device 100 with being partially bent.

[0061] The display panel 110 may include a substrate SUB and pixels PX arranged on the substrate SUB. The pixels PX may be arranged in a display area DA on the substrate SUB.

[0062] The substrate SUB, which is a base member for manufacturing or providing the display panel 110, may form a base surface of the display panel 110. The substrate SUB may include a display area DA and a non-display area NDA disposed around the display area DA.

[0063] The display area DA may have various shapes according to the embodiment. For example, the display area DA may have a quadrilateral shape, a non-quadrilateral polygonal shape, a circular shape, an elliptical shape, an atypical shape, or other shapes. In the embodiment, the display area DA may have a shape corresponding to the shape of the display panel 110, but the embodiment is not limited thereto.

[0064] The display area DA may include a pixel area in which pixels PX are provided and / or arranged. For example, each pixel PX may be arranged in each pixel area arranged in the display area DA. In an embodiment, the display device 100 may be a light-emitting display device, and each pixel PX may include a light-emitting element arranged in each emission area and a pixel circuit connected to the light-emitting element. In describing an embodiment, the term "connection" may include electrical connection and / or physical connection.

[0065] Each pixel region may include an emission region where a light emitting element of a corresponding pixel is arranged and the pixel emits light, and a pixel circuit region where circuit elements constituting / forming a pixel circuit of the corresponding pixel are arranged. The emission region and the pixel circuit region of each pixel PX may overlap each other, but the embodiment is not limited thereto.

[0066] The pixels PX may be arranged in the display area DA. For example, the pixels PX may be arranged in a stripe structure, a delta structure, The structures or other arrangements are arranged in the display area DA.

[0067] The non-display area NDA may include a driving circuit area disposed on at least one side of the display area DA and a pad area PA where pads PD are disposed. At least one driver, pads PD, and / or wirings may be disposed in the non-display area NDA.

[0068] At least one driver or a portion of the driver for driving the pixel PX may be arranged in the driving circuit region. For example, circuit elements constituting / forming the first driver 120 may be arranged in the driving circuit region on the substrate SUB. In an embodiment, the circuit elements of the first driver 120 may be formed in the display panel 110 together with the pixel PX.

[0069] The pads PD may be arranged in the pad area PA. At least one circuit board 140 may be arranged and / or joined in the pad area PA. For example, the circuit boards 140 connected to different pads PD may be arranged in the pad area PA. The pads PD may include signal pads and power pads for transmitting driving signals and power supply voltages required for driving the pixels PX and / or the first driver 120 to the display panel 110.

[0070] The first driver 120 and the second driver 130 may generate a driving signal for controlling the operation timing, brightness, etc. of the pixel PX, and may supply the generated driving signal to the pixel PX. For example, the first driver 120 may be a gate driver including a scan driver, and may be connected to the pixel PX through a corresponding gate line. The first driver 120 may supply a gate signal (for example, including a Figure 3 The second driver 130 may be a data driver including a source driving circuit and may be connected to the pixel PX through a corresponding data line. The second driver 130 may supply a corresponding data signal to the pixel PX.

[0071] In an embodiment, at least one of the first driver 120 and the second driver 130, or a portion of at least one driver may be embedded in the display panel 110. For example, the first driver 120 or a portion of the first driver 120 may be arranged or formed in the non-display area NDA of the display panel 110.

[0072] although Figure 1 It is shown that the first driver 120 is formed on a side (e.g., an opposite side) of the display area DA (e.g., in a non-display area NDA located on the left and right sides of the display area DA), but the embodiment is not limited thereto. For example, in another embodiment, the first driver 120 may be arranged only on one side of the display area DA. In another embodiment, a portion of the first driver 120 (e.g., some of the circuit elements constituting / forming the first driver 120) is arranged in the non-display area NDA, and other portions of the first driver 120 (e.g., the remaining circuit elements of the circuit elements constituting / forming the first driver 120) may be arranged in a non-emission area (e.g., an area between emission areas of the pixels PX) arranged in the display area DA.

[0073] In an embodiment, other drivers of the first driver 120 and the second driver 130 or a portion of other drivers may be arranged or formed outside the display panel 110 to be electrically connected to the display panel 110. For example, the second driver 130 or a portion of the second driver 130 may be implemented by a plurality of integrated circuit chips and may be arranged on a circuit board 140 electrically connected to the pixels PX of the display panel 110. In an embodiment, the second driver 130 and the timing controller may be integrated into separate integrated circuits, or may be integrated into one integrated chip. The second driver 130 may be implemented as at least one integrated circuit chip and mounted in the non-display area NDA of the display panel 110.

[0074] In an embodiment, the display panel 110 may further include a data distributor (e.g., a demultiplexer) connected between the second driver 130 and the pixels PX of the display area DA and formed inside the display panel 110. For example, circuit elements (e.g., transistors and capacitors) constituting / forming the first driver 120 may be formed in a driving circuit region arranged in the non-display area NDA located on the left and / or right side of the display area DA, and circuit elements (e.g., transistors) constituting / forming the data distributor may be formed in a driving circuit region arranged in the non-display area NDA located on the lower side of the display area DA.

[0075] The circuit board 140 may be connected to the display panel 110 through the pad PD. In an embodiment, the circuit board 140 may be a flexible printed circuit board (FPCB), a rigid printed circuit board (RPCB), or a flexible film such as a chip on film (COF). In an embodiment, the circuit board 140 may be connected to the timing controller and / or the power supply unit through another circuit board, a connector, etc.

[0076] Figure 3 is a schematic diagram of an equivalent circuit of a pixel PX according to an embodiment. Figure 3 The pixel PX of is an example, and the structure or type of the pixel PX may be changed in various ways according to embodiments.

[0077] Apart from Figure 1 and Figure 2 In addition, refer to Figure 3 , the pixel PX may include a light emitting element ED and a pixel circuit PC connected to the light emitting element ED. The light emitting element ED may be a light source of the pixel PX, and it may be, for example, an organic light emitting diode. The pixel circuit PC may control the emission time point and brightness of the light emitting element ED.

[0078] The pixel circuit PC may include a pixel transistor Tpx and at least one pixel capacitor Cpx. For example, the pixel circuit PC may include first to fifth pixel transistors T1 to T5 and first and second pixel capacitors C1 and C2. Figure 3 An embodiment in which all pixel transistors Tpx are N-type transistors is shown, but the type of pixel transistors Tpx is not limited thereto. For example, at least one pixel transistor Tpx may be formed by a P-type transistor. The structure of the pixel circuit PC or the type of circuit elements constituting / forming the pixel circuit PC may be changed in various ways according to the embodiment.

[0079] The pixel circuit PC may supply the driving current Id to the light emitting element ED in response to the driving signals supplied from the first driver 120 and the second driver 130. For example, the pixel circuit PC may supply the driving current Id to the light emitting element ED in response to the corresponding gate signal GS supplied from the first driver 120 through the corresponding gate line GL and the data signal DATA supplied from the second driver 130 through the data line DL.

[0080] The first pixel transistor T1 may be a driving element of the pixel PX in which the magnitude of the source-drain current (e.g., the driving current Id) is determined according to the gate-source voltage. The second pixel transistor T2 to the fifth pixel transistor T5 may be a switching element that is turned on or off according to their own gate-source voltage (essentially, their own gate voltage). According to the type (e.g., P-type or N-type) and / or operating conditions of each of the first pixel transistor T1 to the fifth pixel transistor T5, the first electrode of each of the first pixel transistor T1 to the fifth pixel transistor T5 may be a drain electrode or a source electrode, and the second electrode thereof may be an electrode different from the first electrode. For example, in the case where the first electrode is a drain electrode, the second electrode may be a source electrode.

[0081] The pixel PX may be connected to a first gate line GWL (eg, GWL1, GWL2, GWL3, GWL4, . . . (see FIG. 1 )) transmitting a first gate signal GW (eg, a scan signal). Figure 4)), a second gate line GINL transmitting a second gate signal GIN, a third gate line GRL transmitting a third gate signal GR, an emission control line ECL transmitting an emission control signal EM, and a data line DL transmitting a data signal DATA. In addition, the pixel PX may be connected to a first pixel power line VDL transmitting a first pixel voltage ELVDD (also referred to as a “first pixel power supply voltage”) and a second pixel power line VSL transmitting a second pixel voltage ELVSS (also referred to as a “second pixel power supply voltage”). In an embodiment, the pixel PX may also be connected to an initialization power line VIL transmitting an initialization voltage VINT (also referred to as a “third pixel power supply voltage”) and a reference power line VRL transmitting a reference voltage VREF (also referred to as a “fourth pixel power supply voltage”). In an embodiment, the initialization power line VIL may include a plurality of initialization power lines VIL (e.g., a first initialization power line VIL1 and a second initialization power line VIL2) for transmitting initialization voltages VINT having different sizes (e.g., a first initialization voltage VINT1 and a second initialization voltage VINT2).

[0082] In an embodiment, the first pixel transistor T1 to the fifth pixel transistor T5 may be arranged in corresponding pixel regions (eg, Figure 6 The pixel region PXA of any pixel PX in the display area DA may be an oxide transistor (also referred to as an "oxide semiconductor transistor") including an oxide semiconductor (e.g., an oxide semiconductor material). For example, the active layer (also referred to as a "semiconductor pattern layer" or an "active pattern layer") of each of the first pixel transistor T1 to the fifth pixel transistor T5 may be formed of an oxide semiconductor. However, the embodiment is not limited thereto. For example, at least one pixel transistor Tpx may be formed of a semiconductor material other than an oxide semiconductor (e.g., amorphous silicon or polycrystalline silicon).

[0083] The oxide semiconductor may have high carrier mobility (for example, high electron mobility in the case of an N-type transistor) and low leakage current, so the voltage drop may not be large despite the long driving time of the oxide transistor. For example, since the change in brightness and / or color of an image due to the voltage drop is not significant when it is driven at a low frequency, the pixel PX including the oxide transistor may be driven at a low frequency. In the case of the display device 100 in which the first pixel transistor T1 to the fifth pixel transistor T5 include an oxide semiconductor, the leakage current of the pixel PX may be reduced or prevented, and the power consumption may be reduced.

[0084] In an embodiment, a bottom gate electrode (also referred to as a "relative gate electrode" or a "lower electrode") may be arranged below an active layer constituting / forming at least one pixel transistor Tpx (e.g., at least one of the first pixel transistor T1 to the fifth pixel transistor T5). For example, the bottom gate electrode may be arranged below the active layer of the pixel transistor Tpx including an oxide semiconductor. The bottom gate electrode may be arranged to face the gate electrode (e.g., a top gate electrode) when the active layer of the corresponding pixel transistor Tpx is interposed between the bottom gate electrode and the gate electrode.

[0085] In the described embodiment, the bottom gate electrode provided to at least one pixel transistor Tpx is referred to as a “first bottom gate electrode BG1 .” By providing the first bottom gate electrode BG1 to the pixel transistor Tpx, a change in the current amount of the pixel transistor Tpx due to light can be prevented or reduced, and the operating characteristics of the pixel transistor Tpx can be stabilized.

[0086] The first pixel transistor T1 may include a gate electrode connected to the first node N1 (or gate node), a first electrode (e.g., a drain electrode) connected to the second node N2, and a second electrode (e.g., a source electrode) connected to the third node N3. In an embodiment, the first pixel transistor T1 may further include a first bottom gate electrode BG1 (or a first back gate electrode). For example, the first pixel transistor T1 may further include a first bottom gate electrode BG1 connected to the third node N3. In the case where the first bottom gate electrode BG1 of the first pixel transistor T1 is connected to the third node N3 similarly to the second electrode of the first pixel transistor T1, the operating characteristics of the first pixel transistor T1 may be improved. The first electrode of the first pixel transistor T1 may be connected to the first pixel power line VDL via the fifth pixel transistor T5, and the second electrode thereof may be connected to the light emitting element ED. The first pixel transistor T1 may be used as a driving element of the pixel PX, and may control the size (e.g., current amount) of the driving current Id flowing to the light emitting element ED in response to the data signal DATA transmitted according to the switching operation of the second pixel transistor T2.

[0087] In an embodiment, at least one pixel transistor Tpx of the second pixel transistor T2 to the fifth pixel transistor T5 may further include a bottom gate electrode (e.g., a respective first bottom gate electrode BG1). In an embodiment, the bottom gate electrode of at least one pixel transistor Tpx may be connected to an electrode (e.g., a gate electrode) of a corresponding pixel transistor Tpx.

[0088] The second pixel transistor T2 may include a gate electrode connected to the first gate line GWL, a first electrode connected to the data line DL, and a second electrode connected to the first node N1. The second pixel transistor T2 may be turned on by a first gate signal GW (e.g., a gate-on voltage of the first gate signal GW) transmitted to the first gate line GWL to connect the data line DL with the first node N1. Therefore, the data signal DATA transmitted through the data line DL may be transmitted to the first node N1.

[0089] The third pixel transistor T3 may include a gate electrode connected to the third gate line GRL, a first electrode connected to the reference power line VRL, and a second electrode connected to the first node N1. The third pixel transistor T3 may be turned on by a third gate signal GR transmitted through the third gate line GRL, and transmit a reference voltage VREF transmitted to the reference power line VRL to the first node N1.

[0090] The fourth pixel transistor T4 may include a gate electrode connected to the second gate line GINL, a first electrode connected to the third node N3, and a second electrode connected to the initialization power line VIL. The fourth pixel transistor T4 may be turned on by the second gate signal GIN transmitted through the second gate line GINL, and transmit the initialization voltage VINT transmitted to the initialization power line VIL to the third node N3.

[0091] The fifth pixel transistor T5 may include a gate electrode connected to the emission control line ECL, a first electrode connected to the first pixel power line VDL, and a second electrode connected to the second node N2 (or the first electrode of the first pixel transistor T1). The fifth pixel transistor T5 may be turned on by the emission control signal EM (e.g., the gate-on voltage of the emission control signal EM) transmitted to the emission control line ECL to control the emission time point of the pixel PX.

[0092] The first pixel capacitor C1 may be connected between the first node N1 and the third node N3. For example, the first pixel capacitor C1 may be connected between the second electrode and the gate electrode of the first pixel transistor T1. The first pixel capacitor C1 may be a storage capacitor of the pixel PX, and may store therein a threshold voltage of the first pixel transistor T1 and a voltage corresponding to the data signal DATA (e.g., a data voltage).

[0093] The second pixel capacitor C2 may be connected between the first pixel power line VDL and the third node N3. In an embodiment, the capacitance of the second pixel capacitor C2 may be smaller than the capacitance of the first pixel capacitor C1.

[0094] The light emitting element ED may be connected between the third node N3 and the second pixel power supply line VSL. For example, the light emitting element ED may include a first electrode (e.g., an anode), a second electrode (e.g., a cathode) facing the first electrode, and a light emitting layer arranged between the first electrode and the second electrode. The first electrode of the light emitting element ED may be connected to the third node N3. The second electrode of the light emitting element ED may be connected to the second pixel power supply line VSL. In an embodiment, the second electrode of the light emitting element ED may be a common electrode shared by the pixels PX. During a time period in which the drive current Id is supplied from the pixel circuit PC, the light emitting element ED may emit light with a brightness corresponding to the drive current Id.

[0095] Figure 4 is a diagram showing a driving circuit 121 of a first driver 120 according to an embodiment. Figure 4 A type of driving circuit 121 included in the first driver 120 (or constituting / forming the first driver 120) is shown as an example for illustrating the configuration of the first driver 120. In an embodiment, the driving circuit 121 may be a scanning driving circuit (or scanning driver) that outputs a first gate signal GW to the pixel PX, but the embodiment is not limited thereto. For example, Figure 4 The driving circuit 121 is shown as an example, and the type, structure, number and / or input / output signals of the first driver 120 or the driving circuit 121 constituting / forming the first driver 120 may be changed in various ways according to the embodiment.

[0096] In the following description, the term "previous stage (or previous stage)" may refer to a stage that generates a first gate signal GW whose phase is faster than the first gate signal GW output at a specific stage as a reference. In addition, the term "next stage (or next stage)" may refer to a stage that generates a first gate signal GW whose phase is later than the first gate signal GW output at a specific stage as a reference.

[0097] Apart from Figures 1 to 3 In addition, refer to Figure 4 , the driving circuit 121 may include a stage ST.

[0098] Each of the stages ST may receive a plurality of driving power supply voltages and a plurality of external signals. The stage ST may output a corresponding first gate signal GW based on a plurality of driving power supply voltages (or driving voltages) input thereto and a plurality of external signals. In an embodiment, the driving power supply voltage may include a first driving voltage VON (also referred to as a "control voltage") as a high potential voltage, a second driving voltage VSS1 (also referred to as a "first driving power supply voltage" or a "first low potential driving voltage") as a first low potential voltage, and at least one of a third driving voltage VSS2 (also referred to as a "second driving power supply voltage" or a "second low potential driving voltage") as a second low potential voltage. For example, a plurality of external signals may include at least one of a scan start signal STV, a carry signal input from a previous stage, a reset signal input from a lower stage, and a scan clock signal (e.g., a first scan clock signal SCLK and a second scan clock signal SCLKB), but the embodiment is not limited thereto. In an embodiment, the third driving voltage VSS2 may have a potential lower than that of the second driving voltage VSS1.

[0099] The first gate signal GW (eg, GW1, GW2, GW3, GW4, . . . ) output from each stage ST (eg, Figure 4 The first gate signal GW1 outputted by the first stage ST1 may be supplied to the next stage (e.g., the second stage ST2) as a carry signal. Each stage ST may output the first gate signal GW to the first gate line GWL connected thereto in response to the carry signal (e.g., the first carry signal) inputted from the previous stage. Among the stages ST, the first stage ST1 may receive the scan start signal STV from the outside as a carry signal.

[0100] The first gate signal GW output from each stage ST can be supplied to the previous stage as a reset signal (e.g., a second carry signal). Each stage ST can change the potential of the output node from a high potential voltage to a second low potential voltage (e.g., a third driving voltage VSS2) in response to the reset signal input from the lower stage.

[0101] The stage ST may output the first gate signal GW in response to the scan start signal STV. For example, the stage ST may sequentially output the first gate signal GW to the first gate line GWL in response to the scan start signal STV. For example, the nth (n is a natural number greater than 0) stage (for example, Figure 5 The nth stage STn) may generate the nth first gate signal GW (for example, Figure 5 The n-th scanning signal GWn of the first gate line GW1 is output to the n-th first gate line GWL. The scanning start signal STV for controlling the output timing of the first first gate signal GW1 (eg, the first scanning signal) may be supplied to the first stage ST1.

[0102] Each of the stages ST may include a first input terminal IN1 , a second input terminal IN2 , a third input terminal IN3 , a scan clock input terminal CK, a first power input terminal V1 , a second power input terminal V2 , a carry output terminal CR, and an output terminal OUT.

[0103] Each of the stages ST may receive the first scan clock signal SCLK or the second scan clock signal SCLKB through the scan clock input terminal CK. For example, when the even-numbered stages ST2, ST4, ... receive the second scan clock signal SCLKB, the odd-numbered stages ST1, ST3, ... may receive the first scan clock signal SCLK.

[0104] The first scan clock signal SCLK may be a square wave signal (or a pulse signal) that repeats a logic high level and a logic low level. The logic high level may correspond to a gate-on voltage, and the logic low level may correspond to a gate-off voltage. For example, the logic high level may be a gate high voltage having a voltage value in the range of about 10V to about 30V, and the logic low level may be a gate low voltage having a voltage value in the range of about -16V to about -3V.

[0105] The second scan clock signal SCLKB may be a square wave signal (or pulse signal) that repeats a logic high level and a logic low level. In an embodiment, the second scan clock signal SCLKB may be set to a signal having the same period as the first scan clock signal SCLK but having an opposite phase. However, this is an example, and the waveform relationship between the first scan clock signal SCLK and the second scan clock signal SCLKB is not limited thereto. By way of example, a portion of the logic high level period of the first scan clock signal SCLK may overlap a portion of the logic high level period of the second scan clock signal SCLKB.

[0106] For example, the number of scan clock signals supplied to one stage ST is not limited to the above example. For example, two or more scan clock signals may be applied to each of the stages ST.

[0107] The first input terminal IN1 may receive a scan start signal STV or a carry signal of a previous stage. For example, the scan start signal STV may be applied to the first input terminal IN1 of the first stage ST1, and the carry signal of the previous stage may be applied to the first input terminal IN1 of each of the stages ST2, ST3, ST4, ... except the first stage ST1.

[0108] The second input terminal IN2 may receive a carry signal of a lower stage. For example, the carry signal of the lower stage may be one of the carry signals supplied after a selected time has passed from the output of the carry signal of the current stage.

[0109] The third input terminal IN3 may receive a first drive voltage VON. In an embodiment, the first drive voltage VON may be a high potential voltage to be supplied to a source electrode of at least one transistor included in each of the stages ST. For example, the first drive voltage VON may be a constant voltage similar to / equal to a logic high level (e.g., a gate-on voltage) of the first scan clock signal SCLK. For example, the first drive voltage VON may have a voltage value in a range of about 10V to about 30V.

[0110] In an embodiment, the first driving voltage VON and the first scan clock signal SCLK (or the second scan clock signal SCLKB) may be identical to each other. For example, each of the stages ST may receive the same clock signal through the scan clock input terminal CK and the third input terminal IN3.

[0111] The carry output terminal CR may output a carry signal. The carry signal may be provided to the first input terminal IN1 of the next stage.

[0112] The output terminal OUT may output the first gate signal GW generated at each stage ST. The first gate signal GW may be supplied to the pixel PX through the first gate line GWL corresponding thereto.

[0113] The first power input terminal V1 may be supplied with a second driving voltage VSS1, and the second power input terminal V2 may be supplied with a third driving voltage VSS2. The second driving voltage VSS1 and the third driving voltage VSS2 may be set as gate-off voltages. In an embodiment, the second driving voltage VSS1 and the third driving voltage VSS2 may be the same. In an embodiment, a voltage level of the third driving voltage VSS2 may be lower than a voltage level of the second driving voltage VSS1. For example, the second driving voltage VSS1 may be set in a range of about -14V to about -1V, and the third driving voltage VSS2 may be set in a range of about -16V to about -3V.

[0114] Figure 5 is a schematic diagram of an equivalent circuit of the stage STn of the driving circuit 121 according to the embodiment. Figure 5 An n-th stage STn included in the above-described driving circuit 121 (or constituting / forming the driving circuit 121 ) is shown as an example for showing the configuration of the stage ST of the driving circuit 121 . Figure 5 The nth stage STn is an example, and a structure, input / output signals, and / or operation method of the nth stage STn may be variously changed according to embodiments.

[0115] although Figure 5An embodiment in which the driver transistors Tdr constituting / forming the nth stage STn are N-type transistors is shown, but the type of the driver transistors Tdr is not limited thereto. For example, at least one driver transistor Tdr may be formed of a P-type transistor.

[0116] Apart from Figures 1 to 4 In addition, refer to Figure 5 The nth stage STn may include a first input unit 510, a second input unit 520, a first controller 530, an output unit 540, and a leakage controller 550. In an embodiment, the nth stage STn may further include a second controller 560 and a third controller 570.

[0117] In an embodiment, the driver transistor Tdr included in the nth stage STn may be arranged in a driving circuit area of ​​the display panel 110 (for example, a driving circuit area in which the first driver 120 is arranged in the non-display area NDA of the display panel 110). In an embodiment, the driver transistor Tdr may be an oxide transistor including an oxide semiconductor (for example, an oxide semiconductor material). For example, the active layer of each of the driver transistors Tdr may be formed of an oxide semiconductor. In an embodiment, the driver transistor Tdr and the pixel transistor Tpx may be formed simultaneously of the same oxide semiconductor. For example, the active layers of the driver transistor Tdr and the pixel transistor Tpx may include the same oxide semiconductor and may be arranged on the same layer (for example, a buffer layer BFL (see Figure 6 )). However, the embodiment is not limited thereto. For example, at least one driver transistor Tdr may be formed of a semiconductor material other than an oxide semiconductor (eg, amorphous silicon or polycrystalline silicon).

[0118] Each of the driver transistors Tdr may or may not include a bottom gate electrode (e.g., a bottom gate electrode facing the gate electrode (or overlapping the gate electrode) in the case where the respective active layers are interposed between the bottom gate electrode and the gate electrode). In an embodiment, the driver transistor Tdr may include a corresponding bottom gate electrode arranged below the corresponding active layer. When describing the following embodiments, the bottom gate electrode provided to each of the driver transistors Tdr is referred to as a "second bottom gate electrode BG2". By providing the corresponding second bottom gate electrode BG2 to the driver transistor Tdr, the operating characteristics of the driver transistor Tdr can be improved and / or stabilized.

[0119] In an embodiment, at least one driver transistor Tdr may include a second bottom gate electrode BG2 (or a second back gate electrode) connected to a gate electrode of a corresponding transistor. For example, some driver transistors Tdr (e.g., buffer transistors) including the driver transistor Tdr of the output unit 540 that performs a pull-up or pull-down operation, or all driver transistors Tdr constituting / forming the nth stage STn may be transistors of a dual-gate structure including a corresponding second bottom gate electrode BG2 connected to a corresponding gate electrode. Figure 5 An nth stage STn is shown in which all driver transistors Tdr are formed in a dual gate structure.

[0120] By forming the driver transistor Tdr into a dual-gate structure, the operating characteristics of the driver transistor Tdr can be improved. For example, by forming the driver transistor Tdr into a dual-gate structure in which respective gate electrodes are connected to respective second bottom gate electrodes BG2, the turn-off characteristics and switching speed of the driver transistor Tdr can be improved.

[0121] The first input unit 510 may control the voltage of the first node Nd1 in response to the scan start signal STV supplied to the first input terminal IN1 or the (n-1)th carry signal CRn-1 of the previous stage. The voltage of the first node Nd1 may be a voltage for controlling the output of the nth first gate signal (hereinafter referred to as "nth scan signal GWn") and the nth carry signal CRn. For example, the voltage of the first node Nd1 may be a voltage for controlling the pull-up of the nth carry signal CRn and the nth scan signal GWn.

[0122] In an embodiment, the first input unit 510 may include a second driver transistor (e.g., a 2-1st driver transistor M2-1 and a 2-2nd driver transistor M2-2) connected in series between the first input terminal IN1 and the first node Nd1. Gate electrodes of the second driver transistors M2-1 and M2-2 may be commonly connected to the first input terminal IN1.

[0123] The first input unit 510 may transmit the gate-on voltage (e.g., logic high level) of the (n-1)th carry signal CRn-1 to the first node Nd1. For example, the first input unit 510 may precharge the voltage of the first node Nd1 by using the gate-on voltage of the (n-1)th carry signal CRn-1.

[0124] The common node between the second driver transistors M2-1 and M2-2 may correspond to the third node Nd3. For example, the common node between the second driver transistors M2-1 and M2-2 may be connected to the third node Nd3.

[0125] In the case where the voltage of the first node Nd1 is a high voltage at the level of the gate-on voltage, a leakage current may be generated from the first node Nd1 to the first input unit 510 when the voltage of the common node between the second driver transistors M2-1 and M2-2 is lower than a specific reference value. For example, in the case where the threshold voltage is negatively shifted due to degradation of the second driver transistors M2-1 and M2-2, a leakage current may be generated from the first node Nd1 to the first input unit 510.

[0126] In each oxide transistor, the threshold voltage may shift to a negative value (eg, shift negatively) due to degradation, etc. For example, the oxide transistor may suffer an increase in leakage current in an off state, so that the nth stage STn may operate abnormally.

[0127] In a state where the first node Nd1 is charged with the gate-on voltage, a high voltage at the level of the gate-on voltage may be applied to a common node between the second driver transistors M2-1 and M2-2. For example, the (n-1)th carry signal CRn-1 may have a gate-off voltage, and the gate-off voltage may be supplied to the gate electrodes of the second driver transistors M2-1 and M2-2. Therefore, the gate-source voltage of the 2-2nd driver transistor M2-2 may be maintained at a very low value (e.g., a negative value), and current leakage from the first node Nd1 to the first input unit 510 may be prevented despite the degradation of the second driver transistors M2-1 and M2-2.

[0128] The second input unit 520 may control the voltage of the first node Nd1 in response to a reset signal of a lower stage (e.g., the (n+1)th carry signal CRn+1). In an embodiment, the second input unit 520 may provide the third driving voltage VSS2 to the first node Nd1 in response to the (n+1)th carry signal CRn+1. For example, the second input unit 520 may discharge the voltage of the first node Nd1 having a selected high potential voltage.

[0129] The second input unit 520 may include a third driver transistor (eg, a 3-1st driver transistor M3-1 and a 3-2nd driver transistor M3-2) connected in series between the first node Nd1 and the second power input terminal V2. Gate electrodes of the third driver transistors M3-1 and M3-2 may be commonly connected to the second input terminal IN2.

[0130] A common node between the third driver transistors M3-1 and M3-2 may correspond to a third node Nd3. For example, a common node between the third driver transistors M3-1 and M3-2 may be connected to the third node Nd3.

[0131] The first controller 530 may control the voltage of the output terminal OUT outputting the nth scan signal GWn in response to the (n+1)th carry signal CRn+1. In an embodiment, the first controller 530 may provide the second driving voltage VSS1 to the output terminal OUT in response to the (n+1)th carry signal CRn+1.

[0132] In an embodiment, the first controller 530 may include a fourth driver transistor M4 connected between the output terminal OUT and the first power input terminal V1. The gate electrode of the fourth driver transistor M4 may be connected to the second input terminal IN2. The fourth driver transistor M4 may discharge the voltage of the output terminal OUT to the second driving voltage VSS1.

[0133] The output unit 540 may be connected to a scan clock input terminal CK, a first power input terminal V1, and a second power input terminal V2. The output unit 540 may output the nth scan signal GWn and the nth carry signal CRn corresponding to the first scan clock signal SCLK to the output terminal OUT and the carry output terminal CR, respectively, in response to the voltage of the first node Nd1 and the voltage of the second node Nd2. The voltage of the second node Nd2 may control the gate-off voltage (e.g., logic low level) state of the nth scan signal GWn and the nth carry signal CRn. For example, the voltage of the second node Nd2 may be a voltage for controlling the pull-down of the nth carry signal CRn and the nth scan signal GWn. In an embodiment, the output unit 540 may include a fifth driver transistor M5 to an eighth driver transistor M8 and a driver capacitor C.

[0134] The fifth driver transistor M5 may be connected between the scan clock input terminal CK and the output terminal OUT. The fifth driver transistor M5 may include a gate electrode connected to the first node Nd1. The fifth driver transistor M5 may supply a gate-on voltage to the output terminal OUT in response to the voltage of the first node Nd1. For example, the fifth driver transistor M5 may be used as a pull-up buffer.

[0135] The sixth driver transistor M6 may be connected between the output terminal OUT and the first power input terminal V1. The sixth driver transistor M6 may include a gate electrode connected to the second node Nd2. The sixth driver transistor M6 may supply a gate-off voltage to the output terminal OUT in response to the voltage of the second node Nd2. For example, the sixth driver transistor M6 may maintain the voltage of the output terminal OUT at a gate-off voltage level (or a logic low level).

[0136] The seventh driver transistor M7 may be connected between the scan clock input terminal CK and the carry output terminal CR. The seventh driver transistor M7 may include a gate electrode connected to the first node Nd1. The seventh driver transistor M7 may supply a gate-on voltage to the carry output terminal CR in response to the voltage of the first node Nd1. For example, the seventh driver transistor M7 may be used as a pull-up buffer.

[0137] The eighth driver transistor M8 may be connected between the carry output terminal CR and the second power supply input terminal V2. The eighth driver transistor M8 may include a gate electrode connected to the second node Nd2. The eighth driver transistor M8 may supply a gate-off voltage to the carry output terminal CR in response to the voltage of the second node Nd2. For example, the eighth driver transistor M8 may maintain the voltage of the carry output terminal CR at a gate-off voltage level (e.g., a logic low level).

[0138] The driver capacitor C may be connected between the first node Nd1 and the output terminal OUT. The driver capacitor C may be used as a boost capacitor. For example, when the fifth driver transistor M5 is turned on, the driver capacitor C may increase (or bootstrap) the voltage of the first node Nd1 in response to the voltage rise of the output terminal OUT. Therefore, the fifth driver transistor M5 may stably maintain the on state for a selected period of time.

[0139] The second controller 560 may maintain the voltage of the first node Nd1 as a gate-off voltage in response to the voltage of the second node Nd2. In an embodiment, the second controller 560 may provide a third driving voltage VSS2 (eg, a gate-off voltage) to the first node Nd1 in response to the voltage of the second node Nd2.

[0140] In an embodiment, the second controller 560 may include a ninth driver transistor (e.g., a 9-1st driver transistor M9-1 and a 9-2nd driver transistor M9-2) connected in series between the first node Nd1 and the second power input terminal V2. Gate electrodes of the ninth driver transistors M9-1 and M9-2 may be commonly connected to the second node Nd2.

[0141] A common node between the ninth driver transistors M9-1 and M9-2 may correspond to the third node Nd3. For example, the common node between the ninth driver transistors M9-1 and M9-2 may be electrically connected to the third node Nd3.

[0142] Despite Figure 5, two second driver transistors M2-1 and M2-2, two third driver transistors M3-1 and M3-2, and two ninth driver transistors M9-1 and M9-2 are shown, but the number of driver transistors Tdr connected in series is not limited thereto. For example, in the case where three or more third driver transistors are connected in series, at least one common node between the third driver transistors may be electrically connected to a third node Nd3.

[0143] The third controller 570 may control the voltage of the second node Nd2 in response to the first scan clock signal SCLK and the n-th carry signal CRn. In an embodiment, the third controller 570 may transmit the first scan clock signal SCLK to the second node Nd2 in response to the first scan clock signal SCLK, and supply a gate-off voltage to the second node Nd2 in response to the n-th carry signal CRn.

[0144] The voltage of the second node Nd2 may control the gate-off voltage (e.g., logic low level) state of the nth scan signal GWn and the nth carry signal CRn. For example, the voltage of the second node Nd2 may be a voltage for controlling the pull-down of the nth carry signal CRn and the nth scan signal GWn.

[0145] The third controller 570 may include tenth to thirteenth driver transistors M10 to M13 .

[0146] The tenth driver transistor M10 may be connected between the scan clock input terminal CK and the second node Nd2. The gate electrode of the tenth driver transistor M10 may be connected to a common node of the twelfth driver transistor M12 and the thirteenth driver transistor M13. The tenth driver transistor M10 may supply the first scan clock signal SCLK to the second node Nd2 in response to the first scan clock signal SCLK.

[0147] The eleventh driver transistor M11 may be connected between the second node Nd2 and the second power input terminal V2.

[0148] The twelfth driver transistor M12 and the thirteenth driver transistor M13 may be connected in series between the scan clock input terminal CK and the first power supply input terminal V1. The gate electrode of the twelfth driver transistor M12 may be connected to the scan clock input terminal CK. The gate electrodes of the eleventh driver transistor M11 and the thirteenth driver transistor M13 may be commonly connected to the carry output terminal CR.

[0149] In the case of outputting the n-th carry signal CRn (for example, in the case of the n-th carry signal CRn having the gate-on voltage), the thirteenth driver transistor M13 may be turned on to turn off the tenth driver transistor M10, and the eleventh driver transistor M11 may be turned on to supply the third driving voltage VSS2 to the second node Nd2. Therefore, in the case of outputting the n-th carry signal CRn, the second node Nd2 may have the gate-off voltage.

[0150] In an embodiment, the voltage level of the third driving voltage VSS2 may be lower than the voltage level of the second driving voltage VSS1. For example, the third driving voltage VSS2 having a voltage level lower than the voltage level of the second driving voltage VSS1 may be provided to the second node Nd2 by the operation of the eleventh driver transistor M11. This may be performed to prevent the sixth driver transistor M6 and / or the eighth driver transistor M8 from being unexpectedly operated due to the ripple of the voltage of the second node Nd2 when the voltage of the second node Nd2 changes from the gate-on voltage to the gate-off voltage. Therefore, the electrode of the eleventh driver transistor M11 may be applied with the third driving voltage VSS2 having a voltage level lower than the voltage level of the second driving voltage VSS1.

[0151] The leakage controller 550 may supply the first driving voltage VON supplied to the third input terminal IN3 to the first input unit 510, the second input unit 520, and the second controller 560 in response to one of the nth scan signal GWn and the nth carry signal CRn. In an embodiment, the leakage controller 550 may include a first driver transistor M1 connected between the third input terminal IN3 and the third node Nd3. The first driver transistor M1 may include a gate electrode receiving the nth scan signal GWn.

[0152] The first driver transistor M1 may supply the first driving voltage VON to the common node of the driver transistors Tdr respectively connected in series to the first node Nd1 in response to the nth scanning signal GWn. Therefore, in the case where the first node Nd1 is charged (for example, in the case where the voltage of the first node Nd1 is boosted), the high potential first driving voltage VON may be applied to the electrode of the second driver transistor (for example, the 2-2nd driver transistor M2-2), the electrode of the third driver transistor (for example, the 3-1st driver transistor M3-1), and the electrode of the ninth driver transistor (for example, the 9-1st driver transistor M9-1). In the case where the first node Nd1 is charged, the third node Nd3 may be charged with a high potential voltage by the first driving voltage VON. Therefore, in the case where the voltage of the first node Nd1 is boosted, the gate-source voltage of each of the 2-2nd driver transistor M2-2, the 3-1st driver transistor M3-1, and the 9-1st driver transistor M9-1 may have a negative value, and the gate-source voltage of each of the 2-2nd driver transistor M2-2, the 3-1st driver transistor M3-1, and the 9-1st driver transistor M9-1 may be maintained at a value much lower than the threshold voltage. Therefore, leakage current from the first node Nd1 through the 2-2nd driver transistor M2-2, the 3-1st driver transistor M3-1, and the 9-1st driver transistor M9-1 may be prevented or reduced.

[0153] Figure 6 is a schematic cross-sectional view showing a display panel 110 according to an embodiment. For example, Figure 6 A portion of the display area DA and a portion of the non-display area NDA of the display panel 110 are shown.

[0154] Figure 7 is a schematic cross-sectional view showing a display panel 110 according to an embodiment. For example, Figure 7 A portion of the display area DA and a portion of the non-display area NDA of the display panel 110 are shown, and Figure 6 The embodiments are different from those of the first gate insulating layer GI1.

[0155] exist Figure 6 and Figure 7 , as examples of circuit elements that may be provided or arranged in the panel circuit layer PCL of the display panel 110 , any one pixel transistor Tpx (also referred to as “first transistor TFT1 ”) and any one driver transistor Tdr (also referred to as “second transistor TFT2 ”) are shown.

[0156] For example, Figure 6 and Figure 7A light-emitting display panel including a light-emitting element ED (e.g., an organic light-emitting diode) is shown as an example of a display panel 110 to which the embodiment can be applied. However, the embodiment is not limited thereto. For example, the display panel 110 may include a light-emitting element of another type and / or structure, or may be a display panel of another type and / or structure other than a light-emitting display panel.

[0157] Apart from Figures 1 to 5 In addition, refer to Figure 6 and Figure 7 , the display panel 110 may include a substrate SUB (also referred to as a "base member" or "base layer"), a panel circuit layer PCL, a light emitting element layer LEL, and an encapsulation layer ENL. The panel circuit layer PCL, the light emitting element layer LEL, and the encapsulation layer ENL may be arranged or provided to overlap each other on the substrate SUB. For example, with respect to the display area DA, the panel circuit layer PCL, the light emitting element layer LEL, and the encapsulation layer ENL may be sequentially arranged or formed on the substrate SUB along a third direction D3. However, the embodiment is not limited thereto, and the positions of the panel circuit layer PCL, the light emitting element layer LEL, and / or the encapsulation layer ENL may be changed.

[0158] In an embodiment, the display panel 110 may further include additional elements provided above and / or below the encapsulation layer ENL. For example, the display panel 110 may further include at least one of a sensor layer (e.g., a touch sensor layer), an optical layer (e.g., a color filter layer and / or a wavelength conversion layer), and a passivation layer (e.g., a passivation film, an insulating layer, an upper substrate, and / or a window). Each of the sensor layer, the optical layer, and the passivation layer may be provided above the encapsulation layer ENL, or may be provided between the light emitting element layer LEL and the encapsulation layer ENL.

[0159] The substrate SUB as a base member for forming the display panel 110 may be a substrate (or film) having rigid or flexible properties. In an embodiment, the substrate SUB may be a substrate including an insulating material such as glass and having rigid properties, and may not be bent. In another embodiment, the substrate SUB may be a flexible substrate including polyimide or other insulating materials and deformable to be bent, folded, or curled, and may be bent or may not be bent. The type and / or material of the substrate SUB may vary according to the embodiment.

[0160] The substrate SUB may include a display area DA and a non-display area NDA. In an embodiment, the display area DA may include a pixel area PXA corresponding to the pixel PX, and the non-display area NDA may include a driving circuit area DRA. For example, the pixel area PXA where the pixel PX is arranged may be defined in the display area DA, and the driving circuit area DRA where the first driver 120 and / or the data distributor is arranged may be defined in the non-display area NDA.

[0161] In an embodiment, a barrier layer BRL may be provided on the substrate SUB. For example, the display panel 110 may further include a barrier layer BRL disposed between the substrate SUB and the panel circuit layer PCL. In another embodiment, the display panel 110 may not include the barrier layer BRL. For example, the panel circuit layer PCL may be directly disposed on the substrate SUB.

[0162] The blocking layer BRL may include at least one inorganic insulating layer including an inorganic insulating material (e.g., silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide, or other inorganic insulating materials). The blocking layer BRL may protect the pixel PX from moisture penetrating through the substrate SUB susceptible to moisture penetration. The material of the blocking layer BRL may be variously changed according to the embodiment.

[0163] The panel circuit layer PCL may be arranged on the surface of the substrate SUB provided with the barrier layer BRL. The panel circuit layer PCL may include circuit elements including pixel transistors Tpx and driver transistors Tdr and wiring (e.g., signal lines and power lines). In an embodiment, the panel circuit layer PCL may further include an additional conductive pattern layer (e.g., a bridge pattern layer).

[0164] The panel circuit layer PCL may further include an insulating layer arranged on the substrate SUB. For example, the panel circuit layer PCL may include a buffer layer BFL (also referred to as a "first insulating layer"), a gate insulating layer GI (also referred to as a "second insulating layer"), an interlayer insulating layer ILD (also referred to as a "third insulating layer"), and a passivation layer PSV (also referred to as a "fourth insulating layer") sequentially arranged on the substrate SUB along a third direction D3. In an embodiment, the buffer layer BFL, the interlayer insulating layer ILD, and the passivation layer PSV may be entirely (or comprehensively) arranged in the display area DA and the driving circuit area DRA.

[0165] In an embodiment, the gate insulating layer GI may be arranged entirely (or completely) or partially in the display area DA, and may be arranged partially in the driving circuit area DRA. For example, the gate insulating layer GI may include: Figure 6 The first gate insulating layer GI1 is entirely (or fully) arranged in the display area DA as shown in FIG. Figure 7 The first gate insulating layer GI1 partially arranged in the display area DA as shown in FIG. 1 (eg, the first gate insulating layer GI1 individually patterned to correspond to the corresponding pixel transistor Tpx). Figure 6 and Figure 7 As shown in , the gate insulating layer GI may include a second gate insulating layer GI2 partially arranged in the driving circuit area DRA (eg, the second gate insulating layer GI2 individually patterned to correspond to the corresponding driver transistors Tdr).

[0166] In embodiments, the passivation layer PSV may have a multilayer structure including an inorganic layer (eg, an inorganic insulating layer) and an organic layer (eg, an organic insulating layer). For example, the passivation layer PSV may include an inorganic layer IOL and an organic layer ORL sequentially disposed on the interlayer insulating layer ILD.

[0167] In an embodiment, the display panel 110 may further include an additional conductive layer and / or an additional passivation layer. For example, the display panel 110 may further include a fourth conductive layer provided on the passivation layer PSV and an insulating layer covering the fourth conductive layer. In an embodiment in which the display panel 110 further includes a fourth conductive layer, at least one wiring and / or bridge pattern layer (for example, a bridge pattern layer connected between the first source electrode SE1 of the first transistor TFT1 and the first electrode ET1 of the light emitting element ED) or the like may be provided in the fourth conductive layer.

[0168] In an embodiment, each of the buffer layer BFL, the gate insulating layer GI, the interlayer insulating layer ILD and the inorganic layer IOL may include at least one inorganic insulating layer including an inorganic insulating material (e.g., silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide, or other inorganic insulating materials).

[0169] The organic layer ORL may include at least one organic insulating layer including an organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin or other organic insulating materials. A surface such as a top surface or upper surface of the organic layer ORL may be substantially flat.

[0170] The pixel transistor Tpx may be included in the pixel circuit PC of each pixel PX and may be located in the display area DA. For example, each pixel transistor Tpx may be arranged in a pixel area PXA in which a corresponding pixel PX is arranged or formed. Figure 6 , representing pixel transistors Tpx, any one pixel transistor Tpx (eg, a first pixel transistor T1 connected to a light emitting element ED of a corresponding pixel PX) is shown, and this will be referred to as a "first transistor TFT1"

[0171] The driver transistor Tdr may be included in the driving circuit 121 and / or the data distributor of the first driver 120, and may be arranged in the driving circuit area DRA. In an embodiment, the driving circuit area DRA may be arranged in the non-display area NDA. Figure 6 , representing the driver transistor Tdr, any one of the driver transistors Tdr (for example, any one of the fifth to eighth driver transistors M5 to M8 included in the output unit 540 of the nth stage STn) is shown, and this will be referred to as “second transistor TFT2”).

[0172] The first transistor TFT1 may include a first active layer ACT1 (also referred to as a "first active pattern layer") and a first gate electrode GE1. In an embodiment, the first transistor TFT1 may further include a first bottom gate electrode BG1. A buffer layer BFL may be arranged between the first bottom gate electrode BG1 and the first active layer ACT1. A first gate insulating layer GI1 may be arranged between the first active layer ACT1 and the first gate electrode GE1. In an embodiment, all pixel transistors Tpx arranged in the display area DA or the pixel transistors Tpx including Figure 3 Active layers (eg, first active layers ACT1 ) of some of the pixel transistors Tpx of the first pixel transistor T1 may be entirely (or comprehensively) covered by the first gate insulating layer GI1 .

[0173] In an embodiment, all pixel transistors Tpx arranged in the display area DA or the pixel transistors Tpx including Figure 3 The first oxide semiconductor layer OS1 may be disposed on the active layer of some pixel transistors Tpx of the first pixel transistor T1 (for example, the corresponding first active layer ACT1 of the pixel transistor Tpx). For example, the first oxide semiconductor layer OS1 may be disposed between the first active layer ACT1 and the first gate electrode GE1, and the first oxide semiconductor layer OS1 may be disposed on the first gate insulating layer GI1.

[0174] In an embodiment, the first transistor TFT1 may further include a first source electrode SE1 and a first drain electrode DE1 connected to different portions of the first active layer ACT1. In another embodiment, the first transistor TFT1 may not include a separate source electrode and / or a separate drain electrode, and the first source region SR1 and / or the first drain region DR1 of the first active layer ACT1 may be connected to other circuit elements, wirings and / or conductive pattern layers to serve as the source electrode and / or drain electrode of the first transistor TFT1.

[0175] The first bottom gate electrode BG1 may be provided or included in the first conductive layer CDL1 on the substrate SUB. In an embodiment, the first conductive layer CDL1 may be disposed between the substrate SUB and the buffer layer BFL. For example, the first conductive layer CDL1 may be disposed on the barrier layer BRL and may be covered by the buffer layer BFL.

[0176] The first bottom gate electrode BG1 may overlap the first active layer ACT1. For example, the first bottom gate electrode BG1 may be arranged under the first active layer ACT1 to overlap at least the first channel region CH1. The first bottom gate electrode BG1 and the first active layer ACT1 may be spaced apart from each other with the buffer layer BFL interposed between the first bottom gate electrode BG1 and the first active layer ACT1. The first bottom gate electrode BG1 may face the first gate electrode GE1 with the first active layer ACT1 interposed between the first bottom gate electrode BG1 and the first gate electrode GE1. In an embodiment, when the first transistor TFT1 is Figure 3 In the case of the first pixel transistor T1 , the first bottom gate electrode BG1 of the first transistor TFT1 may be connected to the first source electrode SE1 and may function as a back gate electrode for adjusting characteristics of the first pixel transistor T1 .

[0177] The first active layer ACT1 may be provided or included in the first semiconductor layer SCL1 on the substrate SUB. In embodiments, the first semiconductor layer SCL1 may be disposed on the buffer layer BFL and may be covered by the gate insulating layer GI and the interlayer insulating layer ILD.

[0178] The first active layer ACT1 may include a first channel region CH1 and a first source region SR1 and a first drain region DR1 spaced apart from each other, wherein the first channel region CH1 is interposed between the first source region SR1 and the first drain region DR1. For example, the first source region SR1 and the first drain region DR1 may be arranged at sides (e.g., opposite sides) of the first channel region CH1. The first channel region CH1 may be a region that maintains semiconductor characteristics without becoming conductive. The first source region SR1 and the first drain region DR1, which are regions that have become conductive, may have a carrier concentration (e.g., electron concentration) higher than that of the first channel region CH1.

[0179] The first active layer ACT1 may overlap the first bottom gate electrode BG1 and the first gate electrode GE1. For example, a portion of the first active layer ACT1 including the first channel region CH1 may overlap the first bottom gate electrode BG1 and the first gate electrode GE1.

[0180] In an embodiment, the first active layer ACT1 may include an oxide semiconductor. For example, the first active layer ACT1 may include at least one of zinc oxide (ZnO), zinc tin oxide (ZTO), indium zinc oxide (IZO), indium oxide (InO), titanium oxide (TiO), indium gallium oxide (IGO), indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium zinc tin oxide (IZTO), and indium tin gallium zinc oxide (ITGZO), or other oxide semiconductors. In an embodiment, the first active layer ACT1 may be made of a high-mobility oxide semiconductor (e.g., having a conductivity of about 30 cm 2 / Vs or more of an oxide semiconductor material). For example, the first active layer ACT1 may be formed of indium tin gallium zinc oxide (ITGZO) and may have a thickness of about 30 cm 2 / Vs or greater mobility.

[0181] A first gate insulating layer GI1 (also referred to as a 'first gate insulating pattern layer') may be disposed on the first active layer ACT1. The first gate insulating layer GI1 may be disposed between the first active layer ACT1 and the first gate electrode GE1.

[0182] The first gate insulating layer GI1 may entirely (or comprehensively) cover the first active layer ACT1. For example, the first gate insulating layer GI1 may entirely (or comprehensively) cover the first active layer ACT1 except for a portion where at least one contact hole for connection with the first source electrode SE1 and / or the first drain electrode DE1 is formed.

[0183] In an embodiment, Figure 6 As shown in , the first gate insulating layer GI1 may be entirely (or fully) arranged in the display area DA. Figure 7 As shown in , the first gate insulating layer GI1 may be separately formed to correspond to a transistor region where at least one first transistor TFT1 is formed, and thus may be partially arranged in the display area DA. Figure 7 As shown in , the first gate insulating layer GI1 may have a shape and size corresponding to those of the first active layer ACT1, and may be an island-shaped insulating pattern layer covering the top and side surfaces (or upper and side surfaces) of the first active layer ACT1.

[0184] The first oxide semiconductor layer OS1 (also referred to as a "first oxide semiconductor pattern layer") may be disposed on the first gate insulating layer GI1. The first oxide semiconductor layer OS1 may be provided or included in the second semiconductor layer SCL2 on the substrate SUB. The first oxide semiconductor layer OS1 may be disposed between the first gate insulating layer GI1 and the first gate electrode GE1. For example, the first oxide semiconductor layer OS1 may be partially disposed under the first gate electrode GE1.

[0185] The first oxide semiconductor layer OS1 may include an oxide semiconductor (e.g., at least one of oxide semiconductors such as the material of the first active layer ACT1 or other oxide semiconductors), and may be disposed on the first channel region CH1 of the first active layer ACT1. Since the first oxide semiconductor layer OS1 is disposed on the first active layer ACT1, oxygen may be supplied to the first active layer ACT1 in the manufacturing process of the display panel 110. Therefore, although the first active layer ACT1 is formed of a high-mobility oxide semiconductor, the mobility (e.g., electron mobility) and / or carrier concentration of the first active layer ACT1 may be appropriately and / or easily adjusted, and the operating characteristics of the first transistor TFT1 (e.g., operating characteristics suitable for a driving element and / or a switching element of the pixel PX) may be appropriately and / or stably ensured.

[0186] In an embodiment, the first gate electrode GE1 and the first oxide semiconductor layer OS1 may be simultaneously or sequentially formed (e.g., patterned) using one mask, or the first oxide semiconductor layer OS1 may be formed using the first gate electrode GE1 as a mask. Therefore, the first oxide semiconductor layer OS1 may have a shape and size corresponding to those of the first gate electrode GE1. For example, the first oxide semiconductor layer OS1 may be disposed on a portion of the first active layer ACT1 (e.g., the first channel region CH1 located under the first gate electrode GE1), and other portions of the first active layer ACT1 (e.g., the first source region SR1 and the first drain region DR1) may be exposed.

[0187] The first gate electrode GE1 may be disposed on the first oxide semiconductor layer OS1. The first gate electrode GE1 may be provided or included in the second conductive layer CDL2 on the substrate SUB. In an embodiment, the second conductive layer CDL2 may be disposed on the first semiconductor layer SCL1 including the first active layer ACT1, the gate insulating layer GI including the first gate insulating layer GI1, and the second semiconductor layer SCL2 including the first oxide semiconductor layer OS1. The second conductive layer CDL2 may be covered by the interlayer insulating layer ILD.

[0188] The first gate electrode GE1 may be disposed on the first active layer ACT1 to overlap the first channel region CH1. The first gate electrode GE1 and the first active layer ACT1 may be separated and / or spaced apart from each other with the first gate insulating layer GI1 and the first oxide semiconductor layer OS1 interposed therebetween.

[0189] The first source electrode SE1 and the first drain electrode DE1 may be provided or included in a third conductive layer CDL3 on the substrate SUB. In an embodiment, the third conductive layer CDL3 may be arranged on an interlayer insulating layer ILD that entirely (or comprehensively) covers the buffer layer BFL, the first semiconductor layer SCL1, the gate insulating layer GI, the second semiconductor layer SCL2, and the second conductive layer CDL2. The third conductive layer CDL3 may be covered by a passivation layer PSV.

[0190] The first source electrode SE1 may be connected to a portion of the first active layer ACT1. For example, the first source electrode SE1 may be connected to the first source region SR1 through at least one contact hole penetrating the first gate insulating layer GI1 and the interlayer insulating layer ILD. Figure 3 In the case of the first pixel transistor T1, the first source electrode SE1 may be further connected to the first bottom gate electrode BG1. For example, the first source electrode SE1 may be connected to the first bottom gate electrode BG1 through at least one contact hole penetrating the buffer layer BFL, the first gate insulating layer GI1, and the interlayer insulating layer ILD.

[0191] The first drain electrode DE1 may be connected to another portion of the first active layer ACT1. For example, the first drain electrode DE1 may be connected to the first drain region DR1 through at least one contact hole penetrating the first gate insulating layer GI1 and the interlayer insulating layer ILD.

[0192] The second transistor TFT2 may include a second active layer ACT2 (also referred to as a "second active pattern layer") and a second gate electrode GE2. In an embodiment, the second transistor TFT2 may further include a second bottom gate electrode BG2. The buffer layer BFL may be arranged between the second bottom gate electrode BG2 and the second active layer ACT2. The second gate insulating layer GI2 may be arranged between the second active layer ACT2 and the second gate electrode GE2. In an embodiment, the second gate insulating layer GI2 overlapping the second gate electrode GE2 may be partially arranged on all driver transistors Tdr arranged in the driving circuit area DRA or include Figure 5 On the active layer of some driver transistors Tdr (eg, the corresponding second active layer ACT2 of the driver transistor Tdr) of at least one of the fifth to eighth driver transistors M5 to M8, and other portions of the active layer may not be covered by the second gate insulating layer GI2.

[0193] In an embodiment, the second oxide semiconductor layer OS2 may be formed on the active layer (e.g., the second active layer ACT2) of some or all of the driver transistors Tdr arranged in the driving circuit region DRA. For example, the second oxide semiconductor layer OS2 may be arranged between the second active layer ACT2 and the second gate electrode GE2, and the second oxide semiconductor layer OS2 may be arranged on the second gate insulating layer GI2.

[0194] In an embodiment, the second transistor TFT2 may further include a second source electrode SE2 and a second drain electrode DE2 connected to different portions of the second active layer ACT2. In another embodiment, the second transistor TFT2 may not include a separate source electrode and / or a separate drain electrode, and the second source region SR2 and / or the second drain region DR2 of the second active layer ACT2 may be connected to other circuit elements, wirings and / or conductive pattern layers to serve as the source electrode and / or drain electrode of the second transistor TFT2.

[0195] The second bottom gate electrode BG2 may be provided or included in the first conductive layer CDL1 on the substrate SUB. For example, the second bottom gate electrode BG2 may be provided or included in the first conductive layer CDL1 together with the first bottom gate electrode BG1.

[0196] The second bottom gate electrode BG2 may overlap with the second active layer ACT2. For example, the second bottom gate electrode BG2 may be arranged below the second active layer ACT2 to overlap with at least the second channel region CH2. The second bottom gate electrode BG2 and the second active layer ACT2 may be spaced apart from each other with a buffer layer BFL interposed between the second bottom gate electrode BG2 and the second active layer ACT2. The second bottom gate electrode BG2 may face the second gate electrode GE2 with the second active layer ACT2 interposed between the second bottom gate electrode BG2 and the second gate electrode GE2. In an embodiment, the second bottom gate electrode BG2 may be connected to the second gate electrode GE2 and may be used as a back gate electrode for adjusting characteristics of the second transistor TFT2.

[0197] The second active layer ACT2 may be provided or included in the first semiconductor layer SCL1 on the substrate SUB. In embodiments, the first active layer ACT1 and the second active layer ACT2 may be provided and / or arranged on the same layer (eg, buffer layer BFL) on the substrate SUB.

[0198] The second active layer ACT2 may include a second channel region CH2 and a second source region SR2 and a second drain region DR2 spaced apart from each other, wherein the second channel region CH2 is interposed between the second source region SR2 and the second drain region DR2. For example, the second source region SR2 and the second drain region DR2 may be arranged at a side (e.g., an opposite side) of the second channel region CH2. The second channel region CH2 may be a region that maintains semiconductor characteristics without becoming conductive. The second source region SR2 and the second drain region DR2, which are regions that have become conductive, may have a carrier concentration (e.g., an electron concentration) higher than that of the second channel region CH2.

[0199] The second active layer ACT2 may overlap the second bottom gate electrode BG2 and the second gate electrode GE2. For example, a portion of the second active layer ACT2 including the second channel region CH2 may overlap the second bottom gate electrode BG2 and the second gate electrode GE2.

[0200] In an embodiment, the second active layer ACT2 may include an oxide semiconductor. For example, the second active layer ACT2 may include the above oxide semiconductor or other oxide semiconductors as the material of the first active layer ACT1. In an embodiment, the second active layer ACT2 may be formed of a high-mobility oxide semiconductor.

[0201] In an embodiment, the first active layer ACT1 and the second active layer ACT2 may include the same oxide semiconductor. For example, the first active layer ACT1 and the second active layer ACT2 may be simultaneously formed on the buffer layer BFL using the same high-mobility oxide semiconductor. Therefore, the manufacturing process of the display panel 110 may be simplified and / or rationalized, and the manufacturing efficiency may be improved.

[0202] In the case where the first active layer ACT1 and the second active layer ACT2 are formed of a high-mobility oxide semiconductor, the conductivity of the first source region SR1, the first drain region DR1, the second source region SR2, and the second drain region DR2 may be appropriately ensured without performing an additional doping process, etc. Therefore, the manufacturing process of the display device 100 may be further simplified and / or rationalized, and the manufacturing efficiency may be improved.

[0203] In addition, in the case where the first active layer ACT1 and the second active layer ACT2 are formed of a high-mobility oxide semiconductor, it is possible to form a first transistor TFT1 and a second transistor TFT2 having a fine size (for example, including the size of an active layer having a width and / or a length in the range of about several micrometers to tens of micrometers) and also to appropriately ensure the mobility of the first transistor TFT1 and the second transistor TFT2. Therefore, even in a high-resolution display device 100, it is possible to easily arrange and / or form the pixel transistor Tpx and / or the driver transistor Tdr, and appropriately ensure the device characteristics and / or operating characteristics of the pixel transistor Tpx and / or the driver transistor Tdr. In addition, since the first active layer ACT1 and the second active layer ACT2 are formed of a high-mobility oxide semiconductor, the power consumption of the display device 100 can be reduced.

[0204] The second gate insulating layer GI2 (also referred to as a 'second gate insulating pattern layer') may be disposed on the second active layer ACT2. The second gate insulating layer GI2 may be disposed between the second active layer ACT2 and the second gate electrode GE2.

[0205] The second gate insulating layer GI2 may cover a portion (or part) of the second active layer ACT2 that overlaps with the second gate electrode GE2, and may expose other portions (or other parts) of the second active layer ACT2. For example, the second gate insulating layer GI2 may be arranged only on a portion of the second active layer ACT2 to cover the second channel region CH2 and expose the second source region SR2 and the second drain region DR2. In an embodiment, the second gate insulating layer GI2 may be an island-shaped insulating pattern layer having a shape and size corresponding to the shape and size of the second gate electrode GE2, and may be separately formed in each transistor region where each driver transistor Tdr is formed.

[0206] Since the second gate insulating layer GI2 exposes the second source region SR2 and the second drain region DR2, the second source region SR2 and the second drain region DR2 may become conductive appropriately and / or easily in the manufacturing process of the display panel 110. For example, in the step of forming the second gate insulating layer GI2 to expose the second source region SR2 and the second drain region DR2, a large amount of oxygen vacancies (for example, more than the oxygen vacancies in the first source region SR1 and the first drain region DR1) may appear in the second source region SR2 and the second drain region DR2 by etching gas, etc. In addition, by forming the interlayer insulating layer ILD in a state where the second source region SR2 and the second drain region DR2 are exposed, a larger amount of hydrogen may flow into the second source region SR2 and the second drain region DR2. Therefore, the second transistor TFT2 may have a higher mobility than that of the first transistor TFT1, and may have improved switching characteristics. For example, in the case where the first transistor TFT1 and the second transistor TFT2 are N-type oxide transistors, the electron mobility of the second transistor TFT2 may be higher than the electron mobility of the first transistor TFT1.

[0207] The second oxide semiconductor layer OS2 (also referred to as a "second oxide semiconductor pattern layer") may be disposed on the second gate insulating layer GI2. The second oxide semiconductor layer OS2 may be provided or included in the second semiconductor layer SCL2 on the substrate SUB. For example, the second oxide semiconductor layer OS2 and the first oxide semiconductor layer OS1 may be provided on the same layer (e.g., the gate insulating layer GI) on the substrate SUB.

[0208] The second oxide semiconductor layer OS2 may be disposed between the second gate insulating layer GI2 and the second gate electrode GE2. For example, the second oxide semiconductor layer OS2 may be partially disposed under the second gate electrode GE2.

[0209] The second oxide semiconductor layer OS2 may include an oxide semiconductor and may be disposed on the second channel region CH2 of the second active layer ACT2. Since the second oxide semiconductor layer OS2 is disposed on the second active layer ACT2, oxygen may be supplied to the second active layer ACT2 in the manufacturing process of the display panel 110. Therefore, although the second active layer ACT2 is formed of a high-mobility oxide semiconductor, the mobility (e.g., electron mobility) and / or carrier concentration of the second active layer ACT2 can be appropriately and / or easily adjusted, and the operating characteristics of the second transistor TFT2 (e.g., operating characteristics suitable for a switching element and / or a buffer transistor of the driving circuit 121) can also be appropriately and / or stably ensured.

[0210] In an embodiment, the first oxide semiconductor layer OS1 and the second oxide semiconductor layer OS2 may include the same oxide semiconductor. For example, the first oxide semiconductor layer OS1 and the second oxide semiconductor layer OS2 may be simultaneously formed on the first gate insulating layer GI1 and the second gate insulating layer GI2 using the same oxide semiconductor.

[0211] In an embodiment, the second gate electrode GE2 and the second oxide semiconductor layer OS2 may be formed (e.g., patterned) simultaneously or sequentially using one mask, or the second oxide semiconductor layer OS2 may be formed using the second gate electrode GE2 as a mask. Therefore, the second oxide semiconductor layer OS2 may have a shape and size corresponding to those of the second gate electrode GE2. For example, the second oxide semiconductor layer OS2 may be arranged on a portion of the second active layer ACT2 (e.g., the second channel region CH2 located below the second gate electrode GE2), and other portions of the second active layer ACT2 (e.g., the second source region SR2 and the second drain region DR2) may be exposed.

[0212] The second gate electrode GE2 may be disposed on the second oxide semiconductor layer OS2. The second gate electrode GE2 may be provided or included in the second conductive layer CDL2 on the substrate SUB. For example, the first gate electrode GE1 and the second gate electrode GE2 may be provided and / or disposed on the same layer on the substrate SUB.

[0213] The second gate electrode GE2 may be disposed on the second active layer ACT2 to overlap the second channel region CH2. The second gate electrode GE2 and the second active layer ACT2 may be separated and / or spaced apart from each other with the second gate insulating layer GI2 and the second oxide semiconductor layer OS2 interposed therebetween.

[0214] The second source electrode SE2 and the second drain electrode DE2 may be provided or included in the third conductive layer CDL3 on the substrate SUB. For example, the second source electrode SE2, the second drain electrode DE2, the first source electrode SE1 and the first drain electrode DE1 may be arranged on the same layer (eg, interlayer insulating layer ILD) of the substrate SUB.

[0215] The second source electrode SE2 may be connected to a portion of the second active layer ACT2. For example, the second source electrode SE2 may be connected to the second source region SR2 through at least one contact hole penetrating the interlayer insulating layer ILD.

[0216] The second drain electrode DE2 may be connected to another portion of the second active layer ACT2. For example, the second drain electrode DE2 may be connected to the second drain region DR2 through at least one contact hole penetrating the interlayer insulating layer ILD.

[0217] The transistor TFT including the first transistor TFT1 of the pixel PX and the second transistor TFT2 of the driving circuit 121 may be covered by the passivation layer PSV.

[0218] The corresponding electrodes, conductive pattern layers and / or wirings provided or included in the conductive layer of the panel circuit layer PCL may include at least one conductive material, and each may have a single-layer structure or a multi-layer structure. For example, the electrodes, conductive pattern layers and / or wirings provided or included in each of the first conductive layer CDL1, the second conductive layer CDL2 and the third conductive layer CDL3 may include copper (Cu), titanium (Ti), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), tantalum (Ta), tungsten (W), magnesium (Mg) and at least one of other metals, alloys thereof or other conductive materials, and each may have a single-layer structure or a multi-layer structure. In an embodiment, the electrodes, conductive pattern layers and / or wirings arranged or included in the same conductive layer may be formed simultaneously by the same conductive material.

[0219] The light emitting element layer LEL may be disposed on the panel circuit layer PCL and may be disposed in the display area DA. For example, the light emitting element layer LEL may be disposed on the panel circuit layer PCL in the display area DA.

[0220] The light emitting element layer LEL may include a light emitting element ED of the pixel PX. For example, the light emitting element layer LEL may include a pixel defining layer PDL (also referred to as a "bank") that separates the emission regions of the pixel PX and the light emitting element ED arranged in each emission region. In an embodiment, the light emitting element layer LEL may further include a spacer SPC arranged on a portion of the pixel defining layer PDL.

[0221] Each light emitting element ED may include a first electrode ET1 connected to at least one pixel transistor Tpx (e.g., a first pixel transistor T1) included in a corresponding pixel PX, and a light emitting layer EML and a second electrode ET2 sequentially arranged on the first electrode ET1. In an embodiment, the light emitting element ED may further include a first intermediate layer (e.g., a hole layer including a hole transport layer) between the first electrode ET1 and the light emitting layer EML, and a second intermediate layer (e.g., an electron layer including an electron transport layer) between the light emitting layer EML and the second electrode ET2.

[0222] The first electrode ET1 of the light emitting element ED may be arranged on the panel circuit layer PCL to correspond to each emission area. The first electrode ET1 may include a conductive material. In an embodiment, the first electrode ET1 may include a metal material having a high reflectivity. For example, the first electrode ET1 may have a single-layer structure of molybdenum (Mo), titanium (Ti), copper (Cu), or aluminum (Al), or may have a structure including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), gold (Au) and nickel (Ni) multilayer structures (e.g., ITO / Mg, ITO / MgF 2 , ITO / Ag and ITO / Ag / ITO).

[0223] The light emitting layer EML of the light emitting element ED may include a polymer material or a low molecular material. Light emitted from the light emitting layer EML may be used for image display.

[0224] The second electrode ET2 of the light emitting element ED may include a conductive material. In an embodiment, the second electrode ET2 may be a common layer formed across the entire display area DA to cover the light emitting layer EML and the pixel defining layer PDL. In an embodiment, the second electrode ET2 may be formed of a transparent conductive material (TCO) such as ITO, IZO, ZnO or ITZO capable of transmitting light, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag) or an alloy of magnesium (Mg) and silver (Ag).

[0225] The pixel defining layer PDL may have an opening corresponding to each emission region and may surround the emission region. For example, the pixel defining layer PDL may be formed to cover an edge portion of the first electrode ET1 of the light emitting element ED and may include an opening exposing the remaining portion of the first electrode ET1. The area where the exposed first electrode ET1 overlaps the light emitting layer EML may be defined as the emission region of each pixel PX.

[0226] In an embodiment, the pixel defining layer PDL may include at least one organic insulating layer including an organic insulating material. For example, the pixel defining layer PDL may include acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, benzocyclobutene (BCB) or other organic insulating materials.

[0227] The spacer SPC may be arranged on a portion of the pixel defining layer PDL. The spacer SPC may include at least one organic insulating layer including an organic insulating material. The spacer SPC and the pixel defining layer PDL may include the same material, or the spacer SPC may include a material different from that of the pixel defining layer PDL. In an embodiment, the pixel defining layer PDL and the spacer SPC may be sequentially formed by separate mask processes. In another embodiment, the pixel defining layer PDL and the spacer SPC may be an integral pattern layer formed simultaneously using a halftone mask.

[0228] The encapsulation layer ENL may be arranged on the light emitting element layer LEL. The encapsulation layer ENL may cover the light emitting element layer LEL in the display area DA, and may extend to the non-display area NDA to contact the panel circuit layer PCL. For example, the encapsulation layer ENL may be arranged in the display area DA to cover the light emitting element layer LEL, and an end of the encapsulation layer ENL may be arranged in a portion of the non-display area NDA adjacent to the display area DA. The encapsulation layer ENL may block oxygen or moisture from penetrating into the light emitting element layer LEL, and may reduce electrical and / or physical impacts on the panel circuit layer PCL and the light emitting element layer LEL.

[0229] In an embodiment, the encapsulation layer ENL may include a first encapsulation layer ENL1, a second encapsulation layer ENL2, and a third encapsulation layer ENL3 sequentially arranged on the light emitting element layer LEL. Each of the first encapsulation layer ENL1 and the third encapsulation layer ENL3 may be an inorganic encapsulation layer including an inorganic material. The second encapsulation layer ENL2 may be an organic encapsulation layer including an organic material.

[0230] According to the above-described embodiment, the first gate insulating layer GI1 may be disposed on the first active layer ACT1 of the first transistor TFT1 to entirely (or comprehensively) cover the first active layer ACT1. For example, the first gate insulating layer GI1 may entirely (or comprehensively) cover the first active layer ACT1 except for a portion where at least one contact hole for connection with the first source electrode SE1 and / or the first drain electrode DE1 is formed in the first gate insulating layer GI1 and the interlayer insulating layer ILD.

[0231] Therefore, the threshold voltage and driving range of the first transistor TFT1 can be properly ensured, and the operating characteristics of the first transistor TFT1 can be stabilized. For example, in the manufacturing process of the display panel 110, in a state where the first active layer ACT1 is entirely (or comprehensively) covered by the gate insulating layer GI (or the first gate insulating layer GI1), a patterning process (e.g., an etching process) of the gate insulating layer GI, a formation process (e.g., a deposition process) of the interlayer insulating layer ILD and / or a heat treatment process can be performed. Therefore, the threshold voltage shift (e.g., negative shift) of the first transistor TFT1 can be prevented or reduced, and the driving range of the first transistor TFT1 can be properly and / or stably ensured. In addition, compared with the case where the gate insulating layer GI is etched to expose the first source region SR1 and / or the first drain region DR1, the range of the extension of the first source region SR1 and / or the first drain region DR1 (e.g., the length and / or area of ​​the portion where the first source region SR1 and / or the first drain region DR1 are formed in the first active layer ACT1) can be relatively small. Therefore, a first channel region CH1 having a sufficient length can be formed under the first gate electrode GE1, and the parasitic capacitance of the first transistor TFT1 can be reduced. Therefore, in the case where the first active layer ACT1 is formed of a high-mobility oxide semiconductor, the effective channel length can be appropriately ensured, and the operating characteristics of the first transistor TFT1 can be stabilized.

[0232] For example, a second gate insulating layer GI2 partially covering a portion of the second active layer ACT2 overlapping with the second gate electrode GE2 and exposing other portions of the second active layer ACT2 may be arranged on the second active layer ACT2 of the second transistor TFT2. Therefore, in the process of forming the second gate insulating layer GI2 by patterning the gate insulating layer GI, a large number of oxygen vacancies may appear in the oxide semiconductor forming the second active layer ACT2 mainly at the portion (e.g., the second source region SR2 and the second drain region DR2) that does not overlap with the second gate electrode GE2 by etching gas, etc. The oxygen vacancies may be partially diffused to the portion of the second active layer ACT2 that overlaps with the second gate electrode GE2. In addition, in the case where the process of forming the interlayer insulating layer ILD and / or the heat treatment process are performed in a state where the second source region SR2 and the second drain region DR2 are not covered by the second gate insulating layer GI2, the amount of hydrogen flowing into the second source region SR2 and the second drain region DR2 may increase. Therefore, the second source region SR2 and the second drain region DR2 may have a higher conductivity (e.g., a higher mobility and / or carrier concentration). In addition, in the case where each of the second source region SR2 and the second drain region DR2 is extended to a region partially overlapping with the second gate electrode GE2, a large parasitic capacitance may be formed between the second source region SR2 and the second drain region DR2 and the second gate electrode GE2. Therefore, the on-current of the second transistor TFT2 (e.g., the drain-source current in the on state) may be increased, thereby improving the output characteristics (e.g., switching characteristics and / or response speed) of the second transistor TFT2. Since the output characteristics of the second transistor TFT2 are improved, the output characteristics of the driving circuit 121 and the like may be improved, thereby stably driving the pixel PX.

[0233] According to the above-described embodiments, the gate insulating layer GI may be arranged in different shapes on the active layer (e.g., the first active layer ACT1 and the second active layer ACT2) of each transistor TFT according to the characteristics required by each transistor TFT. Therefore, the characteristics of each transistor TFT may be appropriately adjusted and / or optimized.

[0234] For example, at least one pixel transistor Tpx requiring more uniform and stable characteristics may be formed by a first transistor TFT1 including a first active layer ACT1 entirely (or fully) covered by a first gate insulating layer GI1. Therefore, a change in the characteristics of the first transistor TFT1 may be prevented, reduced, or minimized, and a stable operating characteristic may be ensured. Therefore, blurring of an image due to a change in brightness of the pixel PX may be prevented, reduced, or minimized, and the image quality of the display device 100 may be improved.

[0235] For example, at least one driver transistor Tdr that requires a higher on-current to stably drive the pixel PX may be formed by a second transistor TFT2, which includes a second active layer ACT2 in which only a partial area of ​​the lower side of the second gate electrode GE2 is covered by the second gate insulating layer GI2. Therefore, the mobility and / or on-current of the second transistor TFT2 may be appropriately and / or easily increased, and the output characteristics (e.g., switching characteristics and / or response speed) of the second transistor TFT2 may be improved. In addition, since the output characteristics of the second transistor TFT2 are improved, the output characteristics of the driving circuit 121, etc. may be improved, thereby stably driving the pixel PX.

[0236] In an embodiment, among the pixel transistors Tpx arranged in each pixel PX, the pixel transistor Tpx requiring a high-speed switching operation may be formed into a structure different from that of the first transistor TFT1. For example, at least one switching element (e.g., Figure 3 At least one of the second pixel transistor T2 to the fifth pixel transistor T5 in the pixel PX may be formed in a structure in which the active layer is partially covered by the gate insulating layer GI, similar to the second transistor TFT2. For example, all pixel transistors Tpx arranged in each pixel PX may be formed in the same structure as the first transistor TFT1, or some of the pixel transistors Tpx may be formed in the same structure as the first transistor TFT1 and other some of the pixel transistors Tpx may be formed in the same structure as the second transistor TFT2.

[0237] Figure 8 is a schematic cross-sectional view showing a display panel 110 according to an embodiment. For example, Figure 8 A portion of the display area DA and a portion of the non-display area NDA of the display panel 110 are shown, and Figure 6 The embodiments are different from those of the second oxide semiconductor layer OS2.

[0238] Apart from Figures 1 to 7 In addition, refer to Figure 8 , Figure 6 The second oxide semiconductor layer OS2 may not be provided on the second active layer ACT2 of the second transistor TFT2. For example, the second gate electrode GE2 of the second transistor TFT2 may be arranged (e.g., directly arranged) on the second gate insulating layer GI2, and the oxide semiconductor layer may not be provided between the second gate electrode GE2 and the second active layer ACT2.

[0239] In an embodiment, the first oxide semiconductor layer OS1 may be selectively formed only on at least one pixel transistor Tpx (e.g., the first transistor TFT1) that requires more uniform and stable characteristics. In an embodiment, the oxide semiconductor layer may not be formed on other transistors (e.g., the second transistor TFT2) of the display panel 110 and the active layer of the driver transistor Tdr, thereby improving the switching characteristics.

[0240] Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 and Fig.16 FIG. 1 is a diagram showing a method of manufacturing a display device 100 (see FIG. 1 ) according to an embodiment. Figure 1 ) is a schematic cross-sectional diagram of a method. For example, Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 and Fig.16 The sequence shows the manufacturing Figure 6 The step of forming a first transistor TFT1 and a second transistor TFT2 on a substrate SUB is one of the steps of manufacturing a display panel 110.

[0241] Apart from Figures 1 to 7 In addition, refer to Fig. 9 , a substrate SUB including a display area DA and a non-display area NDA may be prepared. In an embodiment, the display area DA defined on the substrate SUB may include a pixel area PXA, and the non-display area NDA may include a driving circuit area DRA.

[0242] In an embodiment, a barrier layer BRL may be formed on a substrate SUB. The barrier layer BRL may be formed in the display area DA and the non-display area NDA. The barrier layer BRL may be formed by an insulating film forming process (eg, a deposition process) using at least one insulating material (eg, an inorganic insulating material) above.

[0243] Apart from Figures 1 to 7 as well as Fig. 9 In addition, refer to Fig.10, a first conductive layer CDL1 including a first bottom gate electrode BG1 and a second bottom gate electrode BG2 may be formed on a substrate SUB (e.g., on a barrier layer BRL). For example, on the substrate SUB, a first bottom gate electrode BG1 may be formed in each pixel region PXA of the display region DA, and a second bottom gate electrode BG2 may be formed in the drive circuit region DRA. The first bottom gate electrode BG1 and the second bottom gate electrode BG2 may be formed by a film formation process (e.g., a deposition process) of a conductive layer using at least one conductive material above and a patterning process (e.g., an etching process using a mask) of the conductive layer.

[0244] Thereafter, a buffer layer BFL covering the first conductive layer CDL1 may be formed on the substrate SUB. The buffer layer BFL may be formed through a film formation process of an insulating layer using at least one insulating material (eg, an inorganic insulating material) above.

[0245] Apart from Figures 1 to 7 as well as Fig. 9 and Fig.10 In addition, refer to Fig.11 , a first semiconductor layer SCL1 including a first active layer ACT1 and a second active layer ACT2 may be formed on a substrate SUB (e.g., on a buffer layer BFL). For example, on the substrate SUB, a first active layer ACT1 may be formed in each pixel area PXA of a display area DA, and a second active layer ACT2 may be formed in a driving circuit area DRA. The first active layer ACT1 may be formed to overlap with the first bottom gate electrode BG1, and the second active layer ACT2 may be formed to overlap with the second bottom gate electrode BG2.

[0246] In an embodiment, the first active layer ACT1 and the second active layer ACT2 may be formed simultaneously from the same oxide semiconductor. For example, the first active layer ACT1 and the second active layer ACT2 may be formed in the display area DA and the driving circuit area DRA, respectively, by a film formation process and a patterning process of a semiconductor layer using at least one oxide semiconductor.

[0247] Apart from Figures 1 to 7 as well as Figures 9 to 11 In addition, refer to Fig.12 , a gate insulating layer GI, an oxide semiconductor layer OSL, and a conductive layer GCDL may be sequentially formed on the substrate SUB on which the first semiconductor layer SCL1 and the like are arranged.

[0248] The gate insulating layer GI may be formed to cover the first semiconductor layer SCL1 including the first and second active layers ACT1 and ACT2. The gate insulating layer GI may be formed by a film forming process of an insulating layer using at least one insulating material (eg, an inorganic insulating material) above.

[0249] The oxide semiconductor layer OSL may be formed to cover the gate insulating layer GI. The oxide semiconductor layer OSL may be formed by a film formation process of a semiconductor layer using at least one oxide semiconductor above.

[0250] The conductive layer GCDL may be formed to cover the oxide semiconductor layer OSL. The conductive layer GCDL may be formed by a film formation process of a conductive layer using the above at least one conductive material.

[0251] Apart from Figures 1 to 7 as well as Figures 9 to 12 In addition, refer to Fig.13 , a second conductive layer CDL2 including a first gate electrode GE1 and a second gate electrode GE2 may be formed on the oxide semiconductor layer OSL (or the first oxide semiconductor layer OS1 and the second oxide semiconductor layer OS2 formed of the oxide semiconductor layer OSL). The first gate electrode GE1 and the second gate electrode GE2 may be formed by a patterning process of the conductive layer GCDL including an etching process. The first gate electrode GE1 may be formed to overlap a portion of the first active layer ACT1, and the second gate electrode GE2 may be formed to overlap a portion of the second active layer ACT2.

[0252] In an embodiment, the first oxide semiconductor layer OS1 and the second oxide semiconductor layer OS2 may be formed by etching the oxide semiconductor layer OSL using a mask for forming the first gate electrode GE1 and the second gate electrode GE2 or using the first gate electrode GE1 and the second gate electrode GE2 as a mask. The first oxide semiconductor layer OS1 may be formed under the first gate electrode GE1 and may have a shape corresponding to the shape of the first gate electrode GE1. For example, the first oxide semiconductor layer OS1 may have a shape and size corresponding to the shape and size of the first gate electrode GE1. The second oxide semiconductor layer OS2 may be formed under the second gate electrode GE2 and may have a shape corresponding to the shape of the second gate electrode GE2. For example, the second oxide semiconductor layer OS2 may have a shape and size corresponding to the shape and size of the second gate electrode GE2.

[0253] Apart from Figures 1 to 7 as well as Figures 9 to 13 In addition, refer to Fig.14, the gate insulating layer GI may be patterned by etching the gate insulating layer GI to form a first gate insulating layer GI1 and a second gate insulating layer GI2. The first gate insulating layer GI1 may be formed to entirely (or comprehensively) cover at least the first active layer ACT1. In an embodiment, the first gate insulating layer GI1 may be entirely (or comprehensively) formed in the display area DA, and a second gate insulating layer GI2 separated from the first gate insulating layer GI1 may be formed by etching the gate insulating layer GI in the driving circuit area DRA. The second gate insulating layer GI2 may be formed to partially cover the second active layer ACT2, and may be separately formed in each second transistor region including each second active layer ACT2.

[0254] In the process of etching the gate insulating layer GI, the property of the second active layer ACT2 may be changed so that a portion of the second active layer ACT2 has different characteristics. Therefore, the second active layer ACT2 may be divided into regions having different characteristics.

[0255] For example, oxygen vacancies may occur in the oxide semiconductor forming the second active layer ACT2 mainly at the portion not overlapping with the second gate electrode GE2 by etching gas, etc. Therefore, the second active layer ACT2 may be divided into regions with different characteristics (e.g., the second channel region CH2, the second source region SR2, and the second drain region DR2). In an embodiment, oxygen vacancies may occur mainly at the portion of the second active layer ACT2 not overlapping with the second gate electrode GE2 (e.g., the second source region SR2 and the second drain region DR2), and may diffuse to a portion of the region overlapping with the second gate electrode GE2.

[0256] Apart from Figures 1 to 7 as well as Figures 9 to 14 In addition, refer to Fig.15 , an interlayer insulating layer ILD may be formed on the substrate SUB to cover the buffer layer BFL, the first semiconductor layer SCL1 including the first active layer ACT1 and the second active layer ACT2, the gate insulating layer GI including the first gate insulating layer GI1 and the second gate insulating layer GI2, the second semiconductor layer SCL2 including the first oxide semiconductor layer OS1 and the second oxide semiconductor layer OS2, and the second conductive layer CDL2 including the first gate electrode GE1 and the second gate electrode GE2. For example, the interlayer insulating layer ILD may be entirely (or comprehensively) formed in the display area DA and the non-display area NDA (for example, the driving circuit area DRA). The interlayer insulating layer ILD may be formed by a film formation process of an insulating layer using at least one insulating material (for example, an inorganic insulating material) above.

[0257] In the process of forming the interlayer insulating layer ILD, hydrogen may flow into the first active layer ACT1 and the second active layer ACT2. In an embodiment, before or after the formation of the interlayer insulating layer ILD, a heat treatment process (e.g., annealing) may be additionally performed on the first active layer ACT1 and the second active layer ACT2. Even in the heat treatment process, hydrogen may flow into the first active layer ACT1 and the second active layer ACT2.

[0258] Since hydrogen flows into the first active layer ACT1 and the second active layer ACT2, a portion of the first active layer ACT1 and a portion of the second active layer ACT2 may become conductive (e.g., conductive as an N type). Therefore, the first active layer ACT1 may be divided into a first source region SR1 and a first drain region DR1 having conductivity and a first channel region CH1 maintaining semiconductor characteristics. Due to the inflow of hydrogen in a subsequent process including a process of forming an interlayer insulating layer ILD, the second source region SR2 and the second drain region DR2, in which a large number of oxygen vacancies have occurred in the process of etching the gate insulating layer GI, may become conductive, thereby having a higher conductivity than that of the first source region SR1 and the first drain region DR1.

[0259] Apart from Figures 1 to 7 as well as Figures 9 to 15 In addition, refer to Fig.16 , a third conductive layer CDL3 including a first source electrode SE1, a first drain electrode DE1, a second source electrode SE2, and a second drain electrode DE2 may be formed on the interlayer insulating layer ILD. In an embodiment, at least one of the first source region SR1, the first drain region DR1, the second source region SR2, and the second drain region DR2 may replace at least one of the first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and the second drain electrode DE2, and at least one of the first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and the second drain electrode DE2 may not be formed.

[0260] The first source electrode SE1 and the first drain electrode DE1 may be formed to be connected to different portions of the first active layer ACT1. For example, the first source electrode SE1 may be connected to the first source region SR1, and the first drain electrode DE1 may be connected to the first drain region DR1. The second source electrode SE2 and the second drain electrode DE2 may be formed to be connected to different portions of the second active layer ACT2. For example, the second source electrode SE2 may be connected to the second source region SR2, and the second drain electrode DE2 may be connected to the second drain region DR2. For example, a contact hole may be formed in the interlayer insulating layer ILD.

[0261] Through the above processes, transistors TFT including first and second transistors TFT1 and TFT2 may be formed in the display area DA and the driving circuit area DRA. In embodiments, elements provided or included in the same conductive layer or the same semiconductor layer in the display panel 110 may be simultaneously formed.

[0262] After forming the transistor TFT, the formation of Figure 6 The process of forming the passivation layer PSV and the like shown in FIG. The passivation layer PSV may cover the transistor TFT. Thus, the panel circuit layer PCL of the display panel 110 may be formed.

[0263] In an embodiment, when the display panel 110 includes a light emitting element layer LEL and an encapsulation layer ENL disposed on the panel circuit layer PCL, the light emitting element layer LEL and the encapsulation layer ENL may be sequentially formed on the panel circuit layer PCL. The display panel 110 according to the embodiment and the display device 100 including the display panel 110 may be manufactured by the above process.

[0264] Figures 17 to 19 FIG. 1 is a diagram showing a method of manufacturing a display device 100 (see FIG. 1 ) according to an embodiment. Figure 1 ) is a schematic cross-sectional diagram of a method. For example, Figures 17 to 19 The sequence shows the manufacturing Figure 8 The step of forming the second semiconductor layer SCL2 and the second conductive layer CDL2 among the steps of manufacturing the display panel 110.

[0265] Apart from Figures 1 to 5 as well as Figure 8 In addition, refer to Fig.17 , a gate insulating layer GI and an oxide semiconductor layer OSL may be sequentially formed on a substrate SUB on which a first conductive layer CDL1 including a first bottom gate electrode BG1 and a second bottom gate electrode BG2 and a first semiconductor layer SCL1 including a first active layer ACT1 and a second active layer ACT2 are arranged. The steps of forming the gate insulating layer GI and the steps of forming the oxide semiconductor layer OSL may be the same as those described with reference to Fig.12 The steps in the described embodiments are substantially the same or similar.

[0266] Apart from Figures 1 to 5 as well as Figure 8 and 17 In addition, refer to Fig.18 The first oxide semiconductor layer OSL may be formed on a portion of the first active layer ACT1 by patterning the oxide semiconductor layer OSL through an etching process using a mask. In embodiments, the oxide semiconductor layer may not be formed on the second active layer ACT2.

[0267] Apart from Figures 1 to 5 as well as Figure 8 , Fig.17 and Fig.18 In addition, refer to Fig.19 , a second conductive layer CDL2 including a first gate electrode GE1 and a second gate electrode GE2 may be formed on the substrate SUB on which the gate insulating layer GI and the first oxide semiconductor layer OS1 are arranged. For example, the first gate electrode GE1 and the second gate electrode GE2 may be formed by a film formation process of a conductive layer using at least one conductive material above and a patterning process of the conductive layer.

[0268] After that, you can execute the reference Figures 14 to 16 The patterning process of the gate insulating layer GI, the forming process of the interlayer insulating layer ILD, and the forming process of the third conductive layer CDL3 are described. Therefore, the transistor TFT including the first transistor TFT1 and the second transistor TFT2 may be formed in the display area DA and the driving circuit area DRA.

[0269] Thereafter, a process of forming a passivation layer PSV, a process of forming a light emitting element layer LEL, and a process of forming an encapsulation layer ENL may be performed. Figure 8 A display panel 110 of an embodiment and a display device 100 including the display panel 110 .

[0270] According to the display device 100 and the manufacturing method thereof according to the above-described embodiments, the first transistor TFT1 arranged in the display area DA and the second transistor TFT2 arranged in the driving circuit area DRA may be formed in different structures according to the operating characteristics required for each transistor TFT. For example, the first gate insulating layer GI1 may be arranged on the first active layer ACT1 of the first transistor TFT1 to entirely (or comprehensively) cover the first active layer ACT1, and the second gate insulating layer GI2 may be arranged on the second active layer ACT2 of the second transistor TFT2 to partially cover the second active layer ACT2. According to the embodiments, the operating characteristics of the first transistor TFT1 and the second transistor TFT2 may be differentiated and / or optimized.

[0271] For example, by covering the entire first active layer ACT1 with the first gate insulating layer GI1, the threshold voltage and the driving range of the first transistor TFT1 can be properly ensured, and the operating characteristics of the first transistor TFT1 can be stabilized. In some embodiments, the first transistor TFT1 can be a pixel transistor Tpx provided to the pixel PX, and the display quality of the display device 100 can be improved by stabilizing the operating characteristics of the first transistor TFT1.

[0272] In the case of the second active layer ACT2, by covering only the portion of the second active layer ACT2 overlapping the second gate electrode GE2 with the second gate insulating layer GI2, the on-current of the second transistor TFT2 can be increased, and the output characteristics can be improved. In some embodiments, the second transistor TFT2 can be a driver transistor Tdr provided to the driving circuit 121, etc., and the output characteristics of the second transistor TFT2 can be improved to improve the output characteristics of the driving circuit 121 and stably drive the pixel PX.

[0273] In addition, according to the display device 100 and the method of manufacturing the same, the first oxide semiconductor layer OS1 may be disposed between the first gate insulating layer GI1 and the first gate electrode GE1 on the first active layer ACT1. Therefore, the operation characteristics of the first transistor TFT1 may be stably ensured.

[0274] At the end of the detailed description, those skilled in the art will appreciate that many changes and modifications can be made to the embodiments without departing substantially from the principles of the invention. Therefore, the disclosed embodiments are used in a general and descriptive sense only and not for the purpose of limitation.

Claims

1. A display device, comprising: A substrate, the substrate comprising a display area and a driving circuit area; A first transistor is arranged in the display area and includes: a first active layer, the first active layer being arranged on the substrate, and a first gate electrode, the first gate electrode being arranged on the first active layer; a first gate insulating layer, the first gate insulating layer being arranged between the first active layer and the first gate electrode and entirely covering the first active layer; A second transistor, the second transistor being arranged in the driving circuit region and comprising: a second active layer, the second active layer being arranged on the substrate, and a second gate electrode, the second gate electrode being arranged on the second active layer; a second gate insulating layer, the second gate insulating layer being arranged between the second active layer and the second gate electrode, covering a portion of the second active layer overlapping the second gate electrode, and exposing other portions of the second active layer; and A first oxide semiconductor layer is disposed between the first gate insulating layer and the first gate electrode.

2. The display device according to claim 1, further comprising: A second oxide semiconductor layer is disposed between the second gate insulating layer and the second gate electrode.

3. The display device according to claim 2, wherein: The first oxide semiconductor layer and the second oxide semiconductor layer include the same oxide semiconductor.

4. The display device according to claim 1, wherein: The second gate electrode is disposed directly on the second gate insulating layer.

5. The display device according to claim 1, wherein: The first gate insulating layer is entirely disposed in the display area.

6. The display device according to claim 1, wherein: The first gate insulating layer has a shape and size corresponding to those of the first active layer, and is an island-shaped insulating pattern layer covering an upper surface and side surfaces of the first active layer.

7. The display device according to claim 1, wherein: The second gate insulating layer is an island-shaped insulating pattern layer having a shape and size corresponding to those of the second gate electrode.

8. The display device according to claim 1, wherein: The first active layer and the second active layer are disposed at the same layer on the substrate and include the same oxide semiconductor.

9. The display device according to claim 1, wherein: The first transistor and the second transistor are N-type oxide transistors, and The electron mobility of the second transistor is higher than the electron mobility of the first transistor.

10. The display device according to claim 1, further comprising: An interlayer insulating layer entirely covers the first and second active layers, the first and second gate insulating layers, the first oxide semiconductor layer, and the first and second gate electrodes.

11. The display device according to claim 10, wherein: The first transistor further includes at least one of a first source electrode and a first drain electrode disposed on the interlayer insulating layer and connected to a different portion of the first active layer.

12. The display device according to claim 11, further comprising: a buffer layer disposed between the substrate and the semiconductor layer including the first active layer and the second active layer, The first transistor further includes a first bottom gate electrode, which is arranged between the substrate and the buffer layer and overlaps with the first gate electrode when the first active layer is arranged between the first bottom gate electrode and the first gate electrode.

13. The display device according to claim 12, wherein: The first bottom gate electrode is connected to the first source electrode.

14. The display device according to claim 10, wherein: The second transistor further includes at least one of a second source electrode and a second drain electrode disposed on the interlayer insulating layer and connected to a different portion of the second active layer.

15. The display device according to claim 1, further comprising: a buffer layer disposed between the substrate and the semiconductor layer including the first active layer and the second active layer, The second transistor further includes a second bottom gate electrode, which is arranged between the substrate and the buffer layer and overlaps with the second gate electrode when the second active layer is arranged between the second bottom gate electrode and the second gate electrode.

16. The display device according to claim 15, wherein: The second bottom gate electrode is connected to the second gate electrode.

17. The display device according to claim 1, further comprising: a pixel arranged in the display area and including the first transistor; as well as A driver circuit is arranged in the driver circuit region and includes the second transistor.

18. A method for manufacturing a display device, the method comprising: preparing a substrate including a display area and a driving circuit area; forming a first active layer and a second active layer on the substrate in the display area and the drive circuit area respectively; sequentially forming a gate insulating layer covering the first active layer and the second active layer and an oxide semiconductor layer covering the gate insulating layer on the substrate; forming a first gate electrode overlapping a portion of the first active layer and a second gate electrode overlapping a portion of the second active layer on the oxide semiconductor layer; By etching the gate insulating layer, patterning the gate insulating layer into a first gate insulating layer that entirely covers the first active layer and a second gate insulating layer that partially covers the second active layer; as well as An interlayer insulating layer covering the first active layer, the second active layer, the first gate insulating layer, the second gate insulating layer, the first gate electrode, and the second gate electrode is formed in the display region and the driving circuit region.

19. The method according to claim 18, further comprising: Before patterning the gate insulating layer into the first gate insulating layer and the second gate insulating layer, a first oxide semiconductor layer having a shape and size corresponding to those of the first gate electrode is formed under the first gate electrode by etching the oxide semiconductor layer.

20. The method of claim 18, further comprising: Before forming the first gate electrode and the second gate electrode, a first oxide semiconductor layer is formed on a portion of the first active layer by etching the oxide semiconductor layer.

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