Multifunctional sensing, storage and calculation integrated memory and preparation method and application thereof

Abstract

The invention provides a multifunctional sensing, storage and calculation integrated memory and a preparation method and application thereof.The multifunctional sensing, storage and calculation integrated memory comprises an I-TO layer, a first in-situ forming layer, an ion regulation and control layer, a second in-situ forming layer and a top electrode layer which are sequentially stacked from top to bottom, and the first in-situ forming layer is formed by an oxidation-reduction reaction of the I-TO layer and the ion regulation and control layer; and the second in-situ formation layer is formed by an oxidation-reduction reaction of the ion regulation layer and the top electrode layer. According to the embodiment of the invention, multiple functions such as gas recognition, nonvolatile storage, logical operation and crosstalk suppression can be realized, and the method and the device can be widely applied to the fields of intelligent sensing, information storage, neuromorphic calculation and the like.

Description

Technical Field

[0001] The present invention relates to the field of resistive random access memory technology, and in particular to a multifunctional sensing-storage-computing integrated memory and a preparation method and application thereof. Background Art

[0002] In the field of advanced electronics, the pursuit of efficient, scalable, and universal memory and computing solutions has led to the exploration of new materials and device architectures. Memory storage devices, characterized by their ability to retain memories of past electronic states, have emerged as promising candidates for next-generation memory and computing applications.

[0003] With the rapid development of information technology, the demand for data storage and processing is growing. The traditional von Neumann architecture faces energy efficiency and latency problems caused by the separation of storage and computing. Therefore, storage and computing integration has become an important direction to solve this problem. Resistive random access memory (RRAM) is considered to be an ideal device for realizing storage and computing integration due to its simple structure, high speed, low power consumption, non-volatility and good scalability. However, RRAM still faces many challenges in practical applications, such as unstable device performance, single function and susceptibility to crosstalk. In addition, gas sensing has broad application prospects in environmental monitoring, industrial production and medical diagnosis. Traditional gas sensors are usually large in size, high in power consumption and low in integration, which makes it difficult to meet the growing demand for portability and intelligence. Therefore, it is of great significance to develop a gas-sensitive storage and computing integrated device with high integration, diverse functions and stable performance. Summary of the invention

[0004] The purpose of the present invention is to provide a multifunctional sensing, storage and computing integrated memory and its preparation method and application, aiming to solve the problem that traditional gas sensors are usually large in size, high in power consumption, low in integration, and difficult to meet the growing demand for portability and intelligence.

[0005] In a first aspect, the present invention provides a multifunctional sensing, storage and computing integrated memory, which comprises, from top to bottom, an ITO layer, a first in-situ formed layer, an ion regulation layer, a second in-situ formed layer, and a top electrode layer stacked in sequence, wherein:

[0006] The first in-situ formed layer is formed by an oxidation-reduction reaction between the ITO layer and the ion regulation layer, and the second in-situ formed layer is formed by an oxidation-reduction reaction between the ion regulation layer and the top electrode layer.

[0007] Furthermore, the ion control layer is at least one of MAPb I3, CsPbBr3, and SrTiO3.

[0008] Furthermore, the top electrode includes at least one of C, Au, Ag, and Cu.

[0009] In a second aspect, the present invention provides a method for preparing a multifunctional sensing-storage-computing integrated memory, which is used to prepare the above-mentioned multifunctional sensing-storage-computing integrated memory, and the preparation method comprises:

[0010] Obtaining an ITO glass substrate, wherein the ITO glass substrate comprises a glass layer and an ITO layer stacked on the glass layer, and pre-treating the ITO glass substrate;

[0011] Preparing a perovskite precursor solution, and depositing an ion regulation layer on the ITO layer according to the perovskite precursor solution;

[0012] A top electrode layer is deposited on the ion regulation layer.

[0013] Furthermore, the step of pre-treating the ITO glass substrate comprises:

[0014] The ITO glass substrate was ultrasonically cleaned for 20 minutes using a deturbidity remover, deionized water, acetone and ethanol respectively, and then dried using a N2 gas flow, and the dried ITO glass substrate was subjected to plasma treatment.

[0015] Furthermore, the step of preparing a perovskite precursor solution and depositing an ion regulation layer on the ITO layer according to the perovskite precursor solution comprises:

[0016] CsBr, PbBr 2、 PEABr was dissolved in dimethyl sulfoxide solution at a molar ratio of 1:1:0.4 to obtain a perovskite precursor solution;

[0017] Under inert atmosphere and active gas, 50 μL of filtered perovskite precursor solution was applied on the ITO layer using a pipette.

[0018] Start the coating machine, spin-coat the perovskite precursor solution on the I TO layer at 500 rpm for 5 seconds, then increase to 3000 rpm and spin-coat the perovskite precursor solution on the I TO layer for 25 seconds. After the spin coating is completed, place the sample on a heating plate and anneal at 100°C for 10 minutes.

[0019] In a third aspect, the present invention provides an application of the multifunctional sensing-storage-computing integrated memory as described above in distinguishing between inert gases and active gases.

[0020] In a fourth aspect, the present invention provides an application of the multifunctional sensing, storage and computing integrated memory as described above in non-volatile storage.

[0021] In a fifth aspect, the present invention provides an application of the multifunctional sensing, storage and computing integrated memory as described above in logical operations.

[0022] In a sixth aspect, the present invention provides an application of the multifunctional sensing-storage-computing integrated memory as described above in suppressing crosstalk.

[0023] Compared with the prior art, the present invention has the following advantages:

[0024] 1. The present invention designs a storage-computing integrated memory that integrates gas identification, logic reconfiguration and anti-crosstalk functions. The memory utilizes a unique material design and device structure to achieve multiple functions such as gas identification, logic reconstruction and anti-crosstalk. In an inert gas environment, the device exhibits WORM (write once read many times) characteristics; in an active gas environment, the device exhibits a high conductivity state at a low voltage and exhibits a repeatable negative differential resistance (NDR) switching characteristic at a high voltage. Based on these characteristics, the device can achieve multiple functions such as gas identification, non-volatile storage, logic operations and crosstalk suppression. The storage-computing integrated memory of the present invention is expected to be widely used in the fields of intelligent sensing, information storage, and neuromorphic computing. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a structural diagram of a multifunctional sensing, storage and computing integrated memory;

[0026] Figure 2 SEM image of quasi-two-dimensional CsPbBr3 film;

[0027] Figure 3 XRD spectra of the newly synthesized and aged quasi-two-dimensional CsPbBr3 thin films;

[0028] Figure 4 UV-visible absorption spectra of three-dimensional CsPbBr3 and quasi-two-dimensional CsPbBr3 films;

[0029] Figure 5 This is one of the IV characteristic test diagrams of the device;

[0030] Figure 6 This is the second IV characteristic test diagram of the device;

[0031] Figure 7 This is the third diagram of the IV characteristic test of the device;

[0032] Figure 8 This is the fourth diagram of the IV characteristic test of the device;

[0033] Fig. 9 The characteristic diagram of the device as WORM storage in an inert gas environment;

[0034] Fig.10 Read the test pattern for the device;

[0035] Fig.11 Write and erase test patterns for the device.

[0036] Explanation of symbols: ITO layer-10; first in-situ formed layer-20; ion regulation layer-30; second in-situ formed layer-40; top electrode layer-50.

[0037] The following specific implementation manner will further illustrate the present invention in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be understood by people with general skills in the field to which the present invention belongs. "Including" and similar words used in this article mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0039] The applicant found that: with the rapid development of information technology, the demand for data storage and processing is increasing. The traditional von Neumann architecture faces energy efficiency and latency problems caused by the separation of storage and computing. Therefore, storage and computing integration has become an important direction to solve this problem. Resistive random access memory (RRAM) is considered to be an ideal device for realizing storage and computing integration due to its simple structure, high speed, low power consumption, non-volatility and good scalability. However, RRAM still faces many challenges in practical applications, such as unstable device performance, single function and susceptibility to crosstalk. In addition, gas sensing has broad application prospects in environmental monitoring, industrial production and medical diagnosis. Traditional gas sensors are usually large in size, high in power consumption, and low in integration, which makes it difficult to meet the growing demand for portability and intelligence. Therefore, it is of great significance to develop a gas-sensitive storage and computing integrated device with high integration, diverse functions and stable performance.

[0040] The resistive switching characteristics of RRAM can be used to design logic circuits. By converting the input signal into an electrical signal, the change in resistance state can be reflected by the change in resistance or current signal. Therefore, specific logic functions can be realized by connecting multiple RRAMs in series or in parallel, matching other electronic components, and reasonably designing peripheral auxiliary circuits. However, most of the current RRAMs used to design logic circuits require multiple input sources (heat, light, stress, etc.) or require the assistance of peripheral circuits to realize logical operations. This will cause RRAM to face problems such as high energy consumption of logical operations, many steps, complex operations, the need for assistance from other electronic components, and the need for additional circuit design when realizing logical operations. As far as we know, there are few reports on the achievements of suppressing undercurrent and realizing various reconfigurable logic memory functions in a single halide perovskite memory resistor, and its underlying mechanism remains elusive.

[0041] Based on this, the present invention designs a storage-computing integrated memory that integrates gas identification, logic reconfiguration and anti-crosstalk functions. The memory utilizes unique material design and device structure to achieve multiple functions such as gas identification, logic reconstruction and anti-crosstalk. In an inert gas environment, the device exhibits WORM (write once read multiple times) characteristics; in an active gas environment, the device exhibits a high conductivity state at a low voltage and exhibits repeatable negative differential resistance (NDR) switching characteristics at a high voltage. Based on these characteristics, the device can achieve multiple functions such as gas identification, non-volatile storage, logic operations and crosstalk suppression. The storage-computing integrated memory of the present invention is expected to be widely used in the fields of intelligent sensing, information storage, and neuromorphic computing.

[0042] like Figure 1 As shown, an embodiment of the present invention provides a multifunctional sensing, storage and computing integrated memory, which includes, from top to bottom, an ITO layer 10, a first in-situ formed layer 20, an ion regulation layer 30, a second in-situ formed layer 40, and a top electrode layer 50 stacked in sequence, wherein:

[0043] The top electrode can be selected from any of the inert electrode, active electrode or oxide electrode; in addition, the electrode material plays a vital role in the resistive memory. Inert electrodes include Au, Pt, etc., which only play the role of transmitting electrons in the resistive memory; while active electrodes include Ag, Cu, etc., in addition to transmitting electrons, under the action of the electric field, the active electrode material may be oxidized and enter the resistive layer, thereby affecting the resistive behavior. Common oxide electrode materials include but are not limited to ITO and FTO. By selecting a suitable top electrode material, the performance of the resistive memory can be effectively regulated and the resistive behavior of the device can be optimized.

[0044] The ion control layer 30 refers to a functional layer in the RRAM device that can control ion migration and resistance change. Its function is to control the migration of mobile ions (such as oxygen vacancies) in the device under the action of an external electric field, thereby causing a reversible change in the resistance of the device and realizing information storage. In some embodiments, the ion migration layer can be a perovskite material, a transition metal oxide, a solid electrolyte material, a polymer material, a two-dimensional material, and some other materials with relatively good ion mobility, etc. For example, the perovskite material can be any one of MAPb I3, CsPbBr3, and SrTiO3; the transition metal oxide can be any one of TiO2, HfO2, and Ta2O5; the solid electrolyte material can be any one of GeSe, AgS, and CuS; the polymer material can be any one of polypyrrole and polyaniline; the two-dimensional material can be any one of MoS2 and h-BN. In summary, the resistance change of the device is regulated by setting the ion control layer 30 to include oxygen vacancies, sulfur vacancies, halogen ions, and metal ions. This resistance change can be used to represent different storage states, enabling the storage, reading and writing of information.

[0045] The first in-situ formed layer 20 and the second in-situ formed layer 40 play a key role in RRAM, and are mainly used for the formation and regulation of conductive channels, thereby realizing the change of resistance state. The in-situ formation of the electro-induced ion migration layer ensures the stability and controllability of the conductive filaments, and can significantly improve the performance and reliability of the memory. Specifically, the in-situ formed layer is located between the top electrode and the ion regulation layer 30, or between the ion regulation layer 30 and the bottom electrode. It provides conductive ions (such as Ag+, Cu+) through electric field induced ion migration and redox reaction, and forms conductive filaments under the action of the electric field.

[0046] The in-situ formed layer can be formed by the reaction of the electrode and the ion control layer 30, and a structure with conductive properties is generated in-situ between the two layers. For example, the halogen elements (C l-, Br-, I-, etc.) in the halogen perovskite or S2- in the sulfide react with the metal ions (Cu2+, Ag+, etc.) in the electrode to generate metal halides (such as CuBr, AgBr, etc.) or metal sulfides (such as CuS, etc.) in situ, thereby forming conductive filaments. In addition, a defect-rich interface layer (such as halogen vacancies, oxygen vacancies, etc.) is also formed in situ at the interface between the ion control layer 30 and the bottom electrode, which can serve as a channel and charge trap for ion migration. Under the action of an external electric field, the migrating ions (such as Br-) move in the interface layer to form and regulate the conductive channel, thereby achieving the regulation of the resistive switching behavior.

[0047] In addition, in this embodiment, the bottom electrode is the ITO layer 10 .

[0048] Preferably, the multifunctional sensing-storage-computing integrated memory exhibits high conductivity (low resistance state) at low voltage under active gas operation, and exhibits a repeatable NDR resistive switching effect when a certain voltage is reached; it realizes integrated non-volatile storage and computing, promotes 12 reconfigurable logic operations in a passive 1R structure, and suppresses the sneak current in the crosstalk setting to achieve anti-crosstalk function.

[0049] In addition, the logic reconstruction function of the multifunctional sensing, storage and computing integrated memory proposes the operating characteristics of 12 sequential logic functions, including TRUE, FALSE, P, NOT p, q, NOT q, AND, RI MP, NI MP, NOR, XOR and XNOR. p represents the first input, q represents the second input, 0 and 1 represent low voltage and high voltage states respectively. Before starting the operation, the device is initialized in HRS. The "number of steps" indicates the number of basic operation steps required to complete a specific logic function.

[0050] In addition, in some embodiments, the top electrode preferably includes a silver electrode, a copper electrode, a gold electrode and a carbon electrode, and the thickness is preferably 20 to 50 nm, and more preferably 30 nm. The metal area of ​​the top electrode is 2 mm*13 mm, and the effective area of ​​a single device is 2 mm*3 mm. The bottom electrode preferably includes an ITO layer, and the thickness is preferably 100 to 200 nm.

[0051] Example 1

[0052] 1) Pretreatment of I TO glass: Before device fabrication, the commercial I TO glass substrate was ultrasonically cleaned with a de-turbidant, deionized water, acetone, and ethanol for 20 min, respectively, and then dried with a stream of N2. The substrate was treated with oxygen plasma for 120 s to make it more hydrophilic.

[0053] 2) Preparation of perovskite precursor solution: 0.064 g CsBr and 0.110 g PbBr2 (1:1 molar ratio), 0.004 g 18-crown-6 ether and 0.024 g PEABr (final molar ratio CsBr:PbBr2:PEABr=1:1:0.4) were dissolved in 1 ml dimethyl sulfoxide (DMSO) solution and stirred at 60°C in an inert gas (nitrogen) environment for 12 hours.

[0054] 3) Preparation of perovskite film: Filter the solution in step 2) through a 0.22 μm organic filter membrane, and use a pipette to apply 50 μL of the filtered solution on the I TO substrate treated in step 1) under an inert gas (nitrogen) environment. Start the coater, spin coat at 500 rpm for 5 seconds, then increase to 3000 rpm for 25 seconds. After spin coating, place the sample on a hot plate and anneal at 100°C for 10 minutes. A quasi-two-dimensional CsPbBr3 film is obtained.

[0055] 4) Preparation of perovskite resistive random access memory: The quasi-two-dimensional CsPbBr3 film in step 3) is placed in the chamber of a high vacuum electron beam physical vapor deposition system. When the vacuum reaches 5.0×10 -4 After Pa, the deposition process begins. Ag was deposited at a rate of 100 nm until the thickness reached 10 nm. The rate was then increased to When the thickness reaches 30nm, the quasi-two-dimensional perovskite resistive random access memory is obtained.

[0056] Example 2

[0057] 1) Pretreatment of I TO glass: Before device fabrication, the commercial I TO glass substrate was ultrasonically cleaned with a de-turbidant, deionized water, acetone, and ethanol for 20 min, respectively, and then dried with a stream of N2. The substrate was treated with oxygen plasma for 120 s to make it more hydrophilic.

[0058] 2) Preparation of perovskite precursor solution: 0.064 g CsBr and 0.110 g PbBr2 (1:1 molar ratio), 0.004 g 18-crown-6 ether and 0.024 g PEABr (final molar ratio CsBr:PbBr2:PEABr=1:1:0.4) were dissolved in 1 ml dimethyl sulfoxide (DMSO) solution and stirred at 60°C in an inert gas (nitrogen) environment for 12 hours.

[0059] 3) Preparation of perovskite film: Filter the solution in step 2) through a 0.22 μm organic filter membrane, and use a pipette to apply 50 μL of the filtered solution on the I TO substrate treated in step 1) under an inert gas (nitrogen) environment. Start the coater, spin coat at 500 rpm for 5 seconds, then increase to 3000 rpm for 25 seconds. After spin coating, place the sample on a hot plate and anneal at 100°C for 10 minutes. A quasi-two-dimensional CsPbBr3 film is obtained.

[0060] 4) Preparation of perovskite resistive random access memory: A carbon electrode paste is used to realize the C electrode, thereby obtaining a quasi-two-dimensional perovskite resistive random access memory.

[0061] Example 3

[0062] 1) Pretreatment of I TO glass: Before device fabrication, the commercial I TO glass substrate was ultrasonically cleaned with a de-turbidant, deionized water, acetone, and ethanol for 20 min, respectively, and then dried with a stream of N2. The substrate was treated with oxygen plasma for 120 s to make it more hydrophilic.

[0063] 2) Preparation of perovskite precursor solution: 0.064 g CsBr and 0.110 g PbBr2 (1:1 molar ratio), 0.004 g 18-crown-6 ether and 0.024 g PEABr (final molar ratio CsBr:PbBr2:PEABr=1:1:0.4) were dissolved in 1 ml dimethyl sulfoxide (DMSO) solution and stirred at 60°C in an inert gas (nitrogen) environment for 12 hours.

[0064] 3) Preparation of perovskite film: Filter the solution in step 2) through a 0.22 μm organic filter membrane, and use a pipette to apply 50 μL of the filtered solution on the I TO substrate treated in step 1) under an inert gas (nitrogen) environment. Start the coater, spin coat at 500 rpm for 5 seconds, then increase to 3000 rpm for 25 seconds. After spin coating, place the sample on a hot plate and anneal at 100°C for 10 minutes. A quasi-two-dimensional CsPbBr3 film is obtained.

[0065] 4) Preparation of perovskite resistive random access memory: The quasi-two-dimensional CsPbBr3 film in step 3) is placed in the chamber of a high vacuum electron beam physical vapor deposition system. When the vacuum reaches 5.0×10 -4 After Pa, the deposition process begins. Au was deposited at a rate of 100 nm until the thickness reached 10 nm. The rate was then increased to When the thickness reaches 30nm, the quasi-two-dimensional perovskite resistive random access memory is obtained.

[0066] Example 4

[0067] 1) Pretreatment of I TO glass: Before device fabrication, the commercial I TO glass substrate was ultrasonically cleaned with a de-turbidant, deionized water, acetone, and ethanol for 20 min, respectively, and then dried with a stream of N2. The substrate was treated with oxygen plasma for 120 s to make it more hydrophilic.

[0068] 2) Preparation of perovskite precursor solution: 0.064 g CsBr and 0.110 g PbBr2 (1:1 molar ratio), 0.004 g 18-crown-6 ether and 0.024 g PEABr (final molar ratio CsBr:PbBr2:PEABr=1:1:0.4) were dissolved in 1 ml dimethyl sulfoxide (DMSO) solution and stirred at 60 °C in an active gas (air) environment for 12 h.

[0069] 3) Preparation of perovskite film: Filter the solution in step 2) through a 0.22 μm organic filter membrane, and use a pipette to apply 50 μL of the filtered solution on the I TO substrate treated in step 1) under an active gas (air) environment. Start the coater, spin coat at 500 rpm for 5 seconds, then increase to 3000 rpm for 25 seconds. After spin coating, place the sample on a hot plate and anneal at 100°C for 10 minutes. A quasi-two-dimensional CsPbBr3 film is obtained.

[0070] 4) Preparation of perovskite resistive random access memory: The quasi-two-dimensional CsPbBr3 film in step 3) is placed in the chamber of a high vacuum electron beam physical vapor deposition system. When the vacuum reaches 5.0×10 -4 After Pa, the deposition process begins. Au was deposited at a rate of 100 nm until the thickness reached 10 nm. The rate was then increased to When the thickness reaches 30nm, the quasi-two-dimensional perovskite resistive random access memory is obtained.

[0071] Example 5

[0072] 1) Pretreatment of I TO glass: Before device fabrication, the commercial I TO glass substrate was ultrasonically cleaned with a de-turbidant, deionized water, acetone, and ethanol for 20 min, respectively, and then dried with a stream of N2. The substrate was treated with oxygen plasma for 120 s to make it more hydrophilic.

[0073] 2) Preparation of perovskite precursor solution: 0.064 g CsBr and 0.110 g PbBr2 (1:1 molar ratio), 0.004 g 18-crown-6 ether and 0.024 g PEABr (final molar ratio CsBr:PbBr2:PEABr=1:1:0.4) were dissolved in 1 ml dimethyl sulfoxide (DMSO) solution and stirred at 60 °C in an active gas (air) environment for 12 h.

[0074] 3) Preparation of perovskite film: Filter the solution in step 2) through a 0.22 μm organic filter membrane, and use a pipette to apply 50 μL of the filtered solution on the I TO substrate treated in step 1) under an active gas (air) environment. Start the coater, spin coat at 500 rpm for 5 seconds, then increase to 3000 rpm for 25 seconds. After spin coating, place the sample on a hot plate and anneal at 100°C for 10 minutes. A quasi-two-dimensional CsPbBr3 film is obtained.

[0075] 4) Preparation of perovskite resistive random access memory: The quasi-two-dimensional CsPbBr3 film in step 3) is placed in the chamber of a high vacuum electron beam physical vapor deposition system. When the vacuum reaches 5.0×10 -4 After Pa, the deposition process begins. Cu was deposited at a rate of 100 nm until the thickness reached 10 nm. The rate was then increased to When the thickness reaches 30nm, the quasi-two-dimensional perovskite resistive random access memory is obtained.

[0076] Test Example 1

[0077] The morphology of the sample surface and cross-section was analyzed using a field emission scanning electron microscope (SEM, FEIQuanta 200FEG).

[0078] X-ray diffraction (XRD) measurements were carried out using a PANalytica l Empyrean X-ray diffractometer with Cu (Kα) as the emission source.

[0079] The low-dimensional phase of quasi-two-dimensional CsPbBr3 was analyzed using UV-visible spectrophotometer.

[0080] Electrical characterization was performed using a Keithley 2636B source measure unit (SMU). During the test, the Keithley 2636B SMU was used together with a probe station to measure the electrical characteristics of the device. The positive electrode was connected to the ITO bottom electrode, while the negative electrode was connected to the top electrode (Ag / Cu / Au / C). For measurements in the glove box, the probe station was placed in the glove box, and the connection wires were connected to the Keithley 2636B, and the electrical level overlap was consistent with that in the air.

[0081] For devices aged in air, the temperature and humidity were approximately 20°C and 65%.

[0082] The quasi-two-dimensional CsPbBr3 thin film obtained in Example 1 was characterized by the above equipment, and the results are as follows:

[0083] Figure 2 The SEM image of the quasi-two-dimensional CsPbBr3 perovskite film is Figure 2 It can be seen that the film prepared by this method is uniform and dense.

[0084] Figure 3 XRD patterns of freshly synthesized and air-aged quasi-two-dimensional perovskite films. Figure 3 It can be seen that the perovskite films all show a cubic CsPbBr3 structure, with strong diffraction peaks at 15.38°, 21.72° and 31.04°, corresponding to the (001), (110) and (002) crystal planes respectively. All the diffraction peaks were calibrated at the same time. By comparing the XRD curves of the phases before and after oxidation, no obvious impurity peaks appeared, indicating that the crystals did not decompose after being placed in the air for one week.

[0085] Figure 4To confirm the existence of the low-dimensional phase, the absorption spectra of quasi-two-dimensional and three-dimensional perovskites were compared. The quasi-two-dimensional perovskite film had weak exciton absorption peaks at 408nm, 438nm and 463nm, corresponding to n=1 phase, n=2 phase and n=3 phase perovskites, respectively.

[0086] Figure 5 The Ag / quasi-two-dimensional CsPbBr3 / I TO device was tested in an inert atmosphere and an active atmosphere. The device exhibited a low resistance state even at high voltage, while the device tested in air exhibited obvious symmetrical NDR behavior at a certain voltage, with the best HRS / LRS ratio of about 10 2 .

[0087] Test Example 2

[0088] The memory obtained in Example 2 and Example 3 was tested. Specifically, devices were manufactured using C and Au as electrodes on a stacked ITO / quasi-2DCsPbBr3 structure. Quasi-2DCsPbBr3 was synthesized under an inert gas atmosphere, and the IV characteristics of the device were tested under an active atmosphere. Figure 6 It can be seen that when the top electrode is C and Au, the device exhibits consistent and reproducible NDR resistance switching, indicating that the device has good storage performance and NDR resistance switching behavior even at an inert electrode level.

[0089] Test Example 3

[0090] The memory obtained in Example 4 and Example 5 was tested. Specifically, the device was manufactured using Ag and Cu as electrodes on the stacked ITO / quasi-2D CsPbBr3 structure. Quasi-2D CsPbBr3 was synthesized in an active gas environment, and the IV characteristics of the device were tested in an inert atmosphere. Figure 7 It can be seen that the devices with Ag electrodes and Cu electrodes exhibited nonvolatile resistance switching during the test. The transition from LRS to HRS occurred during the second cycle and remained in HRS in subsequent cyclic IV measurements. This is in line with the typical characteristics of write-once-read-many (WORM) technology, which allows data to be written to the storage medium only once and then read multiple times. The HRS / LRS ratios of WORM with silver electrodes and copper electrodes tested in N2 atmosphere were 10 3 and 10 4 .

[0091] Test Example 4

[0092] The memory obtained in Example 4 and Example 5 was tested. Specifically, the device was manufactured using Ag and Cu as electrodes on the stacked ITO / quasi-2D CsPbBr3 structure. Quasi-2D CsPbBr3 was synthesized in an active gas environment, and the IV characteristics of the device were tested in an active atmosphere. Figure 8 As can be seen, the voltage was swept from 0V to -5V, then back to 0V, then to 5V, and finally back to 0V, and then cycled. It is worth noting that both positive and negative voltage states show NDR phenomena during the voltage sweep from 0V to higher values. As the sweep voltage increases, the resistance changes from LRS to HRS, and remains at HRS during the voltage return until a sweep voltage of opposite polarity is applied, causing the resistance to return to LRS. This resistance switching behavior is repeated in each test cycle, and the on-off ratio of devices equipped with silver and copper electrodes is about 10 2 .

[0093] Test Example 5

[0094] The memory obtained in Example 1 was tested. First, a WORM test was performed under direct current. Fig. 9 It can be seen that a stable reading process is shown after the write operation.

[0095] also, Fig.10 The device was shown to exhibit a low resistance state (LRS) during +0.5V reading, and a high resistance state (HRS) during -0.5V reading in the ON state, effectively suppressing the undercurrent. Initially, the device was in HRS. Applying -10V V set When it is in LRS, it turns into LRS. Subsequently, it is read using voltages of +0.5V and -0.5V. During +0.5V reading, the device exhibits LRS, while during -0.5V reading, it remains in HRS. When in LRS, the device presents high resistance under reverse current, effectively suppressing reverse current through unselected devices, thereby achieving anti-crosstalk capability.

[0096] also, Fig.11 The writing and erasing processes of non-volatile memory are explored through single and multi-cycles. Write voltage: -10V, erase voltage: 10V, read voltage: -0.5V. Specifically, when a -10V set voltage is applied, the resistance state switches from HRS to LRS, effectively preserving the written electrical information. Subsequently, when 10V is applied for reset, the resistance state switches back to HRS, resulting in the erasure of the stored information. The phenomenon here originates from the symmetrical NDR characteristics of the resistive switching device. At the same time, multiple write-erase cycles were demonstrated, demonstrating the excellent repeated editing capabilities of the perovskite device.

[0097] As shown in Table 1 below, the operational characteristics of these 12 sequential logic functions are briefly described, including T TRUE, FALSE, P, NOT p, q, NOT q, AND, RI MP, NI MP, NOR, XOR, and XNOR. The left part of the table describes the rules governing the logic operations, while the right part details the strategy for configuring the logic variables p and q. Here, p represents the first input, q represents the second input, and 0 and 1 represent low-voltage and high-voltage states, respectively. Before starting the operation, the device is initialized in the HRS. The "number of steps" indicates the number of basic operation steps required to complete a specific logic function. The resistance switching behavior observed in this passive 1R structure (I TO / quasi-2D CSPbBr3 / electrode) can realize an integrated storage and computing unit that is capable of performing 12 reconfigurable logic operations and supporting non-volatile memory. In addition, this unit is the non-volatile storage and computing integrated unit with the simplest structure and the most diverse reconfigurable logic algorithms to date.

[0098] Table 1

[0099]

[0100] In summary, the present invention designs a storage-computing integrated memory that integrates gas identification, logic reconfiguration and anti-crosstalk functions. The memory utilizes a unique material design and device structure to achieve multiple functions such as gas identification, logic reconstruction and anti-crosstalk. In an inert gas environment, the device exhibits WORM (write once read many times) characteristics; in an active gas environment, the device exhibits a high conductivity state at a low voltage and exhibits a repeatable negative differential resistance (NDR) switching characteristic at a high voltage. Based on these characteristics, the device can achieve multiple functions such as gas identification, non-volatile storage, logic operations and crosstalk suppression. The storage-computing integrated memory of the present invention is expected to be widely used in the fields of intelligent sensing, information storage, and neuromorphic computing.

[0101] Although the embodiments of the present invention are described in detail above, it is obvious to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations are within the scope and spirit of the present invention as described in the claims. Moreover, the present invention described herein may have other embodiments and may be implemented or realized in a variety of ways.

Claims

1. A multifunctional sensing, storage and computing integrated memory, characterized in that: From top to bottom, it includes an ITO layer, a first in-situ formed layer, an ion regulation layer, a second in-situ formed layer, and a top electrode layer stacked in sequence, wherein: The first in-situ formed layer is formed by an oxidation-reduction reaction between the ITO layer and the ion regulating layer, and the second in-situ formed layer is formed by an oxidation-reduction reaction between the ion regulating layer and the top electrode layer.

2. The multifunctional sensing, storage and computing integrated memory according to claim 1, characterized in that: The ion control layer is at least one of MAPbI3, CsPbBr3, and SrTiO3.

3. The multifunctional sensing, storage and computing integrated memory according to claim 1, characterized in that: The top electrode includes at least one of C, Au, Ag, and Cu.

4. A method for preparing a multifunctional sensing-storage-computing integrated memory, used for preparing the multifunctional sensing-storage-computing integrated memory as claimed in any one of claims 1 to 3, characterized in that: The preparation method comprises: Obtaining an ITO glass substrate, wherein the ITO glass substrate comprises a glass layer and an ITO layer stacked on the glass layer, and pre-treating the ITO glass substrate; Preparing a perovskite precursor solution, and depositing an ion regulation layer on the ITO layer according to the perovskite precursor solution; A top electrode layer is deposited on the ion regulation layer.

5. The method for preparing the multifunctional sensing-storage-computing integrated memory according to claim 4, characterized in that: The step of pre-treating the ITO glass substrate comprises: The ITO glass substrate was ultrasonically cleaned for 20 minutes using a deturbidity remover, deionized water, acetone and ethanol respectively, and then dried using a N2 gas flow, and the dried ITO glass substrate was subjected to plasma treatment.

6. The method for preparing the multifunctional sensing-storage-computing integrated memory according to claim 4, characterized in that: The step of preparing a perovskite precursor solution and depositing an ion regulation layer on the ITO layer according to the perovskite precursor solution comprises: CsBr, PbBr 2、 PEABr was dissolved in dimethyl sulfoxide solution at a molar ratio of 1:1:0.4 to obtain a perovskite precursor solution; Under inert atmosphere and active gas, 50 μL of filtered perovskite precursor solution was applied on the ITO layer using a pipette. Start the coating machine, spin-coat the perovskite precursor solution on the ITO layer at 500 rpm for 5 seconds, then increase to 3000 rpm and spin-coat the perovskite precursor solution on the ITO layer for 25 seconds. After the spin coating is completed, place the sample on a heating plate and anneal at 100°C for 10 minutes.

7. An application of the multifunctional sensing, storage and computing integrated memory as described in any one of claims 1 to 3 in distinguishing between inert gases and active gases.

8. An application of the multifunctional sensing, storage and computing integrated memory as described in any one of claims 1 to 3 in non-volatile storage.

9. An application of the multifunctional sensing, storage and computing integrated memory as described in any one of claims 1 to 3 in logical operations.

10. An application of the multifunctional sensing-storage-computing integrated memory as described in any one of claims 1 to 3 in suppressing crosstalk.

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