Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises a shift register circuit and a shift detection module, the shift register circuit comprises a plurality of shift register units, and the N shift register units are arranged in a cascade manner; each stage of shift register unit is used for outputting a shift output signal to drive an output signal according to a first clock signal, a second clock signal and an input signal of a signal input end; the shift detection module is electrically connected with the shift output end of each shift register unit; in the scanning stage, the shift detection module is used for obtaining shift output signals output by each shift register unit, and when the shift output signal output by the (i-1) th shift register unit comprises an effective level and the shift output signal output by the ith shift register unit does not comprise the effective level, the shift output signal output by the (i-1) th shift register unit does not comprise the effective level. And an input signal including an effective level is provided for the signal input end of the mth-level shift register unit, so that the abnormal flicker problem of instant blackening of the display panel during electrostatic interference can be effectively improved, and the display effect can be effectively improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of display technology, the integration of display panels is getting higher and higher, and the cost is getting lower and lower. Most of the current display panels use the Gate Driver on Array (GOA) technology, which integrates the gate drive circuit into the peripheral area of ​​the array substrate, thereby effectively improving the integration of the display device and reducing its manufacturing cost while realizing a narrow frame design.

[0003] The existing display panels are prone to static electricity during operation due to the large amount of signal lines and component data, which causes the GOA circuit to output abnormalities, resulting in abnormal display of the display panel. The display panel may suddenly turn black, affecting the display effect of the display panel. Summary of the invention

[0004] The present invention provides a display panel and a display device to improve the abnormal flicker problem of the display panel turning black instantly when electrostatic interference occurs, thereby improving the display effect of the display panel.

[0005] According to one aspect of the present invention, a display panel is provided, comprising: a shift register circuit and a shift detection module; the shift register circuit comprises a plurality of shift register units; wherein N shift register units are cascaded; N ≥ 2, and N is an integer;

[0006] The shift register unit comprises a signal input terminal, a first clock terminal, a second clock terminal, a shift output terminal and a driving output terminal; the first clock terminal is used to receive a first clock signal, and the second clock terminal is used to receive a second clock signal;

[0007] In each of the shift register units arranged in cascade, the signal input end of the first stage of the shift register unit receives a start signal; in two adjacent stages of the shift register units, the signal input end of the shift register unit of the latter stage is electrically connected to the shift output end of the shift register unit of the previous stage; the shift register units of each stage are used to output a shift output signal and a gate drive signal according to the first clock signal, the second clock signal and the input signal of the signal input end;

[0008] The shift detection module is electrically connected to the shift output terminals of the shift register units at each level; a scanning cycle of the display panel includes a scanning phase, during which the shift detection module is used to obtain the shift output signals output by the shift register units at each level, and when the shift output signal output by the i-1th shift register unit includes a valid level, and the shift output signal output by the i-th shift register unit does not include a valid level, provide a restart signal including a valid level to the signal input terminal of the mth shift register unit;

[0009] i and m are both integers, and 1≤i≤N, 1≤m≤N.

[0010] According to another aspect of the present invention, a display device is provided, comprising: the above-mentioned display panel.

[0011] The display panel provided by the present invention is configured to sequentially cascade N shift register units in a shift register circuit so that a signal input end of a first-stage shift register unit receives a start signal, and in two adjacent stages of shift register units, an input signal of a subsequent stage of shift register unit is a shift output signal of a previous stage of shift register unit, and a first clock end of the shift register unit is configured to receive a first clock signal and a second clock end to receive a second clock signal, so that each shift register unit can output a shift output signal and a gate drive signal according to an input signal, a first clock signal, and a second clock signal, and a shift detection module is configured to be electrically connected to a shift output end of each shift register unit, so that the shift register module can obtain a shift output signal of each shift register unit. signal, and in the scanning stage of the scanning cycle, when it is determined that a certain shift register unit does not include a valid level in the outputted shift output signal due to electrostatic interference, it is determined that the shift register unit cannot normally output the valid level of the shift output signal due to the electrostatic interference, and at this time, a restart signal including the valid level is provided to one of the shift register units, so that the shift register unit can output the valid level of the shift output signal under the control of the restart signal, and the subsequent shift register units cascaded with it can all output the valid level of the shift output signal normally, which can effectively reduce the area range of abnormal display due to electrostatic interference, thereby improving the abnormal flickering problem of the display panel turning black instantly during electrostatic interference, and effectively improving the display effect.

[0012] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0014] Figure 1 It is a structural schematic diagram of a display panel in the prior art;

[0015] Figure 2 It is a driving timing diagram of a display panel in the prior art;

[0016] Figure 3 is a schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0017] Figure 4 is a driving timing diagram of a shift register circuit provided by an embodiment of the present invention;

[0018] Figure 5 is a driving timing diagram of another shift register circuit provided by an embodiment of the present invention;

[0019] Figure 6 is a schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0020] Figure 7 is a structural schematic diagram of another display panel provided by an embodiment of the present invention;

[0021] Figure 8 is a structural schematic diagram of another display panel provided by an embodiment of the present invention;

[0022] Fig. 9 is a structural schematic diagram of another display panel provided by an embodiment of the present invention;

[0023] Fig.10 is a structural schematic diagram of another display panel provided by an embodiment of the present invention;

[0024] Fig.11 and Fig.12 is a structural schematic diagram of another display panel provided by an embodiment of the present invention;

[0025] Fig.13 is a structural schematic diagram of a shift register unit provided by an embodiment of the present invention;

[0026] Fig.14 is a structural schematic diagram of a shift register unit provided by an embodiment of the present invention;

[0027] Fig.15is a structural schematic diagram of another shift register unit provided by an embodiment of the present invention;

[0028] Fig.16 is a driving timing diagram of a shift register unit provided by an embodiment of the present invention;

[0029] Fig.17 It is a structural schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0030] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0031] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0032] Figure 1 is a schematic diagram of the structure of a display panel in the prior art, such as Figure 1As shown, the GOA circuit 10' generally includes N cascaded shift register units G', and the output end of each shift register unit G' is electrically connected to the scanning signal line LG' in one-to-one correspondence, and the enable level of the scanning signal is output to each scanning signal line LG' in sequence to realize the row-by-row scanning function of each pixel 20' in the display panel, so that the display panel 100' presents a corresponding display screen. In the prior art, the time for displaying a frame of the display screen is a scanning cycle T', and in a part of a scanning cycle T', each shift register unit G' sequentially outputs the enable level of the scanning signal Gout', which is the scanning stage T1' of the scanning cycle T'; and in another period of a scanning cycle T', each shift register unit G' continuously outputs the non-enable level of the scanning signal Gout', which is the holding stage T2' of the scanning cycle T', at which time the signal output end of each shift register unit G' and the node electrically connected to the signal output end should be maintained at the non-enable level of the scanning signal Gout'.

[0033] Figure 2 This is a driving timing diagram of a display panel in the prior art. Figure 1 and Figure 2 In each cascaded shift register unit G′, only the input signal of the first-stage shift register unit G(1)′ is the start signal STV′ provided by the driver IC, while the input signals of the other stages of the shift register G′ are all the shift output signals of the previous stage shift register unit G′, that is, in two adjacent stages of shift register units G′, the output signal of the next stage shift register unit G′ is the shift output signal Vnext′ of the previous stage shift register unit G′, so that each stage of the shift register unit G′ can output the gate drive signal Gout′ with the effective level shifted in sequence, so that the pixels 20′ can be scanned row by row. Therefore, if static electricity interferes with a certain level of the shift register unit G', for example, the m-th level shift register unit G(m)', after the m-1-th level shift register unit G(m-1)' can normally output the effective level of the shift output signal, the m'-th level shift register unit G(m)' cannot accurately output the effective level of the shift output signal Vnext' due to static electricity interference, which will cause the shift register units G' at all levels after the m-th level shift register unit G(m)' to be unable to normally output the shift output signal V next′ and the gate drive signal Gout′, which will cause the m+1th shift register unit G(m+1)′ to the Nth shift register unit G(n)′ to be unable to scan the connected pixel 20′, making the pixels connected to the m+1th shift register unit G(m+1)′ to the Nth shift register unit G(n)′ unable to display the picture normally, and the normal display can only be restored after the static electricity dissipates. During this period, an abnormal display situation in which the screen turns black instantly, which is visible to the human eye, will occur, affecting the display effect of the display panel.

[0034] To solve the above technical problems, an embodiment of the present invention provides a display panel, comprising: a shift register circuit and a shift detection module; the shift register circuit comprises a plurality of shift register units; wherein N shift register units are cascaded; N ≥ 2, and N is an integer; the shift register unit comprises a signal input terminal, a first clock terminal, a second clock terminal, a shift output terminal and a drive output terminal; the first clock terminal is used to receive a first clock signal, and the second clock terminal is used to receive a second clock signal; in each of the cascaded shift register units, the signal input terminal of the first-stage shift register unit receives a start signal; in two adjacent stages of shift register units, the signal input terminal of the latter-stage shift register unit is electrically connected to the shift output terminal of the previous-stage shift register unit ; Each level of shift register unit is used to output a shift output signal to drive an output signal according to a first clock signal, a second clock signal and an input signal at a signal input end; a shift detection module is electrically connected to the shift output end of each level of shift register unit; a scanning cycle of the display panel includes a scanning phase, during which the shift detection module is used to obtain the shift output signal output by each level of shift register unit, and when the shift output signal output by the i-1th level shift register unit includes a valid level and the shift output signal output by the i-th level shift register unit does not include a valid level, an input signal including a valid level is provided to the signal input end of the m-th level shift register unit; i and m are both integers, and 1≤i≤N, 1≤m≤N.

[0035] By adopting the above technical solution, N shift register units in the shift register circuit are arranged to be cascaded in sequence, so that the signal input end of the first-stage shift register unit receives the start signal, and in two adjacent stages of shift register units, the input signal of the latter-stage shift register unit is the shift output signal of the previous-stage shift register unit, and the first clock end of the shift register unit is arranged to receive the first clock signal, and the second clock end is arranged to receive the second clock signal, so that each shift register unit can output a shift output signal and a gate drive signal according to the input signal, the first clock signal and the second clock signal, and the shift detection module is arranged to be electrically connected to the shift output end of each shift register unit, so that the shift register module can obtain the shift output signal of each shift register unit. signal, and in the scanning stage of the scanning cycle, when it is determined that a certain shift register unit does not include a valid level in the output shift output signal due to electrostatic interference, it is determined that the shift register unit cannot normally output the valid level of the shift output signal due to the electrostatic interference, and at this time, a restart signal including the valid level is provided to one of the shift register units, so that the shift register unit can output the valid level of the shift output signal under the control of the restart signal, and the subsequent shift register units cascaded with it can all output the valid level of the shift output signal normally, which can effectively reduce the area range of abnormal display due to electrostatic interference, thereby improving the abnormal flickering problem of the display panel turning black instantly during electrostatic interference, and effectively improving the display effect.

[0036] The above is the core idea of ​​this application. The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0037] Figure 3 is a schematic diagram of the structure of a display panel provided by an embodiment of the present invention, such as Figure 3 As shown, the display panel 100 includes: a shift register circuit 10 and a shift detection module 20; the shift register circuit 10 includes a plurality of shift register units G; wherein N shift register units G are cascaded; N≥2, and N is an integer. The shift register unit G includes a signal input terminal IN, a first clock terminal CK1, a second clock terminal CK2, a shift output terminal VNEXT, and a drive output terminal GOUT; the first clock terminal CK1 is used to receive a first clock signal ck1, and the second clock terminal CK2 is used to receive a second clock signal ck2; in each cascaded shift register unit G, the signal input terminal of the first stage shift register unit G1 receives a start signal STV; in two adjacent stages of shift register units G, the signal input terminal of the next stage shift register unit G is electrically connected to the shift output terminal of the previous stage shift register unit G; each stage of the shift register unit G is used to output a shift output signal Vnext and a gate drive signal Gout according to the first clock signal ck1, the second clock signal ck2, and the input signal Vin of the signal input terminal IN. Figure 4 is a driving timing diagram of a shift register circuit provided by an embodiment of the present invention, combined with reference Figure 3 and Figure 4 , the shift detection module 20 is electrically connected to the shift output terminal VNEXT of each level of the shift register unit G; a scanning cycle T of the display panel 100 includes a scanning stage T1, in which the shift detection module 20 is used to obtain the shift output signal Vnext output by each level of the shift register unit G, and when the shift output signal Vnext(i-1) output by the i-1th level shift register unit G includes a valid level, and the shift output signal Vnext(i) output by the i-th level shift register unit G does not include a valid level, an input signal Vin including a valid level is provided to the signal input terminal IN of the m-th level shift register unit Gm; i and m are both integers, and 1≤i≤N, 1≤m≤N.

[0038] Specifically, among the multiple shift register units G, N shift register units G can be cascaded, so that among the N cascaded shift register units G, the shift output terminal VNEXT of the previous stage shift register unit G is electrically connected to the signal input terminal IN of the next stage shift register unit G, so that the shift output signal Vnext of the previous stage shift register unit G is the input signal Vin of the next stage shift register unit G, so that when the shift output signal Vnext of the previous stage shift register unit G includes a valid level, the next stage shift register unit G can be driven, so that the next stage shift register unit G outputs the shift output signal Vnext and the gate drive signal Gout including a valid level.

[0039] The display panel may also be provided with a first clock signal line Ck1 and a second clock signal line Ck2. The first clock signal line Ck2 is used to transmit the first clock signal ck1, and the second clock signal line Ck2 is used to transmit the second clock signal ck2. The first clock terminal CK1 of each shift register unit G is electrically connected to the first clock signal line Ck2, and the second clock terminal CK2 of each shift register unit G is electrically connected to the second clock signal line Ck2, so that the first clock signal terminal CK1 of each shift register unit G can receive the first clock signal ck1, and the second clock terminal CK2 of each shift register unit G can receive the second clock signal ck2, so that under the drive of the first clock signal ck1, the second clock signal ck2 and the input signal Vin, the shift output signal Vnext can be output through the shift output terminal, and the gate drive signal Gout can be output through the drive output terminal. In one embodiment, the shift output signal Vnext can be multiplexed as the gate drive signal Gout. In another embodiment, the shift output signal Vnext is one of the control signals of the gate drive signal Gout. The embodiment of the present invention does not specifically limit this. In the absence of special instructions, the following embodiments take the shift output signal Vnext as one of the control signals of the gate driving signal Gout, and the shift output signal Vnext is synchronized with the gate driving signal Gout as an example to explain the technical solution of the present invention.

[0040] The shift detection module 20 may include connection terminals corresponding to each shift register unit G, each connection terminal is electrically connected to the corresponding shift output terminal VNEXT of each shift register unit G, and can obtain the shift output signal Vnext output by the shift register unit G through each connection terminal pair, so as to detect whether the corresponding shift register unit G is working abnormally according to the situation of each shift output signal Vnext.

[0041] Exemplary, reference Figure 3The display panel 100 includes a display area A1 and a non-display area A2 surrounding the display area A1; the shift register circuit 10 and the shift detection module 20 are both located in the non-display area A2; in the display area A1, the display panel 100 also includes a plurality of pixels 20 arranged in an array and a plurality of scanning signal lines LG extending along a first direction Y and arranged along a second direction X; at least part of the pixels 30 located in the same row are electrically connected to the same scanning signal line LG; the scanning signal line LG is used to transmit a gate driving signal Gout; the non-display area A2 also includes detection signal lines LA arranged one-to-one with each shift register unit G; the shift detection module 20 is electrically connected to the shift output terminal VNEXT of each shift register unit G through each detection signal line LA.

[0042] Specifically, the shift register circuit 10 and the shift detection module 20 can be arranged in the non-display area A2, and will not occupy the space of the display area A1, so as to ensure the pixel density of the display area A1 and improve the display effect of the display panel. The driving output terminal GOUT of each shift register unit G can be electrically connected to the scanning signal line LG, and at least part of the pixels 30 in the same row in the display area A1 can be electrically connected to the same scanning signal line LG, so that each level of shift register unit G can realize the row-by-row scanning of the pixels 30 in the display area A1. Figure 2 The example in FIG. 1 shows that all pixels 30 in the same row are electrically connected to the same scanning signal line LG. In other feasible embodiments of the present invention, some pixels 30 in the same row can also be electrically connected to the same scanning signal line LG, and the embodiments of the present invention do not specifically limit this. In the non-display area A2, the detection signal lines LA and the shift register units G are set one-to-one, and the shift detection module 20 can be independently connected to the shift output terminal VNEXT of each shift register unit G through each detection signal line LA, so that the shift detection module 20 can only obtain the shift output signal Vnext of one shift register unit G through one detection signal line LA, and the shift detection module 20 can only provide a corresponding signal to the input terminal of one shift register unit G through one detection signal line LA, which can avoid signal crosstalk and ensure the accuracy of the detection results and control accuracy of each shift register unit G.

[0043] Exemplary, reference Figure 4, a scanning cycle T of the display panel 100 includes a scanning phase T1 and a holding phase T2. When each shift register unit G is operating normally, in the scanning phase T1, the effective level of the shift output signal Vnext output by each shift register unit G is shifted in sequence. In a feasible embodiment, when the shift output signal Vnext output by the shift register unit G is at an effective level, the gate drive signal Gout output by the shift register unit is also at an effective level, so that the shift register unit G can drive the shift register unit G of the next stage through the shift output signal Vnext, and refresh the pixel 30 through the gate drive signal Gout. In the holding phase T2, the shift output signal Vnext and the gate drive signal Gout output by each shift register unit G are maintained at an invalid level, and at this time, each pixel 30 is maintained to display the display grayscale of the scanning phase T1 until the next scanning cycle T re-scans each row of pixels 30 and writes a new data signal.

[0044] Figure 5 is another driving timing diagram of a shift register circuit provided by an embodiment of the present invention, and is combined with reference to Figure 3 and Figure 5When the shift output signal Vnext(i-1) output by the i-1th-stage shift register unit G(i-1) includes a valid level, while the shift output signal Vnext(i) output by the i-th-stage shift register unit G(i) does not include a valid level, it can be determined that the i-th-stage shift register unit G(i) is operating abnormally due to electrostatic interference and is unable to output the valid level of the shift output signal Vnext(i) according to the valid level of the input signal Vin provided by the i-1th-stage shift register unit G(i-1) and the first clock signal ck1 and the second clock signal ck2. At this time, the shift register module 20 can provide a restart signal Vst(m) including a valid level to the signal input end of the m-th shift register unit G(m), so that the m-th shift register unit G(m) uses the restart signal Vst as the input signal Vin, so that the m-th shift register unit G(m) can output a shift output signal Vnext(m) including a valid level according to the restart signal Vst, the first clock signal ck1 and the second clock signal ck2, so that the subsequent cascaded shift register units G can all output the shift output signal Vnext(m) with the valid level shifted in sequence, so that the m+1-th shift register unit G(m+1) to the N-th shift register unit G(n) can all output the gate drive signal Gout with the valid level shifted in sequence. Compared with the prior art, when electrostatic interference makes the i-th shift register unit G(i) unable to output the effective level of the shift output signal Vnext(i), the i-th shift register unit G(i) to the N-th shift register unit G(n) are all unable to output the effective level of the shift output signal Vnext(i) and the effective level of the gate drive signal Gout(n), the area range of abnormal display can be effectively reduced, thereby improving the abnormal flicker problem of the display panel 100 turning black instantly during electrostatic interference, and effectively improving the display effect.

[0045] Exemplary, with reference to Figure 3 , Figure 4 and Figure 5 , m>i. In this way, in the entire scanning period T, only the shift output signal Vnext output by the i-th shift register unit G(i) and a small number of shift register units G(i) between the i-th shift register unit G(i) and the m-th shift register unit G(m) does not include a valid level, that is, the gate drive signal Gout output by the i-th shift register unit G(i) and a small number of shift register units G(i) between the i-th shift register unit G(i) and the m-th shift register unit G(m) does not include a valid level, which can effectively reduce the area range of abnormal display, thereby improving the abnormal flicker problem of the display panel 100 turning black instantly during electrostatic interference, and effectively improving the display effect.

[0046] Wherein, it can be set to mi=1, mi=2, or mi≥3. When m≤N is satisfied, the embodiment of the present invention does not specifically limit the value of m. In one embodiment, the difference between m and i can be set to be smaller, for example, mi=1 or mi=2, so that the distance between the i-th shift register unit G(i) and the m-th shift register unit G(m) is closer, thereby reducing the area range of abnormal display, and significantly improving the problem of abnormal flickering of the display panel 100 due to electrostatic interference. In another embodiment, the difference between m and i can be set to be larger, for example, mi≥3, so that the i-th shift register unit G(i) is far away from the m-th shift register unit G(m). This can avoid the range of electrostatic interference being too large and making it impossible for the m-th shift register unit G(m) to output the effective level of the shift output signal Vnext(m) under the control of the restart signal Vst(m), thereby failing to effectively solve the problem of abnormal flickering of the display panel caused by electrostatic interference. That is, the difference between m and i is set to be larger, which can exceed the range of electrostatic interference, and can ensure that the m-th shift register unit G(m) outputs the effective level of the shift output signal Vnext(m) under the control of the restart signal Vst(m), thereby reducing the area range of abnormal display.

[0047] Among them, the embodiment of the present invention is exemplified by taking the effective level of the shift output signal Vnext and the gate drive signal Gout as a high level and the invalid level as a low level as an example. In other feasible embodiments of the present invention, the effective level of the shift output signal Vnext and the gate drive signal Gout can also be set to a low level and the invalid level to a high level. The embodiment of the present invention does not make specific limitations on this.

[0048] In addition, in the display area A1, the display panel 100 may further include a plurality of data signal lines LD, and at least part of the pixels 30 in the same column are electrically connected to the same data signal line LD, so that one data signal line LD can provide data signals to the pixels 30 in one column. In one embodiment, when the gate driving signal Gout provided to the pixel 30 is at an effective level, the data signal can be written to the pixel 30, so that the pixel displays according to the data signal.

[0049] The display panel provided by the embodiment of the present invention is configured to sequentially cascade N shift register units in a shift register circuit, so that the signal input end of the first-stage shift register unit receives a start signal, and in two adjacent stages of shift register units, the input signal of the latter-stage shift register unit is the shift output signal of the previous-stage shift register unit, and the first clock end of the shift register unit is configured to receive a first clock signal, and the second clock end is configured to receive a second clock signal, so that each shift register unit can output a shift output signal and a gate drive signal according to the input signal, the first clock signal, and the second clock signal, and the shift detection module is configured to be electrically connected to the shift output end of each shift register unit, so that the shift register module can obtain the shift output signal of each shift register unit. Output signal, and in the scanning stage of the scanning cycle, when it is determined that a certain shift register unit does not include a valid level in the output shift output signal due to electrostatic interference, it is determined that the shift register unit cannot normally output the valid level of the shift output signal due to the electrostatic interference, and at this time, a restart signal including the valid level is provided to one of the shift register units, so that the shift register unit can output the valid level of the shift output signal under the control of the restart signal, and the subsequent shift register units cascaded with it can all output the valid level of the shift output signal normally, which can effectively reduce the area range of abnormal display due to electrostatic interference, thereby improving the abnormal flickering problem of the display panel turning black instantly during electrostatic interference, and effectively improving the display effect.

[0050] Optional, Figure 6 is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention, such as Figure 6 As shown, m <i。

[0051] Specifically, when the shift output signal Vnext(i) output by the i-th shift register unit G(i) does not include a valid level, the shift detection module 20 can output a restart signal Vst(m) including a valid level to the m-th shift register unit G(m) located before the i-th shift register unit G(i), so that before the static electricity dissipates, the m-th shift register unit G(m) to the i-1-th shift register unit G(i-1) can cyclically output the shift output signal Vnext(i) of the shift register unit G(m) and the shift register unit G(i-1) of the i-1-th shift register unit G(i-1). The effective level of the shift output signal Vnext(i-1) of the first-stage shift register unit G(i-1) can make the i-th-stage shift register unit G(i) output the shift output signal Vnext(i) including the effective level, so that the i-th-stage shift register unit G(i) to the N-th-stage shift register unit G(n) can output the shift output signal Vnext and the gate drive signal Gout with the effective level shifted in sequence. In this way, it is not necessary to start driving from the shift register unit G (e.g., the first-stage shift register unit G(1)) that is far before the i-th-stage shift register unit G(i) after the static electricity dissipates, and the i-th-stage shift register unit G(i) to the N-th-stage shift register unit G(n) can be quickly controlled to restore the normal output of the shift output signal Vnext and the gate drive signal Gout after the static electricity dissipates, thereby reducing the abnormal display time of the display panel 100 and effectively improving the display effect.

[0052] Exemplarily, it can be set to im=1, im=2, or im≥3. When m≥1 is satisfied, the embodiment of the present invention does not specifically limit the value of m. In one embodiment, the difference between i and m can be set to be smaller, such as im=1 or im=2, so that the i-th shift register unit G(i) is closer to the m-th shift register unit G(m), thereby further reducing the abnormal display time of the display panel 100, thereby effectively improving the display effect. In another embodiment, the difference between i and m can be set to be larger, for example, im≥3, so that the i-th shift register unit G(i) is far away from the m-th shift register unit G(m). In this way, it is possible to avoid electrostatic instability and interference ranging too large, so that the m-th shift register unit G(m) cannot output the effective level of the shift output signal Vnext(m) under the control of the restart signal Vst(m), thereby failing to effectively solve the abnormal flicker problem of the display panel 100 turning black instantly due to electrostatic interference. That is, the difference between i and m is set to be larger, which can exceed the range of electrostatic interference, and can ensure that the m-th shift register unit G(m) outputs the effective level of the shift output signal Vnext(m) under the control of the restart signal Vst(m), which can ensure that the time of abnormal display of the display panel 100 is reduced.

[0053] Optional, Figure 7 is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention, such as Figure 7 As shown, m=i. In this way, after the static electricity dissipates, the first shift register unit G (i.e., the i-th shift register unit G(i)) with an abnormal output can immediately output the effective level of the shift output signal Vnext(i), so that the i-th shift register unit G(i) to the N-th shift register unit G(n) can immediately restore the normal output of the shift output signal Vnext and the gate drive signal Gout after the static electricity is restored, thereby further reducing the abnormal display time of the display panel 100, thereby effectively improving the display effect.

[0054] Optional, reference Figure 3 , Figure 6 or Figure 7 , among the N shift register units G arranged in cascade, the detection signal line LA electrically connected to the k-th shift register unit G(k) is the first detection signal line LA1, and the detection signal line LA electrically connected to the k+1-th shift register unit G(k+1) is the second detection signal line LA2; wherein, 1≤k<N, and k is an integer; in the non-display area A2, the first detection signal line LA1 and the second detection signal line LA2 are arranged adjacent to each other.

[0055] Specifically, the k-th shift register unit G(k), the k+1-th shift register unit G(k+1), the first detection signal line LA1, and the second detection signal line LA2 are not specifically shown in the figure. It can be understood that the k-th shift register unit G(k) can be any one of the 1-th shift register unit G(1) to the N-1-th shift register unit G(n-1). For example, if k=m, the detection signal line electrically connected to the m-th shift register unit G(m) is the first detection signal line LA1, and the detection signal line electrically connected to the m+1-th shift register unit G(m+1) is the second detection signal line LA2. In this way, by arranging the two detection signal lines LA electrically connected to the adjacent two-stage shift register units G adjacent to each other, the detection signal lines LA can be made not to overlap in the non-display area A2, which can effectively avoid signal interference, and is beneficial to improving the accuracy of the obtained shift output signals Vnext and the accuracy of the output restart signals Vst.

[0056] Optional, Figure 8 is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention, such as Figure 8As shown, each scanning signal line LG is electrically connected to two shift register units G respectively; the non-display area A2 includes a first non-display sub-area A21 and a second non-display sub-area A22 located on opposite sides of the display area A1; the two shift register units G electrically connected to the same scanning signal line LG are located in the first non-display sub-area A21 and the second non-display sub-area A22 respectively; the shift register units G located in the first non-display sub-area A21 are cascaded in sequence, and the shift register units G located in the second non-display sub-area A22 are cascaded in sequence.

[0057] Specifically, by setting each scanning signal line LG to be electrically connected to two shift register units G respectively, the gate drive signal Gout can be provided to the same scanning signal line LG through the two shift register units G. By setting the two shift register units G electrically connected to the same scanning signal line LG to be located in the non-display area A2 on opposite sides of the display area A1, the shift register circuit 10 can be symmetrically distributed in the display panel 100, which is beneficial to the aesthetic design of the display panel 100. In one embodiment, the two shift register units G electrically connected to the same scanning signal line LG output the gate drive signal Gout synchronously, that is, the time of outputting the effective level is the same. In this way, when one scanning signal line LG is electrically connected to only one shift register unit G, it can be avoided that the gate drive signal Gout has a voltage drop due to the resistance of the scanning signal line LG, thereby causing the pixels 30 located in the same row to display unevenly, and the display uniformity can be effectively improved. Furthermore, when electrostatic interference occurs in one of the first non-display sub-area A21 and the second non-display sub-area A22, the shift register units G at all levels in the other non-display sub-area can still output the gate drive signal Gout normally, and will not cause the display panel to flicker more obviously, which is beneficial to improving the display effect, and the shift detection module 20 can provide a restart signal Gout to the shift register unit G in the non-display sub-area where electrostatic interference occurs, so that the pixel 30 with electrostatic interference can resume display as soon as possible, thereby further improving the problem of abnormal flickering of the display panel 100 due to electrostatic interference, and further improving the display effect of the display panel.

[0058] Exemplarily, in the present embodiment, the display area A1 may include N rows of pixels 30, the first non-display sub-area A21 includes N shift register units G cascaded in sequence, and the second non-display sub-area A22 includes N shift register units G cascaded in sequence, so that the shift register units G at each level located in the first non-display sub-area A21 and the shift register units G at each level located in the second non-display sub-area A22 drive the rows of pixels 30 accordingly.

[0059] Optional, Fig. 9 is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention, such as Fig. 9As shown, the non-display area A2 includes a first non-display sub-area A21 and a second non-display sub-area A22 located on opposite sides of the display area A1; the scanning signal line LG electrically connected to the pixels 30 of the odd rows is the first scanning signal line LG1, and the scanning signal line electrically connected to the pixels 30 of the even rows is the second scanning signal line LG2; the shift register unit G electrically connected to the first scanning signal line LG1 is located in the first non-display sub-area A21, and the shift register unit G electrically connected to the second scanning signal line LG2 is located in the second non-display sub-area A22; the shift register units G located in the first non-display sub-area A21 are cascaded in sequence, and the shift register units G located in the second non-display sub-area A22 are cascaded in sequence. Or, Fig.10 is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention, such as Fig.10 As shown, the shift register units G electrically connected to the pixels 30 in each row are cascaded in sequence.

[0060] Specifically, refer to Fig. 9 By setting the first scanning signal line LG1 to be electrically connected to the pixels 30 of the odd rows, the second scanning signal line LG2 to be electrically connected to the pixels 30 of the even rows, and making the shift register unit G electrically connected to the first scanning signal line LG1 located in the first non-display sub-area A21, and the shift register unit G electrically connected to the second scanning signal line LG2 located in the second non-display sub-area A22, each shift register unit G located in the first non-display sub-area A21 can provide a gate drive signal Gout to the pixels 30 of the odd rows, and each shift register unit G located in the second non-display sub-area A22 can provide a gate drive signal Gout to the pixels 30 of the even rows. At this time, the shift register units G of various levels electrically connected to the odd-numbered row pixels 30 in the first non-display sub-area A21 are G(1), G(3), ..., G(i), G(i+2), ..., G(x), respectively, where i and x are both odd numbers greater than zero; the shift register units G of various levels electrically connected to the even-numbered row pixels 30 in the second non-display sub-area A22 are G(2), G(4), ..., G(i+1), G(i+3), ..., G(x+1), respectively, where x+1=2*N, and N is an odd number, so that the first non-display sub-area A21 and the second non-display sub-area A22 have N cascaded shift register units G respectively.

[0061] Taking the occurrence of static electricity in the first non-display sub-area A21 as an example, when static electricity occurs in the first non-display sub-area A21 and causes one of the shift register units G (e.g., the i-th shift register unit G(i)) to be unable to output the effective level of the shift output signal Vnext, the i+1-th shift register unit G(i+1) located in the second non-display sub-area A22 can still normally output the effective level of the shift output signal Vnext, so that before the static electricity dissipates, the i-th shift register unit G(i) to the N-th shift register unit G(n) can still output the effective level of the shift output signal Vnext. Half of the shift register units G can normally output the effective level of the shift output signal Gout, so as to at least drive the pixels 30 of the even-numbered rows in the display area A1 to display normally, and can improve the abnormal flickering phenomenon during the electrostatic interference process, and the shift detection module 20 can provide a restart signal Gout to the shift register unit G in the first non-display sub-area A21 where the electrostatic interference occurs, so that the pixels 30 of the odd-numbered rows can resume display as soon as possible, thereby further improving the problem of abnormal flickering of the display panel 100 due to electrostatic interference, and further improving the display effect of the display panel. When electrostatic interference occurs in the second non-display sub-area A22, the principle is the same as the above principle, which will not be repeated here.

[0062] refer to Fig.10 , the shift register units G electrically connected to each row of pixels in the first non-display sub-area A21 and the second non-display sub-area A22 are sequentially cascaded. Taking the occurrence of electrostatic interference in the first non-display sub-area A21 as an example, when the electrostatic interference occurs in the first non-display sub-area A21 so that one of the shift register units G (for example, the third-stage shift register unit G(3)) cannot output the effective level of the shift output signal Vnext, the fourth-stage shift register unit G(4) located in the second non-display sub-area A22 can still normally output the effective level of the shift output signal Vnext(4), so that before the static electricity dissipates, the fourth-stage shift register unit G(4) to the Nth-stage shift register unit G(n) can all normally output the effective level of the shift output signal Gout, which can further reduce the number of pixel rows that do not perform signal scanning, and can effectively solve the abnormal flickering phenomenon during the electrostatic interference process. At this time, m<i or m=i can be set, and m is an odd number, so that the few rows of pixels 30 with abnormal display in odd rows can resume display as soon as possible, thereby further improving the problem of abnormal flickering of the display panel 100 and further improving the display effect of the display panel 100.

[0063] The principle when electrostatic interference occurs in the second non-display sub-area A22 is the same as the above principle. For example, when electrostatic interference occurs in the first non-display sub-area A21, the second-stage shift register unit G(2) (i is an even number) normally outputs the effective level of the shift output signal Vnext(2), and the fourth-stage shift register unit G(4) cannot output the effective level of the shift output signal Vnext(4), so that the fifth-stage shift register unit G(5) located in the first non-display sub-area A21 can still normally output the effective level of the shift output signal Vnext(5), so that before the static electricity dissipates, the fifth-stage shift register unit G(5) to the Nth-stage shift register unit G(n) can all normally output the effective level of the shift output signal Gout, which can further reduce the number of pixel rows that do not perform signal scanning, and can effectively solve the abnormal flicker phenomenon during the electrostatic interference process. At this time, m<i or m=i, and m is an even number, can effectively solve the abnormal flicker phenomenon during the electrostatic interference process.

[0064] Optional, reference Figure 8 , Fig. 9 or Fig.10 In the first non-display sub-area A21, two detection signal lines LA respectively connected to two adjacent shift register units G are arranged adjacent to each other; and in the second non-display sub-area A22, two detection signal lines LA respectively connected to two adjacent shift register units G are arranged adjacent to each other. In this way, the detection signal lines LA can be made not to overlap in the non-display area A2, signal interference can be effectively avoided, and the accuracy of each shift output signal Vnext obtained can be improved, as well as the accuracy of each output restart signal Vst can be improved.

[0065] Optional, Fig.11 and Fig.12 is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention, referring to Fig.11 or Fig.12 , the display panel further includes a driver IC 40, and the shift detection module 20 is integrated in the driver IC 40. In this way, the electrostatic interference condition of each shift register unit G can be detected by the driver IC 40, and a restart signal Vst is provided to the corresponding shift register unit G according to the detection condition, which is conducive to simplifying the circuit structure of the display panel 100. At this time, the first clock signal line Ck1 and the second clock signal line Ck2 can both be electrically connected to the driver IC 40, and the driver IC 40 provides the first clock signal ck1 to the first clock signal line Ck1, and the driver IC 40 provides the first clock signal ck2 to the second clock signal line Ck2. In addition, the driver IC 40 can provide a start signal to the phase shift register circuit 10.

[0066] Optional, Fig.13is a structural diagram of a shift register unit provided by an embodiment of the present invention, such as Fig.13 As shown, the shift register unit G includes a latch module 11, a NAND logic operation module 12 and a buffer module 13; the signal input end of the latch module 11 receives the input signal Vin, the clock input end of the latch module 11 receives the first clock signal ck1, and the output end of the latch module 11 outputs the shift output signal Vnext; the input end of the NAND logic operation module 12 is electrically connected to the output end of the latch module 11, the clock input end of the NAND logic operation module 12 receives the second clock signal ck2, and the output end of the NAND logic operation module 12 is electrically connected to the buffer module 13; the output end of the buffer module 13 is used to output the gate drive signal Gout.

[0067] Specifically, the first clock signal ck1 and the second clock signal ck2 can be synchronous signals, that is, they output a high level and a low level at the same time. At this time, one of the clock input terminal of the latch module 11 and the clock input terminal of the NAND logic operation module 12 can be set as the first clock terminal CK1, and the other can be set as the second clock terminal CK2. The latch module 11 is used to transmit and latch the input signal Vin. Exemplarily, in one embodiment, after the effective level of the input signal Vin is written to the latch module 11, when the first clock signal ck1 jumps to the enable level, the latch module 11 outputs the latched effective level as the shift output signal Vnext, so that the shift output signal Vnext jumps to the effective level; the NAND logic operation module 12 outputs the initial gate drive signal Gout when the shift output signal Vnext is at the effective level and the second clock signal ck2 is at the enable level, and the buffer module 13 stabilizes the initial gate drive signal Gout and outputs the gate drive signal Gout to the scanning signal line LG.

[0068] Optional, Fig.14 is a structural diagram of a shift register unit provided by an embodiment of the present invention, such as Fig.14As shown, the shift register unit G includes: a first control module 14, a charge pump module 15, a second control module 16 and an output module 17; in the same shift register unit G: the first control module 14 receives the input signal Vin and the first clock signal ck1, and controls the signal of the first node N1; the charge pump module 15 receives the second clock signal ck2, and controls the coupling amount to the first node N1; the second control module 16 receives at least the signal of the first node N1, the first clock signal ck1, the second clock signal ck2, the first level signal Vgl and the second level signal Vgh, and controls the signal of the second node N2; the output module 17 receives the signal of the first node N1, the signal of the second node N2, the first level signal Vgh and the second level signal Vgl, and controls the shift output signal Vnext; the shift output signal Vnext is multiplexed as the gate drive signal Gout.

[0069] Specifically, the first control module 14 is electrically connected to the signal input terminal VIN and the first clock terminal CK1, and is used to receive the input signal Vin through the signal input terminal VIN, and receive the first clock signal ck1 through the first clock terminal CK1, so as to control the signal of the first node N1 according to the input signal Vin and the first clock signal ck. The charge pump module 15 is electrically connected to the second clock terminal CK2, and is used to receive the second clock signal ck2 through the second clock terminal CK2, so as to control the coupling amount to the first node N1 according to the second clock signal ck2. The second control module 16 is electrically connected to the first clock terminal CK1, the second clock terminal CK2 and the first level terminal VGL, and is used to receive the first clock signal ck1 through the first clock terminal CK1, the second clock signal ck2 through the second clock terminal CK2, and the first level signal Vgl through the first level terminal VGL, so as to control the signal of the second node N2 according to the first clock signal ck1, the second clock signal ck and the first level signal Vgl. The output module 17 is electrically connected to the first node N1, the second node N2, the first level terminal VGL and the second level terminal VGH, and can control the shift output signal Vnext (i.e., the gate drive signal Gout) by the signal of the first node N1, the signal of the second node N2, the first level signal Vgh and the second level signal Vgl.

[0070] Among them, the first level signal Vgl of the first level terminal VGL and the second level signal Vgh of the second level terminal VGH can be two fixed signals with opposite polarities, for example, when the first level signal Vgl of the first level terminal VGL is a low level signal, the second level signal Vgh of the second level terminal VGH can be a high level signal; conversely, when the first level signal Vgl of the first level terminal VGL is a high level signal, the second level signal Vgh of the second level terminal VGH can be a low level signal. It can be understood that the first level signal Vgl of the first level terminal VGL and the second level signal Vgh of the second level terminal VGH can be set as needed, and the embodiment of the present invention does not specifically limit this. In the absence of special instructions, the following embodiments are all exemplified by taking the first level signal Vgl as a low level signal and the second level signal Vgh as a high level signal as an example. Among them, the first level signal Vgl is preferably the invalid level of the gate drive signal Gout and the shift output signal Vnext, and the second level signal Vgh is preferably the valid level of the gate drive signal Gout and the shift output signal Vnext.

[0071] In an optional embodiment, Fig.15 is a schematic diagram of the structure of another shift register unit provided by an embodiment of the present invention, referring to Fig.15 In the same shift register unit G, the first control module 14 may include a first transistor T1, wherein a gate of the first transistor T1 is electrically connected to the first clock terminal CK1, a first electrode of the first transistor T1 is electrically connected to the signal input terminal IN, and a second electrode of the first transistor T1 is electrically connected to the first node N1. When the first clock signal ck1 of the first clock terminal CK1 is an effective level capable of controlling the first transistor T1 to be turned on, a signal received by the signal input terminal IN can be transmitted to the first node N1 through the first transistor T1, and when the first clock signal ck1 of the first clock terminal CK1 is an invalid level for controlling the first transistor T1 to be turned off, a signal received by the signal input terminal IN cannot be transmitted to the first node N1 through the first transistor T1.

[0072] Continue to refer Fig.15The charge pump module 15 includes a first capacitor C1, which is electrically connected between the second clock signal terminal CK2 and the first node N1. When the second clock signal ck2 of the second clock signal terminal CK2 jumps to an invalid level (e.g., a high level), the potential of the first node N1 is the same as the invalid level of the second clock signal ck2 through the coupling effect of the first capacitor C1. Similarly, when the second clock signal ck2 of the second clock signal terminal CK2 jumps to an effective level (e.g., a low level), the potential of the first node N1 is the same as the effective level of the second clock signal ck2 through the coupling effect of the first capacitor C1. Since the second clock signal ck2 only changes from an invalid level to a valid level once when the gate drive signal Gout output by the shift register unit 10 changes from an invalid level to a valid level, and only changes from a valid level to an invalid level once during the period when the gate drive signal Gout remains at a valid level, the first capacitor C1 will not couple the valid level of the second clock signal ck2 to the first node N1 during the period when the gate drive signal Gout remains at a valid level, thereby ensuring that the potential of the first node N1 can be maintained at an invalid level during the period when the gate drive signal Gout remains at a valid level, so that the scanning signal gate drive signal Gout output by the register unit G remains stable.

[0073] Continue to refer Fig.15, the second control module 16 includes a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5 and a second capacitor C2. Among them. The gate of the second transistor T2 is electrically connected to the first node N1, the first electrode of the second transistor T2 is electrically connected to the first clock terminal CK, the second electrode of the second transistor T2 is electrically connected to the second electrode of the third transistor T3, the gate of the fourth transistor T4, and the first end of the second capacitor C2 are electrically connected to the third node N3, the gate of the third transistor T3 is electrically connected to the first clock terminal CK, the first electrode of the third transistor T3 is electrically connected to the first level terminal VGL, the second end of the second capacitor C2 is electrically connected to the second electrode of the fourth transistor and the first electrode of the fifth transistor T5 are electrically connected to the fourth node N4, the first electrode of the fourth transistor T4 and the gate of the fifth transistor T5 are both electrically connected to the second clock terminal CK2, and the second electrode of the fifth transistor T5. In this way, the second transistor T2 can be turned on or off under the control of the potential of the first node N1, and transmits the first clock signal ck of the first clock terminal CK to the third node N3 when it is turned on; the third transistor T3 can be turned on or off under the control of the first clock signal ck, and transmits the first level signal Vgl of the first level terminal VGL to the third node N3 when it is turned on; the fourth transistor T4 can be turned on or off under the control of the potential of the third node N3, and transmits the second clock signal xck of the second clock terminal CK2 to the fourth node N4 when it is turned on; the fifth transistor T5 can be turned on or off under the control of the second clock signal xck, and transmits the potential of the fourth node N4 to the second node N2 when it is turned on, so that the potential of the second node N2 is an enable level; due to the action of the second capacitor C2, the potential of the second node N2 can be more stably maintained at an effective level.

[0074] Continue to refer Fig.15, the output module 17 includes a sixth transistor T6, a seventh transistor T7 and a third capacitor C3. The gate of the sixth transistor T6 and the first end of the third capacitor C3 are electrically connected to the second node N2. The second end of the third capacitor C3 and the first electrode of the sixth transistor T6 are both electrically connected to the second level end VGH, the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 are both electrically connected to the signal output end GOUT, the first electrode of the seventh transistor T7 is electrically connected to the first level end VGL, and the gate of the first transistor T1 is electrically connected to the first node N1. When the potential of the first node N1 is an effective level that can control the seventh transistor T7 to be turned on, the first level signal Vgl of the first level end VGL is transmitted to the signal output end GOUT through the seventh transistor T7; when the potential of the first node N1 is an invalid level that controls the seventh transistor T7 to be turned off, the first level signal Vgl of the first level end VGL cannot be transmitted to the signal output end GOUT through the seventh transistor T7. When the potential of the second node N2 is an effective level that can control the sixth transistor T6 to be turned on, the second level signal Vgh of the second level terminal VGH is transmitted to the signal output terminal OUT through the sixth transistor T6; when the potential of the second node N2 is an invalid level that controls the sixth transistor T6 to be turned off, the second level signal Vgh of the second level terminal VGH cannot be transmitted to the signal output terminal OUT through the sixth transistor T6.

[0075] It can be understood that each transistor in the shift register unit G can be an N-type transistor or a P-type transistor. When each transistor is an N-type transistor, the effective level that controls the conduction of the transistor is a high level. When each transistor is a P-type transistor, the effective level that controls the conduction of the transistor is a low level. The type of transistor can be set according to needs, and the embodiment of the present invention does not specifically limit this.

[0076] The working process of each shift register unit G is similar, and they are only shifted sequentially in timing. Therefore, for the convenience of explanation, here, each transistor in each shift register unit G is a P-type transistor, and only the working process of one stage of the shift register unit G is taken as an example for exemplary explanation.

[0077] Fig.16 is a driving timing diagram of a shift register unit provided by an embodiment of the present invention, combined with reference to Fig.15 and Fig.16 , take the working process of the shift register unit G as an example to illustrate, combined with reference Figure 2 and Figure 3In the stage t1-t2, the start signal STV received by the signal input terminal IN of the stage shift register unit G is at a high level, the second clock signal ck2 received by the second clock terminal CK2 is at a high level, and the first clock signal ck1 received by the first clock terminal CK1 is at a low level, so that the first transistor T1 in the first control module 14 is turned on under the control of the first clock signal ck1, and the high level of the input signal Vin is transmitted to the first node N1, and the potential of the first node N1 is at a high level. Since the second clock signal ck2 remains at a high level in the stage t1-t2, the charge amount coupled by the charge pump module 10b to the first node N1 remains unchanged. In the second control module 16, the second transistor T2 is disconnected under the control of the first node N1, the third transistor T3 is turned on under the control of the first clock signal ck1, the first level signal Vgl is transmitted to the third node N3 through the third transistor T3, the third node N3 is at a low level, so that the fourth transistor T4 is turned on, the high level signal of the second clock signal ck2 is written to the first electrode of the fifth transistor T5 and controls the fifth transistor T5 to be disconnected, so that the first level signal Vgl of the first level end VGL cannot be transmitted to the second node N2, so that the potential of the second node N2 remains at the high level of the previous stage. Since the potentials of the first node N1 and the second node N2 are both high levels, the gate drive signal Gout output by the output module 17 of the shift register unit G remains at the low level of the previous stage.

[0078] In the stage t3-t4, the first clock signal ck1 received by the first clock terminal CK1 of the shift register unit G is an invalid level, and the second clock signal ck2 received by the second clock terminal CK2 thereof jumps to a low level. The first transistor T1 in the first control module 14 is turned off under the control of the first clock signal ck1, and the first node N1 remains at a high level in the previous stage. In the second control module 16, the second transistor T2 is turned off, and the third node N3 remains at a low level in the previous stage, so that the low level of the second clock signal ck2 is transmitted to the first electrode of the fifth transistor T5 through the fourth transistor T4, and the low level of the second clock signal ck2 controls the fifth transistor T5 to turn on, thereby transmitting the first level signal Vgl of the first level terminal VGL to the second node N2, and the potential of the second node N2 changes from a high level to a low level, so that the output module 17 transmits the second level signal Vgh of the second level terminal VGH to the signal output terminal GOUT according to the low level signal of the second node N2, that is, at this time, the gate drive signal Gout output by the shift register unit G is a high level.

[0079] In the stage t5-t6, the input signal Vin remains at a high level, the first clock signal ck1 is at a low level, and the second clock signal ck2 is at a high level, so that the first node N1 is at a high level and the second node N2 remains at the low level of the previous stage. At this time, the gate drive signal Gout output by the shift register unit G is the high level of the previous stage.

[0080] In the stage from t7 to t8, the first clock signal ck1 is at a high level, the low level of the input signal Vin cannot be written to the first node N1, the first node N1 maintains the high level of the previous stage, and the second node N2 maintains the low level of the previous stage. At this time, the gate drive signal Gout output by the shift register unit G is the high level of the previous stage.

[0081] In the stage T9~t10, the first clock signal ck1 is at a low level, the low level of the input signal Vin is written to the first node N1, the output module 17 outputs the first level signal Vgl as the gate drive signal Gout, the low level signal of the first node N1 controls the second transistor T2 to turn on, the low level of the first clock signal ck1 is written to the third node N3, the fourth transistor T4 is turned on, so that the high level of the second clock signal ck2 is written to the N2 node, and the output module 17 cannot transmit the first level signal Vgl to the driving output terminal GOUT, that is, at this time, the gate drive signal Gout output by the shift register unit G is at a low level.

[0082] After time t11, the input signal Vin remains at a low level, and the transition of the first clock signal ck1 and the second clock signal ck2 does not affect the gate driving signal Gout, so that the gate driving signal Gout remains at a low level.

[0083] It should be noted that Figure 13 to Figure 15 The structures of several shift register units are provided by way of example only, but not all of them are included. Under the premise that the core inventive point of the embodiment of the present invention can be realized, the embodiment of the present invention does not limit the specific structure of the pixel circuit.

[0084] Based on the same inventive concept, an embodiment of the present invention further provides a display device, which includes the display panel provided by any embodiment of the present invention. Therefore, the display device provided by the embodiment of the present invention includes the technical features of the display panel provided by any embodiment of the present invention, and can achieve the beneficial effects of the display panel provided by any embodiment of the present invention. The similarities can be referred to the above description of the display panel provided by the embodiment of the present invention, and will not be repeated here.

[0085] For example, Fig.17 is a schematic diagram of the structure of a display device provided by an embodiment of the present invention, such as Fig.17As shown, the display device 200 includes the display panel 100 provided in the embodiment of the present invention. The display device 200 provided in the embodiment of the present invention can be any electronic product with a display function, including but not limited to the following categories: mobile phones, televisions, laptops, desktop displays, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, medical equipment, industrial control equipment, touch interactive terminals, etc., and the embodiment of the present invention does not specifically limit this.

[0086] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0087] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A display panel, characterized in that: include: A shift register circuit and a shift detection module; the shift register circuit comprises a plurality of shift register units; wherein N shift register units are cascaded; N ≥ 2, and N is an integer; The shift register unit comprises a signal input terminal, a first clock terminal, a second clock terminal, a shift output terminal and a driving output terminal; the first clock terminal is used to receive a first clock signal, and the second clock terminal is used to receive a second clock signal; In each of the shift register units arranged in cascade, the signal input end of the first stage of the shift register unit receives a start signal; in two adjacent stages of the shift register units, the signal input end of the shift register unit of the latter stage is electrically connected to the shift output end of the shift register unit of the previous stage; the shift register units of each stage are used to output a shift output signal and a gate drive signal according to the first clock signal, the second clock signal and the input signal of the signal input end; The shift detection module is electrically connected to the shift output terminals of the shift register units at each level; a scanning cycle of the display panel includes a scanning phase, during which the shift detection module is used to obtain the shift output signals output by the shift register units at each level, and when the shift output signal output by the i-1th shift register unit includes a valid level, and the shift output signal output by the i-th shift register unit does not include a valid level, provide a restart signal including a valid level to the signal input terminal of the mth shift register unit; i and m are both integers, and 1≤i≤N, 1≤m≤N.

2. The display panel according to claim 1, characterized in that: m>i.

3. The display panel according to claim 1, characterized in that: m <i。 4. The display panel according to claim 1, characterized in that: m=i.

5. The display panel according to claim 1, characterized in that: Also includes a display area and a non-display area surrounding the display area; The shift register circuit and the shift detection module are both located in the non-display area; In the display area, the display panel further includes a plurality of pixels arranged in an array and a plurality of scanning signal lines extending along a first direction and arranged along a second direction; at least part of the pixels in the same row are electrically connected to the same scanning signal line; the scanning signal line is used to transmit the gate driving signal; The non-display area further includes detection signal lines arranged in one-to-one correspondence with each of the shift register units; The shift detection module is electrically connected to the shift output end of each shift register unit through each detection signal line.

6. The display panel according to claim 5, characterized in that: Among the N shift register units arranged in cascade, the detection signal line electrically connected to the k-th shift register unit is a first detection signal line, and the detection signal line electrically connected to the k+1-th shift register unit is a second detection signal line; wherein 1≤k<N, and k is an integer; In the non-display area, the first detection signal line is disposed adjacent to the second detection signal line.

7. The display panel according to claim 5, characterized in that: Each of the scanning signal lines is electrically connected to two of the shift register units respectively; The non-display area includes a first non-display sub-area and a second non-display sub-area located at opposite sides of the display area; The two shift register units electrically connected to the same scan signal line are respectively located in the first non-display sub-area and the second non-display sub-area; The shift register units located in the first non-display sub-area are cascaded in sequence, and the shift register units located in the second non-display sub-area are cascaded in sequence.

8. The display panel according to claim 5, characterized in that: The non-display area includes a first non-display sub-area and a second non-display sub-area located at opposite sides of the display area; The scanning signal lines electrically connected to the pixels in odd-numbered rows are first scanning signal lines, and the scanning signal lines electrically connected to the pixels in even-numbered rows are second scanning signal lines; The shift register unit electrically connected to the first scan signal line is located in the first non-display sub-area, and the shift register unit electrically connected to the second scan signal line is located in the second non-display sub-area; The shift register units located in the first non-display sub-area are cascaded in sequence, and the shift register units located in the second non-display sub-area are cascaded in sequence; Alternatively, the shift register units electrically connected to the pixels in each row are cascaded in sequence.

9. The display panel according to any one of claims 7 or 8, characterized in that: In the first non-display sub-area, two detection signal lines respectively connected to two adjacent shift register units are arranged adjacent to each other; Furthermore, in the second non-display sub-area, two detection signal lines respectively connected to two adjacent shift register units are arranged adjacent to each other.

10. The display panel according to claim 1, characterized in that: It also includes driver IC; The displacement detection module is integrated in the driving IC.

11. The display panel according to claim 1, characterized in that: The shift register unit includes a latch module, a NAND logic operation module and a buffer module; The signal input end of the latch module receives an input signal, the clock input end of the latch module receives a first clock signal, and the output end of the latch module outputs the shift output signal; The input end of the NAND logic operation module is electrically connected to the output end of the latch module, the clock input end of the NAND logic operation module receives the second clock signal, and the output end of the NAND logic operation module is electrically connected to the buffer module; The output end of the buffer module is used to output the gate driving signal.

12. The display panel according to claim 1, characterized in that: The shift register unit comprises: a first control module, a charge pump module, a second control module and an output module; In the same shift register unit: The first control module receives the input signal and the first clock signal, and controls the signal of the first node; The charge pump module receives the second clock signal and controls the coupling amount to the first node; The second control module receives at least the signal of the first node, the first clock signal, the second clock signal, the first level signal and the second level signal, and controls the signal of the second node; The output module receives the signal of the first node, the signal of the second node, the first level signal and the second level signal, and controls the shift output signal; The shift output signal is multiplexed as the gate driving signal.

13. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 12.

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