High and low frequency separation signal conditioning circuit for peak power probe

Abstract

The invention discloses a high and low frequency separation signal conditioning circuit for a peak power probe, and belongs to the technical field of testing. The circuit comprises a signal amplification circuit and a filter circuit. The problems of gain, bandwidth and noise are solved; higher common-mode rejection capability is obtained by using the fully differential amplifier, the symmetry of differential signals can be better ensured, and the signal output common-mode voltage can be conveniently adjusted; the bandwidth of the whole circuit is not limited by the first-stage operational amplifier, high bandwidth is obtained under high gain, and noise is as low as possible; common-mode interference can be better suppressed by adopting the fully differential amplifier, output common-mode voltage can be conveniently adjusted, and the driving capability is high.

Description

Technical Field

[0001] The invention belongs to the field of testing technology, and in particular relates to a high- and low-frequency separation signal conditioning circuit for a peak power probe. Background Art

[0002] In peak power measurement, there is usually a contradiction between the bandwidth and gain of the signal conditioning circuit. The product of the noise gain of the voltage feedback op amp and the bandwidth at the gain is fixed. If the circuit is to obtain a higher bandwidth at a certain gain, it is generally chosen to increase the number of amplifier cascades, and obtain the required gain and bandwidth through multiple stages of amplification, but increasing the number of amplifier stages will usually increase the noise. If you do not want to increase the number of amplifier stages, in order to obtain low noise at a certain gain and bandwidth, a series composite amplifier circuit is usually used to amplify the signal, and the first-stage precision op amp is used to correct the offset drift voltage and noise through inter-stage feedback.

[0003] The existing peak power measurement signal conditioning circuit has certain disadvantages:

[0004] Currently, a series composite amplifier circuit is often used to generate lower noise at a specific gain and bandwidth, but the circuit bandwidth is usually limited by the bandwidth index of the first-stage precision op amp. The bandwidth that the entire circuit can ultimately achieve is basically determined by the bandwidth of the first-stage op amp.

[0005] In order to obtain a higher bandwidth at a certain gain, get rid of the bandwidth limitation of the first-stage precision operational amplifier, and minimize the noise generated by the circuit, the present invention adopts a high-low frequency separation method to design a signal conditioning circuit. Summary of the invention

[0006] In view of the above technical problems existing in the prior art, the present invention proposes a high- and low-frequency separation signal conditioning circuit for a peak power probe, which has a reasonable design, overcomes the shortcomings of the prior art, and has good effects.

[0007] In order to achieve the above object, the present invention adopts the following technical solution:

[0008] A high-low frequency separation signal conditioning circuit for a peak power sensor, comprising a signal amplification circuit and a filtering circuit;

[0009] A signal amplification circuit, configured to amplify a signal; comprising a first precision operational amplifier circuit, a second precision operational amplifier circuit and a fully differential amplifier circuit;

[0010] A filter circuit, configured to filter a signal; comprising a seventh resistor R7, a fourteenth resistor R14, a fifth capacitor C5, a sixth capacitor C6 and a seventh capacitor C7;

[0011] The first precision operational amplifier circuit includes a first precision operational amplifier A1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first capacitor C1, and a second capacitor C2;

[0012] One end of the first resistor R1, one end of the sixth resistor R6, and one end of the first capacitor C1 form a common end connected to the non-inverting input end of the first precision operational amplifier A1 through a line; one end of the second resistor R2 and one end of the third resistor R3 form a common end connected to the inverting input end of the first precision operational amplifier A1 through a line; one end of the fourth resistor R4 is connected to the output end of the first precision operational amplifier A1 through a line; the other end of the first capacitor C1 and one end of the fifth resistor R5 are connected through a line; the other end of the third resistor R3 and one end of the second capacitor C2 are connected through a line;

[0013] The second precision operational amplifier circuit includes a second precision operational amplifier A2, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a third capacitor C3, and a fourth capacitor C4;

[0014] One end of the eighth resistor R8, one end of the third capacitor C3, and one end of the thirteenth resistor R13 form a common end, which are connected to the in-phase input terminal of the first precision operational amplifier A2 through a line; one end of the ninth resistor R9 and one end of the tenth resistor R10 form a common end, which are connected to the inverting input terminal of the first precision operational amplifier A2 through a line; one end of the eleventh resistor R11 is connected to the output terminal of the first precision operational amplifier A2 through a line; the other end of the tenth resistor R10 and one end of the fourth capacitor C4 are connected through a line; the other end of the third capacitor C3 and one end of the twelfth resistor R12 are connected through a line; the other end of the twelfth resistor R12, the other end of the eleventh resistor R11, and the other end of the fourth capacitor C4 form a common end, which are connected to the inverting input terminal of the full differential amplifier A3 through a line; the other end of the thirteenth resistor R13 is connected to the in-phase output terminal of the full differential amplifier A3 through a line;

[0015] The fully differential amplifier circuit includes a fully differential amplifier A3, a sixth resistor R6 and a thirteenth resistor R13;

[0016] The other end of the fifth resistor R5, the other end of the fourth resistor R4, and the other end of the second capacitor C2 form a common end connected to the non-inverting input end of the full differential amplifier A3 through a line; the other end of the sixth resistor R6 and one end of the seventh resistor R7 form a common end connected to the inverting output end of the full differential amplifier A3 through a line; one end of the fourteenth resistor R14 is connected to the non-inverting output end of the full differential amplifier A3 through a line; the other end of the seventh resistor R7, one end of the fifth capacitor C5, and one end of the sixth capacitor C6 form a common end connected to a differential inverting output of the signal conditioning circuit through a line; the other end of the sixth capacitor C6 and one end of the seventh capacitor C7 are connected through a line; the other end of the fourteenth resistor R14, the other end of the fifth capacitor C5, and the other end of the seventh capacitor C7 form a common end connected to a differential non-inverting output of the signal conditioning circuit through a line;

[0017] The positive signal is divided into two paths after passing through the first resistor R1: one path enters the non-inverting input terminal of the first precision operational amplifier A1, and remains in phase after being amplified and output. The output signal reaches the input terminal of the fully differential amplifier A3 after passing through the fourth resistor R4, and is fed back to the inverting input terminal of the first precision operational amplifier A1 through the second capacitor C2 and the third resistor R3. The inverting input terminal of the first precision operational amplifier A1 is grounded through the second resistor R2; the other path is transmitted to the feedback point of the first precision operational amplifier A1 and the input terminal of the fully differential amplifier A3 through the first capacitor C1 and the fifth resistor R5, and is mixed and superimposed with the output signal of the first precision operational amplifier A1 to enter the fully differential amplifier A3; the signals of the two paths of the positive signal both enter the fully differential amplifier A3 in phase, are inverted after being amplified by the fully differential amplifier A3, and then return to the non-inverting input terminal of the first precision operational amplifier A1 through the sixth resistor R6.

[0018] Preferably, the entire signal conditioning circuit is differentially symmetrical, and symmetrical resistors and capacitors play the same role.

[0019] Preferably, the first precision operational amplifier A1 is a common-mode proportional amplifier configured to process DC, low-frequency signals; the fully differential amplifier A3 is configured to process high-frequency signals, provide high bandwidth and high common-mode rejection ratio, process differential signals, reduce common-mode interference, and change the common-mode voltage of the differential output by adjusting Vocm.

[0020] Preferably, the non-inverting input terminal of the first precision operational amplifier A1 is both the point where the positive signal is divided into two paths and the summing point where the fully differential amplifier A3 is fed back to the first precision operational amplifier A1, and the phase of the fully differential amplifier A3 fed back to this point is opposite to the phase of the positive signal, forming inter-stage negative feedback of the two-stage amplifier, and the first precision operational amplifier A1 and the fully differential amplifier A3 both operate in a negative feedback state.

[0021] Preferably, the positive signal is divided into two paths at the in-phase input terminal of the first precision operational amplifier A1, one path is the lower frequency component in the signal, the bandwidth of the first precision operational amplifier A1 is limited, and it can only amplify the lower frequency part of the signal, and the other path is the higher frequency component in the signal, because the first capacitor C1 and the fifth resistor R5 form a high-pass filter, which only allows the higher frequency component in the positive signal to pass; the low-frequency part of the signal is amplified by the in-phase ratio of the first precision operational amplifier A1 and then output to the input terminal of the fully differential amplifier A3, and the high-frequency part of the signal passes through the high-pass filter directly to the input terminal of the fully differential amplifier A3, and the high-frequency signal and the low-frequency signal take different paths to reach the fully differential amplifier A3.

[0022] Preferably, the first resistor R1 is the input resistor of the entire circuit, the sixth resistor R6 is the feedback resistor of the entire circuit, and the gain of the amplifier circuit composed of the first precision operational amplifier A1 and the fully differential amplifier A3 is -R6 / R1; the first capacitor C1 and the fifth resistor R5 form a high-pass filter for separating high and low frequency signals; the second capacitor C2 and the third resistor R3 form intra-stage feedback, which is used to feed back the input signal of the fully differential amplifier A3 to the inverting input terminal of the first precision operational amplifier A1, the second resistor R2 is the inverting input resistor of the first precision operational amplifier A1, and the fourth resistor R4 is used to isolate the output terminal of the first precision operational amplifier A1 from the second capacitor C2, and superimpose the low-frequency signal and the high-frequency signal output by the first precision operational amplifier A1 at the input terminal of the fully differential amplifier A3.

[0023] Preferably, the low-pass filter composed of the seventh resistor R7, the fourteenth resistor R14, the fifth capacitor C5, the sixth capacitor C6 and the seventh capacitor C7 is used to limit the channel bandwidth of the signal conditioning and perform anti-aliasing; the fifth capacitor C5 is a differential mode capacitor used to reduce differential mode interference, and the sixth capacitor C6 and the seventh capacitor C7 are common mode capacitors used to reduce common mode interference.

[0024] Beneficial technical effects brought by the present invention:

[0025] The present invention uses a method for separating and resynthesizing high and low frequencies of signals to solve the gain, bandwidth and noise problems; uses a fully differential amplifier to obtain a higher common-mode suppression capability, can better ensure the symmetry of the differential signal, and facilitates the adjustment of the signal output common-mode voltage; the bandwidth of the entire circuit of the present invention can be free from the limitation of the first-stage operational amplifier, and a high bandwidth can be obtained under high gain, and the noise is as low as possible; the use of a fully differential amplifier can better suppress common-mode interference, facilitate the adjustment of the output common-mode voltage, and has a strong driving capability. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a schematic diagram of a signal conditioning channel circuit of the present invention;

[0027] Figure 2 Schematic diagram of amplitude-frequency characteristics of the signal amplifier circuit when G=20;

[0028] Figure 3 Schematic diagram of the output voltage noise of the signal amplifier circuit when G=20. DETAILED DESCRIPTION

[0029] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0030] Figure 1 Shown is a schematic diagram of the signal conditioning channel circuit of the present invention.

[0031] When the power sensor inputs a pulse modulated signal, the pulse modulated signal is detected and filtered by the microwave component to obtain a differential positive and negative voltage pulse envelope, which is then sent to the signal conditioning circuit for amplification and filtering. The signal conditioning circuit consists of a signal amplification circuit (precision op amps A1, A2 and fully differential amplifier A3) and a filter circuit (R7, R14, C5, C6, C7).

[0032] Taking the flow path of Signal+ as an example, Signal+ is divided into two paths after passing through the first resistor R1: one path enters the non-inverting input terminal of the first precision operational amplifier A1, and remains in phase after being amplified and output. The output signal reaches the input terminal of the fully differential amplifier A3 after passing through the fourth resistor R4, and is fed back to the inverting input terminal of the first precision operational amplifier A1 through the second capacitor C2 and the third resistor R3. The inverting input terminal of the first precision operational amplifier A1 is grounded through the second resistor R2; the other path is transmitted to the feedback point of the first precision operational amplifier A1 and the input terminal of the fully differential amplifier A3 through the first capacitor C1 and the fifth resistor R5, and is mixed and superimposed with the output signal of the first precision operational amplifier A1 to enter the fully differential amplifier A3; the signals of the two paths of the positive signal both enter the fully differential amplifier A3 in phase, are inverted after being amplified by the fully differential amplifier A3, and then return to the non-inverting input terminal of the first precision operational amplifier A1 through the sixth resistor R6. The non-inverting input terminal of the first precision op amp A1 is both the point where Signal+ is divided into two paths and the summing point where the fully differential amplifier A3 feeds back to the first precision op amp A1. The phase of the signal fed back to this point by the fully differential amplifier A3 is opposite to the phase of Signal+, thus forming inter-stage negative feedback of the two-stage amplifier. In this way, both the first precision op amp A1 and the fully differential amplifier A3 operate in a negative feedback state.

[0033] Signal+ is divided into two paths at the in-phase input of the first precision op amp A1. One path is the lower frequency component of the signal. Because the precision op amp A1 has limited bandwidth, it can only amplify the lower frequency part of the signal. The other path is the higher frequency component of the signal. Because C1 and R5 form a high-pass filter, only the higher frequency component of Signal+ is allowed to pass. The low-frequency signal is amplified by the in-phase ratio of the first precision op amp A1 and then output to the input of A3. The high-frequency signal goes directly to the input of the fully differential amplifier A3 through the high-pass filter. The high-frequency signal and the low-frequency signal take different paths to reach the fully differential amplifier A3.

[0034] Since there is inter-stage feedback of R6 between the first precision op amp A1 and the fully differential amplifier A3, the amplification gain of the entire circuit is guaranteed to be constant. Therefore, although Signal+ is divided into high-frequency and low-frequency parts and amplified through different paths, the amplification gain of the high-frequency signal and the low-frequency signal from the in-phase input of the first precision op amp A1 to the output of the fully differential amplifier A3 is basically the same, which ensures that the high-frequency signal and the low-frequency signal can be synthesized. The high and low frequency signals are synthesized at the input of the fully differential amplifier A3. The bandwidth of the fully differential amplifier A3 is sufficient to amplify the high and low frequency signals well. The signal is divided into a high-frequency part and a low-frequency part, and the signal conditioning is performed separately along different paths. Finally, the gain can be guaranteed to be consistent for synthesis. This is the signal conditioning method of the high and low frequency separation path. The signal conditioning principle and process of Signal- are the same.

[0035] R1 is the input resistor of the whole circuit, R6 is the feedback resistor of the whole circuit, and the gain of the amplifier circuit composed of the first precision op amp A1 and the fully differential amplifier A3 is -R6 / R1. C1 and R5 form a high-pass filter, which plays a role in separating high and low frequency paths. The intra-stage feedback composed of C2 and R3 is to feed back the input signal of the fully differential amplifier A3 to the inverting input of the first precision op amp A1, which is conducive to reducing the peaking degree of the amplitude-frequency characteristic of the signal conditioning circuit and improving the frequency response flatness after signal synthesis. R2 is the inverting input resistor of the first precision op amp A1 in-phase proportional amplifier, and is the key to the intra-stage feedback of the first precision op amp A1. R4 isolates the output of the first precision op amp A1 from the capacitor C2 in the circuit, and superimposes the low-frequency signal output by the first precision op amp A1 with the high-frequency signal at the input of the fully differential amplifier A3. The entire signal conditioning circuit is differentially symmetrical, and the symmetrical resistors and capacitors play the same role.

[0036] The first precision op amp A1 is a precision op amp with the characteristics of low bandwidth, low offset and drift, and low noise. The fully differential amplifier A3 is a fully differential amplifier with strong driving capability, high bandwidth, high offset and relatively high noise. The method of high and low frequency separation and resynthesis can combine the DC and low frequency characteristics of the precision op amp with the high frequency characteristics of the fully differential amplifier, and can simultaneously obtain high gain, high bandwidth, low noise, low offset and drift. The first precision op amp A1 processes DC and low frequency signals in the circuit, and the high frequency signals outside the bandwidth of the first precision op amp A1 are directly processed by the fully differential amplifier A3. Therefore, the first stage op amp will not limit the bandwidth of the entire signal amplification circuit. The bandwidth of the entire circuit is determined according to the -3dB bandwidth of the specific model of the fully differential amplifier A3 at different gains. There is inter-stage feedback between the first precision op amp A1 and the fully differential amplifier A3. Within the bandwidth range of the first precision op amp A1, the offset, drift and noise of the entire circuit can be corrected by the first precision op amp A1, thus ensuring that the offset, drift and noise of the entire circuit are as low as possible.

[0037] The second-stage amplifier uses a fully differential amplifier A3 to obtain a higher common-mode rejection ratio, is more conducive to processing differential signals, reduces common-mode interference, and can change the common-mode voltage of the differential output by adjusting Vocm.

[0038] After the signal is output from the fully differential amplifier A3, it enters the low-pass filter composed of R7, R14, C5, C6, and C7. The low-pass filter is used to limit the bandwidth of the signal conditioning channel and can also play an anti-aliasing role. C5 is a differential mode capacitor to reduce differential mode interference, and C6 and C7 are common mode capacitors to reduce common mode interference. In the case of high speed and high sampling rate, a reasonable filter should be designed based on the ADC sampling rate, equivalent input impedance, and stopband attenuation requirements for the filter circuit.

[0039] Figure 2 This is the amplitude-frequency characteristic of the signal amplifier circuit composed of A1, A2, and A3. It can be seen that when G=20 (26dB), the bandwidth can reach 90MHz. Figure 3 This is the output voltage noise of the signal amplifier circuit. It can be seen that when it reaches 50MHz, the output noise is about 300uVrms when G=20. This is the output noise of the signal amplifier circuit. The output noise of the entire signal conditioning circuit also needs to consider the effect of the filter.

[0040] Of course, the above description is not a limitation of the present invention, and the present invention is not limited to the above examples. Changes, modifications, additions or substitutions made by technicians in this technical field within the essential scope of the present invention should also fall within the protection scope of the present invention.

Claims

1. A high- and low-frequency separation signal conditioning circuit for a peak power sensor, characterized in that: Including signal amplification circuit and filtering circuit; A signal amplification circuit, configured to amplify a signal; comprising a first precision operational amplifier circuit, a second precision operational amplifier circuit and a fully differential amplifier circuit; A filter circuit, configured to filter a signal; comprising a seventh resistor R7, a fourteenth resistor R14, a fifth capacitor C5, a sixth capacitor C6 and a seventh capacitor C7; The first precision operational amplifier circuit includes a first precision operational amplifier A1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first capacitor C1, and a second capacitor C2; One end of the first resistor R1, one end of the sixth resistor R6, and one end of the first capacitor C1 form a common end connected to the non-inverting input end of the first precision operational amplifier A1 through a line; one end of the second resistor R2 and one end of the third resistor R3 form a common end connected to the inverting input end of the first precision operational amplifier A1 through a line; one end of the fourth resistor R4 is connected to the output end of the first precision operational amplifier A1 through a line; the other end of the first capacitor C1 and one end of the fifth resistor R5 are connected through a line; the other end of the third resistor R3 and one end of the second capacitor C2 are connected through a line; The second precision operational amplifier circuit includes a second precision operational amplifier A2, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a third capacitor C3, and a fourth capacitor C4; One end of the eighth resistor R8, one end of the third capacitor C3, and one end of the thirteenth resistor R13 form a common end, which are connected to the in-phase input terminal of the first precision operational amplifier A2 through a line; one end of the ninth resistor R9 and one end of the tenth resistor R10 form a common end, which are connected to the inverting input terminal of the first precision operational amplifier A2 through a line; one end of the eleventh resistor R11 is connected to the output terminal of the first precision operational amplifier A2 through a line; the other end of the tenth resistor R10 and one end of the fourth capacitor C4 are connected through a line; the other end of the third capacitor C3 and one end of the twelfth resistor R12 are connected through a line; the other end of the twelfth resistor R12, the other end of the eleventh resistor R11, and the other end of the fourth capacitor C4 form a common end, which are connected to the inverting input terminal of the full differential amplifier A3 through a line; the other end of the thirteenth resistor R13 is connected to the in-phase output terminal of the full differential amplifier A3 through a line; The fully differential amplifier circuit includes a fully differential amplifier A3, a sixth resistor R6 and a thirteenth resistor R13; The other end of the fifth resistor R5, the other end of the fourth resistor R4, and the other end of the second capacitor C2 form a common end connected to the non-inverting input end of the full differential amplifier A3 through a line; the other end of the sixth resistor R6 and one end of the seventh resistor R7 form a common end connected to the inverting output end of the full differential amplifier A3 through a line; one end of the fourteenth resistor R14 is connected to the non-inverting output end of the full differential amplifier A3 through a line; the other end of the seventh resistor R7, one end of the fifth capacitor C5, and one end of the sixth capacitor C6 form a common end connected to a differential inverting output of the signal conditioning circuit through a line; the other end of the sixth capacitor C6 and one end of the seventh capacitor C7 are connected through a line; the other end of the fourteenth resistor R14, the other end of the fifth capacitor C5, and the other end of the seventh capacitor C7 form a common end connected to a differential non-inverting output of the signal conditioning circuit through a line; The positive signal is divided into two paths after passing through the first resistor R1: one path enters the non-inverting input terminal of the first precision operational amplifier A1, and remains in phase after being amplified and output. The output signal reaches the input terminal of the fully differential amplifier A3 after passing through the fourth resistor R4, and is fed back to the inverting input terminal of the first precision operational amplifier A1 through the second capacitor C2 and the third resistor R3. The inverting input terminal of the first precision operational amplifier A1 is grounded through the second resistor R2; the other path is transmitted to the feedback point of the first precision operational amplifier A1 and the input terminal of the fully differential amplifier A3 through the first capacitor C1 and the fifth resistor R5, and is mixed and superimposed with the output signal of the first precision operational amplifier A1 to enter the fully differential amplifier A3; the signals of the two paths of the positive signal both enter the fully differential amplifier A3 in phase, are inverted after being amplified by the fully differential amplifier A3, and then return to the non-inverting input terminal of the first precision operational amplifier A1 through the sixth resistor R6.

2. The high- and low-frequency separation signal conditioning circuit for a peak power sensor according to claim 1, characterized in that: The entire signal conditioning circuit is differentially symmetrical, and the symmetrical resistors and capacitors play the same role.

3. The high- and low-frequency separation signal conditioning circuit for a peak power sensor according to claim 1, characterized in that: The first precision operational amplifier A1 is a common-phase proportional amplifier configured to process DC, low-frequency signals; the fully differential amplifier A3 is configured to process high-frequency signals, provide high bandwidth and high common-mode rejection ratio, process differential signals, reduce common-mode interference, and change the common-mode voltage of the differential output by adjusting Vocm.

4. The high- and low-frequency separation signal conditioning circuit for a peak power sensor according to claim 1, characterized in that: The non-inverting input terminal of the first precision operational amplifier A1 is both the point where the positive signal is divided into two paths and the summing point where the fully differential amplifier A3 feeds back to the first precision operational amplifier A1. The phase of the fully differential amplifier A3 fed back to this point is opposite to the phase of the positive signal, forming inter-stage negative feedback of the two-stage amplifier. Both the first precision operational amplifier A1 and the fully differential amplifier A3 operate in a negative feedback state.

5. The high- and low-frequency separation signal conditioning circuit for a peak power sensor according to claim 1, characterized in that: The positive signal is divided into two paths at the in-phase input terminal of the first precision operational amplifier A1. One path is the lower frequency component in the signal. The bandwidth of the first precision operational amplifier A1 is limited and can only amplify the lower frequency part of the signal. The other path is the higher frequency component in the signal. Because the first capacitor C1 and the fifth resistor R5 form a high-pass filter, only the higher frequency component in the positive signal is allowed to pass through; the low-frequency part of the signal is amplified by the in-phase ratio of the first precision operational amplifier A1 and then output to the input terminal of the fully differential amplifier A3, and the high-frequency part of the signal passes through the high-pass filter directly to the input terminal of the fully differential amplifier A3. The high-frequency signal and the low-frequency signal take different paths to reach the fully differential amplifier A3.

6. The high- and low-frequency separation signal conditioning circuit for a peak power sensor according to claim 1, characterized in that: The first resistor R1 is the input resistor of the entire circuit, the sixth resistor R6 is the feedback resistor of the entire circuit, and the gain of the amplifier circuit composed of the first precision operational amplifier A1 and the fully differential amplifier A3 is -R6 / R1; the first capacitor C1 and the fifth resistor R5 form a high-pass filter for separating high and low frequency signals; the second capacitor C2 and the third resistor R3 form intra-stage feedback, which is used to feed back the input signal of the fully differential amplifier A3 to the inverting input terminal of the first precision operational amplifier A1, the second resistor R2 is the inverting input resistor of the first precision operational amplifier A1, and the fourth resistor R4 is used to isolate the output terminal of the first precision operational amplifier A1 from the second capacitor C2, and superimpose the low-frequency signal and the high-frequency signal output by the first precision operational amplifier A1 at the input terminal of the fully differential amplifier A3.

7. The high- and low-frequency separation signal conditioning circuit for a peak power sensor according to claim 1, characterized in that: The low-pass filter composed of the seventh resistor R7, the fourteenth resistor R14, the fifth capacitor C5, the sixth capacitor C6, and the seventh capacitor C7 is used to limit the channel bandwidth of the signal conditioning to achieve anti-aliasing effect; the fifth capacitor C5 is a differential mode capacitor used to reduce differential mode interference, and the sixth capacitor C6 and the seventh capacitor C7 are common mode capacitors used to reduce common mode interference.

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