High bandgap device with doped high bandgap gate electrode extension

Abstract

A microelectronic device (100) includes a GaN FET (102) on a substrate (104), such as silicon, and a buffer layer (106) of p-type GaN semiconductor material. The GaN FET (102) includes a gate electrode extension (146) including a p-type GaN semiconductor material (120) in electrical contact with a gate electrode p-type GaN stack (124). The gate electrode extension (146) including a p-type GaN semiconductor material (120) in electrical contact with the gate electrode p-type GaN stack (124) may improve characteristics of the GaN FET (102), such as off-state leakage, sub-threshold voltage, and post stress Vt shift.

Description

Technical Field

[0001] The present description relates to the field of microelectronic devices. More particularly, but not exclusively, the present description relates to microelectronic devices having a layout including a gate electrode extension inside the device active area to improve leakage and subthreshold characteristics. Background Art

[0002] Semiconductor components are continually being improved to operate at higher potentials where gate leakage is critical to device performance. It is challenging to fabricate semiconductor components with low leakage at higher and higher potentials. Summary of the invention

[0003] This Summary is provided to introduce a brief selection of described concepts in a simplified form that are further described below in the Detailed Description including the provided figures. This Summary does not limit the scope of the claimed subject matter.

[0004] The described examples include a microelectronic device including a gallium nitride field effect transistor (GaN FET) having a gate layout design containing a p-type GaN gate electrode extension within an active region of the microelectronic device to improve leakage and subthreshold performance. The described examples provide an associated process flow for forming such an integrated GaN FET microelectronic device. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1A is a top-down view of a GaN FET including a gate electrode extension.

[0006] Figure 1B This is a cross section of a GaN FET.

[0007] Figure 1C This is a cross section of a GaN FET.

[0008] Figure 2 yes Figure 1A and Figure 1B Flowchart of the formation of GaN FET shown in FIG.

[0009] Figure 3 is a graph demonstrating improved gate leakage of a GaN FET including a gate electrode extension inside the GaN FET isolation compared to a GaN FET with the gate electrode extension outside the GaN FET isolation and compared to a GaN FET without the gate electrode extension.

[0010] Figure 4is a graph demonstrating the improved off-state Vt of a GaN FET including a gate electrode extension inside the GaN FET isolation compared to a GaN FET with the gate electrode extension outside the GaN FET isolation and compared to a GaN FET without the gate electrode extension.

[0011] Figure 5 is a graph demonstrating the improved subthreshold voltage of a GaN FET including a gate electrode extension inside the GaN FET isolation compared to a GaN FET with the gate electrode extension outside the GaN FET isolation and compared to a GaN FET without the gate electrode extension. DETAILED DESCRIPTION

[0012] This specification is provided with reference to the accompanying drawings. The drawings are not drawn to scale and are provided only for illustration of this specification. Several aspects of this specification are provided below with reference to example applications for illustration. Many specific details, relationships and methods are set forth to provide an understanding of this specification. This specification is not limited by the order in which the actions or events are described, as some actions may occur in a different order and / or simultaneously with other actions or events. In addition, not all described actions or events are required to implement the methods in this specification.

[0013] Although some of the examples described herein are shown in two-dimensional views, where the various regions have depth and width, these regions are merely illustrations of a portion of a device that is actually a three-dimensional structure. Therefore, when manufactured on an actual device, these regions will have three dimensions, including length, width, and depth. In addition, although this specification is illustrated by examples for active devices, these illustrations do not limit the scope or applicability of this specification. The active devices of this specification are not limited to the physical structures described. These structures are included to show the utility and application of this specification to the currently preferred embodiments.

[0014] For the purposes of this specification, the term "III-N" refers to semiconductor materials in which the Group III elements, i.e., aluminum, gallium, and indium, and possibly boron, provide a portion of the atoms in the semiconductor material and nitrogen atoms provide another portion of the atoms in the semiconductor material. Examples of III-N semiconductor materials are gallium nitride, gallium boron nitride, aluminum gallium nitride, indium nitride, and indium aluminum gallium nitride. Terms describing the elemental formula of a material do not imply a particular stoichiometry of the elements. For example, aluminum gallium nitride can be written as AlGaN, which covers a range of relative proportions of aluminum and gallium.

[0015] It should be noted that terms such as top, bottom, over, above, and below may be used in this specification. These terms should not be understood as limiting the position or orientation of structures or elements, but are used to provide spatial relationships between structures or elements. The terms "lateral" and "laterally" refer to a direction parallel to the plane of the top surface of the channel layer.

[0016] An enhancement or depletion mode gallium nitride field effect transistor (GaN FET) is a high bandgap (high bandgap greater than 2 eV) transistor that may have a floating p-type doped III-N layer, referred to herein as a p-type GaN layer, between a gate metal layer and a channel layer. The gate of the GaN-FET consists of a first portion of a p-type GaN layer and a first portion of a gate metal layer, referred to herein as a gate electrode p-type GaN stack. The p-type GaN layer is floating due to the Schottky diode nature of the contact with the gate electrode p-type GaN stack. Because the channel potential of the GaN FET with a floating p-type GaN layer between the gate metal layer and the channel layer is not directly controlled by the gate metal layer, but rather controlled through the p-type GaN layer, some electrical characteristics such as subthreshold voltage, gate leakage, and off-state Vt shift may be degraded. The GaN-FET includes a gate electrode extension, the gate electrode extension including a second portion of the p-type GaN layer and a second portion of the gate metal layer, the gate electrode extension being in electrical contact with the first portion of the p-type GaN layer, wherein the p-type GaN gate electrode extension is inside an isolation region surrounding the GaN FET. Adding a gate electrode extension including p-GaN below the gate electrode within the active region of the GaN FET provides additional coupling of the p-GaN between the gate electrode and the source, which results in a more stable p-GaN potential relative to the drain voltage and results in lower drain-to-source leakage. The increased coupling also results in a steeper subthreshold slope and an improved off-state Vt shift compared to a similar GaN FET without a gate electrode extension.

[0017] Figure 1A A top-down view of a microelectronic device 100 is shown, which includes a gallium nitride field effect transistor 102 (referred to herein as a GaN FET) having a gate electrode p-type GaN stack 124. The gate electrode p-type GaN stack 124 includes a p-type GaN gate electrode extension (referred to herein as a gate electrode extension) 146, which is formed simultaneously with the gate electrode p-type GaN stack 124 and is electrically connected to the gate electrode p-type GaN stack 124. The gate electrode extension 146 is completely contained within an isolation region 145 of the microelectronic device 100, which forms a continuous region around the GaN FET 102 and the gate electrode extension 146. Figure 1AIn the example shown in , the gate electrode extension 146 also serves as a gate electrode landing pad region for the GaN FET 102, but other locations of the gate electrode extension 146, such as any region adjacent to the GaN FET 102 while still electrically connected to the gate electrode p-type GaN stack 124 and within the isolation region 145 are within the scope of the present description. The GaN FET 102 includes a source access region 128 and a drain access region 129, which are components of the two-dimensional electron gas (2DEG) 114, such as Figure 1B . The GaN FET 102 includes a gate electrode p-type GaN stack 124 between a source access region 128 and a drain access region 129, a row of source contacts 144 over a source (not specifically shown) in the source access region 128, a row of drain contacts 142 over a drain (not specifically shown) in the drain access region 129, a gate contact 143 on the gate electrode p-type GaN stack 124, and a drain bonding pad 152. For clarity, the metallization has been removed except for the metallization 148 that bonds the source bonding pad 150 to the source access region 128.

[0018] Figure 1B can be used in the microelectronic device 100 to implement Figure 1A A cross section of an enhancement mode example GaN FET structure of GaN FET 102 is shown. Depletion mode GaN FETs are within the scope of this specification. The gate electrode extension 146 is Figure 1B. The microelectronic device 100 can be formed on a substrate 104 such as a silicon wafer, a sapphire wafer, or a silicon carbide wafer. The GaN FET 102 includes a buffer layer 106 of III-N semiconductor material (referred to herein as a buffer layer), a channel layer 108 of III-N semiconductor material (referred to herein as a channel layer), gallium nitride over the buffer layer 106 in this example, an optional high bandgap layer 110 of III-N semiconductor material over the channel layer 108 (referred to herein as an optional high bandgap layer), and a barrier layer 112 of III-N semiconductor material over the optional high bandgap layer 110 (if present) and over the channel layer 108 (if the optional high bandgap layer 110 is not present). The barrier layer 112 induces a 2DEG 114 in the channel layer 108 adjacent to the barrier layer 112. The 2DEG 114 includes a channel region 126 below the gate electrode p-type GaN stack 124. The channel region 126 is between a drain access region 129 and a source access region 128, which are opposite to the channel region 126 but located adjacent to the channel region. The 2DEG 114 includes a source region 130 in the region for the source of the GaN FET 102. The source region 130 is laterally separated from the channel region 126 by the source access region 128. The 2DEG 114 includes a drain region 132 in the region for the drain of the GaN FET 102. The drain region 132 is laterally separated from the channel region 126 by the drain access region 129 and is located opposite to the source region 130.

[0019] The GaN FET 102 may include an optional etch stop layer 116 on the barrier layer 112. A gate electrode p-type GaN stack 124 is defined on the barrier layer 112 of the GaN FET. The gate electrode p-type GaN stack 124 is composed of a p-type GaN layer 120 on the barrier layer 112 or on the optional etch stop layer 116 (if present) and a gate metal layer 122 on the p-type GaN layer 120. Portions of the gate metal layer 122 and the p-type GaN layer 120 are etched away during semiconductor processing, leaving the gate electrode p-type GaN stack 124 and the gate electrode extension ( Figure 1A). The gate electrode p-type GaN stack 124 has a bottom surface 136 adjacent to the barrier layer 112 or the optional etch stop layer 116 (if present), the bottom surface not extending beyond the top surface 138 of the barrier layer 112, and positioned opposite the channel layer 108. The GaN FET 102 includes a dielectric layer 134 above the gate electrode p-type GaN stack 124. The GaN FET 102 includes a gate contact 143 and a drain contact 142 and a source contact 144. For example, the gate contact 143 can be formed of aluminum, tungsten, or TiW. The gate contact 143 forms an electrical contact with the gate electrode p-type GaN stack 124. Both the drain contact 142 and the source contact 144 form electrical contacts through the barrier layer 112 and the optional high bandgap layer 110 to the channel layer 108. The GaN FET 102 includes an isolation region 145. The isolation region 145 can be formed by an implantation process utilizing ions such as argon, fluorine, or nitrogen, which causes damage to the barrier layer 112, the optional high bandgap layer 110, the channel layer 108, and portions of the buffer layer 106 in the isolation region 145, or the isolation region 145 can be formed by a plasma etching process that removes the barrier layer 112, the optional high bandgap layer 110, the channel layer 108, and portions of the buffer layer 106 in the isolation region 145.

[0020] Figure 1C A cross section of a microelectronic device 100 through a gate electrode length 154 is shown including a gate electrode extension 146, a drain bonding pad 152, and a gate electrode p-type GaN stack 124. The microelectronic device 100 may include a substrate 104 such as a silicon wafer, a sapphire wafer, or a silicon carbide wafer. The GaN FET 102 (out of the plane of the cross section) includes a buffer layer 106 of one or more layers of III-N semiconductor material on the substrate 104, a channel layer 108 over the buffer layer 106, an optional high bandgap layer 110 over the channel layer 108, and a barrier layer 112 of III-N semiconductor material over the optional high bandgap layer 110 (if present) and over the channel layer 108 (if the optional high bandgap layer 110 is not present). The barrier layer 112 induces a 2DEG 114 in the channel layer 108 adjacent to the barrier layer 112. An optional etch stop layer 116 may be formed over the barrier layer 112. 2DEG 114 includes a channel region 126 below a gate electrode gate electrode p-type GaN stack 124, which is composed of a p-type GaN layer 120 and a gate metal layer 122. A gate contact 143 is shown contacting the gate electrode p-type GaN stack 124 through a dielectric layer 134. Figure 1C In FIG. 1 , the 2DEG 114 below the drain bonding pad 152 and the area that is not part of the channel region 126 induces a drain access region 129 .

[0021] exist Figure 1C The left and right edges of the isolation region 145 are located, and the isolation region is a portion of the isolation region 145 surrounding the microelectronic device 100, such as Figure 1B The source access region 128 is Figure 1C The leftmost edge of the drain pad 152 is adjacent to the isolation region 145, and the channel region 126 with the associated p-type GaN layer 120 and gate metal layer 122 is above the source access region 128. The drain bonding pad 152 is provided for Figure 1B The drain access region 129 is bonded to a region of a semiconductor package (not specifically shown). Figure 1C A gate electrode length 154 is shown spanning between the drain bonding pad 152 and the gate electrode extension 146. In the example shown, the gate electrode extension 146 also acts as a gate bonding pad. The p-type GaN layer 120 and the gate metal layer 122 are continuous between the edge of the gate electrode length 154 and the gate electrode extension 146.

[0022] Figure 2 Presentation Figure 1A and Figure 1B 2 is a flow chart of an example method 200 of a microelectronic device 100 of the present invention. The method 200 includes step 202, which may include forming a buffer layer 106 on a substrate 104. In a version of this example where the substrate 104 is implemented as a silicon wafer or a sapphire wafer, the buffer layer 106 may include a nucleation layer having a stoichiometry including aluminum to match the lattice constant of the substrate 104. The buffer layer 106 may further include a gallium nitride aluminum sublayer with a reduced aluminum content, ultimately forming an unintentionally doped gallium nitride layer. The buffer layer 106 on silicon or sapphire may be 1 micron to several microns thick. In a version of this example where the substrate 104 is implemented as a silicon carbide wafer, the buffer layer 106 may be thinner due to the tighter match of the lattice constant between gallium nitride and silicon carbide. The buffer layer 106 may be formed by a buffered metal organic vapor phase epitaxy (MOVPE) process with several operations to form the nucleation layer and sublayers. The buffer layer 106 overlaps the area for the GaN FET 102.

[0023] The method 200 continues with step 204, which includes forming a channel layer 108 of a III-N semiconductor material on the buffer layer 106. The channel layer 108 includes gallium and nitrogen, and may include primarily gallium nitride and optionally trace amounts of other group III elements, such as aluminum or indium. The channel layer 108 may be formed by a channel metal organic vapor phase epitaxy (MOVPE) process using a gallium-containing gas reagent and a nitrogen-containing gas reagent. During the channel MOVPE process, the substrate 104 may be heated to 900° C. to 1100° C. For example, the gallium-containing gas reagent may be implemented as trimethyl gallium or triethyl gallium. For example, the nitrogen-containing gas reagent may be implemented as ammonia, hydrazine, or 1,1-dimethylhydrazine. The channel MOVPE process uses a carrier gas. The carrier gas may include primarily hydrogen, or may include hydrogen and another gas, such as nitrogen. For example, the channel layer 108 may be 1 nanometer to 10 nanometers thick. In an alternative version of this example, the channel layer 108 may be formed as the last portion of the buffer layer 106. During operation of the GaN FET 102, the channel layer 108 supports the 2DEG 114.

[0024] The method 200 continues at step 206 by forming an optional high bandgap layer 110 of a III-N semiconductor material on the channel layer 108. The optional high bandgap layer 110 comprises primarily aluminum and nitrogen to provide a higher bandgap than a subsequently formed barrier layer 112. In some versions of this example, the optional high bandgap layer 110 may consist primarily of aluminum nitride, with trace amounts of other Group III elements, such as gallium.

[0025] The optional high bandgap layer 110 can be formed by a high bandgap MOVPE process using an aluminum-containing gas reagent and a nitrogen-containing gas reagent. For example, the aluminum-containing gas reagent can be implemented as trimethylaluminum or triethylaluminum. The nitrogen-containing gas reagent can be implemented as ammonia, hydrazine, or 1,1-dimethylhydrazine, as described with reference to forming the channel layer 108. During the high bandgap MOVPE process, the substrate 104 can be heated to 900° C. to 1100° C. The high bandgap MOVPE process uses a carrier gas. The carrier gas can contain mainly hydrogen, or can contain hydrogen and another gas, such as nitrogen. For example, the optional high bandgap layer 110 can be 0.5 nanometers to 3 nanometers thick. The optional high bandgap layer 110, if formed, can improve charge confinement in the subsequently formed 2DEG 114 by providing a deeper quantum well in the channel layer 108, thereby advantageously providing an increased free charge carrier density in the 2DEG 114.

[0026] The method 200 continues with step 208, which includes forming a barrier layer 112 of III-N semiconductor material over the channel layer 108 or on the optional high bandgap layer 110 (if present). The barrier layer 112 may include aluminum and nitrogen. In one version of this example, the barrier layer 112 may also include gallium (Al). x Ga yN), where the sum of x and y is equal to one, and x and y may be in the range between 0.01 and 0.99. In another version of this example, the barrier layer 112 may have Al within a few atomic percent. .83 In .17 N stoichiometry, which provides a close lattice match with gallium nitride. In another version, the barrier layer 112 may include gallium and indium; the gallium may improve the uniformity of the indium in the barrier layer 112. The barrier layer 112 may have a thickness of 1 nanometer to 600 nanometers.

[0027] The barrier layer 112 may be formed by a barrier MOVPE process using an aluminum-containing gas reagent and a nitrogen-containing gas reagent. For example, the aluminum-containing gas reagent may be implemented as trimethylaluminum or triethylaluminum. The nitrogen-containing gas reagent may be implemented as ammonia, hydrazine, or 1,1-dimethylhydrazine, as described with reference to forming the channel layer 108.

[0028] In a version of this example where the barrier layer 112 includes gallium, the barrier MOVPE process uses a gallium-containing gas reagent in addition to an aluminum-containing gas reagent and a nitrogen-containing gas reagent. The gallium-containing gas reagent may be implemented as trimethyl gallium or triethyl gallium, as described with reference to forming the channel layer 108. In a version of this example where the barrier layer 112 includes indium, the barrier MOVPE process uses an indium-containing gas reagent. For example, the indium-containing gas reagent may be implemented as trimethyl indium or triethyl indium. The barrier MOVPE process uses a carrier gas. The carrier gas may primarily include hydrogen, or may include hydrogen and another gas, such as nitrogen. During the barrier MOVPE process, the substrate 104 may be heated to 900° C. to 1100° C.

[0029] The barrier layer 112 induces a 2DEG 114 in the channel layer 108 adjacent to the barrier layer 112. The stoichiometry and thickness of the barrier layer 112 can provide a 3×10 12 cm -2 Up to 2×10 13 cm -2 The free charge carrier density of the GaN FET 102 is increased to provide a desired on-state resistance for the GaN FET 102.

[0030] The method 200 continues with step 210, which includes forming an optional etch stop layer 116 on the barrier layer 112. The optional etch stop layer 116 has a higher aluminum content than the barrier layer 112. The optional etch stop layer 116 may primarily include an aluminum nitride semiconductor material. The optional etch stop layer 116 may be 0.5 nanometers to 3 nanometers thick and may be formed by an etch stop MOVPE process similar to the high bandgap MOVPE process used to form the optional high bandgap layer 110. The optional etch stop layer 116 may advantageously reduce or eliminate etching of the barrier layer 112 during a subsequent gate etch process.

[0031] The method 200 continues with step 212, which includes forming a p-type III-N semiconductor material, referred to herein as a p-type GaN layer 120, as a layer above the barrier layer 112. The p-type GaN layer 120 may include primarily gallium nitride with a magnesium dopant to provide p-type conductivity. In some versions of this example, the p-type GaN layer 120 may include less than 10 atomic % of other Group III elements, such as aluminum or indium.

[0032] The p-type GaN layer 120 can be formed by a MOVPE process using a gallium-containing gas reagent, a nitrogen-containing gas reagent, and a p-type dopant gas. For example, the gallium-containing gas reagent can be implemented as trimethylgallium or triethylgallium. The nitrogen-containing gas reagent can be implemented as ammonia, hydrazine, or 1,1-dimethylhydrazine, as described with reference to forming the channel layer 108. For example, the p-type dopant gas reagent can be implemented as bis(cyclopentadienyl)magnesium. Other sources of magnesium-containing gas reagents are within the scope of this example. In addition, other implementations of p-type dopant gases for providing p-type dopants other than magnesium are also within the scope of this example. In a version of this example where the p-type dopant is implemented as magnesium, the magnesium concentration in the p-type GaN layer 120 can be 1×10 17 cm -3 to 1×10 20 cm -3 , thereby providing the desired threshold potential for the GaN FET 102.

[0033] In a version of this example where the p-type GaN layer 120 includes aluminum, the MOVPE process uses an aluminum-containing gas reagent. The aluminum-containing gas reagent may be implemented as trimethylaluminum or triethylaluminum, as described with reference to forming the barrier layer 112. In a version of this example where the p-type GaN layer 120 includes indium, the MOVPE process uses an indium-containing gas reagent. The indium-containing gas reagent may be implemented as trimethylindium or triethylindium, as described with reference to forming the barrier layer 112. The p-type GaN layer 120 formation MOVPE process uses a carrier gas. The carrier gas may primarily include hydrogen, or may include hydrogen and another gas, such as nitrogen. During the MOVPE process, the substrate 104 may be heated to 900° C. to 1100° C.

[0034] The p-type GaN layer 120 may be 5 nanometers to 500 nanometers thick to provide a desired threshold potential for the GaN FET 102. The p-type GaN layer 120 reduces the free charge carrier density in the 2DEG 114 by 25% to 99% due to the work function of the gate layer reducing the quantum wells in the channel layer 108. After forming the p-type GaN layer 120, the 2DEG 114 maintains a finite free charge carrier density of electrons.

[0035] The method 200 continues with step 214, which includes forming a gate metal layer 122 on the p-type GaN layer 120. The gate metal layer 122 may be one selected from the group of titanium, nickel, titanium nitride, titanium tungsten, and tungsten. Other metals for the gate metal layer 122 are within the scope of the present specification. The gate metal layer 122 may be deposited by a sputtering process, a plasma deposition process, or a CVD process. For example, the gate metal layer 122 is between 50 nanometers and 3 micrometers.

[0036] The method 200 continues with step 216, which includes forming an isolation region 145 surrounding the GaN FET 102. To form the isolation region 145, a photolithography step is used to cover the GaN FET 102 including the gate electrode extension 146 with a photoresist, thereby exposing the isolation region 145 to an isolation region implant (not specifically shown). The isolation region implant may include an implant of argon, fluorine, or nitrogen ions implanted at an energy between 100 kiloelectronvolts (keV) and 300 keV, with an implant dose of 1×10 14 ions / cm 2 Up to 1×10 16 ions / cm 2 The isolation region implant creates an amorphous damaged region during the formation of the isolation region 145, which results in an increase in the resistance of the exposed layer, so that acceptable isolation characteristics are achieved for the function of the GaN FET 102. The isolation region 145 can also be formed using a photolithography step to cover the GaN FET 102, thereby exposing the isolation region 145, followed by a plasma etching process that removes the barrier layer 112, the optional high bandgap layer 110, the channel layer 108, and removes portions of the buffer layer 106.

[0037] The method 200 continues with step 218, which includes patterning and etching the gate metal layer 122 and the p-type GaN layer 120 to define a gate electrode p-type GaN stack 124. In the gate electrode p-type GaN stack 124 formation process, a gate mask (not specifically shown) is formed on the gate metal layer 122, the gate mask covering the gate metal layer 122 and the region of the underlying p-type GaN layer 120. In one version of this example, the gate mask may include a photoresist formed directly by a photolithography process. The gate mask may include an organic anti-reflective material, such as a bottom anti-reflective coating (BARC) layer below the photoresist. The BARC layer may be patterned after the photolithography process is completed. In another version of this example, the gate mask may include an inorganic hard mask material, such as silicon oxide or silicon nitride. In another version, for example, the gate mask may include a metal hard mask material, such as silicon nitride. The hard mask material (inorganic or metal) can be patterned by forming a photoresist pattern over the hard mask material and then etching the hard mask material using a reactive ion etching (RIE) process with fluorine radicals or an ion milling process. The hard mask material in the gate mask can provide improved control over the lateral dimensions of the gate electrode p-type GaN stack 124. The gate electrode p-type GaN stack 124 formation process continues with a gate etching process (not specifically shown) that removes the gate metal layer 122 and the p-type GaN layer 120 exposed by the gate mask, thereby leaving the gate metal layer 122 and the p-type GaN layer 120 under the gate mask to form the gate electrode p-type GaN stack 124. The gate etching process can be performed in an inductively coupled plasma (ICP) etcher that generates a plasma containing chemically reactive neutral species, ions, and electrons. The gate etching process includes a chemical etchant species, a physical etchant species, and an aluminum passivation species. For example, the chemical etchant species may be implemented as chlorine radicals or bromine radicals. The chlorine radicals may be provided by chlorine gas, silicon tetrachloride, boron trichloride, or a combination thereof. For example, the bromine radicals may be provided by boron tribromide.

[0038] The gate electrode p-type GaN stack 124 etching process may also include a physical etchant substance that may be implemented by one or more ionic substances. Examples of physical etchant substances include fluorine ions, inert gas ions (such as argon ions or helium ions), and oxygen ions. Other ionic substances in the physical etchant substance are within the scope of this example. For example, fluorine ions may be provided by silicon hexafluoride, carbon tetrafluoride, or nitrogen trifluoride. Inert gas ions may be provided by argon or helium. For example, oxygen ions may be provided by oxygen or carbon monoxide gas.

[0039] The gate electrode p-type GaN stack 124 etching process also includes an aluminum passivation substance, which can be implemented as an oxygen radical or a fluorine radical. The oxygen radical can be provided by oxygen. For example, the fluorine radical can be provided by silicon hexafluoride, carbon tetrafluoride or nitrogen trifluoride.

[0040] The chemical etchant substance combines with the gallium atoms and nitrogen atoms in the gate layer. The physical etchant substance strikes the gate layer and imparts sufficient energy to promote the separation of the gallium atoms and nitrogen atoms bonded to the chemical etchant substance from the gate layer. The gallium atoms and nitrogen atoms separated from the gate layer are removed by the ICP etcher. The ICP etcher has: a first power supply, the first power supply is used to form a plasma, the plasma produces a chemical etchant substance, a physical etchant substance and an aluminum passivation substance; and a second power supply, the second power supply is used to independently control the potential difference between the plasma and the substrate 104. For example, for a 150 mm wafer, the first power supply can be operated at a power of 250 watts to 500 watts. The second power supply can be adjusted to initially operate at 20 watts to 100 watts to provide sufficient impact energy of the physical etchant substance to promote the separation of gallium atoms and nitrogen atoms from the gate layer. When the gate etching process is nearing completion, the power level of the second power supply can be reduced to 20 watts to 50 watts to reduce the energy provided for the chemical reaction, which more significantly reduces the removal of aluminum than the removal of gallium, thereby providing etching selectivity. Reducing the power level of the second power supply can therefore reduce the etch rate of the optional etch stop layer 116 (if present) or the barrier layer 112 (if the optional etch stop layer 116 is not present) relative to the gate layer because the gate layer contains more gallium and less aluminum than the optional etch stop layer 116 and the barrier layer 112.

[0041] The gate etching process may be performed at a pressure of 10 mTorr to 50 mTorr to improve etching selectivity. The aluminum passivation substance further improves etching selectivity by preferentially combining with aluminum in the optional etch stop layer 116 (if present) or in the barrier layer 112 (if the optional etch stop layer 116 is not present), thereby minimizing the sites available for chemical etchant substances to react with gallium and nitrogen. Therefore, the gate etching process may completely remove the gate layer exposed by the gate mask without removing a large amount of the optional etch stop layer 116 or the barrier layer 112. After the gate layer is removed outside the gate electrode p-type GaN stack 124, the gate etching process may continue in an over-etching step. Reducing the power level of the second power supply and providing the aluminum passivation substance may advantageously enable complete removal of the gate layer across the substrate 104, regardless of the thickness variation of the gate layer across the substrate 104, without removing a large amount of the optional etch stop layer 116 or the barrier layer 112.

[0042] The 2DEG 114 includes a channel region 126 below the gate electrode p-type GaN stack 124. The free charge carrier density in the channel region 126 is maintained at a low value because the thickness of the gate metal layer 122 and the p-type GaN layer 120 remain constant in the gate electrode p-type GaN stack 124. The 2DEG 114 includes a source access region 128 and a drain access region 129, both of which are adjacent to the channel region 126. As the gate layer is removed, the free charge carrier density in the 2DEG 114 increases in the source access region 128 and the drain access region 129, wherein the gate metal layer 122 and the p-type GaN layer 120 are removed.

[0043] The 2DEG 114 includes a source region 130 in the region for the source of the GaN FET 102. The source region 130 is laterally separated from the channel region 126 by one of the source access regions 128. The 2DEG 114 includes a drain region 132 in the region for the drain of the GaN FET 102. The drain region 132 is laterally separated from the channel region 126 by the drain access region 129 and is positioned opposite the source region 130.

[0044] After the gate electrode p-type GaN stack 124 is formed, the free charge carrier density of the 2DEG 114 in the source access region 128 and the drain access region 129 can be increased to a value comparable to the free charge carrier density before the gate metal layer 122 and the p-type GaN layer 120 are formed. The free charge carrier density of the 2DEG 114 in the source access region 128 and the drain access region 129 can be 3×10 12 cm -2 to 2×10 13 cm -2 , thereby providing the desired on-state resistance for the GaN FET 102. The channel region 126 of the 2DEG 114 maintains a non-zero electron density, ie, 1% to 75% of the free charge carrier density of the 2DEG 114 in the source access region 128 and the drain access region 129.

[0045] A bottom surface 136 of the gate electrode p-type GaN stack 124 adjacent to the barrier layer 112 does not extend beyond a top surface 138 of the barrier layer 112 positioned opposite the channel layer 108, thereby advantageously enabling the GaN FET 102 to be formed without etching a gate recess, which would increase manufacturing cost and complexity. The GaN FET 102 may be free of any dielectric material between the gate electrode p-type GaN stack 124 and the barrier layer 112, thereby advantageously enabling the GaN FET 102 to be formed without forming a gate dielectric layer, which would also increase manufacturing cost and complexity. The GaN FET 102 may be free of III-N semiconductor material adjacent to the gate electrode p-type GaN stack 124 extending above the bottom surface 136 of the gate electrode p-type GaN stack 124, thereby advantageously enabling the GaN FET 102 to be formed without forming a barrier regrowth layer, which would further increase manufacturing cost and complexity. Other methods of forming the gate electrode p-type GaN stack 124 are within the scope of the present description.

[0046] The method 200 continues with step 220, which includes forming a dielectric layer 134 over the gate electrode p-type GaN stack 124 and over the barrier layer 112 adjacent to the gate electrode p-type GaN stack 124. The dielectric layer 134 may include one or more sublayers of silicon dioxide, silicon nitride, aluminum oxide, or any combination thereof. For example, the dielectric layer 134 may be formed by one or more low pressure chemical vapor deposition (LPCVD) processes, plasma enhanced chemical vapor deposition (PECVD) processes, high density plasma (HDP) processes, or atomic layer deposition (ALD) processes. The dielectric layer 134 may advantageously protect the gate electrode p-type GaN stack 124 and the barrier layer 112 from physical or chemical degradation.

[0047] The method 200 continues with step 222, which includes forming a source contact 144 to the source region 130, a drain contact 142 to the drain region 132, and a gate contact 143 to the gate electrode p-type GaN stack 124. The gate contact 143 is formed through the dielectric layer 134 to contact the gate electrode p-type GaN stack 124. The gate contact 143 may be aligned with an opening through the dielectric layer 134, or may extend partially around the opening over the dielectric layer 134. The drain contact 142 is formed through the dielectric layer 134 and the barrier layer 112 to contact the 2DEG 114 in the drain region 132. The source contact 144 is formed through the dielectric layer 134 and the barrier layer 112 to contact the 2DEG 114 in the source region 130. The gate contact 143, drain contact 142, and source contact 144 are electrically conductive and may include one or more metals, such as titanium, tungsten, or aluminum, or may include other conductive materials, such as carbon nanotubes or graphene.

[0048] Figure 3 is a graph comparing the off-state leakage of a GaN FET 102 without a gate electrode extension (not specifically shown), a GaN FET with a gate electrode extension outside the isolation of the GaN FET (not specifically shown), and a gate electrode extension 146 included within the isolation region 145 of the GaN FET 102. The gate electrode extension 146 of the gate electrode p-type GaN stack 124 is advantageous within the isolation because the p-GaN of the GaN FET 102 as the gate electrode extension 146 is not damaged during the isolation implant, and thus provides additional coupling between the gate electrode p-type GaN stack 124 and the source region 130, which results in lower off-state leakage. When the gate electrode extension is outside the isolation, since the gate electrode extension is damaged during the isolation implant, the gate electrode extension coupling is reduced, and the improvement in off-state leakage is similar to that of a transistor without a gate electrode extension.

[0049] Figure 4 1 is a graph comparing the off-state Vt shift of a GaN FET 102 without a gate electrode extension (not specifically shown), a GaN FET with a gate electrode extension outside the isolation of the GaN FET (not specifically shown), and a GaN FET 102 including a gate electrode extension 146 within the isolation region 145 of the GaN FET 102. The gate electrode extension 146 of the gate electrode p-type GaN stack 124 is advantageous within the isolation because the p-GaN of the GaN FET 102 as the gate electrode extension 146 is not damaged during the isolation implant, and thus provides additional coupling between the gate electrode p-type GaN stack 124 and the source region 130, which results in improved subthreshold characteristics. When the gate electrode extension is outside the isolation, the gate electrode extension coupling is reduced because the gate electrode extension is damaged during the isolation implant, and the improvement in the off subthreshold voltage is similar to that of a transistor without a gate electrode extension.

[0050] Figure 5is a graph comparing the subthreshold voltage of a GaN FET 102 without a gate electrode extension (not specifically shown), a GaN FET with a gate electrode extension outside the isolation of the GaN FET (not specifically shown), and a GaN FET 102 including a gate electrode extension 146 within the isolation region 145 of the GaN FET 102. The gate electrode extension 146 of the gate electrode p-type GaN stack 124 being inside the isolation is advantageous because the GaN FET 102, which is the p-GaN of the gate electrode extension 146, is not damaged during the isolation implant and provides an excellent hole reservoir that can provide holes to the gate electrode p-type GaN stack 124 of the GaN FET when the GaN FET 102 returns from an off state, compared to a device in which the p-GaN extension is outside the isolation and damaged during isolation formation or a device with no gate electrode extension.

[0051] Although various examples of the present specification have been provided above, these examples are presented by way of example only and not limitation. Many changes may be made to the examples described in the specification herein without departing from the spirit or scope of the present specification. Therefore, the breadth and scope of the present specification are not limited by any of the above examples. On the contrary, the breadth and scope of the present specification are defined in the appended claims and their equivalents.

Claims

1. A microelectronic device comprising: A gallium nitride field effect transistor (GaN FET), comprising: A channel layer of III-N material; A barrier layer of III-N material above the buffer layer; a p-type GaN layer on the barrier layer; A gate metal layer on the p-type GaN layer; a gate comprising a first portion of the p-type GaN layer and a first portion of the gate metal layer; as well as a p-type GaN gate electrode extension comprising a second portion of the p-type GaN layer and a second portion of the gate metal layer, the p-type GaN gate electrode extension being in electrical contact with the first portion of the p-type GaN layer, wherein the p-type GaN gate electrode extension extends beyond the gate but within an isolation region surrounding the GaN FET.

2. The microelectronic device of claim 1, wherein the GaN FET includes a high bandgap layer of III-N semiconductor material between the channel layer and the barrier layer. 3 . The microelectronic device of claim 1 , wherein the p-type GaN gate electrode extension is below a gate electrode bond pad of the GaN FET. The microelectronic device of claim 1 , wherein an etch stop layer is above the barrier layer. 5 . The microelectronic device of claim 1 , wherein the p-type GaN gate electrode extension is composed of a p-type GaN layer and a gate metal layer above the barrier layer. The microelectronic device of claim 1 , wherein a gate contact of the gate metal layer forms a Schottky diode.

7. The microelectronic device of claim 1, wherein the GaN FET is an enhancement mode transistor.

8. The microelectronic device of claim 1, wherein the GaN FET is a depletion mode transistor.

9. The microelectronic device of claim 1, wherein the isolation region is an amorphous region of the barrier layer.

10. The microelectronic device of claim 1, wherein the isolation region is free of the barrier layer.

11. A method of forming a microelectronic device having a gallium nitride field effect transistor (GaN FET), comprising: forming a channel layer of III-N semiconductor material; forming a barrier layer of III-N semiconductor material on the channel layer; forming a p-type GaN layer over the barrier layer, wherein the p-type GaN layer extends into a p-type GaN gate electrode extension; forming a gate metal layer above the p-type GaN layer; as well as An isolation region is formed that is continuous around the GaN FET and the p-type GaN gate electrode extension.

12. The method of claim 11, further comprising forming a high bandgap layer of III-N semiconductor material between the channel layer and the barrier layer.

13. The method of claim 11, wherein the p-type GaN gate electrode extension is below a gate electrode bond pad of the GaN FET.

14. The method of claim 11, further comprising forming an etch stop layer over the barrier layer. 15 . The method of claim 11 , wherein the p-type GaN gate electrode extension consists of the p-type GaN layer and the gate metal layer above the barrier layer. The method of claim 11 , wherein the gate electrode contact forms a Schottky diode.

17. The method of claim 11, wherein the GaN FET is an enhancement mode transistor.

18. The method of claim 11, wherein the GaN FET is a depletion mode transistor. The method according to claim 11 , wherein the isolation region is formed as an amorphous region of the barrier layer.

20. The method according to claim 11, wherein the isolation region is formed without the barrier layer.

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