MCU controller

Abstract

The invention provides an MCU controller. The MCU controller comprises a kernel, a read-only memory, a read-write memory, a register, a flash memory controller and a flash memory, the read-only memory and the read-write memory store different data types and different mapping addresses; the kernel is respectively connected with the read-only memory, the read-write memory and the register through a plurality of buses, and the plurality of buses are separated and parallel; the flash memory controller is connected with the read-only memory and the read-write memory, and the flash memory controller is switched between the bus master device and the bus slave device; when the flash memory controller is switched to the bus master device, the flash memory controller transmits the data to be transmitted from the flash memory to the read-write memory; when the flash memory controller is switched to a bus slave device, the kernel performs read-write operation on the register; parallel access of instructions, data and external data is achieved through separated bus interfaces, and the system efficiency is improved; the dynamic master-slave switching of the flash memory controller optimizes the starting efficiency and the flexibility during operation.

Description

Technical Field

[0001] The embodiments of the present application relate to the semiconductor field, and in particular to an MCU controller. Background Art

[0002] For MCU controller architecture, instructions and data are currently mainly read from NOR FLASH. However, due to the read and write delay of FLASH, this method leads to low read and write efficiency on MCU products with a main frequency of more than 100MHz, making it difficult to improve system performance. Summary of the invention

[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0004] The purpose of this application is to solve one of the technical problems existing in the related art to at least a certain extent. The embodiment of this application provides an MCU controller that can improve system performance.

[0005] An embodiment of the first aspect of the present application, an MCU controller, includes: a core, multiple read-only memories, multiple read-write memories, registers, a flash memory controller and flash memory; the multiple read-only memories and the multiple read-write memories store different data types and have different mapping addresses; the core is respectively connected to the multiple read-only memories, the multiple read-write memories and the registers through multiple different buses, and the multiple buses are separated and parallel; the flash memory controller is connected to the multiple read-only memories and the multiple read-write memories, and the flash memory controller switches between a bus master device and a bus slave device; when the flash memory controller switches to the bus master device, the flash memory controller transfers the data to be transmitted from the flash memory to the read-write memory; when the flash memory controller switches to the bus slave device, the core performs read and write operations on the register.

[0006] According to an embodiment of the first aspect of the present application, the bus includes a first bus, a second bus and a third bus, the read-only memory includes a first read-only memory and a second read-only memory, and the read-write memory includes a first read-write memory and a second read-write memory; the first read-only memory is used to store a boot program, the second read-only memory is used to store instructions and constants, the first read-write memory is used to store a stack and variables, and the second read-write memory is used to store external data.

[0007] According to an embodiment of the first aspect of the present application, the core is connected to the first read-only memory, the second read-only memory and the first read-write memory through the first bus.

[0008] According to an embodiment of the first aspect of the present application, the core is connected to the first read-only memory, the second read-only memory and the first read-write memory through the second bus.

[0009] According to an embodiment of the first aspect of the present application, the core is connected to the second read-write memory through the third bus.

[0010] According to an embodiment of the first aspect of the present application, the mapping address range of the first read-only memory is 0x00000000 to 0x00007FFF, the mapping address range of the second read-only memory is 0x00008000 to 0x0002FFFF, the mapping address range of the first read-write memory is 0x00030000 to 0x00057FFF, and the mapping address range of the second read-write memory is 0x20000000 to 0x20037FFF.

[0011] According to an embodiment of the first aspect of the present application, when the flash memory controller switches to the bus slave device, the core performs read and write operations on the register through the third bus.

[0012] According to an embodiment of the first aspect of the present application, the MCU controller also includes an AHB bus, the core is connected to the AHB bus via a third bus, and the flash memory controller and the register are connected to the AHB bus.

[0013] According to an embodiment of the first aspect of the present application, the first bus, the second bus, the third bus and the fourth bus are integrated into a bus matrix; the fourth bus is a data line for the flash memory controller to connect the first read-only memory, the second read-only memory and the first read-write memory.

[0014] According to an embodiment of the first aspect of the present application, when the MCU controller is powered on and reset, the kernel reads the boot program from the first read-only memory, configures the flash memory controller as a bus master device according to the boot program, transfers the instructions and constants in the flash memory to the first read-write memory, the program counter of the kernel jumps to the mapping address of the first read-write memory, and the kernel runs the main program.

[0015] The above scheme has at least the following beneficial effects: by setting the data types stored in the read-only memory and the read-write memory to be different and the mapping addresses to be different; the kernel is connected to the read-only memory, the read-write memory and the register respectively through multiple buses, and the multiple buses are separated and parallel; the flash memory controller is connected to the read-only memory and the read-write memory, and the flash memory controller switches between the bus master device and the bus slave device; when the flash memory controller switches to the bus master device, the flash memory controller transfers the data to be transmitted from the flash memory to the read-write memory; when the flash memory controller switches to the bus slave device, the kernel performs read and write operations on the register; through separate bus interfaces, parallel access to instructions, data and external data is achieved, thereby improving system efficiency; the flash memory controller dynamically switches between master and slave to optimize startup efficiency and runtime flexibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings are used to provide further understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0017] Figure 1 This is a structural diagram of the MCU controller provided in the embodiment of the present application Figure 2 is a specific structural diagram of the MCU controller provided in the embodiment of the present application; Figure 3 is a structural diagram of a bus matrix provided in an embodiment of the present application; Figure 4 It is the power-on flowchart of the MCU controller. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0019] It should be noted that, although the functional modules are divided in the device schematic diagram and the logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the device or the order in the flowchart. The terms "first", "second", etc. in the specification, claims or the above drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0020] For MCU controller architecture, the traditional method is mainly to read instructions and data from NOR FLASH. However, due to the read and write delay of FLASH, it is difficult to improve system performance on MCU products with a main frequency of more than 100MHz.

[0021] In order to solve the above problems, an embodiment of the present application provides an MCU controller.

[0022] The embodiments of the present application are further described below in conjunction with the accompanying drawings.

[0023] Reference Figure 1 The MCU controller includes: a core, multiple read-only memories, multiple read-write memories, registers, a flash memory controller and flash memory; the multiple read-only memories and the multiple read-write memories store different data types and have different mapping addresses; the core is connected to the multiple read-only memories, the multiple read-write memories and the registers through multiple different buses, and the multiple buses are separated and parallel; the flash memory controller is connected to the multiple read-only memories and the multiple read-write memories, and the flash memory controller switches between the bus master device and the bus slave device; when the flash memory controller switches to the bus master device, the flash memory controller transfers the data to be transmitted from the flash memory to the read-write memory; when the flash memory controller switches to the bus slave device, the core performs read and write operations on the register.

[0024] The core adopts the ARM Cortex-M3 core. Of course, in other embodiments, other types of processor cores with similar structures can also be adopted.

[0025] The bus includes a first bus, a second bus and a third bus, the read-only memory includes a first read-only memory and a second read-only memory, and the read-write memory includes a first read-write memory and a second read-write memory; the first read-only memory is used to store a boot program, the second read-only memory is used to store instructions and constants, the first read-write memory is used to store a stack and variables, and the second read-write memory is used to store external data.

[0026] The ARM Cortex-M3 core is provided with ICODE bus interface, DCODE bus interface and SYS bus interface.

[0027] The first bus is the ICODE bus, the second bus is the DCODE bus, and the third bus is the SYS bus. The ICODE bus and the DCODE bus can only access addresses 0x00000000 to 0x1fffffff (512MB), while the SYS bus can access addresses after 0x20000000. The three buses are separated and can access different address ranges in parallel.

[0028] Reference Figure 2 The kernel is connected to the ICODE bus through the ICODE bus interface, to the DCODE bus through the DCODE bus interface, and to the SYS bus through the SYS bus interface.

[0029] The read-only memory includes a first read-only memory and a second read-only memory, and the read-write memory includes a first read-write memory and a second read-write memory. The first read-only memory is a ROM memory, marked as BOOT_ROM; the second read-only memory is an SRAM memory, marked as SRAM1; the first read-write memory is an SRAM memory, marked as SRAM2; the second read-write memory is an SRAM memory or a register of a FLASH controller of a module hanging on the AHB bus, marked as SRAM3.

[0030] Static Random-Access Memory (SRAM) is a semiconductor memory that uses a bistable latch circuit (flip-flop) to store each bit of data. SRAM can retain data as long as power is supplied, so it is fast and has low density. When the power supply stops, the data stored in SRAM disappears.

[0031] The first read-only memory is used for storing a boot program, the second read-only memory is used for storing instructions and constants, the first read-write memory is used for storing a stack and variables, and the second read-write memory is used for storing external data.

[0032] Reference Figure 3 The core is connected to the first read-only memory, the second read-only memory and the first read-write memory through the first bus.

[0033] The core is connected to the first read-only memory, the second read-only memory and the first read-write memory through a second bus.

[0034] The core is connected to the second read-write memory via a third bus.

[0035] Different buses are mapped to different storage areas (such as Flash, SRAM, and peripheral registers). By strictly dividing SRAM1 (read-only instruction area) and SRAM2 (readable and writable data area), bus conflicts are further optimized and parallel efficiency is improved.

[0036] The mapping address range of the first read-only memory is 0x00000000 to 0x00007FFF (32KB), the mapping address range of the second read-only memory is 0x00008000 to 0x0002FFFF (160KB), the mapping address range of the first read-write memory is 0x00030000 to 0x00057FFF (160KB), and the mapping address range of the second read-write memory is 0x20000000 to 0x20037FFF (224KB).

[0037] The address range is divided more finely (such as the capacity and permission allocation of SRAM1 / SRAM2 / SRAM3), and the access priority is optimized according to the Cortex-M3 bus characteristics.

[0038] The kernel can access BOOT_ROM, SRAM1 and SRAM2 through the ICODE bus. The kernel can access BOOT_ROM, SRAM1 and SRAM2 through the DCODE bus, and the kernel can access SRAM3 through the SYS bus.

[0039] By making maximum use of the separate bus interfaces (ICODE bus / DCODE bus / SYS bus) of the Cortex-M3 core, the MCU can reach a CPU main frequency of 200MHz (SMIC 40nm, tt), greatly improving the overall system performance of the MCU. Through the separate bus interfaces, parallel access to instructions, data and external data is achieved, improving system efficiency.

[0040] SRAM1 is accessed through the ICODE bus to read instructions and constants, SRAM2's stack and variables are accessed through the DCODE bus, and SRAM3 and module registers are accessed through the SYS bus. SRAM3 can store some external data that needs to be processed, such as data collected by the camera, voice data, etc. The register is used as a software interface to achieve the function of programmable configuration of the MCU. Different address intervals can be accessed in parallel through the three separate buses of the Cortex-M3 core.

[0041] The MCU controller also includes an AHB bus, the core is connected to the AHB bus via a third bus, and the flash memory controller and the register are connected to the AHB bus.

[0042] The flash controller switches between the bus master and the bus slave. When the flash controller switches to the bus master, that is, the flash controller acts as the AHB MASTER, the flash controller obtains access permission to the AHB bus, and the flash controller transfers the data to be transferred from the flash memory to the read-write memory. The data to be transferred are code and variables. The flash controller transfers the code and variables to SRAM1 or SRAM2.

[0043] Compared with moving data through the CPU, moving data through the flash memory controller can save the tedious process of CPU instruction fetching, translation and execution.

[0044] The benefit of moving code and constants to SRAM1 is that the Cortex-M3 core does not need to insert a wait cycle when accessing SRAM1 to fetch instructions. The zero wait cycle of the SRAM partition is isolated from the data, reducing bus contention.

[0045] When the flash controller switches to the bus slave device, the core reads and writes registers through the third bus.

[0046] Flash controller dynamic master-slave switching optimizes boot efficiency and runtime flexibility.

[0047] The first bus, the second bus, the third bus and the fourth bus are integrated into a bus matrix. The fourth bus is a bus for the flash memory controller to connect the first read-only memory, the second read-only memory and the first read-write memory.

[0048] The flash memory is NAND FLASH, and the flash memory controller is a FLASH controller.

[0049] The kernel is connected to the ICODE_S interface of the bus matrix through the ICODE bus, and the ICODE bus derived from the ICODE_S interface is connected to the BOOT_ROM_M interface, SRAM1_M interface and SRAM2_M interface of the bus matrix.

[0050] The core is connected to the DCODE_S interface of the bus matrix through the DCODE bus, and the DCODE bus derived from the DCODE_S interface is connected to the BOOT_ROM_M interface, SRAM1_M interface and SRAM2_M interface of the bus matrix.

[0051] The core is connected to the SYSBUS_S interface of the bus matrix through the SYS bus, and the SYS bus derived from the SYSBUS_S interface is connected to the SRAM3_M interface of the bus matrix. The core is connected to the AHB bus through the SYS bus.

[0052] The flash controller is connected to the AHB bus via the AHB_SLAVE_IF interface, the flash controller is connected to the FLASH_CTRL_S interface of the bus matrix via the AHB_MASTER_IF interface, and the fourth bus derived from the FLASH_CTRL_S interface is connected to the BOOT_ROM_M interface, the SRAM1_M interface and the SRAM2_M interface of the bus matrix.

[0053] The BOOT_ROM_M interface is connected to BOOT_ROM, the SRAM1_M interface is connected to SRAM1, and the SRAM2_M interface is connected to SRAM2.

[0054] When the flash controller switches to the bus master, the FLASH controller downloads the code and variables from the NAND FLASH, and transfers the code and variables to SRAM1 or SRAM2 through the AHB_MASTER_IF interface, FLASH_CTRL_S interface and SRAM1_M interface in sequence.

[0055] When the flash controller switches to the bus slave device, the kernel reads and writes information to the registers through the SYS bus, SYSBUS_S interface, and SRAM3_M interface.

[0056] Reference Figure 4 ,For the startup and operation process of the MCU controller, when the MCU controller is powered on and reset, the kernel reads the boot program from the first read-only memory, the kernel configures the flash memory controller as a bus master device according to the boot program, transfers the instructions and constants in the flash memory to the first read-write memory, the kernel's program counter jumps to the mapping address of the first read-write memory, and the kernel runs the main program.

[0057] Exemplarily, when the MCU controller is powered on and reset, the program counter of the kernel jumps to the mapping address interval of BOOT_ROM, the kernel reads the boot program from BOOT_ROM, the kernel configures the flash memory controller as the bus master device according to the boot program, the flash memory controller transfers the instructions and constants in NAND FLASH to SRAM1, the program counter jumps to the mapping address interval of SRAM1, and the kernel runs the main program.

[0058] The Program Counter (PC) is a register used to store the address of the next instruction to be executed. It is one of the core components of the MCU to execute instructions and ensure that the program can be executed in sequence.

[0059] When the MCU controller is powered on and reset, the program counter is initialized to the starting address of BOOT_ROM (such as 0x00000000), and the kernel reads the boot program from this address. After the boot program is executed, the program counter is updated to the address range of SRAM1 (such as 0x00008000), and the kernel runs the main program.

[0060] The above is a specific description of the preferred implementation of the present application, but the present application is not limited to the embodiments. Technical personnel familiar with the field can make various equivalent modifications or substitutions without violating the spirit of the present application. These equivalent modifications or substitutions are all included in the scope defined by the claims of the present application.

Claims

1. An MCU controller, characterized in that: include: core, multiple read-only memories, multiple read-write memories, registers, flash controller, and flash memory; The multiple read-only memories and the multiple read-write memories store different data types and have different mapping addresses; the kernel is respectively connected to the multiple read-only memories, the multiple read-write memories and the registers through multiple different buses, and the multiple buses are separated and parallel; the flash memory controller is connected to the multiple read-only memories and the multiple read-write memories, and the flash memory controller switches between a bus master device and a bus slave device; When the flash memory controller switches to the bus master device, the flash memory controller transfers the data to be transmitted from the flash memory to the read-write memory; When the flash memory controller switches to the bus slave device, the core performs read and write operations on the register.

2. The MCU controller according to claim 1, characterized in that: The bus includes a first bus, a second bus and a third bus, the read-only memory includes a first read-only memory and a second read-only memory, and the read-write memory includes a first read-write memory and a second read-write memory; the first read-only memory is used to store a boot program, the second read-only memory is used to store instructions and constants, the first read-write memory is used to store a stack and variables, and the second read-write memory is used to store external data.

3. The MCU controller according to claim 2, characterized in that: The core is connected to the first read-only memory, the second read-only memory and the first read-write memory through the first bus.

4. The MCU controller according to claim 2, characterized in that: The core is connected to the first read-only memory, the second read-only memory and the first read-write memory through the second bus.

5. The MCU controller according to claim 2, characterized in that: The core is connected to the second read-write memory via the third bus.

6. The MCU controller according to claim 2, characterized in that: The mapping address range of the first read-only memory is 0x00000000 to 0x00007FFF, the mapping address range of the second read-only memory is 0x00008000 to 0x0002FFFF, the mapping address range of the first read-write memory is 0x00030000 to 0x00057FFF, and the mapping address range of the second read-write memory is 0x20000000 to 0x20037FFF.

7. The MCU controller according to claim 2, characterized in that: When the flash memory controller switches to the bus slave device, the core performs read and write operations on the register through the third bus.

8. The MCU controller according to claim 2, characterized in that: The MCU controller further comprises an AHB bus, the core is connected to the AHB bus via a third bus, and the flash memory controller and the register are connected to the AHB bus.

9. The MCU controller according to claim 2, characterized in that: The first bus, the second bus, the third bus and the fourth bus are integrated into a bus matrix; the fourth bus is a data line for the flash memory controller to connect the first read-only memory, the second read-only memory and the first read-write memory.

10. The MCU controller according to claim 2, characterized in that: When the MCU controller is powered on and reset, the kernel reads the boot program from the first read-only memory, configures the flash memory controller as a bus master according to the boot program, transfers the instructions and constants in the flash memory to the first read-write memory, the program counter of the kernel jumps to the mapping address of the first read-write memory, and the kernel runs the main program.

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