Memory and operating method thereof

Abstract

The invention relates to a memory and an operating method thereof. The memory comprises a memory array and an access interface for externally accessing the memory array comprising at least one data / address multiplexing line for transmitting data and addresses. The method comprises the following steps: starting a specified fixed-number random access mode, and performing continuous read / write operation on a storage array in response to a plurality of received fixed-number random access addresses in the mode; sequentially and continuously receiving a preset fixed number of access addresses through the data / address multiplexing line; a control unit configured to sequentially and continuously output data read in response to the received access addresses via the data / address multiplexing line when the mode indicates a read operation, or sequentially and continuously receive data written in response to the received access addresses via the data / address multiplexing line when the mode indicates a write operation; and ending the mode by receiving an invalid chip enable signal. According to the scheme, the access speed of the memory can be increased.

Description

Technical Field

[0001] The present disclosure relates to the field of storage, and in particular to a storage device and an operating method thereof. Background Art

[0002] Memory usually plays an important role in electronic devices such as computers. There are many different types of memory, including static random access memory (SRAM), dynamic random access memory (DRAM), pseudo static random access memory (PSRAM), and flash memory (flash). As the performance standards of various electronic devices are getting higher and higher, faster access to memory is usually required.

[0003] Therefore, it is expected to improve the access speed of the memory. Summary of the invention

[0004] A technical problem to be solved by the present disclosure is to provide a memory and an operation method thereof, which can improve the access speed.

[0005] According to a first aspect of the present disclosure, a method for operating a memory is provided, wherein the memory comprises a memory array and an access interface for externally accessing the memory array, the access interface comprising at least one data / address multiplexing line for transmitting data and addresses, the method comprising: starting a specified fixed number random access mode, in which the memory array can be continuously read or written in response to a fixed number of multiple random access addresses received; sequentially and continuously receiving the preset fixed number of access addresses via the data / address multiplexing line; in a case where the specified fixed number random access mode indicates a read operation, sequentially and continuously outputting data read in response to each received access address via the data / address multiplexing line, or in a case where the specified fixed number random access mode indicates a write operation, sequentially and continuously receiving data to be written in response to each received access address via the data / address multiplexing line; and terminating the fixed number random access mode by receiving an invalid chip enable signal.

[0006] Optionally, the fixed number of access addresses have the same row address and random column address; and the step of sequentially and continuously receiving the preset fixed number of access addresses includes: sequentially and continuously receiving a common row address and the preset fixed number of column addresses.

[0007] Optionally, from the start of the first read / write operation to the end of the last read / write operation, the word line of the memory array corresponding to the received common row address remains in an open state.

[0008] Optionally, the access addresses received successively in sequence all include random row addresses and random column addresses.

[0009] Optionally, the output processing of data in the prior read operation via the data / address multiplexing line is performed at least partially in parallel with the word line switching processing required for the subsequent read operation; or, the word line switching processing required for the subsequent write operation is started before the data in response to the subsequent write operation is received via the data / address multiplexing line.

[0010] Optionally, the word line switching process includes: closing the word line corresponding to the row address of the previous read / write operation and opening the word line corresponding to the row address of the subsequent read / write operation.

[0011] Optionally, after receiving the access address and before outputting or receiving the read or written data, a second preset number of clock cycles preset according to the frequency of the clock cycle is waited.

[0012] Optionally, the second preset number is determined by receiving a predetermined instruction or by a pre-set mode register, wherein, when the specified fixed number of random access modes indicates a read operation, the data / address multiplexing line is released to a high impedance state during the second preset number of clock cycles.

[0013] Optionally, in the event that an invalid chip enable signal is received when a read / write operation in response to a received column address or access address is not completed, the column address or access address for which the read operation has not yet been started or the column address or access address for which any corresponding write data has not yet been received is discarded, and in the event that a write operation is in progress or write data is being received, part of the write data is discarded.

[0014] Optionally, the access interface further comprises a chip enable line, and the chip enable signal is received from the host via the chip enable line.

[0015] Optionally, the access interface also includes a transmission line, which is used to output a signal for synchronizing the sampling of data output on the data / address multiplexing line in the case of a read operation, and to receive a signal for shielding the data received on the data / address multiplexing line in the case of a write operation.

[0016] Optionally, the memory is PSRAM or Flash.

[0017] Optionally, the access interface adopts the SPI protocol.

[0018] Optionally, the number of the data / address multiplexing lines is 2N, and 2N or 2N+1 bits of data or address are output or received in each clock cycle via the data / address multiplexing lines, where N is a non-negative integer.

[0019] Optionally, the amount of data read or written by each access address is burst length*8 bits, wherein the burst length is preset in a mode register.

[0020] Optionally, a fourth preset number of clock cycles preset according to the frequency of the clock cycle is waited between outputting / receiving two data read / written in response to two access addresses.

[0021] Optionally, the fourth preset number is preset in the mode register according to the time required to complete the word line switching process and / or the time required for the refresh operation, and the frequency of the clock cycle.

[0022] Optionally, the specified fixed number random access mode is initiated by receiving a predetermined instruction via the data / address multiplexing line or by a pre-set mode register.

[0023] Optionally, the fixed number of preset access addresses is determined by receiving a predetermined instruction or by a preset mode register.

[0024] Optionally, the order of the read or written data transmitted through the data / address multiplexing line is consistent with the order of the received addresses.

[0025] The above-mentioned optional features can be combined with each other as required.

[0026] According to a second aspect of the present disclosure, a memory is provided, comprising: a memory array; an access interface for externally accessing the memory array, the access interface comprising at least one data / address multiplexing line for transmitting data and addresses; and a control component configured to control the memory to execute the method provided according to the first aspect of the present disclosure.

[0027] Therefore, the present disclosure proposes a new memory access mode for a memory with data / address line multiplexing on an access interface, which can continuously perform multiple corresponding access operations for multiple random access addresses, and compared with the existing memory access method, reduces the interval time between two accesses, thereby improving the access speed. In addition, in a fixed number random access mode, a fixed number (for example, M beats) of addresses are sent in advance, and no new access addresses are inserted during data input and output, and there is no need to switch the IO direction of the data / address multiplexing line, which can further improve the interface throughput in some cases. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other objects, features and advantages of the present disclosure will become more apparent through a more detailed description of exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, wherein like reference numerals generally represent like components in the exemplary embodiments of the present disclosure.

[0029] Figure 1 A schematic diagram showing an exemplary composition of a memory according to an embodiment of the present disclosure is shown.

[0030] Figure 2 A timing diagram showing an example of a read operation mode in a random column access mode according to an embodiment of the present disclosure is shown.

[0031] Figure 3 A timing diagram showing another example of a read operation mode in a random column access mode according to an embodiment of the present disclosure is shown.

[0032] Figure 4 A timing diagram showing an example of a write operation mode in a random column access mode according to an embodiment of the present disclosure is shown.

[0033] Figure 5 A timing diagram showing an example of a read operation mode in a random row access mode according to an embodiment of the present disclosure.

[0034] Figure 6 and Figure 7 A timing diagram showing two cases of an example of a write operation mode in a random row access mode according to an embodiment of the present disclosure is shown.

[0035] Figure 8 A timing diagram showing an example of a read operation mode in a fixed number random access mode according to an embodiment of the present disclosure.

[0036] Fig. 9 A timing diagram showing an example of a write operation mode in a fixed number random access mode according to an embodiment of the present disclosure.

[0037] Fig.10 A timing diagram showing another example of a read operation mode in a fixed number random access mode according to an embodiment of the present disclosure.

[0038] Fig.11 and Fig.12 A timing diagram showing two cases of another write operation mode example in a fixed number random access mode according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0039] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to make the present disclosure more thorough and complete, and to fully convey the scope of the present disclosure to those skilled in the art.

[0040] The technical solution of the present disclosure will be described in detail below using pseudo-static random access memory (PSRAM) as an example. However, those skilled in the art will appreciate that the present disclosure is not limited thereto but can also be applied to other memories having similar access interfaces, such as SRAM, DRAM or flash memory.

[0041] In some embodiments, the internal storage particles of PSRAM are the same as DRAM, but the external interface is different from the commonly used DRAM: in the interface of commonly used DRAM, the data (DATA) line and the command / address (Command / Address) line are separated, but in the interface of PSRAM, the DATA and Command / Address lines are usually fully or partially multiplexed (for example, the A / DQ line shown in the drawings described later transmits both data and commands and addresses).

[0042] In order to distinguish the address phase and data phase of the instruction, when performing multiple read / write operations, PSRAM usually transmits the instruction and address of the first access on the A / DQ line first, then the data corresponding to the first access, then the instruction and address of the second access, and then the data corresponding to the second access. After the first access is completed, at least a preparation time (such as tCPH shown in the following figure) is required to start the second access. The preparation time is, for example, the time required to close the word line (WordLine, WL) of the previous access, save the corresponding data and ensure that the next access can start. The preparation time is usually also the time when the chip enable signal CE# is pulled high and maintained.

[0043] The disclosure finds that the existence of the preparation time affects the access speed. In addition, the disclosure finds that the subsequent access operation (read / write operation) does not need to wait until the previous access operation is completely finished before starting, but can process a part of the read / write operations performed successively in parallel, similar to pipeline operation.

[0044] Therefore, the present disclosure proposes a variety of new memory access modes, which can continuously perform multiple corresponding access operations for multiple random access addresses, and reduce the interval time between two accesses compared to the existing access mode, thereby improving the access speed. In this article, the so-called "random" address means an address that can be arbitrarily specified by the user.

[0045] The solution of the present disclosure is described in detail below in conjunction with specific embodiments.

[0046] Figure 1 A schematic diagram showing an exemplary composition of a memory according to an embodiment of the present disclosure is shown.

[0047] like Figure 1 As shown, the memory 100 includes a memory array 110 and an access interface 120 for externally accessing the memory array, wherein the access interface 120 includes at least one data / address multiplexing line A / DQ for transmitting data and addresses.

[0048] Figure 1 is an exemplary internal block diagram of the memory 100 showing some PSRAM as an example, and Figure 1 The access interface 120 in the embodiment may use the SPI (Serial Peripheral Interface) protocol to communicate with an external host. The SPI protocol in the present disclosure may include various versions thereof, such as single-port, dual-port, 4-port or 8-port SPI protocols, etc.; the "single-port, dual-port, 4-port or 8-port" here refers to the number of data / address multiplexing lines A / DQ being 1, 2, 4 or 8 (the A / DQ line may also be referred to as 1 bit wide, 2 bits wide, 4 bits wide or 8 bits wide), so that the number of data / address bits that can be transmitted in parallel is 1 bit, 2 bits, 4 bits or 8 bits. The following will take an 8-port SPI (A / DQ transmits 1 byte (byte), i.e. 8 bits) in parallel each time) as an example to describe the various embodiments of the present disclosure, but those skilled in the art will understand that the technical solution of the present disclosure does not limit its number of bits, nor is it limited to the SPI protocol. The embodiments of the present disclosure are also applicable to other access interfaces 120 that multiplex data and address lines. In summary, the number of A / DQ lines is 2 N , output or receive 2 via the A / DQ line in each clock cycle N bit or 2 N+1 bit of data or address (wherein, if the access interface 120 adopts SDR timing, A / DQ transmits 2 bits per clock cycle N If the access interface 120 uses DDR timing, then A / DQ transmits 2 bits per clock cycle. N+1 bits), where N is a non-negative integer. It is worth noting that in one embodiment of the present disclosure, each access address is in bytes as the minimum addressing unit (i.e., the subsequent Figures 2 to 12In the waveform diagram, the amount of data for each Dout / Din is 1 byte). If accessed in burst mode, the amount of data read or written by each access address is burst length*8 bits, where burst length is the burst length, which represents the amount of data read / written by each access address (in bytes), which is preset in the mode register. In addition, in some embodiments, in addition to the data / address multiplexing line A / DQ, the access interface 120 may also include other transmission lines to transmit part of the data or address separately; for example, the access interface 120 may also include a separate address line to transmit the address in parallel with the data / address multiplexing line A / DQ.

[0049] Those skilled in the art will understand that Figure 1 The internal circuit of the memory 100 shown is only a simplified block diagram for illustrating the basic processing involved in the read and write operations of the storage array. Other components / modules may be omitted and not shown. Moreover, the arrangement and connection relationship of these internal circuit modules are not limited to Figure 1 As shown, it can be set according to the needs of the memory.

[0050] In some embodiments, Figure 1 As shown, the access interface 120 includes a clock signal line CLK, a chip enable line CE#, and a group (8) of data / address multiplexing lines A / DQ for implementing the SPI protocol; in addition, optionally, the access interface 120 also includes a transmission line DQS / DM, which is used to output a signal DQS for synchronizing the sampling of the data output on the A / DQ line in the case of a read operation, and receive a signal DM for shielding the data received on the A / DQ line in the case of a write operation. When the host performs an access operation (read / write operation) on the memory 100, the host can output a clock signal CLK to the memory to control the signal transmission timing, pull down the CE# signal to select the memory, and use the A / DQ line to exchange instructions, addresses, and data related to the read and write operations with the memory. In addition, when performing a read operation, the memory can use the DQS signal to ensure that the host correctly obtains the read data; and when performing a write operation, the host can use the DM signal to shield part of the input data so that it is not written to the corresponding address, thereby providing a more flexible writing method for the user. In addition, although not shown, as will be described in detail later, in some embodiments, the access interface 120 may further include transmission lines for other purposes, for example, another transmission line for implementing a handshake with the host to indicate that a new address can be received.

[0051] In some embodiments, Figure 1As shown, in addition to the aforementioned storage array 110 and access interface 120, the memory 100 may also include an instruction / address decoder 130, a data input / output module 140, an address latch 150, a data latch / register 160, a burst counter 170, a row / column decoder 180, and a sense amplifier (SA) / page buffer 190, which are used to perform corresponding read and write operations on the storage array 110 according to the information received by the access interface 120. In the present disclosure, these components (such as the internal circuit of the memory) used to perform read and write operations on the storage array Figure 1 The modules other than the access interface 120 and the storage array 110, including other possible modules not shown, can be collectively referred to as a control unit, which is configured to control the memory to perform corresponding preset read and write operations on the storage array according to the information received by the access interface (for example, executing the memory operation mode in each embodiment described later).

[0052] In some embodiments, the instruction / address decoder 130 can decode the instruction received by using the A / DQ line, thereby generating various control signals related to the corresponding operation mode, and sequentially storing the received addresses in the address latch 150. The size of the address latch 150 can be set according to needs (for example, the number of addresses that need to be pre-stored). Registers can also be used instead of latches to achieve the same function. The address latch 150 can be a first-in-first-out latch, so that the read and write operations can be performed sequentially according to the order in which the addresses are received, so that the order of the read or written data transmitted through the A / DQ line is consistent with the order in which the addresses are received. The address latch 150 sends a pre-stored access address to the row / column decoder 180, and the row / column decoder 180 decodes the row address and the column address therein respectively, thereby opening the word line WL corresponding to the row address and the bit line BL corresponding to the column address respectively, thereby performing corresponding read / write operations on the storage cells selected by the opened WL and BL in the storage array 110. For a read operation, the read data can be sent to the data latch / register 160 through the sense amplifier / page buffer 190, where the data can be converted from serial to parallel as needed and sent to the data input / output module 140 for subsequent serial output through the access interface 120. For a write operation, the data input / output module 140 can be used to receive the data to be written input by the access interface 120 and send it to the data latch / register 160, where the data can be converted from serial to parallel as needed and sent to the sense amplifier / page buffer 190 for subsequent parallel writing to the storage unit. The size of the data latch / register 160 and the sense amplifier / page buffer 190 used for serial-to-parallel conversion can be appropriately adjusted according to the specific application or the frequency that needs to be met.

[0053] In addition, as mentioned above, in some embodiments, the read / write operation is usually performed in a burst mode. For example, after starting the read / write operation for an access address, the bytes of the preset burst length must be read and written continuously, that is, the burst length of bytes are automatically and continuously read and written starting from the access address. The burst length can usually be set in advance by the user. Therefore, when performing the read / write operation, the burst counter 170 can be used to determine whether the burst transmission of the read / write operation is completed. The burst counter 170 can be as follows: Figure 1 It is shown as being independently arranged, or it may be multiplexed with other counters (eg, a wrap counter).

[0054] The following will be combined Figure 1 Several embodiments of the access mode of the present disclosure are described in detail with reference to the access interface examples.

[0055] Example 1: Random column access mode

[0056] In the present disclosure, "random column access" means accessing (reading / writing) operations on multiple random column addresses in the same row. Furthermore, "the same row" refers to accessing storage cells in multiple random bit lines BL corresponding to the same word line WL in the memory array 110.

[0057] The present disclosure notes that in the random column access of the traditional PSRAM (taking the read operation as an example), after the chip enable signal CE# is pulled low, it is necessary to first receive the row address (RowAddress, RA) and column address (ColumnAddress, CA) of the first access through the A / DQ line, decode through the internal circuit to control the opening of the corresponding WL and BL, read the corresponding data and put it on the A / DQ line, and then turn off the WL, pull CE# high for a certain time (for example, tCPH) and then pull it low again to start the second access, which repeats the above operation of the first access. Therefore, after each access, it is necessary to pull up CE# and wait for tCPH, and the delay from sending the first access column address CA0 on the A / DQ line to returning the first data D0 corresponding to CA0 can be, for example, as described later. Figure 2 The "read latency" shown in the figure. As mentioned above, since the instruction / address and data multiplex the A / DQ lines, the WL must be turned off after each access regardless of whether the RA is the same. Therefore, each access has the aforementioned read latency and tCPH. Moreover, even if multiple CAs of the same RA are accessed continuously, the PSRAM of the prior art needs to switch the WL multiple times. Since each switch of the WL is very time-consuming, it affects the access speed.

[0058] Therefore, the first embodiment of the present disclosure proposes a new random column access mode, in which a continuous read operation or write operation can be performed on a storage array in response to multiple access addresses received, wherein the multiple access addresses have the same row address and random column address. After starting the random column access mode of the present disclosure, multiple access addresses can be received via the A / DQ line, wherein the multiple access addresses are transmitted in the form of a common row address RA and at least one column address CA, and read and write operations are performed in response to these access addresses respectively, until CE# is pulled high (i.e., an invalid chip enable signal is received) to end the mode, thereby saving the tCPH time between two accesses, and since part of the read / write operations performed successively can be processed in parallel (for example, while the previously read data is output through the A / DQ line, the BL corresponding to the subsequent CA can be opened in parallel and its corresponding data can be read out), the delay required for subsequent CA reading and writing can also be shortened.

[0059] In some embodiments, in the random column access mode of the present disclosure, since the RAs accessed continuously are the same, the corresponding WL can remain open to continuously perform read / write operations on multiple random CAs until CE# is pulled high at the end, which not only saves the tCPH time between two accesses, but also further shortens or even saves the delay required for subsequent CA reading and writing. That is, in some random column access mode examples of the present disclosure, the word line corresponding to the received common row address remains open from the start of the first read / write operation to the end of the last read / write operation.

[0060] Several examples of random column access modes are discussed in detail below in conjunction with the timing diagrams shown in the accompanying drawings. Those skilled in the art will appreciate that many of the following details are only provided as examples for the sake of completeness of the solution and are not intended to limit the technical solution of the present disclosure.

[0061] Read operation example 1:

[0062] Figure 2 A timing diagram of a read operation pattern example 1 in a random column access mode according to an embodiment of the present disclosure is shown.

[0063] like Figure 2 As shown, the host sends a clock signal CLK to the memory, pulls the chip enable signal CE# low (for this signal, a low level indicates validity, and a high level indicates invalidity), and sends a random column read instruction ( Figure 2In the embodiment, the instruction is "03H"), thereby starting the random column access mode specified by the instruction. Those skilled in the art should understand that "03H" and the instruction values ​​in the following embodiments are only 1-byte hexadecimal numbers for illustration, and do not have any restrictions on the values ​​of the instructions; any numerical value can be agreed in advance as the value of each instruction as needed, and the number of bits is not limited.

[0064] In addition, in other implementations, a specific register in the memory (such as a mode register) may be pre-set to start a specified random column access mode, thereby eliminating the need for Figure 2 and the instruction values ​​in the timing diagrams in the subsequent embodiments ( Figure 2 The embodiment refers to the transmission of "03H"), which further saves time.

[0065] After the transmission instruction, the host sends a common row address RA and two column addresses CA0 and CA1 on the A / DQ line. In this example, the row address and column address are both 16 bits (2 bytes), and the bit width of the SPI interface is 8 bits (for example, OctalSPI is used), so sending each address takes up 2 transmission clocks (hereinafter referred to as clk); in the example timing diagram of this article, the data transmission on the A / DQ line adopts DDR (Double Data Rate) timing, that is, A / DQ can be sent on the rising edge and falling edge of CLK, so each transmission clock clk is actually half a clock cycle. Those skilled in the art understand that the embodiments of the present disclosure are not limited to DDR timing, and SDR (Single Data Rate) timing may also be used, that is, data is sent only once on the rising edge or falling edge of a clock cycle.

[0066] like Figure 2 As shown, after the host sends CA0 and the initial read delay has passed, it starts to receive data from CA0 (i.e., data burst read from the storage unit selected by RA and CA0); at this time, the burst length is set to 4 bytes, so 4 bytes of data D0-D3 are continuously output. In some embodiments, the burst length of each read / write operation can be set by pre-setting the mode register or setting the default burst length.

[0067] exist Figure 2 In the example of , from the end of data transmission from CA0 to the start of data transmission from CA1, there is still a read delay between two consecutive read operations, but because part of the stage of the read operation in response to CA1 can be performed in parallel with the read operation in response to CA0 as described above, the read delay is shortened relative to the initial read delay, for example Figure 2The "reduced read latency" shown. Figure 2 The example suggests that a new column address (eg, CA2, CA3, etc.) may be inserted during the required read delay period, ie, between every two read data outputted sequentially, thereby further reducing the time required for access and improving the access speed.

[0068] The time when the host can send (i.e., the memory receives) a new column address can be determined by the amount of data of the previous read operation that is preset (for example, 4 different burst lengths can be set through MRX[1:0] in the mode register) or the number of clock cycles required for the previous read operation. In other embodiments, a transmission line can be added to the SPI interface or a transmission line with other functions can be multiplexed to achieve handshake with the host, so as to determine when to switch the transmission content on the A / DQ line from output data to receiving address (for the host, the direction of the A / DQ line is switched from receiving data to sending new address). For example, the memory can use the handshake line to send a signal to the host to allow the new address to be sent at an appropriate time. After detecting the signal, the host starts to send the new address on the A / DQ line and uses the handshake line to notify the memory that the new address has been sent.

[0069] Since the read data and the new address have different transmission directions, Figure 2 As shown, before and after the host sends a new address, it is necessary to wait for at least a first preset number of clock cycles (also referred to as IO switching clock cycles) to switch the data transmission direction of the A / DQ line. The number of IO switching clock cycles can be pre-agreed through instructions or registers or other methods, indicating the time required to wait for switching the data transmission direction of the A / DQ line between "receiving" and "sending". In some embodiments, the host can determine how many clock cycles are required for IO switching based on the operating frequency synchronized with the PSRAM (i.e., the frequency of the clock signal CLK, such as 200M, etc.), and then set the number of clock cycles in the mode register.

[0070] In addition, if Figure 2As shown, if the initial read delay is longer than the time of IO switching plus CA0+CA1 transmission, an additional waiting time is set between CA1 and the data from CA0. "Dummy clk", that is, a dummy clock cycle can be used to represent the total waiting time between the completion of CA1 transmission and the start of transmission of data from CA0, during which IO switching can be performed. In some embodiments, the number of dummy clks here can be represented as a second preset number, which can be preset in the mode register according to the initial read delay and the frequency of the clock signal CLK. In addition, similarly, if the shortened read delay is longer than the time of two IO switching plus CA2 transmission, an additional waiting time is also set between CA2 and the data from CA1, during which IO switching can be performed. "Dummy clk", that is, a dummy clock cycle can also be used to represent the total waiting time between CA2 and the data from CA1. In some embodiments, the number of dummy clks here can be represented as a third preset number, which can be preset in the mode register according to the shortened read delay and the frequency of the clock signal CLK. In other embodiments, alternatively, the additional waiting time can be set between CA2 and the previous data from CA0, or dispersedly set between CA2 and the two previous and next read data. In addition, in some cases, the data from CA0 may be long enough and / or the interval between the two read operations may be short enough, so that there is no read delay or a very short read delay between the transmission of the data from CA0 and the data from CA1; at this time, a new column address can also be inserted between each two read data output in sequence, and only the waiting time required for IO switching (i.e., the aforementioned first preset number of "IO switching clock cycles") is required to be set between the new address and the two previous and next data. In some embodiments, during the IO switching clock cycle and / or dummy clock cycle of the aforementioned read operation, the data / address multiplexing line A / DQ is released to a high impedance state due to the need to switch the transmission direction of the data / address multiplexing line A / DQ, which can be represented by "Hiz" or "..." in each timing diagram of the present disclosure.

[0071] Then, if Figure 2 As shown, after the memory outputs the data from CA1, it can continue to receive the new column address CA3 and then output the data from CA2. Figure 2 After the host receives the data from CA2, it pulls CE# high to end the current command mode, but those skilled in the art will understand that Figure 2The number of read operations is only exemplary. The number of read operations that can be performed in the random column access mode (i.e., the total number of column addresses received) is unlimited. The memory can receive a new column address after each read data as needed, and perform a read operation in response to the new column address, and then output the corresponding read data, and continue the cycle until the host no longer needs to continue the read operation and pulls CE# high to end the random column access mode. In addition, if Figure 2 As shown, in this command mode, the last received new column address (eg CA3) will usually be discarded, that is, there is actually no need to perform a corresponding read operation on it.

[0072] In some embodiments, in the random column access mode of the present disclosure and the embodiments discussed later, when an invalid chip enable signal is received (i.e., CE# is pulled high), if there is still a read / write operation in response to the received column address or access address that has not been completed (including the case where it has not yet started), the column address or access address for which the read operation has not yet started can be discarded, or the column address or access address for which any corresponding write data has not yet been received can be discarded, that is, no read / write operation will be performed on it. For the ongoing read operation, the mode can be terminated after it is completed, or the read operation can be abandoned and the output of the data that has been read can be abandoned; for the ongoing write operation or the write operation that is receiving write data, part of the write data can be discarded, for example, for the input data that does not reach an integer multiple of 2 to the power of N (such as 8, 16, 32, etc.) when CE# is pulled high, the part of the data that does not reach the power of 2 to the power of N will not be written into the storage array, where N is a predetermined setting or agreement. It can be agreed or set in advance which of the above processing methods to be used.

[0073] From the above, it can be concluded that Figure 2 The read timing corresponding to an exemplary read instruction "03H" of the random column access mode represented by the timing diagram can be expressed as follows (it is worth noting that, as mentioned above, the present invention is not limited to starting the random column read mode with a specific read instruction "03H". In other embodiments, the random column read mode can also be started by presetting a specific mode register):

[0074] cmd+RA+CA0+CA1+dummy clk+CA0_data+dummy clk+CA2+dummy clk+CA1_data+dummy clk+CA3+dummy clk+CA2_data+……

[0075] Where "cmd" represents the instruction, "CA0" represents the column address, and "dummy clk" represents the dummy clock cycle required to be set according to the circuit implementation of the memory. Figure 2 In the embodiment, it is mainly used for the clock cycle of IO switching, the waiting time required for read delay, etc.), which can also be removed in some cases, and "CA0_data" etc. represent the data read in response to the corresponding column address CA0, etc. It should be understood by those skilled in the art that, as mentioned above, the number of clock cycles of the dummy clk at various places in the timing can be a first preset number, a second preset number, or a third preset number, which can be the same or different. In some embodiments, during each dummy clock cycle (dummy clk) during which the transmission direction of the data / address multiplexing line A / DQ needs to be switched, the A / DQ lines are released to a high impedance state.

[0076] In addition, optionally, while transmitting each read data, the memory can output a DQS signal to the host on the DQS / DM line, so that the host can better synchronize the acquired read data. "Hiz" in the timing diagram of the present disclosure indicates a high impedance state.

[0077] In addition, those skilled in the art should understand that Figure 2 The read instruction format is not intended to limit the solution of the present disclosure. For example, Figure 2 The read instruction format may also have various variations, for example, only one column address CA0 may be received in the initial stage, a new column address may be received after any selected read data rather than after each read data, or more than one new column address may be received continuously at one time, etc.; the above-mentioned various variations and combinations thereof are all within the scope of the scheme claimed to be protected by the present disclosure.

[0078] Read operation example 2:

[0079] Figure 3 is a timing diagram of another example of a read operation mode in a random column access mode according to an embodiment of the present disclosure.

[0080] Figure 3 Examples with Figure 2 The difference from the example is that when the host does not need the data from the CA1 address, it can pull CE# high in advance to end the instruction mode (03H) in advance. In other words, even if the format of the random column read instruction "03H" requires sending two column addresses (CA0+CA1) at the beginning, it is also possible to end the mode by reading only the first CA0 data. Therefore, the host can use the above read instruction "03H" mode to implement any number of read operations as needed.

[0081] As described in detail in the read operation example 1 above, the processing of the received address and data after CE# is pulled high can be agreed upon or set in advance.

[0082] Write operation example 1:

[0083] Figure 4 is a timing diagram of an example of a write operation mode in a random column access mode according to an embodiment of the present disclosure.

[0084] like Figure 4 As shown, the host sends a clock signal CLK to the memory, pulls the chip enable signal CE# low, and sends a random column write instruction ( Figure 4 In the embodiment, the instruction is "83H"), thereby starting the random column access mode specified by the instruction.

[0085] In addition, similar to the above example, in other implementations, the random column access mode can also be started by presetting a specific register (such as a mode register) in the memory, thereby eliminating the need for Figure 4 The transmission of instruction values ​​in the command can further save time.

[0086] After the transmission command, the host sends the common row address RA and the first column address CA0 on the A / DQ line. As in the previous example, sending each address occupies 2 clks.

[0087] like Figure 4 As shown in FIG. 1 , after the host sends CA0 and the initial write delay has passed, it starts to send data for CA0 (i.e., data to be written to the storage units selected by RA and CA0 in a burst, also referred to as "write data" for short); at this time, the burst length is set to 4 bytes, so the host sends 4 bytes of data D0-D3 in succession. In some cases, as described above, Figure 2 Similar to the read operation example, a second preset number of clock cycles can be set between the completion of CA0 transmission and the start of transmission of data for CA0 according to the initial write delay and the frequency of the clock signal CLK, which can be represented by "dummy clk", i.e., dummy clock cycles. The second preset number can be preset in the mode register. In other cases, such as when there is enough space inside the memory to pre-store write data, data for CA0 can be sent immediately after CA0 without arranging a preset number of dummy clock cycles (dummy clk) according to the initial write delay.

[0088] Since parts of the two consecutive write operations can be performed in parallel as described above, the subsequent write delay is shorter than the initial write delay, or may even be non-existent. Figure 4As shown, after the host sends the data for CA0, it can seamlessly continue to send the new column address CA1 and the write data for CA1 and the subsequent new column address CA2 and the write data for CA2, and then pull CE# high to end the current instruction mode. In the present disclosure, "seamless" sending or receiving means that there is no need to wait before sending or receiving. Since the transmission direction of the address and write data during the write operation is from the host to the memory, there is no IO switching and the required waiting time (i.e., "IO switching clock cycle") in the aforementioned read operation example, and the host can insert CA seamlessly between two adjacent write data sent on the A / DQ line.

[0089] Those skilled in the art will understand that Figure 4 The number of write operations is only exemplary. The number of write operations that can be performed in the random column access mode (i.e., the total number of column addresses received by the memory) is unlimited. The host can also Figure 4 After receiving the write data for CA2, any number of new column addresses and their write data are sent, and then CE# is pulled high to end the current command mode. In other words, the memory can receive a new column address and the write data in response to it after each write data is received, and perform the corresponding write operation on it, and the cycle continues until the host no longer needs to continue the write operation, and then CE# is pulled high to end the random column access mode.

[0090] As described in the previous read operation example 1, in some embodiments, when an invalid chip enable signal is received (i.e., CE# is pulled high), the last write data may not have been transmitted or not completed. At this time, the last write operation can be abandoned or the part of the data that does not make up 2 to the power of N can be discarded and not written into the storage array, where N is a predetermined setting or agreement. For example, in some cases, 2 to the power of 6 (i.e., 64 bits) of data are written into the storage array in parallel each time inside the memory, so for the write data transmitted with an 8-bit width, 8 write data (a total of 8 bytes) are used as a group for writing, and if the last group of write data does not make up 8 when CE# is pulled high, the group of data is completely discarded, that is, not written into the storage array (for example, if CE# is pulled high before data D10 is transmitted, the previously transmitted D0-D7 make up a group and can be written, but the last remaining D8-D10 does not make up a group and is completely discarded).

[0091] From the above, it can be concluded that Figure 4The write timing corresponding to an exemplary write instruction "83H" of the random column access mode represented by the timing diagram can be expressed as follows (it is worth noting that, as mentioned above, the present invention is not limited to starting the random column write mode with a specific write instruction "83H". In other embodiments, the random column write mode can also be started by presetting a specific mode register):

[0092] cmd+RA+CA0+dummy clk+CA0_data+CA1+CA1_data+CA2+CA2_data……

[0093] Where "cmd" represents the instruction, "CA0" represents the column address, and "dummy clk" represents the dummy clock cycle required to be set according to the circuit implementation of the memory. Figure 4 The embodiment mainly includes the waiting time required for the initial write delay, and its number may be the second preset number mentioned above. In some cases, it may also be removed. "CA0_data" etc. represents the data to be written in response to the corresponding column address CA0 etc.

[0094] Additionally, optionally, Figure 4 As shown, while transmitting each write data, the host can send a DM signal on the DQS / DM line, thereby shielding the write data as needed. Although "×" is used to represent the value of the DM signal in the figure, it should be understood that the DM signal in the period of sending each data can be set to a high level or a low level as needed. For example, in some cases, the DM signal is valid at a high level. If the host does not want to write the D1 data in the data for CA0 into the storage array, the DM signal of the half clock cycle that is the same as the transmission of the D1 data can be set to 1, thereby shielding the D1 data.

[0095] In addition, those skilled in the art should understand that Figure 4 The write instruction format is not intended to limit the solution of the present disclosure. For example, Figure 4 There may be various variations of the write instruction format, for example, more than one column address (for example, CA0+CA1+...) may be received in the initial stage, a new column address may be received after any selected write data rather than after each write data, and more than one new column address may be received continuously at one time; the above-mentioned variations and combinations thereof are all within the scope of the scheme claimed to be protected by the present disclosure.

[0096] In the read / write operation examples given above, the number of consecutive read / write operations does not need to be preset, that is, any number of consecutive read / write operations can be performed; as long as the specific access mode that is activated has not ended (that is, the high CE# is not received), the memory can continue to receive new addresses and perform read / write operations based on them.

[0097] In addition, in other embodiments, as will be described in detail in Example 3, the random column access mode of the present disclosure may also include a method, that is, presetting the number of consecutive read / writes, and after the startup mode, sequentially receiving a common row address and a predetermined number of column addresses, and then sequentially transmitting the corresponding read and write data for the received addresses. Although this method is discussed as a specific example of a fixed number random access mode in Example 3, it can also be called a specific example of a random column access mode; these two modes are divided from different perspectives, which does not mean that the two are completely different modes.

[0098] Example 2: Random row access mode

[0099] This mode can also be called multi-page access mode, which means access (read / write) operations are performed on random column addresses in multiple random rows (multiple random pages). One page corresponds to one row and refers to the total amount of data stored in one WL (e.g., 1K).

[0100] For conventional DRAM, since DRAM is divided into banks, all WLs corresponding to the banks can be opened, and data in different banks can be accessed in parallel by switching different RAs and CAs. However, for conventional PSRAM, due to cost considerations, PSRAM is usually not divided into multiple banks, so only one WL can be opened at the same time. Also, because its instruction / address and data multiplex the A / DQ lines, the efficiency is low when performing multi-page access.

[0101] Therefore, the second embodiment of the present disclosure designs a random row access mode for different RA switching (i.e., different WL switching), in which a continuous read operation or write operation can be performed on the storage array in response to multiple access addresses received, wherein the multiple access addresses have random row addresses and random column addresses. After starting the random row access mode of the present disclosure, at least two access addresses can be initially received via the A / DQ line, and a new access address can be optionally received later, and read and write operations are performed in response to these access addresses, respectively, until CE# is pulled high (i.e., an invalid chip enable signal is received) to terminate the mode, thereby eliminating the tCPH time between two accesses, and since part of the stages of the read operations performed successively can be processed in parallel, the delay required for subsequent reads can also be shortened. In one embodiment, before the data in response to the previous read operation RA0CA0 is outputted via the A / DQ line, the word line switching process required for the subsequent read operation RA1CA1 is started, and the word line switching process is, for example, closing the word line WL0 corresponding to the row address RA0 of the previous read operation and opening the word line WL1 corresponding to the row address RA1 of the subsequent read operation. In other embodiments, since multiple read operation addresses, such as RA0CA0, RA1CA1, and RA2CA2, have been pre-stored in the address latch 150, if the number of data latches / registers 160 is sufficient, the word line switching process required for the subsequent read operation RA2CA2 can be performed even while the data in response to the previous read operation RA0CA0 is outputted via the A / DQ line.

[0102] Several examples of random row access modes are discussed in detail below in conjunction with the timing diagrams shown in the accompanying drawings. Those skilled in the art will appreciate that many of the following details are only provided as examples for the sake of completeness of the solution and are not intended to limit the technical solution of the present disclosure.

[0103] Read operation example 1:

[0104] Figure 5 A timing diagram of a read operation pattern example 1 in a random row access mode according to an embodiment of the present disclosure is shown.

[0105] like Figure 5 As shown, the host sends a clock signal CLK to the memory, pulls the chip enable signal CE# low, and sends a random row read instruction ( Figure 5 In the embodiment, the instruction is "02H"), thereby starting the random row access mode specified by the instruction.

[0106] In addition, in other implementations, a specific register (such as a mode register) in the memory may be pre-set to start the specified random row access mode, thereby eliminating the need for Figure 5 The instruction value in ( Figure 5The embodiment refers to the transmission of "02H"), which further saves time.

[0107] After the transmission instruction, the host sends two access addresses on the A / DQ line, namely RA0+CA0 and RA1+CA1. Similar to the previous example, sending each row address or column address occupies 2 clks.

[0108] like Figure 5 As shown, after the host sends CA0 and the initial read delay, it starts to receive data from RA0CA0 (i.e., the data read in burst from the storage unit selected by RA0 and CA0); at this time, the burst length burstlength is set to 16 bytes, so 16 bytes of data D0-D15 are output continuously, that is, opening one WL requires 16 consecutive reads Dout. In some embodiments, the burst length of each read / write operation or the default burst length can be set by presetting the mode register. In some embodiments of the random row access mode, the lowest 3 bits of each column address are set to 0, that is, CA[2:0]=000.

[0109] In some implementations, the PSRAM first turns on the WL corresponding to RA0, then turns on the BL corresponding to CA0, and reads out the data (D0-D15) from RA0CA0 and sends it to the IO bus. While sending these read data out through the A / DQ line, since the PSRAM has pre-stored the address RA1+CA1 for the next access, the WL corresponding to RA0 can be turned off, the WL corresponding to RA1 can be turned on, and the BL corresponding to CA1 can be turned on to read out the data from RA1CA1. Therefore, the output processing of the data in the previous read operation and the word line switching processing required for the subsequent read operation are at least partially performed in parallel, and at least the time of these parallel processing can be saved between two consecutive read operations.

[0110] Combined with the previous Figure 2 Similar to the example described above, Figure 5 In the example, a new access address (such as RA2+CA2, RA3+CA3, etc.) can be inserted during the read delay period between two consecutive read operations, that is, between every two read data output in sequence, thereby further reducing the access time and improving the access speed.

[0111] Combined with the previous Figure 2Similar to the above example, the time when the host can send (i.e., the memory receives) a new access address can be determined by presetting the amount of data of the previous read operation (e.g., burst length) or the number of clock cycles required for the previous read operation, and the PSRAM can also know when to turn off the currently turned-on WL. In other implementations, a transmission line can be added to the SPI interface or a transmission line with other functions can be multiplexed to achieve handshake with the host, so as to determine when to switch the transmission content on the A / DQ line from outputting data to receiving addresses (for the host, the direction of the A / DQ line is switched from receiving data to sending new addresses).

[0112] Combined with the previous Figure 2 Similar to the example described above, since the read data and the new address are transferred in different directions, Figure 5 As shown, before and after the host sends a new address, it is necessary to wait for at least a first preset number of clock cycles to switch the data transmission direction of the A / DQ line. The first preset number can be pre-agreed through instructions or registers or other methods, indicating the time required to wait for switching the data transmission direction of the A / DQ line between "receiving" and "sending". In some embodiments, the host can determine how many clock cycles are required for IO switching based on the operating frequency synchronized with the PSRAM, and then set the number of clock cycles in the mode register.

[0113] Combined with the previous Figure 2The example described is similar, if the initial read delay is longer than the time of IO switching plus RA0+CA0+RA1+CA1 transmission, then an additional waiting time is set between CA1 and the data from RA0CA0. "Dummy clk", that is, a dummy clock cycle, can be used to represent the total waiting time between the completion of CA1 transmission and the start of transmission of data from RA0CA0, during which IO switching can be performed. In some embodiments, the number of dummy clks here can be represented as a second preset number, which can be preset in the mode register according to the initial read delay and the frequency of the clock signal CLK. In addition, similarly, if the subsequent shortened read delay is longer than the time of two IO switching plus RA2+CA2 transmission, then an additional waiting time is set between RA2+CA2 and the data from RA1CA1 and / or between RA2+CA2 and the previous data from RA0CA0, during which IO switching can be performed. "Dummy clk", that is, a dummy clock cycle, can also be used to represent the total waiting time between RA2+CA2 and the data from RA1CA1 and / or between RA2+CA2 and the previous data from RA0CA0. In some embodiments, the number of dummy clks here can be represented as a third preset number, which can be preset in the mode register according to the time required for the word line switching operation, that is, the time required to close the word line corresponding to the previous access address RA0 and open the word line corresponding to the next access address RA1 and the frequency of the clock signal CLK. In addition, in some cases, the data from RA0CA0 may be long enough and / or the interval between two read operations is short enough, so that there is no read delay or a very short read delay between the transmission of the data from RA0CA0 and the data from RA1CA1; at this time, a new access address can also be inserted between each two read data output in sequence, and only the waiting time required for IO switching (that is, the aforementioned first preset number of "IO switching clock cycles") is required to be set between the new address and the two previous and next data. In some embodiments, during the aforementioned IO switching clock cycle and / or dummy clock cycle, when indicating a read operation, the data / address multiplexing line A / DQ is released to a high impedance state because the transmission direction of the data / address multiplexing line A / DQ needs to be switched.

[0114] Then, if Figure 5 As shown, after the memory outputs the data from RA1CA1, it can continue to receive the new access address RA3+CA3 and then output the data from RA2CA2. Figure 5 After the host receives the data from RA2CA2, it pulls CE# high to end the current instruction mode, but those skilled in the art will understand that Figure 5The number of read operations is only exemplary. The number of read operations that can be performed in the random row access mode (i.e., the total number of access addresses received) is unlimited. The memory can receive a new access address after each read data as needed, and perform a read operation in response to the new access address, and then output the corresponding read data, and continue the cycle until the host no longer needs to continue the read operation and pulls CE# high to end the random row access mode. In addition, if Figure 5 As shown, in this instruction mode, the last received new access address (eg RA3+CA3) will usually be discarded, that is, there is actually no need to perform a corresponding read operation on it.

[0115] As in front Figure 2 As described in the example of , in some implementations, CE# may be pulled high in advance, and various processing methods agreed upon or set in advance may be used for read operations that are not completed at this time.

[0116] From the above, it can be concluded that Figure 5 The read timing corresponding to an exemplary read instruction "02H" of the random row access mode represented by the timing diagram can be expressed as follows (it is worth noting that, as mentioned above, the present disclosure is not limited to starting the random row read mode with a specific read instruction "02H". In other embodiments, the random row read mode can also be started by presetting a specific mode register):

[0117] cmd+RA0+CA0+RA1+CA1+dummy clk+RA0CA0_data+dummy clk+RA2+CA2+dummy clk+RA1CA1_data+dummy clk+RA3+CA3+dummy clk+RA2CA2_data+……

[0118] Wherein "cmd" represents an instruction, "RA0" etc. represent each row address, "CA0" etc. represent each column address, "dummy clk" represents a dummy clock cycle (including IO switching clock cycle, waiting time required for read delay, etc.) required to be set according to the circuit implementation of the memory, which can also be removed in some cases, and "RA0CA0_data" etc. represent data read in response to the corresponding row address RA0 and column address CA0, etc. It should be understood by those skilled in the art that, as mentioned above, the number of clock cycles of the dummy clk at each place in the timing can be a first preset number, a second preset number, or a third preset number, which can be the same or different. In addition, whether dummy clk is needed and how many dummy clks are needed are related to the specific design of the memory. In some embodiments, during each dummy clock cycle (dummy clk) during which the transmission direction of the data / address multiplexing line A / DQ needs to be switched, the A / DQ line is released to a high impedance state.

[0119] In addition, combined with the previous Figure 2 Similar to the example described above, optionally, while transmitting each read data, the memory can output a DQS signal to the host on the DQS / DM line, so that the host can better synchronize the acquisition of the read data.

[0120] In addition, those skilled in the art should understand that Figure 5 The read instruction format is not intended to limit the solution of the present disclosure. For example, Figure 5 The read instruction format may also have various variations, for example, more than two access addresses may be received in the initial stage, a new access address may be received after any selected read data rather than after each read data, or more than one new access address may be received continuously at one time, etc.; the above-mentioned variations and combinations thereof are all within the scope of the scheme claimed to be protected by the present disclosure.

[0121] Write operation example 1:

[0122] Figure 6 and Figure 7 A timing diagram showing two cases of an example of a write operation mode in a random row access mode according to an embodiment of the present disclosure is shown.

[0123] As can be seen from the two figures, Figure 7 and Figure 6 The only difference is Figure 7There is no additional write delay caused by refresh. Specifically, PSRAM is self-refreshing, and its refresh operation has its own independent execution order in parallel with reading and writing. Therefore, some read and write operations may encounter refresh, that is, the row to be read or written is undergoing refresh operation. In some cases, for write operations, it may take longer to wait when there is refresh, that is, if Figure 6 and Figure 7 As shown, there is an initial write delay when refreshing ( Figure 6 ) is longer than the initial write latency when no refresh is present ( Figure 7 In some implementations, the write delays (or the number of corresponding dummy clock cycles (dummyclk)) in these two cases may be agreed upon in advance, and corresponding settings may be selected according to the refresh conditions during the write operation.

[0124] The following is Figure 6 Let's discuss this write mode example in detail.

[0125] like Figure 6 As shown, the host sends a clock signal CLK to the memory, pulls the chip enable signal CE# low, and sends a random column write instruction ( Figure 6 In the embodiment, the instruction is "82H"), thereby starting the random row access mode specified by the instruction.

[0126] In addition, similar to the above example, in other implementations, the random row access mode can also be started by presetting a specific register (such as a mode register) in the memory, thereby eliminating the need for Figure 6 and Figure 7 The transmission of instruction values ​​in the command can further save time.

[0127] After the transmission instruction, the host sends two access addresses on the A / DQ line, namely RA0+CA0 and RA1+CA1. Similar to the previous example, sending each row address or column address occupies 2 clks.

[0128] like Figure 6 As shown in FIG. 1 , after the host sends CA1 and the initial write delay has passed, it starts to send data for RA0CA0 (i.e., data to be written to the storage units selected by RA0 and CA0 in a burst, also referred to as "write data" for short); at this time, the burst length is set to 16 bytes, so the host sends 16 bytes of data D0-D15 in succession. In some cases, as described above, Figure 2Similar to the read operation example, a second preset number of clock cycles can be set between the completion of CA1 transmission and the start of transmission of data for RA0CA0 according to the initial write delay and the frequency of the clock signal CLK, which can be represented by "dummy clk", i.e., dummy clock cycles. The second preset number can be preset in the mode register. In other cases, such as when there is enough space inside the memory to pre-store write data, data for RA0CA0 can also be sent immediately after CA1 without arranging a preset number of dummy clock cycles (dummy clk) according to the initial write delay.

[0129] Similar to the above example, since the access address of the subsequent operation is pre-stored, some stages of the two write operations performed successively can be performed in parallel. In one embodiment, before the data in response to the subsequent write operation RA1CA1 is received via the A / DQ line, the word line switching process required for the subsequent write operation is started. The word line switching process is, for example: closing the word line WL0 corresponding to the row address RA0 of the previous write operation and opening the word line WL1 corresponding to the row address RA1 of the subsequent write operation. In other embodiments, since the addresses RA0CA0, RA1CA1, etc. of multiple write operations have been pre-stored in the address latch 150 in advance, if the number of data latches / registers 160 is sufficient, the receiving process of the data of the subsequent write operation RA1CA1 can even be performed in parallel with the word line switching process required for the previous write operation RA0CA0, thereby reducing the time of continuous write operations and improving the access speed. In some cases, since WL switching is required between the two access operations in the random row access mode, the subsequent write delay is longer than that in the random column access mode, which is different from the previous Figure 5 Similar to the example of , a third preset number of dummy clock cycles (dummy clk) can be inserted between the two previous write data as needed. For example, the third preset number can be preset in the mode register according to the word line switching operation, that is, the time required to close the word line corresponding to the previous access address and open the word line corresponding to the next access address and the frequency of the clock signal CLK. Thus, if Figure 6 As shown, after the host sends the data for RA0CA0, it can seamlessly continue to send the new access address RA2+CA2, and then send the write data for RA1CA1 after waiting for a preset number of dummy clock cycles, and then pull CE# high to end the current instruction mode.

[0130] Those skilled in the art will understand that Figure 6 The number of write operations is only exemplary. The number of write operations that can be performed in the random row access mode (i.e., the total number of access addresses received by the memory) is unlimited. The host can also Figure 6After the write data for RA1CA1, the new access address RA3+CA3 and the write data for RA2CA2 are sent, and the cycle continues until the host no longer needs to continue the write operation and pulls CE# high to end the current instruction mode. In other words, the memory can receive a new access address between each two data written in response to the two previously received access addresses, and the cycle continues until the host pulls CE# high to end the mode. In addition, if Figure 6 As shown, in this instruction mode, the last received new access address (eg RA2+CA2) will usually be discarded, that is, there is actually no need to perform a corresponding write operation on it.

[0131] As described in the previous examples, in some embodiments, when an invalid chip enable signal is received (i.e., CE# is pulled high), the last write data may not have been transmitted or not fully transmitted. At this time, the last write operation can be abandoned or the last part of the data that does not reach the power of 2N can be discarded and not written into the storage array, where N is a predetermined setting or agreement.

[0132] From the above, it can be concluded that Figure 6 and Figure 7 The write timing corresponding to an exemplary write instruction "82H" of the random row access mode represented by the timing diagram can be expressed as follows (it is worth noting that, as mentioned above, the present disclosure is not limited to starting the random row write mode with a specific write instruction "82H". In other embodiments, the random row write mode can also be started by presetting a specific mode register):

[0133] cmd+RA0+CA0+RA1+CA1+dummy clk+RA0CA0_data+RA2+CA2+dummy clk+RA1CA1_data+RA3+CA3+dummy clk+RA2CA2_data+……

[0134] Among them, "cmd" represents the instruction, "RA0" etc. represent the row addresses, "CA0" etc. represent the column addresses, "dummy clk" represents the dummy clock cycle required to be set according to the circuit implementation of the memory, which can also be removed in some cases, and "RA0CA0_data" etc. represent the data to be written in response to the corresponding row address RA0 and column address CA0 etc.

[0135] In addition, if Figure 7 As shown, in some embodiments, when no refresh occurs, the dummy clk between the second access address RA1+CA1 and the data RA0CA0_data to be written in the first access may be omitted.

[0136] In addition, in other embodiments, the dummy clk between the third access address RA2+CA2 and the data RA1CA1_data to be written in the second access can be changed to be set between RA2+CA2 and the previous written data RA0CA0_data, or distributed between RA2+CA2 and the previous and next two written data.

[0137] In addition, similar to the above-mentioned write operation example, optionally, Figure 6 As shown, while transmitting each write data, the host can send a DM signal on the DQS / DM line to mask the write data as needed.

[0138] In addition, those skilled in the art should understand that Figure 6 The write instruction format is not intended to limit the solution of the present disclosure. For example, Figure 6 The write instruction format may also have various variations, for example, more than two access addresses (for example, RA0+CA0+RA1+CA1+RA2+CA2+...) may be received in the initial stage, a new access address may be received after any selected write data rather than after each write data, or more than one new access address may be received continuously at one time, etc.; the above-mentioned variations and combinations thereof are all within the scope of the scheme claimed to be protected by the present disclosure.

[0139] In the read / write operation examples given above, there is no need to preset the number of consecutive read / write operations, that is, any number of consecutive read / write operations can be performed; as long as the specific access mode that is activated has not ended (that is, the high CE# has not been received), the memory can continue to receive new access addresses and perform read / write operations based on them.

[0140] In addition, in other embodiments, as will be described in detail in Example 3, the random row access mode of the present disclosure may also include a method, that is, presetting the number of consecutive read / writes, and after the startup mode, sequentially receiving a predetermined number of access addresses, and then sequentially transmitting the corresponding read and write data for the received addresses. Although this method is discussed as a specific example of a fixed number random access mode in Example 3, it can also be called a specific example of a random row access mode; these two modes are divided from different perspectives, which does not mean that the two are completely different modes.

[0141] Example 3: Fixed number random access mode

[0142] Embodiment 3 of the present disclosure proposes a fixed number random access mode, which means that access (read / write) operations are performed on a fixed number of access addresses (also referred to as fixed M-th access addresses, where M>1).

[0143] In the aforementioned examples, the host needs to insert new column / row addresses that need to be accessed later between reading data / writing data, and there is no limit on the total number of column / row addresses. In contrast, in a fixed number random access mode, a fixed number (e.g., M beats) of addresses are sent in advance using the waiting time of the initial delay, and no new access addresses are inserted during data input and output, and there is no need to switch the IO direction of the data / address multiplexing line, which can further improve the throughput of the interface in some cases. In particular, for read operations, the switching between data and addresses requires the host and PSRAM to continuously switch the IO transmission direction, which will increase the design complexity and additional delays, while the fixed number random access mode reduces the need for the above-mentioned IO direction switching. In some embodiments, the host can determine the value of M by presetting a register in the memory (e.g., a mode register), or can specify the value of M by setting a few bits in the instruction transmitted at the beginning.

[0144] In conjunction with the timing diagram shown in the accompanying drawings, several examples of fixed number random access modes are discussed in detail by taking the example of sending 4-beat addresses (M=4) in advance, wherein read operation example 1 and write operation example 1 correspond to the previous embodiment 1, and can also be regarded as read / write examples in the random column access mode, and read operation example 2 and write operation example 2 correspond to the previous embodiment 2, and can also be regarded as read / write examples in the random row access mode. Those skilled in the art will understand that many of the following details are only exemplified for the completeness of the scheme, and are not intended to limit the technical solution of the present disclosure.

[0145] Read operation example 1:

[0146] Figure 8 A timing diagram of a read operation pattern example 1 in a fixed number random access mode according to an embodiment of the present disclosure is shown.

[0147] Figure 8 The read operation is similar to the above Figure 2 The read operations are similar to those of Figure 8 The address and data transmission order in the above example can be found in the previous section for details and variations of other operations. Figure 2 The relevant description will not be repeated here.

[0148] like Figure 8 As shown, the host sends a clock signal CLK to the memory, pulls the chip enable signal CE# low, and sends a fixed number of random read instructions on the A / DQ line ( Figure 8 In the embodiment, the instruction is "04H"), thereby starting the fixed number random access mode specified by the instruction.

[0149] After the transmission command, the host sends the common row address RA and 4 column addresses CA0-CA3 on the A / DQ line. Then, after the above Figure 2 After a second preset number of dummy clock cycles (dummy clk) similar to the example, the host starts to receive data from CA0; at this time, the burst length is set to 16 bytes, so 16 bytes of data D0-D15 are continuously output. Then, the host continues to receive data from CA1, data from CA2, and data from CA3. After the predetermined 4 read data are received, the host pulls up CE# to end the instruction mode. In this instruction mode, no new address will be inserted between 2 data. In some cases, if the host does not need to read 4 data, for example, the host only wants to perform 3 read operations in succession, then CE# can be pulled high after receiving the data from CA2 to end the instruction mode in advance, or the value of M can be adjusted to 3 through a register or a partial bit in the instruction.

[0150] From the above, it can be concluded that Figure 8 The read timing corresponding to an exemplary read instruction "04H" of the fixed number random access mode represented by the timing diagram can be expressed as follows (it is worth noting that, as mentioned above, the present disclosure is not limited to starting the fixed number random read mode with a specific read instruction "04H". In other embodiments, the fixed number random read mode can also be started by presetting a specific mode register):

[0151] cmd+RA+CA0+…+CAn+dummy clk+CA0_data+…+CAn_data

[0152] Where n is equal to the value of (M-1), "cmd" represents the instruction, "CA0" etc. represent the column addresses, "dummy clk" represents the dummy clock cycle required to be set according to the circuit implementation of the memory (including the IO switching clock cycle, the waiting time required for the read delay, etc.), which can also be removed in some cases, and "CA0_data" etc. represent the data read in response to the corresponding column address CA0 etc. In addition, in some cases, "dummyclk" can be added between the read data as needed.

[0153] In addition, those skilled in the art should understand that Figure 8 The read instruction format is not intended to limit the solution of the present disclosure. For example, Figure 8 There may be various variations of the read instruction format, for example, the transmission order of each address or each data may be changed, or "dummy clk" may be added at any appropriate position as needed; the above-mentioned variations and combinations thereof are all within the scope of the solution claimed to be protected by the present disclosure.

[0154] Write operation example 1:

[0155] Fig. 9 A timing diagram of write operation pattern example 1 in a fixed number random access mode according to an embodiment of the present disclosure is shown.

[0156] Fig. 9 The write operation is the same as the above Figure 4 The write operations are similar to those of Fig. 9 The address and data transmission order in the above example can be found in the previous section for details and variations of other operations. Figure 4 The relevant description will not be repeated here.

[0157] like Fig. 9 As shown, the host sends a clock signal CLK to the memory, pulls the chip enable signal CE# low, and sends a fixed number of random write instructions on the A / DQ line ( Fig. 9 In the embodiment, the instruction is "84H"), thereby starting the fixed number random access mode specified by the instruction.

[0158] After the transmission command, the host sends the common row address RA and 4 column addresses CA0-CA3 on the A / DQ line. Then, after the above Figure 4 After a second preset number of dummy clock cycles (dummy clk) similar to the example, the host starts to send data for CA0; at this time, the burst length is set to 16 bytes, so 16 bytes of data D0-D15 are sent continuously. Then, the host continues to send data for CA1, data for CA2, and data for CA3. After the predetermined 4 write data are sent, the host pulls up CE# to end the instruction mode. In some cases, if the host does not need to write 4 data, for example, the host only wants to perform 3 write operations in succession, then CE# can be pulled high after sending the data for CA2 to end the instruction mode in advance, or the value of M can be adjusted to 3 through some bits in the register or instruction. In some cases, when CE# is pulled high in advance, the current write data has not been transmitted, so similar to the previous example, the part of the write data that does not reach the Nth power of 2 in the end may not be written into the storage array.

[0159] From the above, it can be concluded that Fig. 9The write timing corresponding to an exemplary write instruction "84H" of the fixed number random access mode represented by the timing diagram can be expressed as follows (it is worth noting that, as mentioned above, the present disclosure is not limited to starting the fixed number random write mode with a specific write instruction "84H". In other embodiments, the fixed number random write mode can also be started by presetting a specific mode register):

[0160] cmd+RA+CA0+…+CAn+dummy clk+CA0_data+…+CAn_data

[0161] Where n is equal to the value of (M-1), "cmd" represents the instruction, "CA0" etc. represent the column addresses, "dummy clk" represents the dummy clock cycle required to be set according to the circuit implementation of the memory, which may also be removed in some cases, and "CA0_data" etc. represent the data written in response to the corresponding column address CA0 etc. In addition, in some cases, "dummy clk" may be added between the written data as needed.

[0162] In addition, those skilled in the art should understand that Fig. 9 The write instruction format is not intended to limit the solution of the present disclosure. For example, Fig. 9 There may be various variations of the write instruction format, for example, the transmission order of each address or each data may be changed, or "dummy clk" may be added at any appropriate position as needed; the above-mentioned variations and combinations thereof are all within the scope of the scheme claimed for protection by the present disclosure.

[0163] Read operation example 2:

[0164] Fig.10 A timing diagram of read operation pattern example 2 in a fixed number random access mode according to an embodiment of the present disclosure is shown.

[0165] Fig.10 The read operation is similar to the above Figure 5 The read operations are similar to those of Fig.10 The address and data transmission order in the above example can be found in the previous section for details and variations of other operations. Figure 5 The relevant description will not be repeated here.

[0166] like Fig.10 As shown, the host sends a clock signal CLK to the memory, pulls the chip enable signal CE# low, and sends a fixed number of random read instructions on the A / DQ line ( Fig.10 In the embodiment, the instruction is "05H"), thereby starting the fixed number random access mode specified by the instruction.

[0167] After the transmission instruction, the host sends four access addresses RA0+CA0, RA1+CA1, RA2+CA2, and RA3+CA3 on the A / DQ line. Figure 5 After the second preset number of dummy clock cycles (dummyclk) similar to the example set, the host starts to receive data from RA0CA0; at this time, the burst length is set to 16 bytes, so 16 bytes of data D0-D15 are continuously output. Then, after the fourth preset number of dummy clock cycles (dummy clk), the host continues to receive data from RA1CA1, data from RA2CA2, and data from RA3CA3, wherein the fourth preset number of dummy clock cycles (dummy clk) must be waited between each two read data. In some embodiments, the fourth preset number can be preset in the mode register according to the time required to complete the word line switching process and the frequency of the clock cycle. After the predetermined 4 read data are received, the host pulls up CE# to end the instruction mode. In this instruction mode, a new address will not be inserted between 2 data. In some cases, if the host does not need to read 4 data, for example, the host only wants to perform 3 consecutive read operations, it can pull CE# high after receiving the data from RA2CA2 to end the instruction mode early, or the value of M can be adjusted to 3 through some bits in the register or instruction.

[0168] From the above, it can be concluded that Fig.10 The read timing corresponding to an exemplary read instruction "05H" of the fixed number random access mode represented by the timing diagram can be expressed as follows (it is worth noting that, as mentioned above, the present disclosure is not limited to starting the fixed number random read mode with a specific read instruction "05H". In other embodiments, the fixed number random read mode can also be started by presetting a specific mode register):

[0169] cmd+RA0+CA0+……+RAn+CAn+dummy clk+RA0CA0_data+dummy clk+……+RAnCAn_data

[0170] Where n is equal to the value of (M-1), "cmd" represents the instruction, "RA0" etc. represent the row addresses, "CA0" etc. represent the column addresses, "dummy clk" represents the dummy clock cycle required to be set according to the circuit implementation of the memory (including the IO switching clock cycle, the waiting time required for the read delay, etc.), which can also be removed in some cases, "RA0CA0_data" etc. represent the data read in response to the corresponding access address RA0+CA0, etc. It should be understood by those skilled in the art that, as mentioned above, the number of clock cycles of the dummy clk at each location in the timing can be the second preset number or the fourth preset number, which can be the same or different.

[0171] Similar to the above example, since the access address (e.g., RA1CA1) of the subsequent read operation is pre-stored, some stages of the two consecutive read operations can be performed in parallel: for example, the output processing of the data of the previous read operation via the A / DQ line and the word line switching processing required for the subsequent read operation can be at least partially performed in parallel, thereby reducing the time of the continuous read operation and improving the access speed. In one embodiment, before the data output in response to the previous read operation via the A / DQ line is completed, the word line switching processing of the subsequent read operation is started, and the word line switching processing includes: closing the word line (e.g., WL0) corresponding to the row address (e.g., RA0) of the previous read operation and opening the word line (e.g., WL1) corresponding to the row address (e.g., RA1) of the subsequent read operation.

[0172] In addition, those skilled in the art should understand that Fig.10 The read instruction format is not intended to limit the solution of the present disclosure. For example, Fig.10 There may be various variations of the read instruction format, for example, the transmission order of each address or each data may be changed, or "dummy clk" may be added at any appropriate position as needed; the above-mentioned variations and combinations thereof are all within the scope of the solution claimed to be protected by the present disclosure.

[0173] Write operation example 2:

[0174] Fig.11 and Fig.12 Timing diagrams of two cases of write operation pattern Example 2 in a fixed number random access mode according to an embodiment of the present disclosure are shown.

[0175] Fig.11 and Fig.12 The write operation is the same as the above Figure 6 and Figure 7 The write operation is similar to that of , the difference mainly lies in the order of address and data transfer and the number of write operations. Fig.11 and Fig.12The only difference is that the write operation needs to wait for an additional delay when it encounters a refresh operation. Therefore, the following mainly describes Fig.12 The address and data transmission order in the above example can be found in the previous section for details and variations of other operations. Figure 6 and Figure 7 The relevant description will not be repeated here.

[0176] like Fig.12 As shown, the host sends a clock signal CLK to the memory, pulls the chip enable signal CE# low, and sends a fixed number of random write instructions on the A / DQ line ( Fig.12 In the embodiment, the instruction is "85H"), thereby starting the fixed number random access mode specified by the instruction.

[0177] After the transmission instruction, the host sends four access addresses RA0+CA0, RA1+CA1, RA2+CA2, and RA3+CA3 on the A / DQ line. Figure 6 After the second preset number of dummy clock cycles (dummyclk) similar to the example, the host starts to send data for RA0CA0; at this time, the burst length is set to 16 bytes, so 16 bytes of data D0-D15 are sent continuously. Then, after the fourth preset number of dummy clock cycles (dummy clk), the host continues to send data for RA1CA1, data for RA2CA2 and data for RA3CA3, wherein the fourth preset number of dummy clock cycles (dummy clk) must be waited for between each two write data. In some embodiments, the fourth preset number can be preset in the mode register according to the time required to complete the word line switching process and / or the time required for the refresh operation, and the frequency of the clock cycle. After the predetermined 4 write data are sent, the host pulls up CE# to end the instruction mode. In some cases, if the host does not need to write 4 data, for example, the host only wants to perform 3 write operations continuously, then after sending the data for RA2CA2, CE# can be pulled high to end the instruction mode in advance, or the value of M can be adjusted to 3 through a register or a partial bit in the instruction. In some cases, when CE# is pulled high in advance, the current write data has not been completely transmitted, so similar to the previous example, the portion of the write data that does not reach 2 to the power of N may not be written to the storage array.

[0178] From the above, it can be concluded that Fig.12The write timing corresponding to an exemplary write instruction "85H" of the fixed number random access mode represented by the timing diagram can be expressed as follows (it is worth noting that, as mentioned above, the present disclosure is not limited to starting the fixed number random write mode with a specific write instruction "85H". In other embodiments, the fixed number random write mode can also be started by presetting a specific mode register):

[0179] cmd+RA0+CA0+……+RAn+CAn+dummy clk+RA0CA0_data+dummy clk+……+RAnCAn_data

[0180] Where n is equal to the value of (M-1), "cmd" represents the instruction, "RA0" etc. represent the row addresses, "CA0" etc. represent the column addresses, "dummy clk" represents the dummy clock cycle required to be set according to the circuit implementation of the memory, which can also be removed in some cases, and "RA0CA0_data" etc. represent the data read in response to the corresponding access address RA0+CA0 etc. It should be understood by those skilled in the art that, as mentioned above, the number of clock cycles of the dummy clk at each location in the timing can be the second preset number or the fourth preset number, which can be the same or different. In addition, whether dummy clk is needed and how many dummy clks are needed are related to the specific design of the memory.

[0181] Similar to the above example, since the access address (e.g., RA1CA1) of the subsequent write operation is pre-stored, the partial stages of the two consecutive write operations can be performed in parallel, thereby reducing the time of the continuous write operation and improving the access speed. In one embodiment, before the data RA1CA1_data in response to the subsequent write operation is received via the A / DQ line, the word line switching process of the subsequent write operation is started, and the word line switching process includes: closing the word line (e.g., WL0) corresponding to the row address (e.g., RA0) of the previous write operation and opening the word line (e.g., WL1) corresponding to the row address (e.g., RA1) of the subsequent write operation. In other embodiments, since the addresses RA0CA0, RA1CA1, etc. of multiple write operations have been pre-stored in the address latch 150 in advance, if the number of data latches / registers 160 is sufficient, the RA1CA1_data receiving process of the data of the subsequent write operation can even be performed in parallel with the word line switching process required for the previous write operation RA0CA0.

[0182] In addition, those skilled in the art should understand that Fig.12 The write instruction format is not intended to limit the solution of the present disclosure. For example, Fig.12There may be various variations of the write instruction format, for example, the transmission order of each address or each data may be changed, or "dummy clk" may be added at any appropriate position as needed; the above-mentioned variations and combinations thereof are all within the scope of the scheme claimed for protection by the present disclosure.

[0183] In addition, in the above embodiments / examples, the number of each "dummy clk" can be changed according to the operating frequency. For example, the host can determine the number of each "dummyclk" according to the clock cycle (i.e., the operating frequency) of the clock CLK synchronized with the PSRAM, and then set the determined number in a register (e.g., a mode register) in advance.

[0184] In addition, the various setting operations on registers in the memory (such as mode registers) mentioned in the above-mentioned embodiments / examples (such as starting a specified access mode, setting the burst length or default burst length of each access operation, setting the number of access addresses in a fixed number of random access modes, setting the number of IO switching clock cycles or the number of dummy clock cycles, etc.) can be performed in a unified manner. For example, a write operation to the mode register is performed in advance, so that the code data corresponding to the various settings are written into the corresponding mode register.

[0185] In addition, unless obviously contradictory, various details or variations mentioned in the above embodiments / examples can be combined with other embodiments / examples.

[0186] As described above, the present disclosure can select different instructions (such as 03H, 83H, 02H, 82H, 04H, 84H, 05H, 85H, etc.) according to different access requirements to start the appropriate random access mode, so as to more appropriately improve the access speed (for example, in view of the characteristics of random column access, the present disclosure can further improve the access speed by not switching WL).

[0187] As mentioned above, each of the new schemes disclosed herein can improve the access speed of multiple random addresses. In some cases, at the same interface frequency, the data throughput of the new scheme disclosed herein can be improved by more than 50% compared to traditional PSRAM, and no additional pins (i.e., transmission lines in the interface) are required. In some cases, the new scheme disclosed herein can support different address quantities and data quantities required during host use.

[0188] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A method for operating a memory, wherein the memory comprises a memory array and an access interface for externally accessing the memory array, wherein the access interface comprises at least one data / address multiplexing line for transmitting data and addresses, The method comprises: Initiating a specified fixed number random access mode, in which a continuous read operation or write operation can be performed on the storage array in response to a fixed number of multiple random access addresses received; Continuously receiving the preset fixed number of access addresses in sequence via the data / address multiplexing line; sequentially outputting data read in response to each received access address via the data / address multiplexing line in a case where the specified fixed number random access pattern indicates a read operation, or sequentially receiving data to be written in response to each received access address via the data / address multiplexing line in a case where the specified fixed number random access pattern indicates a write operation; and The fixed number random access mode is terminated by receiving an invalid chip enable signal.

2. The method according to claim 1, wherein: The fixed number of access addresses have the same row address and random column addresses; as well as The step of sequentially and continuously receiving a preset fixed number of access addresses comprises: A common row address and the preset fixed number of column addresses are received in sequence and continuously.

3. The method according to claim 2, wherein: From the start of the first read / write operation to the end of the last read / write operation, the word line of the memory array corresponding to the received common row address remains in an open state.

4. The method according to claim 1, wherein: The access addresses received successively in sequence all include a random row address and a random column address.

5. The method according to claim 4, wherein: The output process of the data via the data / address multiplexing line in the previous read operation is at least partially performed in parallel with the word line switching process required for the subsequent read operation; or, Before the data in response to the subsequent write operation is completely received via the data / address multiplexing line, a word line switching process required for the subsequent write operation is started.

6. The method according to claim 5, wherein: The word line switching process includes: closing the word line corresponding to the row address of the previous read / write operation and opening the word line corresponding to the row address of the subsequent read / write operation.

7. The method according to claim 1, wherein: After receiving the access address and before outputting or receiving the read or written data, a second preset number of clock cycles preset according to the frequency of the clock cycle is waited.

8. The method according to claim 7, wherein: The second preset number is determined by receiving a predetermined instruction or by a pre-set mode register, wherein, when the specified fixed number random access mode indicates a read operation, the data / address multiplexing line is released to a high impedance state during the second preset number of clock cycles.

9. The method according to any one of claims 1 to 8, wherein: In the event that an invalid chip enable signal is received when a read / write operation in response to a received column address or access address is not completed, the column address or access address for which the read operation has not been started or the column address or access address for which any corresponding write data has not been received is discarded, and in the event that a write operation is in progress or write data is being received, part of the write data is discarded.

10. The method according to any one of claims 1 to 9, wherein: The access interface further includes a chip enable line, and the chip enable signal is received from the host via the chip enable line.

11. The method according to any one of claims 1 to 10, wherein: The access interface also includes a transmission line for outputting a signal for synchronizing sampling of data output on the data / address multiplexing line in the case of a read operation, and receiving a signal for shielding data received on the data / address multiplexing line in the case of a write operation.

12. The method according to any one of claims 1 to 11, wherein: The memory is PSRAM or Flash.

13. The method according to any one of claims 1 to 12, wherein: The access interface adopts the SPI protocol.

14. The method according to any one of claims 1 to 13, wherein: The number of data / address multiplexing lines is 2 N , output or receive 2 via the data / address multiplex line in each clock cycle N or 2 N+1 bits of data or addresses, where N is a non-negative integer; and / or The amount of data read or written by each access address is the burst length*8 bits, wherein the burst length is preset in the mode register.

15. The method according to claim 4, wherein: A fourth preset number of clock cycles preset according to the frequency of the clock cycles is waited between outputting / receiving two data read / written in response to the two access addresses.

16. The method according to claim 15, wherein: The fourth preset number is preset in the mode register according to the time required to complete the word line switching process and / or the time required for the refresh operation, and the frequency of the clock cycle.

17. The method according to any one of claims 1 to 16, wherein: The specified fixed number random access mode is initiated by receiving a predetermined instruction via the data / address multiplexing line or by a pre-set mode register.

18. The method according to any one of claims 1 to 17, wherein: The fixed number of preset access addresses is determined by receiving a predetermined instruction or by a preset mode register.

19. The method according to any one of claims 1 to 18, wherein: The order of the read or written data transmitted through the data / address multiplexing line is consistent with the order of the received addresses.

20. A memory comprising: Storage arrays; An access interface for externally accessing the storage array, the access interface comprising at least one data / address multiplexing line for transmitting data and addresses; as well as A control component configured to control the memory to execute the method according to any one of claims 1-19.

Images