Gallium oxide enhanced transistor with high power merit figure and manufacturing method thereof

Abstract

The invention discloses a gallium oxide enhanced transistor with a high power figure of merit and a manufacturing method of the gallium oxide enhanced transistor. The problem that enhancement of an existing gallium oxide device is difficult to achieve is mainly solved, and a Ga2O3 enhanced field effect transistor with the high power figure of merit is achieved. According to the manufacturing scheme of the device, a gallium oxide unintentional doping layer and a gallium oxide channel layer are sequentially grown on a gallium oxide substrate by adopting an MOCVD (Metal Organic Chemical Vapor Deposition) method; selectively growing P-type NiOX in a partial region under the gate, and then depositing gate metal; and sequentially manufacturing a source electrode, a drain electrode and a gate dielectric layer on the gallium oxide channel layer, and finally manufacturing a SiNx passivation layer and a field plate structure to complete the manufacturing of the gallium oxide enhanced transistor device. Half of the gate metal is located above the NiOX, and the other half of the gate metal is directly located above the beta-Ga2O3 layer, so that a Schottky junction between the metal and gallium oxide and a PN junction between the NiOX and the gallium oxide are formed. The two junctions play a role in regulating and controlling the channel at the same time, so that the power merit figure of the gallium oxide enhanced field effect transistor is effectively improved.

Description

Technical Field

[0001] The invention belongs to the field of microelectronic technology, and in particular relates to a gallium oxide enhanced transistor which can be used as a power electronic device. Background Art

[0002] Since Ga2O3 crystal materials have ultra-wide bandgap width and high breakdown field strength, power devices made of Ga2O3 have the characteristics of high withstand voltage and high power, and have the potential for application in the field of power electronics. Since high-quality P-type doping of gallium oxide is still not possible, for Ga2O3-based power field effect transistors, in order to achieve enhancement mode, high-K materials are usually used as dielectric layers, or under-gate etching is used to reduce the channel thickness, or a heterojunction structure is used to form a PN junction. Although these methods can achieve enhancement mode operation, the depletion of channel electrons will undoubtedly significantly increase the on-resistance of the device. Power figure of merit is one of the key indicators for evaluating the applicability of power devices in power electronic systems. To improve the power figure of merit, the device needs to have the characteristics of high breakdown voltage and low on-resistance at the same time. Therefore, the compatibility of breakdown voltage and on-resistance has become the main technical difficulty encountered by Ga2O3-based enhancement-type power devices at present; and the production of Ga2O3 enhancement-type field effect transistors with higher power figure of merit is still the difficulty and challenge faced by Ga2O3 power devices at present.

[0003] Patent document with publication number CN116053312A discloses a P-type gate-enhanced gallium oxide-based current aperture vertical electron transistor CAVET device and its preparation method. The device is provided with a P-type semiconductor layer under the gate, which forms a PN junction with the channel layer, depletes the electrons in the channel layer to achieve enhancement mode. However, as a vertical device, it has a relatively complex structure and is difficult to prepare. In actual industry, it will incur higher production costs and has certain disadvantages in large-scale applications.

[0004] Patent document with publication number CN117790575A discloses a vertical device of a ring-gate field effect transistor based on a gallium oxide substrate and a preparation method thereof. The device adopts a columnar channel, and the gate dielectric and the gate metal surround the channel in a ring shape, thereby increasing the contact area between the gate and the channel, thereby improving the gate control capability. However, since the device has no heterojunction structure, it is difficult to achieve enhancement mode only by relying on the work function difference between the gate metal and the channel semiconductor, and its use scenarios in actual applications will therefore be limited. Summary of the invention

[0005] The purpose of the present invention is to provide a high-power gallium oxide enhancement mode transistor and a method for manufacturing the same, so as to solve the technical problems of the existing Ga2O3 power transistors, such as complex structure, high difficulty in preparation, low power figure of merit, and difficulty in achieving enhancement mode.

[0006] To achieve the above object, the technical solution of the present invention includes the following:

[0007] 1. A high-power gallium oxide enhancement transistor, comprising an insulating substrate, a barrier layer, a channel layer, a P-type NiO X layer, dielectric layer, passivation layer, source, gate, drain and source field plate, characterized in that:

[0008] Two left and right areas are provided below the grid;

[0009] The P-type NiO X The layer is located in the right region of the gate;

[0010] The channel layer is located in the left region of the gate and the P-type NiO X layer, and in direct contact with both, respectively with P-type NiO X The layer forms a PN junction and a Schottky junction with the left region to simultaneously achieve the regulation of the channel.

[0011] Furthermore, the insulating substrate, the barrier layer, and the channel layer are distributed from bottom to top, wherein:

[0012] The substrate may be made of insulating β-Ga2O3 with a crystal orientation of (010), (100), (001) or (-201); the barrier layer may be made of unintentionally doped β-Ga2O3 with a thickness of 100 to 700 nm and a carrier concentration of 1×10 14 cm -3 ~1×10 16 cm -3 The channel layer is made of β-Ga2O3, has a thickness of 100 to 700 nm, and a doping concentration of 1×10 16 cm -3 ~1×10 19 cm -3 ;

[0013] Furthermore, the P-type NiO X The layer is located above the channel layer, with a thickness of 40 to 100 nm, a length of 1 to 9 μm, and a carrier concentration of 1×10 18 cm -3 ~5×10 20 cm -3 ;

[0014] The dielectric layer is located between the channel layer and the P-type NiO X The passivation layer is located above the dielectric layer, and its thickness is 50 to 300 nm. The material is SiN x Or SiO2, or Al2O3.

[0015] Furthermore, the source and drain are located on both sides above the channel layer, and the material is a metal stack Ti / Au with a thickness of 20 / 200nm respectively; the gate is located between the source and the drain and relatively close to the source, and its material is a metal stack Ni / Au with a thickness of 45 / 400nm respectively; the source field plate is located above the passivation layer and is connected to the source.

[0016] 2. A method for preparing a high-power gallium oxide enhancement mode transistor with a high merit, comprising the following steps:

[0017] 1) On a β-Ga2O3 insulating substrate (1), a non-intentionally doped β-Ga2O3 barrier layer (2) with a thickness of 100 to 700 nm is grown using a metal organic chemical vapor deposition device; on the barrier layer (2), a layer with a thickness of 100 to 700 nm and a doping concentration of 1×10 16 ~1×10 19 cm -3 Si-doped β-Ga2O3 channel layer (3);

[0018] 2) thinning the middle region of the channel layer (3) by ICP dry etching, wherein the remaining thickness is less than 50 nm;

[0019] 3) Implanting Si ions into the areas on both sides of the thinned channel to form a heavily doped layer, and depositing a Ti / Au stack with a thickness of 20 / 200 nm as the source (7) and drain (9) metals;

[0020] 4) Sputter a layer of 1×10 18 ~5×10 20 cm -3 , P-type NiO with a thickness of 40 to 100 nm and a length of 1 to 9 μm X Layer (4);

[0021] 5) In part of the channel layer (3) and NiO X (4) A Ni / Au stack with a thickness of 45 / 400 nm is deposited on top as a gate metal (8), which covers part of the NiO X The length of layer (4) is 0.5 to 5 μm;

[0022] 6) Using ALD equipment, the channel layer (3) not covered by the gate metal (8) and the P-type NiO XA 10-30 nm thick Al2O3 or HfO2 layer is grown on the dielectric layer (4) as the dielectric layer (5), and a 50-300 nm thick SiN layer is grown on the dielectric layer surface by using a plasma enhanced chemical vapor deposition (PECVD) device. x Or SiO2 or Al2O3 as passivation layer (6);

[0023] 7) using ICP equipment to etch away the dielectric layer (5) and the passivation layer (6) above the source electrode (7), the gate electrode (8), and the drain electrode (9) to expose the metal electrode;

[0024] 8) Metal Au is deposited on the side of the passivation layer (6) close to the source electrode (7) and connected to the source electrode metal to form a field plate structure (10), and finally interconnection metal is deposited to complete the device preparation.

[0025] Compared with the prior art, the present invention has the following advantages:

[0026] Firstly, the present invention combines the Schottky junction with the heterogeneous PN junction at the lower portion of the gate, which can effectively improve the current density of the device while realizing the enhancement mode, thereby reducing the on-resistance of the device.

[0027] Secondly, the present invention converts P-type NiO X There is an extension portion located below the gate and on the side close to the drain, which can form a field terminal structure, effectively improving the breakdown voltage while realizing an enhancement-mode device.

[0028] Thirdly, compared with vertical enhancement type devices, the present invention effectively reduces the manufacturing cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a schematic diagram of the overall structure of the device of the present invention;

[0030] Figure 2 It is a schematic diagram of the manufacturing process flow of the device of the present invention. DETAILED DESCRIPTION

[0031] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0032] Reference Figure 1 The device of the present invention comprises a β-Ga2O3 insulating substrate 1, an unintentionally doped β-Ga2O3 barrier layer 2, a Si-doped β-Ga2O3 channel layer 3, a P-type NiO X Layer 4, dielectric layer 5, passivation layer 6, Ti / Au source 7, Ni / Au gate 8, Ti / Au drain 9, source field plate 10. Among them:

[0033] The bottom layer is a β-Ga2O3 insulating substrate 1, and above the substrate is a non-doped β-Ga2O3 barrier layer 2 with a thickness of 100 to 700 nm;

[0034] The β-Ga2O3 channel layer 3 is located above the barrier layer, has a thickness of 100-700 nm, and a doping concentration of 1×10 16 cm -3 ~1×10 19 cm -3 ;

[0035] The P-type NiO X Layer 4 is located above the channel layer near the drain end, with a thickness of 40 to 100 nm and a P-type carrier concentration of 1×10 18 cm -3 ~5×10 20 cm -3 ;

[0036] The dielectric layer 5 is located above the channel layer and has a thickness of 10 to 30 nm;

[0037] The passivation layer 6 is located above the dielectric layer 5 and has a thickness of 50 to 300 nm;

[0038] The source electrode 7 and the drain electrode 9 are located on both sides above the channel layer 3, and both are made of Ti / Au metal stacks with thicknesses of 20 / 200 nm respectively;

[0039] The gate 8 is located on the P-type NiO X Layer 4 and the β-Ga2O3 channel layer 3, which uses a Ni / Au metal stack with a thickness of 45 / 400nm respectively;

[0040] The source field plate 10 is located above the passivation 6 and is connected to the source metal 7 .

[0041] Reference Figure 2 The present invention provides the following three embodiments for making the above-mentioned device:

[0042] Example 1: Preparation of a passivation layer made of SiN on an Fe-doped (010) oriented insulating β-Ga2O3 substrate x The dielectric layer material is Al2O3, the barrier layer thickness is 100nm, and the P-type NiO X Gallium oxide enhancement mode transistor with a layer length of 1μm and a channel layer thickness of 100nm.

[0043] Step 1, epitaxial material growth.

[0044] On a (010) oriented Fe-doped insulating β-Ga2O3 substrate, a 100 nm thick non-intentionally doped β-Ga2O3 barrier layer was grown using a MOCVD process at a reaction chamber temperature of 700°C, a pressure of 40 mba, an oxygen source of high purity oxygen, a gallium source of TEGa, a carrier gas of argon, and a TEGa to O2 molar flow ratio of 1:5000.

[0045] On the barrier layer, a Si-doped β-Ga2O3 channel layer with a thickness of 100 nm and a doping concentration of 1×10 was grown using the MOCVD process under the following process conditions: the reaction chamber temperature was 700°C, the pressure was 40 mba, the oxygen source was high-purity oxygen, the gallium source was TEGa, the doping source was silane, the carrier gas was argon, the molar flow ratio of TEGa to O2 was 1:5000, and the molar flow rate of silane was 50 μmol / min. 19 cm -3 .

[0046] Step 2: channel layer etching and source and drain fabrication.

[0047] 2.1) Using ICP equipment, selective etching is performed on the middle area of ​​the channel, with an etching depth of 50nm or more;

[0048] 2.2) Si ions are implanted on both sides of the Si-doped β-Ga2O3 channel to reduce the ohmic contact resistance. The process conditions are as follows: the implanted ions are Si, the implantation angle is 6°, the beam current is 25 mA, and the implantation concentration is 10 21 cm -3 The source and drain metals are deposited by electron beam evaporation, and the metals are Ti / Au with thickness of 20 / 200nm respectively;

[0049] 2.3) Perform rapid thermal annealing for 30 seconds in a N2 atmosphere at 450°C in an annealing furnace to alloy the source and drain metals and complete the fabrication of the source and drain electrodes.

[0050] Step 3, NiO X Deposition and gate fabrication.

[0051] 3.1) Sputtering equipment was used to prepare a 40nm thick, 1μm long, and 5×10 20 cm -3 P-type NiO X The process conditions are as follows: first, the vacuum of the Sputter equipment is broken, the cleaned sample is sent into its chamber, and the NiO X The target material is then pumped down to vacuum, the temperature is set to room temperature, the power is 100W, and the ratio of Ar to O2 is 10:1.

[0052] 3.2) In the channel layer and NiOX A Ni / Au stack is deposited on top as the gate metal, and the gate metal covers 0.5μm NiO X layer, and the remaining gate portion directly covers the Ga2O3 channel;

[0053] 3.3) Using ALD equipment to grow Al2O3 dielectric layer with a thickness of 10nm, the process conditions are as follows: first, place the sample in the ALD equipment chamber, set the chamber pressure to 0.1torr, the temperature to 150℃, select trimethylaluminum as the precursor, and introduce trimethylaluminum, nitrogen, H2O, and nitrogen into the chamber in sequence, and repeat this step 100 times; at the same time, use PECVD equipment to grow SiN x Passivation layer, thickness is 50nm.

[0054] Step 4: Fabrication of interconnect metal and field plate.

[0055] 4.1) Using ICP equipment, SiN x The layer and the Al2O3 dielectric layer are completely etched away;

[0056] 4.2) Ti / Au metals were sequentially deposited using an electron beam evaporation station with thicknesses of 20 / 400 nm respectively, and the interconnection technology and field plate fabrication were completed by stripping.

[0057] Example 2: A passivation layer material of SiO2, a dielectric layer material of HfO2, a barrier layer thickness of 500 nm, and a P-type NiO are prepared on an Fe-doped (100) oriented insulating β-Ga2O3 substrate. X Gallium oxide enhancement mode transistor with a layer length of 5μm and a channel layer thickness of 500nm.

[0058] Step A, epitaxial material growth.

[0059] On a (100) oriented Fe-doped insulating β-Ga2O3 substrate, a 500nm thick non-intentionally doped β-Ga2O3 barrier layer was grown by MOCVD process at a reaction chamber temperature of 800°C, a pressure of 120mba, an oxygen source of high purity oxygen, a gallium source of TEGa, an argon carrier gas, and a TEGa to O2 molar flow ratio of 1:3000.

[0060] On the barrier layer, a layer with a thickness of 500 nm and a doping concentration of 5×10 was grown using the MOCVD process under the conditions of a reaction chamber temperature of 800°C, a pressure of 120 mba, an oxygen source of high purity oxygen, a gallium source of TEGa, a doping source of silane, an argon carrier gas, a TEGa to O2 molar flow ratio of 1:3000, and a silane molar flow of 28 μmol / min. 17 cm -3Si-doped β-Ga2O3 channel layer.

[0061] Step B: channel layer etching and source and drain fabrication.

[0062] B1) using ICP equipment, selectively etching the middle area of ​​the channel layer, with an etching depth of 450nm or more;

[0063] B2) Si ions are injected on both sides of the Si-doped β-Ga2O3 channel to reduce the ohmic contact resistance. The process conditions are as follows: the injected ions are Si, the injection angle is 7°, the beam current is 20 mA, and the injection concentration is 10 20 cm -3 The source and drain metals are deposited by electron beam evaporation, and the metals are Ti / Au with thickness of 20 / 200nm respectively;

[0064] B3) Perform rapid thermal annealing for 30 seconds in a N2 atmosphere at 450°C in an annealing furnace to alloy the source and drain metals, thereby completing the production of the source and drain electrodes.

[0065] Step C, NiO X Deposition and gate fabrication.

[0066] C1) Sputtering equipment was used to prepare a 70nm thick, 5μm long, and 1×10 19 cm -3 P-type NiO X The process conditions are as follows: first, the vacuum of the Sputter equipment is broken, the cleaned sample is sent into its chamber, and the NiO X The target material is then pumped down to vacuum, the temperature is set to room temperature, the power is 150W, and the ratio of Ar to O2 is 10:2;

[0067] C2) In the channel layer and NiO X A Ni / Au stack is deposited on top as the gate metal, and the gate metal covers 2.5μm of NiO X layer, and the remaining gate portion directly covers the Ga2O3 channel;

[0068] C3) Using ALD equipment, a HfO2 dielectric layer with a thickness of 20 nm is grown on the surface. The process conditions are as follows: first, the sample is placed in the ALD equipment chamber, the chamber pressure is set to 0.3 torr, the temperature is set to 300°C, tetrakis(dimethylamino)hafnium is selected as the precursor, and tetrakis(dimethylamino)hafnium, nitrogen, H2O, and nitrogen are introduced into the chamber in sequence, and this step is repeated 400 times; at the same time, a SiO2 passivation layer with a thickness of 200 nm is grown using PECVD equipment.

[0069] Step D: fabrication of interconnect metal and field plate.

[0070] D1) Using ICP equipment, completely etch away the SiO2 layer and HfO2 dielectric layer above the gate, source and drain metals;

[0071] D2) Ti / Au metals are sequentially deposited using an electron beam evaporation station with thicknesses of 20 / 400 nm respectively, and the interconnection technology and field plate fabrication are completed by stripping.

[0072] Example 3: Preparation of a passivation layer made of SiN on an Fe-doped (001) oriented insulating β-Ga2O3 substrate x , the dielectric layer material is HfO2, the barrier layer thickness is 700nm, and the P-type NiO X Gallium oxide enhancement mode transistor with a layer length of 9μm and a channel layer thickness of 700nm.

[0073] Step 1: epitaxial material growth.

[0074] On a (001) oriented Fe-doped insulating β-Ga2O3 substrate, a 700nm thick non-intentionally doped β-Ga2O3 barrier layer was grown by MOCVD process at a reaction chamber temperature of 900°C, a pressure of 200mba, an oxygen source of high purity oxygen, a gallium source of TEGa, an argon carrier gas, and a TEGa to O2 molar flow ratio of 1:200.

[0075] On the barrier layer, a Si-doped β-Ga2O3 channel layer with a thickness of 700 nm and a doping concentration of 1×10-1 was grown using the MOCVD process under the following process conditions: the reaction chamber temperature was 900°C, the pressure was 200 mba, the oxygen source was high-purity oxygen, the gallium source was TEGa, the doping source was silane, the carrier gas was argon, the molar flow ratio of TEGa to O2 was 1:200, and the molar flow rate of silane was 5 μmol / min. 16 cm -3 .

[0076] Step 2: channel layer etching and source and drain fabrication.

[0077] Using ICP equipment, selective etching is performed on the middle area of ​​the channel, with an etching depth of 650nm or more;

[0078] Si ions were implanted above the Si-doped β-Ga2O3 channel to reduce the ohmic contact resistance. The process conditions were as follows: the implanted ions were Si, the implantation angle was 8°, the beam current was 15 mA, and the implantation concentration was 10 19 cm -3 , and deposit source and drain metals by electron beam evaporation, the metals are Ti / Au, with thickness of 20 / 200nm respectively;

[0079] A rapid thermal annealing is performed for 30 seconds in a N2 atmosphere at 450°C in an annealing furnace to alloy the source and drain metals, thereby completing the production of the source and drain electrodes.

[0080] Step 3, NiO X Deposition and gate fabrication.

[0081] The thickness of the prepared film was 100 nm, the length was 9 μm, and the carrier concentration was 1×10 18 cm -3 P-type NiO X The process conditions are as follows: first, the vacuum of the Sputter equipment is broken, the cleaned sample is sent into its chamber, and the NiO X The target material is then pumped down to vacuum, the temperature is set to room temperature, the power is 200W, and the ratio of Ar to O2 is 10:3;

[0082] In the channel layer and NiO X A Ni / Au stack is deposited on top as the gate metal, and the gate metal covers 4.5μm of NiO X layer, and the remaining gate portion directly covers the Ga2O3 channel;

[0083] Using ALD equipment, a HfO2 dielectric layer with a thickness of 30nm was grown on the surface. The process conditions were as follows: first, the sample was placed in the ALD equipment chamber, the chamber pressure was set to 0.5torr, the temperature was set to 450℃, tetrakis(dimethylamino)hafnium was selected as the precursor, tetrakis(dimethylamino)hafnium, nitrogen, H2O, nitrogen were introduced into the chamber in sequence, and this step was repeated 700 times; at the same time, SiN was grown using PECVD equipment. x Passivation layer, thickness is 300nm.

[0084] Step 4: Fabrication of interconnect metal and field plate.

[0085] Using ICP equipment, SiN x The layer and HfO2 dielectric layer are completely etched away;

[0086] Ti / Au metals were sequentially deposited using an electron beam evaporation station with thicknesses of 20 / 400 nm respectively, and the interconnection technology and field plate fabrication were completed by stripping.

[0087] The above descriptions are only three specific examples of the present invention and do not constitute any limitation to the present invention. Obviously, for professionals in this field, after understanding the content and principles of the present invention, it is possible to make various modifications and changes in form and details without departing from the principles and structures of the present invention. For example, the source and drain ohmic electrodes can be Ti / Al / Ni / Au metal stacks in addition to Ti / Au metal stacks; the insulating β-Ga2O3 substrate can be Mg-doped in addition to Fe-doped. However, these modifications and changes based on the ideas of the present invention are still within the scope of protection of the claims of the present invention.

Claims

1. A high-power gallium oxide enhancement transistor, comprising an insulating substrate (1), a barrier layer (2), a channel layer (3), a P-type NiO X layer (4), a dielectric layer (5), a passivation layer (6), a source electrode (7), a gate electrode (8), a drain electrode (9) and a source field plate (10), characterized in that: Two left and right areas are provided below the gate (8); The P-type NiO X Layer (4) is located in the right region of gate (8); The channel layer (3) is located in the left region of the gate (8) and the P-type NiO X layer (4) and directly contact with both of them, respectively with P-type NiO X The layer (4) forms a PN junction and a Schottky junction with the left region, so as to simultaneously realize the regulation of the channel.

2. The structure according to claim 1, characterized in that: The insulating substrate (1), the barrier layer (2), and the channel layer (3) are arranged from bottom to top, wherein: The substrate (1) may be made of insulating β-Ga2O3 with a crystal orientation of (010), (100), (001) or (-201); The barrier layer (2) is made of unintentionally doped β-Ga2O3, has a thickness of 100 to 700 nm, and a carrier concentration of 1×10 14 cm -3 ~1×10 16 cm -3 ; The channel layer (3) is made of β-Ga2O3, has a thickness of 100 to 700 nm, and a doping concentration of 1×10 16 cm -3 ~1×10 19 cm -3 .

3. The structure according to claim 1, characterized in that: The P-type NiO X The layer (4) is located above the channel layer (3) and has a thickness of 40 to 100 nm, a length of 1 to 9 μm, and a doping concentration of 1×10 18 cm -3 ~5×10 20 cm -3 ; The dielectric layer (5) is located between the channel layer (3) and the P-type NiO X Above the layer (4), the material is Al2O3 or HfO2, and the thickness is 10 to 30 nm; The passivation layer (6) is located above the dielectric layer (5) and has a thickness of 50 to 300 nm. The material is SiN x Or SiO2, or Al2O 3。 4. The structure according to claim 1, characterized in that: The source electrode (7) and the drain electrode (9) are located on both sides above the channel layer (3), and are made of metal stack Ti / Au with thicknesses of 20 / 200 nm respectively; The gate (8) is located between the source (7) and the drain (9) and is relatively close to the source (7). The gate (8) is made of a metal stack Ni / Au with thicknesses of 45 / 400 nm respectively. The source field plate (10) is located above the passivation layer (6) and is connected to the source electrode (7).

5. A method for preparing a high-power gallium oxide enhancement mode transistor with a high merit, comprising the following steps: 1) On a β-Ga2O3 insulating substrate (1), a non-intentionally doped β-Ga2O3 barrier layer (2) with a thickness of 100 to 700 nm is grown by a metal organic chemical vapor deposition (MOCVD) process; on the barrier layer (2), a layer with a thickness of 100 to 700 nm and a doping concentration of 1×10 16 ~1×10 19 cm -3 Si-doped β-Ga2O3 channel layer (3); 2) thinning the middle region of the channel layer (3) by ICP dry etching, wherein the remaining thickness is less than 50 nm; 3) Implanting Si ions into the areas on both sides of the thinned channel to form a heavily doped layer, and depositing a Ti / Au stack with a thickness of 20 / 200 nm as the source (7) and drain (9) metals; 4) Sputter a layer of doping concentration of 1×10 18 ~5×10 20 cm -3 , P-type NiO with a thickness of 40 to 100 nm and a length of 1 to 9 μm X Layer (4); 5) In part of the channel layer (3) and NiO X (4) A Ni / Au stack with a thickness of 45 / 400 nm is deposited on top as a gate metal (8), which covers part of the NiO X The length of layer (4) is 0.5 to 5 μm; 6) Using ALD equipment, the channel layer (3) not covered by the gate metal (8) and the P-type NiO X A 10-30 nm thick Al2O3 or HfO2 layer is grown on the dielectric layer (4) as the dielectric layer (5), and a 50-300 nm thick SiN layer is grown on the dielectric layer surface by using a plasma enhanced chemical vapor deposition (PECVD) device. x Or SiO2 or Al2O3 as passivation layer (6); 7) using ICP equipment to etch away the passivation layer (5) and dielectric layer (6) above the source electrode (7), the gate electrode (8), and the drain electrode (9) to expose the metal electrode; 8) Metal Au is deposited on the side of the passivation layer (5) close to the source electrode (7) and connected to the source electrode metal to form a field plate structure (10), and finally interconnection metal is deposited to complete the device preparation.

6. The method according to claim 5, characterized in that In step 1), an unintentionally doped β-Ga2O3 barrier layer (2) is grown on the substrate (1) by using a MOCVD method, and the process conditions are as follows: The temperature of the reaction chamber is 700-900°C and the pressure is 40mba-200mba; The oxygen source is high-purity oxygen, the gallium source is TEGa, and the carrier gas is argon; The molar flow ratio of TEGa to O2 is 1:5000 to 1:

200.

7. The method according to claim 5, characterized in that In step 1), a Si-doped β-Ga2O3 channel layer (3) is grown on the unintentionally doped β-Ga2O3 barrier layer (2) by MOCVD method, and the process conditions are: The temperature of the reaction chamber is 700-900°C and the pressure is 40mba-200mba; The oxygen source is high-purity oxygen, the gallium source is TEGa, the doping source is silane, and the carrier gas is argon; The molar flow ratio of TEGa to O2 is 1:5000 to 1:200, and the molar flow rate of silane is 5 to 50 μmol / min.

8. The method according to claim 5, characterized in that : In the step 3), ion implantation is performed on both sides of the thinned channel in the source and drain regions, and the process conditions are as follows; The implanted ions are Si, The injection angle is 6 to 8 degrees. The beam current is 15~25mA. The injection concentration is 10 19 ~10 21 cm -3 .

9. The method according to claim 5, characterized in that In step 4), a layer of P-type NiO is sputtered on a portion of the area above the thinned channel using a Sputter device. X Layer, implemented as follows: Break the vacuum of the Sputter device, place the cleaned sample into its chamber, and set the NiO X Target material; The chamber was then evacuated to vacuum, the temperature was set to room temperature, the power was 100-200 W, the ratio of Ar to O2 was 10:1-10:3, and a layer with a thickness of 40-100 nm and a length of 1-9 μm was grown by sputtering. The P-type carrier concentration was 1×10 18 ~5×10 20 cm -3 NiO X layer.

10. The method according to claim 5, characterized in that: In step 6), an ALD atomic layer deposition device is used to deposit a layer of P-type NiO on the channel layer. X Al2O3 or HfO2 is deposited on top of the layer, which is achieved as follows: 6a) placing the sample in the ALD equipment chamber, setting the chamber pressure to 0.1-0.5 torr and the temperature to 150-450° C.; 6b) selecting trimethylaluminum or tetrakis(dimethylamino)hafnium as a precursor, and introducing trimethylaluminum or tetrakis(dimethylamino)hafnium, nitrogen, H2O, and nitrogen into the chamber in sequence; 6c) Repeat step 6b) for 100 to 700 times, and deposit the P-type NiO on the channel layer by atomic layer deposition. X A 10nm to 30nm thick Al2O3 or HfO2 dielectric layer is grown on the layer.

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