Carbon nanotube thin film transistor, preparation method thereof and phase inverter constructed by carbon nanotube thin film transistor

Abstract

The invention discloses a carbon nanotube thin film transistor, a preparation method thereof and a constructed inverter. The carbon nanotube thin film transistor comprises a substrate, a gate electrode layer, a gate dielectric layer, a semiconductor type single-walled carbon nanotube thin film and a high-temperature-resistant polyimide thin film which are sequentially stacked, and further comprises a source electrode and a drain electrode which are arranged on the side, away from the gate electrode layer, of the gate dielectric layer. The complementary metal oxide semiconductor phase inverter comprises a carbon nano tube thin film transistor and an indium tin zinc oxide thin film transistor, wherein the indium tin zinc oxide thin film transistor is manufactured by adopting a high-temperature annealing process. The carbon nanotube thin film transistor has the advantages of being low in preparation cost, compatible in back-end process, capable of being prepared in a large area and the like, the mobility of the carbon nanotube thin film transistor is matched with that of an ITZO thin film transistor, a manufactured CMOS phase inverter is high in gain, and the carbon nanotube thin film transistor has wide application prospects in flexible integrated circuits, wearable electronic equipment and Internet of Things sensors.

Description

Technical Field

[0001] The invention relates to the technical field of flat panel displays, and in particular to a carbon nanotube thin film transistor and a preparation method thereof and an inverter constructed therefrom. Background Art

[0002] Thin-film transistors (TFTs) have the advantages of low preparation cost, large-area preparation, and good mechanical flexibility. They have been widely used in liquid crystal displays, sensors, wearable devices and other fields. Complementary metal oxide semiconductor (CMOS) technology is the key technical difficulty in the application of TFTs in logic circuits, sensors, and memory devices. At present, TFTs with n-type field-effect transistor conductive characteristics mainly include indium gallium zinc oxide thin-film transistors (IGZO-TFTs), indium tin zinc oxide thin-film transistors (ITZO-TFTs) and zinc oxide thin-film transistors (ZnO-TFTs), and their preparation and application technologies have become mature. However, the performance of p-type TFTs that are compatible with oxide thin-film transistor processes is not ideal.

[0003] Among the optional p-type TFTs, carbon nanotube thin film transistors (CNT-TFTs) have the advantages of low preparation cost, large-area preparation at room temperature, and high mobility, which have won the favor of researchers. However, CNT-TFTs will suffer irreversible damage in high-temperature air environments (the failure of CNT-TFTs at high temperatures is mainly related to the adsorption of oxygen by CNTs in high-temperature environments. Although the traditional method of using photoresist to encapsulate CNT-TFTs can achieve the purpose of isolating oxygen, photoresists can only withstand temperatures below 150°C. Excessive temperatures will cause the photoresist to deform and lose the ability to isolate oxygen), making it difficult to be compatible with high-temperature processes. In CMOS device applications, high-performance oxide thin film transistors usually require a high-temperature annealing process of 300°C or above in an air environment during preparation. Although low-temperature annealing technology for oxide thin film transistors has been developed in recent years, the key performance parameters such as mobility and stability of the obtained TFTs are not comparable to those of oxide thin film transistors prepared by high-temperature annealing processes of 300°C or above.

[0004] Therefore, developing a high-temperature process-compatible CNT-TFTs is of great significance for the development of TFT-based CMOS circuits. Summary of the invention

[0005] One of the purposes of the present invention is to solve the problem that the existing carbon nanotube thin film transistor is difficult to be compatible with high temperature processes, and to provide a carbon nanotube thin film transistor that is compatible with high temperature processes.

[0006] A second object of the present invention is to provide a method for preparing the carbon nanotube thin film transistor.

[0007] The third object of the present invention is to provide a complementary metal oxide semiconductor inverter constructed by the above-mentioned carbon nanotube thin film transistor and an indium tin zinc oxide thin film transistor made by a high temperature annealing process.

[0008] The technical solution adopted by the present invention is:

[0009] A carbon nanotube thin film transistor comprises a substrate, a gate electrode layer, a gate dielectric layer, a semiconductor single-walled carbon nanotube film and a high-temperature resistant polyimide film stacked in sequence, and also comprises a source electrode and a drain electrode arranged on the side of the gate dielectric layer away from the gate electrode layer.

[0010] Preferably, the substrate is one of a silicon substrate, a glass substrate and a polyimide substrate.

[0011] Preferably, the gate electrode layer is composed of aluminum and has a thickness of 30 nm to 100 nm.

[0012] Preferably, the gate dielectric layer is composed of aluminum oxide and has a thickness of 20 nm to 200 nm.

[0013] Preferably, the semiconductor single-walled carbon nanotube film has a two-dimensional network structure, is composed of semiconductor single-walled carbon nanotubes interwoven together, and has a thickness of 3 nm to 8 nm.

[0014] Preferably, the semiconductor single-walled carbon nanotube film is a patterned semiconductor single-walled carbon nanotube film.

[0015] Preferably, the high temperature resistant polyimide film is made of polyimide photoresist which is resistant to high temperature above 330°C.

[0016] Further preferably, the high temperature resistant polyimide film is made of P3000 photosensitive polyimide photoresist produced by Deni New Materials (Suzhou) Co., Ltd.

[0017] Preferably, the thickness of the high temperature resistant polyimide film is 5 μm to 20 μm. The thickness of the high temperature resistant polyimide film is ≥ 5 μm to give the carbon nanotube thin film transistor excellent high temperature resistance, so that the carbon nanotube thin film transistor can still maintain excellent performance after a long period of high temperature annealing in an air atmosphere or oxygen atmosphere above 300°C, and finally solve the problem of incompatibility between high performance oxide thin film transistors and carbon nanotube thin film transistors.

[0018] Preferably, the high temperature resistant polyimide film is a patterned high temperature resistant polyimide film.

[0019] Preferably, the source electrode is composed of at least one of titanium, gold, palladium and platinum, and has a thickness of 30 nm to 100 nm.

[0020] Preferably, the drain electrode is composed of at least one of titanium, gold, palladium and platinum, and has a thickness of 30 nm to 100 nm.

[0021] Preferably, the source electrode is in contact with the semiconductor single-walled carbon nanotube film and the polyimide film.

[0022] Preferably, the drain electrode is in contact with the semiconductor single-walled carbon nanotube film and the polyimide film.

[0023] A method for preparing the carbon nanotube thin film transistor as described above comprises the following steps:

[0024] 1) depositing electrode material on one side of the substrate to form a gate electrode layer;

[0025] 2) depositing a gate dielectric material on the surface of the gate electrode layer to form a gate dielectric layer;

[0026] 3) coating a semiconductor single-walled carbon nanotube dispersion on the surface of the gate dielectric layer to form a semiconductor single-walled carbon nanotube film;

[0027] 4) depositing electrode materials on the surface of the gate dielectric layer to form a source electrode and a drain electrode;

[0028] 5) Coating a high temperature resistant polyimide photoresist on the surface of the semiconductor single-walled carbon nanotube film, and then performing photolithography and heat curing to form a patterned high temperature resistant polyimide film, thereby obtaining a carbon nanotube thin film transistor.

[0029] Preferably, the coating method in step 3) is one of dip coating, spin coating and spray coating.

[0030] A complementary metal oxide semiconductor inverter comprises the carbon nanotube thin film transistor and the indium tin zinc oxide thin film transistor; the carbon nanotube thin film transistor and the indium tin zinc oxide thin film transistor are prepared at different positions on the same surface of the same substrate; the indium tin zinc oxide thin film transistor is an indium tin zinc oxide thin film transistor made by a high temperature annealing process.

[0031] Preferably, the ITO thin film transistor comprises a substrate, a gate electrode layer, a gate dielectric layer and an ITO thin film stacked in sequence, and also comprises a source electrode and a drain electrode arranged on a side of the gate dielectric layer away from the gate electrode layer.

[0032] Preferably, the gate electrode layer is composed of aluminum and has a thickness of 30 nm to 100 nm.

[0033] Preferably, the gate dielectric layer is composed of aluminum oxide and has a thickness of 20 nm to 200 nm.

[0034] Preferably, the thickness of the indium tin zinc oxide thin film is 30 nm to 100 nm.

[0035] Preferably, the indium tin zinc oxide thin film is a patterned indium tin zinc oxide thin film.

[0036] Preferably, the source electrode is made of indium tin oxide and has a thickness of 100 nm to 300 nm.

[0037] Preferably, the drain electrode is made of indium tin oxide and has a thickness of 100 nm to 300 nm.

[0038] Preferably, the source electrode is in contact with the indium tin zinc oxide thin film.

[0039] Preferably, the drain electrode is in contact with the indium tin zinc oxide thin film and the drain electrode of the carbon nanotube thin film transistor.

[0040] A method for preparing the complementary metal oxide semiconductor inverter as described above comprises the following steps:

[0041] a) depositing an electrode material on a single side of the substrate to form a gate electrode layer;

[0042] b) depositing a gate dielectric material on the surface of the gate electrode layer to form a gate dielectric layer;

[0043] c) coating a semiconductor single-walled carbon nanotube dispersion on the surface of the gate dielectric layer to form a semiconductor single-walled carbon nanotube film;

[0044] d) depositing electrode materials on the surface of the gate dielectric layer to form a source electrode and a drain electrode of the carbon nanotube thin film transistor;

[0045] e) coating a high temperature resistant polyimide photoresist on the surface of the semiconductor single-walled carbon nanotube film, and then performing photolithography and heat curing to form a patterned high temperature resistant polyimide film;

[0046] f) depositing indium tin zinc oxide on the surface of the gate dielectric layer to form an indium tin zinc oxide film;

[0047] g) depositing electrode materials on the surface of the gate dielectric layer to form source and drain electrodes of an indium tin zinc oxide thin film transistor, and then performing annealing to obtain a complementary metal oxide semiconductor inverter.

[0048] Preferably, the annealing in step g) is carried out in an air atmosphere or an oxygen atmosphere at a temperature of 300° C. to 350° C., and the annealing time is 1 h to 2 h.

[0049] A display device comprises the carbon nanotube thin film transistor.

[0050] The beneficial effects of the present invention are as follows: the carbon nanotube thin film transistor of the present invention has the advantages of low preparation cost, back-end process compatibility, large-area preparation, etc., and its mobility matches that of the ITZO thin film transistor, and the CMOS inverter prepared has high gain, and has broad application prospects in flexible integrated circuits, wearable electronic devices, and Internet of Things sensors.

[0051] Specifically:

[0052] 1) The carbon nanotube thin film transistor of the present invention is provided with a high temperature resistant polyimide (PI) film, which has good thermal stability and gas isolation, and can not only isolate oxygen, but also enable the CNT-TFTs to maintain excellent performance after long-term high temperature annealing in an air atmosphere or an oxygen atmosphere above 300°C, thus solving the problem of incompatibility between high-performance oxide thin film transistors and CNT-TFTs processes;

[0053] 2) The carbon nanotube thin film transistor of the present invention is provided with a high temperature resistant polyimide film, which can be directly patterned, greatly simplifying the preparation steps of CNT-TFTs compatible with high temperature processes and reducing production costs;

[0054] 3) The mobility of CNT-TFTs in the present invention is 15 cm 2 ·V -1 ·s -1 ~40cm 2 ·V -1 ·s -1 In the range of 15 cm 2 ·V -1 ·s -1 ~30cm 2 ·V -1 ·s -1 In the range, high mobility and good characteristic matching make the fabricated CMOS inverter have high gain and high noise margin;

[0055] 4) The ITZO-TFTs and CNT-TFTs in the CMOS inverter of the present invention are directly prepared on the same substrate without the need for transfer operation, and the preparation method is compatible with the back-end-of-line (BEOL) process, and can be prepared on a large area, which has great practical application potential;

[0056] 5) The carbon nanotube thin film transistor of the present invention has the advantages of low preparation cost, back-end process compatibility, and large-area preparation, and has very broad application prospects in flexible integrated circuits, wearable electronic devices, and Internet of Things sensors. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1It is a schematic diagram of the structure of the carbon nanotube thin film transistor in the present invention.

[0058] Figure 2 1 is a transfer characteristic curve of the carbon nanotube thin film transistor of Example 1 before and after heating in an air environment at 330° C.

[0059] Figure 3 FIG. 4 is a schematic diagram of the structure of a complementary metal oxide semiconductor inverter in the present invention.

[0060] Explanation of the reference numerals: 10, substrate; 20, gate electrode layer; 30, gate dielectric layer; 40, semiconductor single-walled carbon nanotube film; 50, high temperature resistant polyimide film; 60, source electrode (CNT-TFTs); 70, drain electrode (CNT-TFTs); 80, indium tin zinc oxide film; 90, drain electrode (ITZO-TFTs); 100, source electrode (ITZO-TFTs).

[0061] Figure 4 1 is a transfer characteristic curve of the carbon nanotube thin film transistor in the complementary metal oxide semiconductor inverter of Example 2 before and after heating in an air environment at 330° C.

[0062] Figure 5 This is an output characteristic curve of the carbon nanotube thin film transistor in the complementary metal oxide semiconductor inverter of Example 2 after being heated in an air environment at 330° C.

[0063] Figure 6 1 and 2 are transfer characteristic curves and output characteristic curves of the ITO thin film transistor in the complementary metal oxide semiconductor inverter of Example 2.

[0064] Figure 7 This is a graph showing the test results of the characteristics matching between the carbon nanotube thin film transistor and the indium tin zinc oxide thin film transistor in the complementary metal oxide semiconductor inverter of Example 2.

[0065] Figure 8 Graph showing voltage transfer characteristic curve and gain test result of the complementary metal oxide semiconductor inverter of Example 2.

[0066] Fig. 9 4 is a dynamic response characteristic curve of the complementary metal oxide semiconductor inverter of Example 2.

[0067] Fig.10 This is a transfer characteristic curve of the carbon nanotube thin film transistor of the comparative example before heating in an air environment at 330°C.

[0068] Fig.11 This is a transfer characteristic curve of the carbon nanotube thin film transistor of the comparative example after being heated in an air environment at 330°C. DETAILED DESCRIPTION

[0069] The present invention will be further explained and illustrated below in conjunction with specific embodiments.

[0070] Embodiment 1:

[0071] A carbon nanotube thin film transistor (schematic diagram as shown in Figure 1 As shown in the figure, it comprises a substrate 10, a gate electrode layer 20, a gate dielectric layer 30, a semiconductor single-walled carbon nanotube film 40, a high-temperature resistant polyimide film 50, a source electrode 60 and a drain electrode 70; the substrate 10, the gate electrode layer 20, the gate dielectric layer 30, the semiconductor single-walled carbon nanotube film 40 and the high-temperature resistant polyimide film 50 are stacked in sequence from bottom to top; the source electrode 60 and the drain electrode 70 are arranged on the side of the gate dielectric layer 30 away from the gate electrode layer 20; the substrate 10 is a glass substrate; the gate electrode layer 20 is composed of aluminum with a thickness of 50nm; the gate dielectric layer 30 is composed of aluminum oxide with a thickness of 20nm; the semiconductor single-walled carbon nanotube film 40 has a two-dimensional network structure, and is composed of semiconductor The single-walled carbon nanotubes are interwoven and have a thickness of 5nm; the semiconductor single-walled carbon nanotube film 40 is a patterned semiconductor single-walled carbon nanotube film; the thickness of the high-temperature resistant polyimide film 50 is 10μm; the high-temperature resistant polyimide film 50 is a patterned high-temperature resistant polyimide film; the source electrode 60 is composed of gold and has a thickness of 50nm; the drain electrode 70 is composed of gold and has a thickness of 50nm; the width and length of the channel between the source electrode 60 and the drain electrode 70 are both 100μm; the source electrode 60 is in contact with the semiconductor single-walled carbon nanotube film 40 and the high-temperature resistant polyimide film 50; the drain electrode 70 is in contact with the semiconductor single-walled carbon nanotube film 40 and the high-temperature resistant polyimide film 50.

[0072] The preparation method of the carbon nanotube thin film transistor is as follows:

[0073] 1) A glass substrate with a size of 10 mm×10 mm×0.5 mm was ultrasonically cleaned with deionized water and isopropyl alcohol for 20 min each, then placed in a drying oven at 90° C. for 20 min, and then a 50 nm thick Al thin film was deposited on one side of the glass substrate using a thermal evaporation coating machine, and patterned using a metal mask to form a gate electrode layer;

[0074] 2) using trimethylaluminum as an aluminum source, an atomic layer deposition device is used to deposit a 20 nm thick Al2O3 film on the surface of the gate electrode layer to form a gate dielectric layer;

[0075] 3) immersing the entire device obtained in step 2) into a semiconductor single-walled carbon nanotube dispersion for 2 hours, then taking it out and patterning it using standard photolithography and reactive ion etching to form a patterned semiconductor single-walled carbon nanotube film;

[0076] 4) using a thermal evaporation coating machine to deposit a 50 nm thick Au film on the surface of the gate dielectric layer, and patterning it through a metal mask to form a source electrode and a drain electrode;

[0077] 5) Spin coating the surface of the semiconductor single-walled carbon nanotube film with P3000 photosensitive polyimide photoresist (Deni New Materials (Suzhou) Co., Ltd.), and then heat it at 120°C in a glue baking machine for 1 min. Then pattern it using standard photolithography to expose the gate, source, and drain electrodes so that the polyimide film only covers the channel region formed by the semiconductor single-walled carbon nanotube film. Then, cure it at 330°C in a N2 environment for 60 min to form a patterned high-temperature resistant polyimide film (10 μm thick), thereby obtaining a carbon nanotube thin film transistor.

[0078] Note:

[0079] The semiconductor single-walled carbon nanotube dispersion is prepared by the following method: single-walled carbon nanotubes (Nanjing Xianfeng Nanomaterial Technology Co., Ltd.) and poly [9-(1-octylnonyl)-9H-carbazole] are ultrasonically dispersed in toluene, and then centrifuged at 25°C for 2.5 hours with a centrifugal force of 50,000 g, and 80% of the volume of the upper supernatant is taken to obtain a semiconductor single-walled carbon nanotube dispersion (commercially available single-walled carbon nanotubes contain both metallic single-walled carbon nanotubes and semiconductor single-walled carbon nanotubes, and centrifugal separation is required to obtain high-purity semiconductor single-walled carbon nanotubes).

[0080] Performance Testing:

[0081] The transfer characteristic curves of the carbon nanotube thin film transistor of this embodiment before and after heating in an air environment at 330° C. (high temperature resistance test) are shown in FIG. Figure 2 shown.

[0082] Depend on Figure 2 It can be seen that the threshold voltage (V th ) is -0.64V, mobility (μ FE ) is 17.92cm 2 ·V -1 ·s -1 , subthreshold swing (SS) is 158mV·dec -1 , switching ratio (I on / I off ) is 2.6×10 6 , after heating V th -0.36V, μ FE 19.88cm 2 ·V -1 ·s -1 , SS is 284mV·dec-1 , I on / I off 6.1×10 3 This shows that although the key performance parameters of carbon nanotube thin film transistors have decreased after high temperature resistance testing, they can still maintain good switching characteristics and are suitable for use in CMOS inverters.

[0083] Embodiment 2:

[0084] A complementary metal oxide semiconductor inverter (schematic diagram as shown in Figure 3 ), which is composed of a carbon nanotube thin film transistor and an indium tin zinc oxide thin film transistor, which are prepared on different parts of the same surface of the same substrate; the carbon nanotube thin film transistor is exactly the same as the carbon nanotube thin film transistor of Example 1; the indium tin zinc oxide thin film transistor is composed of a substrate 10, a gate electrode layer 20, a gate dielectric layer 30, an indium tin zinc oxide thin film 80, a source electrode 100 and a drain electrode 90; the substrate 10, the gate electrode layer 20, the gate dielectric layer 30 and the indium tin zinc oxide thin film 80 are stacked in sequence from bottom to top; the source electrode 100 and the drain electrode 90 are arranged on the gate dielectric layer 30 away from the gate The substrate 10 is a glass substrate; the gate electrode layer 20 is composed of aluminum with a thickness of 50nm; the gate dielectric layer 30 is composed of aluminum oxide with a thickness of 20nm; the thickness of the indium tin zinc oxide film 80 is 40nm; the source electrode 100 is composed of indium tin oxide with a thickness of 200nm; the drain electrode 90 is composed of indium tin oxide with a thickness of 200nm; the width and length of the channel between the source electrode 100 and the drain electrode 90 are both 300μm; the source electrode 100 is in contact with the indium tin zinc oxide film 80; the drain electrode 90 is in contact with the indium tin zinc oxide film 80 and the drain electrode 70 of the carbon nanotube thin film transistor.

[0085] The preparation method of the complementary metal oxide semiconductor inverter is as follows:

[0086] 1) preparing a carbon nanotube thin film transistor by referring to the operation of Example 1;

[0087] 2) depositing an indium tin zinc oxide film with a thickness of 40 nm on the surface of the gate dielectric layer by a magnetron sputtering device using a multi-target co-sputtering method, and patterning the film through a metal mask to form a patterned indium tin zinc oxide film;

[0088] 3) A 200 nm thick indium tin oxide film is deposited on the surface of the gate dielectric layer by magnetron sputtering equipment, and patterned by a metal mask to form a source electrode and a drain electrode, which is then annealed at 330° C. for 1 h in an air environment and cooled naturally to obtain a complementary metal oxide semiconductor inverter.

[0089] Performance Testing:

[0090] 1) The transfer characteristic curves of the carbon nanotube thin film transistor in the complementary metal oxide semiconductor inverter of this embodiment before and after heating (high temperature annealing) in an air environment at 330°C are shown in FIG. Figure 4 As shown, the output characteristic curve after heating is as follows Figure 5 shown.

[0091] Depend on Figure 4 It can be seen that the V of the carbon nanotube thin film transistor after heating th -0.27V, μ FE 36.35cm 2 ·V -1 ·s -1 , SS is 330mV·dec -1 , I on / I off 2×10 3 , which is consistent with the conclusion in Example 1, although the key performance parameters of the carbon nanotube thin film transistor decrease after the high temperature annealing process, it can still maintain good switching characteristics and is suitable for use in CMOS inverters.

[0092] Depend on Figure 5 It can be seen that the carbon nanotube thin film transistor maintains good output performance, which means that the carbon nanotube thin film transistor with high temperature resistant polyimide film still maintains good electrical properties after being heated in an air environment at 330°C for 1 hour, and can be compatible with the high temperature annealing process of indium tin zinc oxide thin film transistor to form a complementary metal oxide semiconductor inverter.

[0093] 2) The transfer characteristic curve and output characteristic curve of the indium tin zinc oxide thin film transistor in the complementary metal oxide semiconductor inverter of this embodiment are as follows: Figure 6 (a is the transfer characteristic curve, b is the output characteristic curve).

[0094] Depend on Figure 6 It can be seen that the V of the ITO thin film transistor is th 0.18V, μ FE 21.98cm 2 ·V -1 ·s -1 , SS is 162.5mV·dec -1 , I on / I off 1.6×10 8 , indicating that the indium tin zinc oxide thin film transistor has high mobility and exhibits good electrical properties.

[0095] 3) The characteristic matching test results of the carbon nanotube thin film transistor and the indium tin zinc oxide thin film transistor in the complementary metal oxide semiconductor inverter of this embodiment are as follows: Figure 7 shown.

[0096] Depend on Figure 7 It can be seen that the carbon nanotube thin film transistor and the indium tin zinc oxide thin film transistor have good electrical property matching.

[0097] 4) The voltage transfer characteristic curve and gain of the complementary metal oxide semiconductor inverter of this embodiment are as follows: Figure 8 shown.

[0098] Depend on Figure 8 It can be seen that the high-level noise margin of the complementary metal oxide semiconductor inverter is 26%, the low-level noise margin is 48%, and a gain of 50 dB is achieved, indicating that the complementary metal oxide semiconductor inverter has good voltage transfer characteristics and voltage gain.

[0099] 5) The dynamic response characteristic curve of the complementary metal oxide semiconductor inverter of this embodiment is as follows: Fig. 9 shown.

[0100] Depend on Fig. 9 It can be seen that the complementary metal oxide semiconductor inverter has a rail-to-rail output capability.

[0101] Comparative Example:

[0102] A carbon nanotube thin film transistor is identical to the carbon nanotube thin film transistor of embodiment 1 except that it does not contain a "high temperature resistant polyimide film 50".

[0103] Performance Testing:

[0104] The transfer characteristic curves of the carbon nanotube thin film transistor of this comparative example before and after heating in an air environment at 330°C (high temperature resistance test) are shown in FIG. Fig.10 and Fig.11 shown.

[0105] Depend on Fig.10 and Fig.11 It can be seen that the carbon nanotube thin film transistor almost completely loses its switching characteristics after heating, indicating that the high-temperature resistant polyimide film can indeed enable the carbon nanotube thin film transistor to maintain good performance in an air environment above 300°C.

[0106] The above embodiments are preferred implementation modes of the present invention, but the implementation modes of the present invention are not limited to the above embodiments. Any other changes, modifications, substitutions, combinations, and simplifications that do not deviate from the spirit and principles of the present invention should be equivalent replacement methods and are included in the protection scope of the present invention.

Claims

1. A carbon nanotube thin film transistor, characterized in that: The composition includes a substrate, a gate electrode layer, a gate dielectric layer, a semiconductor single-walled carbon nanotube film and a high-temperature resistant polyimide film which are stacked in sequence, and also includes a source electrode and a drain electrode which are arranged on the side of the gate dielectric layer away from the gate electrode layer.

2. The carbon nanotube thin film transistor according to claim 1, characterized in that: The gate electrode layer is composed of aluminum, with a thickness of 30nm to 100nm; the gate dielectric layer is composed of aluminum oxide, with a thickness of 20nm to 200nm.

3. The carbon nanotube thin film transistor according to claim 1 or 2, characterized in that: The semiconductor single-walled carbon nanotube film presents a two-dimensional network structure, is composed of semiconductor single-walled carbon nanotubes interwoven together, and has a thickness of 3nm to 8nm.

4. The carbon nanotube thin film transistor according to claim 1 or 2, characterized in that: The high temperature resistant polyimide film is made of polyimide photoresist which can withstand high temperature above 330° C.; the thickness of the high temperature resistant polyimide film is 5 μm to 20 μm.

5. The carbon nanotube thin film transistor according to claim 1 or 2, characterized in that: The source electrode is composed of at least one of titanium, gold, palladium and platinum, and has a thickness of 30nm to 100nm; the drain electrode is composed of at least one of titanium, gold, palladium and platinum, and has a thickness of 30nm to 100nm.

6. A method for preparing a carbon nanotube thin film transistor according to any one of claims 1 to 5, characterized in that: The following steps are involved: 1) depositing electrode material on one side of the substrate to form a gate electrode layer; 2) depositing a gate dielectric material on the surface of the gate electrode layer to form a gate dielectric layer; 3) coating a semiconductor single-walled carbon nanotube dispersion on the surface of the gate dielectric layer to form a semiconductor single-walled carbon nanotube film; 4) depositing electrode materials on the surface of the gate dielectric layer to form a source electrode and a drain electrode; 5) Coating a high temperature resistant polyimide photoresist on the surface of the semiconductor single-walled carbon nanotube film, and then performing photolithography and heat curing to form a patterned high temperature resistant polyimide film, thereby obtaining a carbon nanotube thin film transistor.

7. A complementary metal oxide semiconductor inverter, characterized in that: The composition includes the carbon nanotube thin film transistor and the indium tin zinc oxide thin film transistor as described in any one of claims 1 to 5; the carbon nanotube thin film transistor and the indium tin zinc oxide thin film transistor are prepared on different parts of the same surface of the same substrate; the indium tin zinc oxide thin film transistor is an indium tin zinc oxide thin film transistor made by a high temperature annealing process.

8. The complementary metal oxide semiconductor inverter according to claim 7, characterized in that: The ITO thin film transistor comprises a substrate, a gate electrode layer, a gate dielectric layer and an ITO thin film which are stacked in sequence, and also comprises a source electrode and a drain electrode which are arranged on the side of the gate dielectric layer away from the gate electrode layer.

9. The complementary metal oxide semiconductor inverter according to claim 8, characterized in that: The thickness of the indium tin zinc oxide film is 30nm-100nm.

10. A display device, characterized in that: A carbon nanotube thin film transistor comprising any one of claims 1 to 5.

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