Quarter-rate 8-phase sampling and decision feedback equalizer circuit and method

Abstract

The invention discloses a quarter-rate eight-phase sampling and decision feedback equalizer circuit and a quarter-rate eight-phase sampling and decision feedback equalizer method, and relates to the technical field of circuit design and digital information transmission. The multi-tap time-interleaved decision feedback equalizer circuit can be realized only by switching two adder circuits through the MUX switch, and meanwhile, the use of the MUX switch on a first-stage tap feedback path is avoided through a connection mode of directly feeding back the outputs of two time-interleaved samplers to the input end of the adder, so that the feedback delay time is effectively shortened, and the service life of the multi-tap time-interleaved decision feedback equalizer circuit is prolonged. And the working speed of the decision feedback equalizer is improved. By adopting a low-speed clock with a quarter rate, the area and the power consumption of a receiver circuit can be effectively reduced, the delay time of a feedback path is reduced, and a higher transmission rate is obtained under the condition of limited power consumption.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit design and digital information transmission, and in particular to a quarter rate 8-phase sampling and decision feedback equalizer circuit and method. Background Art

[0002] With the development of information technology, the transmission rate of signals continues to increase. However, the limited channel bandwidth will cause serious loss of high-frequency signals, resulting in serious intersymbol interference (ISI), affecting the signal quality at the receiving end, and bringing challenges to large-bandwidth data transmission. In channels where frequency-related signal attenuation occurs, serializer / deserializer (SerDes) links are usually used to transmit data. One way to compensate for signal distortion caused by limited bandwidth is to add equalization to the SerDes link. Different equalization techniques can be used to compensate for this ISI in the transmitter and receiver. Common equalization techniques in high-speed SerDes links can be divided into linear equalizers and decision feedback equalizers (DFE).

[0003] The linear equalizer uses the frequency characteristics of the variable gain amplifier to compensate for channel loss, but for high-speed signals, the use of a linear equalizer alone is no longer applicable because the signal jitter may exceed one symbol interval (UI). On the other hand, the linear equalizer amplifies the noise and the signal together, which does not improve the bit error rate performance of the communication system. Therefore, a DFE equalizer circuit is needed to eliminate residual ISI together with the linear equalizer. As a nonlinear equalizer, DFE can compensate for ISI and flatten the channel response without amplifying noise or crosstalk, effectively improving the signal-to-noise ratio characteristics.

[0004] The existing DFE circuit structure usually uses a full-rate, half-rate or quarter-rate clock signal to drive the sampler to sample the input signal, and then implements the delay and multi-level feedback equalization compensation of the sampled signal through latches and multiplexers (MUX).

[0005] In the prior art, when the transmission rate of the latch is extremely high, the clock generation circuit and the driving circuit will consume very large power; there is a DFE circuit structure that will cause the number of adder circuits and sampler circuits to double, resulting in an increase in chip area and power consumption; there is a problem that the reduction in clock rate can reduce the power consumption of the clock generation circuit and the driving circuit, but it also causes the number of samplers to double compared to the half-rate structure, resulting in an increase in chip area and power consumption; after the sampling results of the 4-phase clocks are directly fed back to the adder at the input end of the adjacent branch for equalization compensation in a time-interleaved manner, there is a problem of a large number of adders and increased power consumption.

[0006] Based on the shortcomings of the existing SerDes receiver sampling and DFE technical solutions, it is necessary to design a technical solution with a smaller circuit area, lower power consumption, and a higher transmission rate under limited power consumption conditions. The technical solution must also be able to simultaneously output the data intermediate sampling signal and the edge sampling signal to be suitable for the clock and data recovery loop (CDR) of the SerDes receiver system. Summary of the invention

[0007] The technical problem to be solved by the present invention is that under limited power consumption conditions, the power consumption of a sampling and decision feedback equalizer circuit in a SerDes receiver is inversely proportional to the transmission rate and has poor coordination ability. The purpose is to provide a quarter-rate 8-phase sampling and decision feedback equalizer circuit and method, by sampling signals respectively through multiple clock phases of a quarter rate, only two adder circuits are needed to switch through a MUX switch to realize a multi-tap time-interleaved decision feedback equalizer circuit, and at the same time, the connection mode of directly feeding back the output of the two-way sampler of the time interleaving to the input end of the adder avoids the use of the MUX switch on the first-stage tap feedback path, effectively shortens the feedback delay time, improves the working rate of the DFE (Decision Feedback Equalizer, decision feedback equalizer), can simultaneously reduce the number of samplers and adders, and effectively reduces the area and power consumption of the SerDes receiver circuit.

[0008] The present invention is achieved through the following technical solutions: A first aspect of the present invention provides a quarter rate 8 phase sampling and decision feedback equalizer circuit, comprising: MUX switches, multiple adders, and multiple sampling and delay branches; Each sampling and delay branch includes: a return-to-zero sampler, an SR latch and a clock-driven latch, the output of the return-to-zero sampler is connected to the SR latch, and the output of the SR latch is connected to the clock-driven latch; The outputs of the zeroing sampler, the SR latch and the clock-driven latch are respectively selected by the MUX switch and input into different adders as the feedback signals of each order of the decision feedback equalizer, thereby forming a multi-tap time-interleaved decision feedback equalizer circuit.

[0009] Furthermore, the sampling clock of the return-to-zero sampler includes at least 8 sampling clock signals, namely 0 degree phase clock CK0, 45 degree phase clock CK45, 90 degree phase clock CK90, 135 degree phase clock CK135, 180 degree phase clock CK180, 225 degree phase clock CK225, 270 degree phase clock CK270, and 315 degree phase clock CK315.

[0010] Furthermore, the output data signal of the return-to-zero sampler is S<0-3>, the data signal S<0-3> outputs the data signal L<0-3> after passing through the SR latch, and the data signal L<0-3> outputs the final data signal D<0-3> after passing through the clock-driven latch.

[0011] Furthermore, the signals finally outputted by the sampling and delay branches corresponding to the sampling clocks CK0, CK90, CK180, and CK270 are data signals D <0> , D <1> , D <2> , D <3> ; The final output signals of the sampling and delay branches connected to the sampling clocks CK45, CK135, CK225, and CK315 are edge signals E <0> , E <1> , E <2> , E <3> ; Among them, the data signal D <0> , D <1> , D <2> , D <3> The delay time of the corresponding branch is half a clock cycle; the edge signal E <0> , E <1> , E <2> , E <3> The delay time of the corresponding branch is 3 / 8 clock cycle.

[0012] Furthermore, the sampling and delay branches connected to the sampling clock CK0 correspond to the data signal D <0> sampling; The sampling clock CK45 corresponds to the sampling and delay branches connected to the edge signal E <0> sampling; The sampling clock CK180 corresponds to the sampling and delay branches connected to the data signal D <2> sampling; The sampling clock CK225 corresponds to the sampling and delay branches connected to the edge signal E <2> sampling; The sampling clock CK90 corresponds to the sampling and delay branches connected to the data signal D <1> sampling; The sampling clock CK135 corresponds to the sampling and delay branches connected to the edge signal E <1> sampling; The sampling clock CK270 corresponds to the sampling and delay branches connected to the data signal D <3> sampling; The sampling clock CK315 corresponds to the sampling and delay branches connected to the edge signal E <3> sampling.

[0013] A second aspect of the present invention provides a decision feedback equalization method, which is applied to a quarter rate 8 phase sampling and decision feedback equalizer circuit, comprising the following specific steps: The output signal of the zeroing sampler is fed back to the adder of the complementary branch to form a first-order feedback path; The output signal of the SR latch is fed back to the adder of this branch after being selected by the MUX switch, forming a second-order feedback path; The output signal of the SR latch is fed back to the adder of the complementary branch after being selected by the MUX switch, forming a third-order feedback path; The output signal of the clock-driven latch is fed back to the adder of this branch after being selected by the MUX switch, forming a 4th-order feedback path; The sampling and delay branch includes an even branch and an odd branch. The even branch is connected to the adder SUM1, and the odd branch is connected to the adder SUM2. The even branch and the odd branch are complementary branches.

[0014] Furthermore, the signal feedback process of the first-order feedback path specifically includes: The output signal S of the return-to-zero sampler of the even-numbered branch <0> and S <2> At the same time, it is directly fed back to the adder SUM2 of the odd-numbered branches to form the feedback path of the first-order tap DFE, and the feedback coefficient is H1; The output signal S of the return-to-zero sampler of the odd-numbered branch <1> and S <3> At the same time, it is directly fed back to the adder SUM1 of the even-numbered branches to form a complementary first-order tap DFE feedback path, and the feedback coefficient is H1; Among them, the even-numbered branch output signal S <0> and S <2> The return-to-zero sampler driving clocks are CK0 and CK180 respectively, and the odd-numbered branch output signal S <1> and S <3> The return-to-zero sampler driving clocks are CK90 and CK270 respectively.

[0015] Furthermore, the signal feedback process of the second-order feedback path specifically includes: The output signal L of the SR latch of the even branch <0> and L <2> After being selected by the MUX switch driven by the CK270 clock signal, it is fed back to the SUM1 adder, and the feedback coefficient is H2; The output signal L of the SR latch of the odd branch <1> and L <3> The MUX switch driven by the CK180 clock signal selects and then feeds back to the SUM2 adder, with a feedback coefficient of H2.

[0016] Furthermore, the signal feedback process of the third-order feedback path specifically includes: The output signal L of the SR latch of the even branch <0> and L <2> The MUX switch driven by the CK180 clock signal is selected and then fed back to the SUM2 adder, and the feedback coefficient is H3; The output signal L of the SR latch of the odd branch <1> and L <3> The MUX switch driven by the CK270 clock signal selects and then feeds back to the SUM1 adder, with a feedback coefficient of H3.

[0017] Furthermore, the signal feedback process of the 4th-order feedback path specifically includes: The output signal D of the latch of the even branch <0> and D <2> After being selected by the MUX switch driven by the CK270 clock signal, it is fed back to the SUM1 adder, and the feedback coefficient is H4; The output signal D of the latch of the odd branch <1> and D <3> The MUX switch driven by the CK180 clock signal selects and then feeds back to the SUM2 adder, with a feedback coefficient of H4.

[0018] Compared with the prior art, the present invention has the following advantages and beneficial effects: By sampling the signals separately at multiple clock phases of a quarter rate, only two adder circuits need to be switched through a MUX switch to realize a multi-tap time-interleaved decision feedback equalizer circuit. At the same time, the two time-interleaved sampler outputs are directly fed back to the adder input, thereby avoiding the use of a MUX switch on the first-stage tap feedback path, effectively shortening the feedback delay time, and improving the working rate of the DFE (Decision Feedback Equalizer). The number of samplers and adders can be reduced at the same time, effectively reducing the area and power consumption of the SerDes receiver circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and should not be regarded as limiting the scope. For those of ordinary skill in the art, other relevant drawings can be obtained based on these drawings without creative work. In the drawings: Figure 1 is a structural diagram of an existing full-rate DFE in an embodiment of the present invention; Figure 2 is a structural diagram of an existing half-rate sampling DFE based on inference results in an embodiment of the present invention; Figure 3 is a structural diagram of an existing quarter-rate sampling DFE based on inference results in an embodiment of the present invention; Figure 4 A structural diagram of an existing quarter-rate sampling time-interleaved feedback DFE in an embodiment of the present invention; Figure 5 It is a circuit structure of a quarter rate 8 phase sampling and decision feedback equalizer in an embodiment of the present invention; Figure 6 It is a timing waveform diagram of an 8-phase sampling and decision feedback equalizer circuit in an embodiment of the present invention; Figure 7 A SUM adder circuit that can be used in an embodiment of the present invention; Figure 8 is an RZ sampler circuit that can be used in an embodiment of the present invention; Fig. 9 It is an SR latch circuit that can be used in the embodiment of the present invention. DETAILED DESCRIPTION

[0020] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with embodiments and drawings. The exemplary embodiments of the present invention and their description are only used to explain the present invention and are not intended to limit the present invention.

[0021] like Figure 1 The figure shows an existing full-rate DFE structure diagram, which uses latches to implement multi-level clock delays, and uses adders at the input end to add feedback signals of different weights to offset the impact of ISI, and then performs signal sampling. The clock frequency of this structure is equal to the bit rate of system transmission. When the transmission rate is extremely high, the clock generation circuit and the drive circuit will consume very large power, and the maximum operating frequency of the transistors inside the chip will limit the further increase of the transmission rate.

[0022] like Figure 2 As shown in FIG. , it is a half-rate sampling DFE circuit structure based on the predictive result (Predictive), such as Figure 2 As shown, by inferring that the result of the previous bit output by another branch is '1' or '0', two adder circuits (adder) are used to perform operations with weights of +C1 and -C1, and then two independent samplers (sampler) are used to sample respectively. The two output signals after sampling are selected by the MUX selector according to the result of the output of the other branch. In this way, the influence of circuit delay can be reduced, and the signal output by a branch sampling is allowed to have a delay of up to 2 symbol intervals (UI), thereby increasing the maximum operating rate of the receiving circuit. The patent also uses a three-level delay feedback compensation DFE structure with C2 and C3 weights. This DFE circuit structure based on the inference result will double the number of adder circuits and sampler circuits, resulting in an increase in chip area and power consumption.

[0023] like Figure 3 As shown in the figure, it is a DFE circuit structure with a quarter rate sampling based on the predictive result. This result also uses the DFE circuit structure based on the predictive result. The main difference is that it uses a quarter rate 4-phase clock for sampling, and uses the signal output by the adjacent phase clock sampling to control the MUX selector to perform a two-choice operation. This structure can reduce the power consumption of the clock generation circuit and the driving circuit due to the reduction of the clock rate, but it also causes the number of samplers to double compared to the half-rate structure, resulting in an increase in chip area and power consumption.

[0024] like Figure 4 As shown in FIG. 1 , it is a diagram of an existing quarter-rate sampling time-interleaved feedback DFE structure. This structure uses time interleaving to directly feed back the sampling results of the four phase clocks to the adders at the input ends of adjacent branches for equalization compensation. Since each branch requires an adder, the number of adders is large and the power consumption increases. This interleaved feedback DFE structure has very high requirements on the delay of the signal feedback path between adjacent branches, such as Figure 4 In the picture marked as (a), the feedback path goes from the sampler output point A to point B and then to point C. The picture marked as (b) shows that the total delay time from the sampler output point A to point B and then to point C must be less than 1 symbol interval (UI). Therefore, the delay of the feedback path determines the maximum operating rate of the DFE circuit, and appropriate technical solutions must be used to minimize the delay.

[0025] Based on the above problems, this example provides a quarter-rate 8-phase sampling and decision feedback equalizer circuit to solve the problems of the above technology. This implementation samples 4 groups of data signals (D<0-3>) and 4 groups of edge signals (E<0-3>) through 8 clock phases of a quarter rate. Only two adder circuits are needed to switch through the MUX switch to realize the multi-tap time-interleaved decision feedback equalizer circuit. At the same time, the connection method of directly feeding back the two-way sampler (Sampler) output of the time interleaving to the adder input end avoids the use of the MUX switch on the first-stage tap feedback path, effectively shortens the feedback delay time, and improves the working rate of the DFE. The technical solution provided by this implementation adopts a quarter-rate low-speed clock and reduces the number of samplers and adders, so it can effectively reduce the area and power consumption of the SerDes receiver circuit.

[0026] Specifically, Figure 5As shown, the receiving circuit sends the signal from the linear equalizer (CTLE) output to two adders SUM1 and SUM2 at the same time. The output of each adder is connected to 4 return-to-zero type samplers (RZ Sampler). Each sampler uses a clock signal with a different phase to sample the input data. The frequency of the sampling clock is one-fourth of the SerDes data transmission rate. The 8 sampling clock signals are 0-degree phase clock CK0, 45-degree phase clock CK45, 90-degree phase clock CK90, 135-degree phase clock CK135, 180-degree phase clock CK180, 225-degree phase clock CK225, 270-degree phase clock CK270, and 315-degree phase clock CK315. The 8 sampling clock signals include 4 even branches and 4 odd branches. Among them, the even branches use CK0, CK180, CK45, and CK225 clocks to sample D respectively. <0> , D <2> The corresponding data signal sampling, for E <0> 、E <2> The corresponding edge signal sampling; the odd branches use CK90, CK270, CK135, CK315 clocks to sample D <1> , D <3> The corresponding data signal sampling, for E <1> 、E <3> The corresponding edge signal is sampled. The output data signal of the RZ sampler is S<0-3>, which is outputted through the SR latch as the data signal L<0-3>, and finally outputted through the common latch (Latch) as the final data signal D<0-3>. The SR latch and the common latch (Latch) realize the latching and delay control of the signal. The 4-order tap decision feedback equalizer (DFE) circuit feeds back the S<0-3> signal, L<0-3> signal and D<0-3> signal to the SUM1 and SUM2 adders at the input end through the MUX switch for equalization compensation; the 1st-order feedback path feeds back the S<0-3> signal directly to the adder of the complementary branch, with a feedback coefficient of H1, the 2nd-order feedback path feeds back the L<0-3> signal to the adder of the current branch after being selected by the MUX switch, with a feedback coefficient of H2, the 3rd-order feedback path feeds back the L<0-3> signal to the adder of the complementary branch after being selected by the MUX switch, with a feedback coefficient of H3, and the 4th-order feedback path feeds back the D<0-3> signal to the adder of the current branch after being selected by the MUX switch, with a feedback coefficient of H4.

[0027] In some possible implementations, the SUM1 adder is connected to the even branch (even), and its output is connected to 4 samplers, and the sampling clocks are CK0, CK45, CK180 and CK225 respectively; the SUM2 adder is connected to the odd branch (odd), and its output is connected to 4 samplers, and the sampling clocks are CK90, CK135, CK270 and CK315 respectively.

[0028] In some possible implementations, the output of each sampler is connected to an SR latch (set-reset latch, SR Latch), and the output of the SR latch is connected to a clock-driven latch (Latch). The three stages of circuits connected in series in sequence form a sampling and delay branch, in which the output of each stage of the circuit is selected by the MUX switch and then used as the feedback signal of each order of the decision feedback equalizer (DFE). The signal finally output by the sampling and delay branch connected to the sampling clocks CK0, CK90, CK180, and CK270 is the data signal D <0> , D <1> , D <2> , D <3> The final output signal of the sampling and delay branches connected to the sampling clocks CK45, CK135, CK225, and CK315 is the edge signal E. <0> , E <1> , E <2> , E <3> The data signals D<0-3> and edge signals E<0-3> are multiplexed through latches and multiplexers (DMUX) and then used for subsequent data processing of the SerDes receiver, including data serial-to-parallel conversion and clock data recovery (CDR).

[0029] In some possible implementations, due to the different phase differences between the sampler clock and the final latch clock, the delay times of the sampling and delay branches corresponding to the data signal D<0-3> and the edge signal E<0-3> are different. The delay time of the data signal branch is half a clock cycle, while the delay time of the edge signal branch is 3 / 8 of a clock cycle. The selection of different clock phase differences in the sampling and delay branches is very critical. Incorrect clock selection will lead to a decrease in the maximum operating rate of the SerDes and will also cause errors in the decision feedback equalizer DFE function.

[0030] In some possible implementations, Figure 5 The circuit structure shown shows a 4-tap DFE structure, where the tap coefficients of each order are H1, H2, H3, and H4. Depending on the embodiment, the DFE structure can be expanded to any order of tap coefficients by adding multiple stages of serial latches. Similar extended structures are within the protection scope of this embodiment.

[0031] The provided DFE structure is implemented through a time interleaving feedback control structure between an even branch and an odd branch, the even branch and the odd branch are complementary to each other, and a MUX switch is used to switch and select delayed data signals with different sampling clocks to be fed back to an adder at the input end.

[0032] In some possible implementations, the feedback equalization process of the quarter rate 8 phase sampling and decision feedback equalizer circuit includes: The output signal S of the reset-to-zero type sampler (RZ sampler) of the even branch <0> and S <2> At the same time, it is directly fed back to the adder SUM2 of the odd-numbered branch to form the feedback path of the first-order tap DFE, and the feedback coefficient is H1; similarly, the sampler output signal S of the odd-numbered branch <1> and S <3> At the same time, it is directly fed back to the adder SUM1 of the even branch to form a complementary first-order tap DFE feedback path. The return-to-zero type sampler (RZ Sampler) outputs a valid sampling result when the driving clock signal is at a high level, and resets the output sampling result to zero when the driving clock signal is at a low level; in the quarter-rate 8-phase sampling technical solution provided in this embodiment, the driving clocks of the data signal samplers (RZ Sampler) of the same even branch or odd branch are in opposite phases, for example, the output signal S <0> and S <2> The sampler driving clocks are CK0 and CK180 respectively, the clock phases are just opposite, and the odd-numbered branch output signal S <1> and S <3> The sampler driving clocks are CK90 and CK270 respectively, and the clock phases are also inverted. Therefore, the signals output by the data samplers in the same branch will not be valid at the same time. When the output signal of one sampler is valid, the output signal of the other sampler will be in a reset state. Based on the phase inversion characteristic of the data signal sampler (RZ Sampler), the technical solution provided in this embodiment feeds back the outputs of the two data signal samplers (RZ Sampler) to the adder of the complementary branch at the same time to perform the first-order tap DFE compensation, so that the latch is no longer required on the first-order DFE feedback path, and the MUX selector is also not required. The output of the sampler is directly connected to the adder, which effectively shortens the delay time of the feedback path and improves the maximum operating rate of the DFE circuit.

[0033] The second-order feedback path of DFE does not adopt the interleaved feedback structure between the even branch and the odd branch. Instead, the output signal of the SR latch corresponding to the branch is selected by the MUX switch to be fed back to the input adder of the branch. Specifically, the output signal L of the SR latch of the even branch is <0> , L <2> After being selected by the MUX switch driven by the CK270 clock signal, it is fed back to the SUM1 adder, and the feedback coefficient is H2; the output signal L of the SR latch of the odd branch <1> , L <3> The MUX switch driven by the CK180 clock signal selects and then feeds back to the SUM2 adder, with a feedback coefficient of H2.

[0034] The third-order feedback path of DFE adopts an interleaved feedback structure between the even branch and the odd branch. The output signal of the SR latch corresponding to the branch is selected by the MUX switch and fed back to the input adder of the complementary branch. Specifically, the output signal L of the SR latch of the even branch is <0> , L <2> After being selected by the MUX switch driven by the CK180 clock signal, it is fed back to the SUM2 adder, and the feedback coefficient is H3; the output signal L of the SR latch of the odd branch <1> , L <3> The MUX switch driven by the CK270 clock signal selects and then feeds back to the SUM1 adder, with a feedback coefficient of H3.

[0035] The fourth-order feedback path of DFE does not adopt the interleaved feedback structure between the even branch and the odd branch. Instead, the output signal of the latch corresponding to the branch is selected by the MUX switch to be fed back to the input adder of the branch. Specifically, the output signal D of the latch of the even branch is <0> , D <2> The MUX switch driven by the CK270 clock signal is selected and fed back to the SUM1 adder, and the feedback coefficient is H4; the output signal D of the latch of the odd branch <1> , D <3> The MUX switch driven by the CK180 clock signal selects and then feeds back to the SUM2 adder, with a feedback coefficient of H4.

[0036] The DFE circuit structure provided in this embodiment is not limited to a DFE structure with 4 tap coefficients. The number of tap orders can be reduced, and can also be expanded to a DFE structure with 5-order, 6-order or any order tap coefficients by adding multiple stages of serial latches. Similar extended structures are within the protection scope of this embodiment.

[0037] In some possible implementations, the present embodiment provides Figure 5 The common latch (Latch) used in the circuit structure diagram can be any type of latch structure, such as a D flip-flop, a latch of CML logic, etc.

[0038] Figure 6 A timing waveform diagram of the 8-phase sampling and decision feedback equalizer circuit provided by this embodiment is given, and the figure shows the data sampling D during the second cycle of the even branch. <4> and edge sampling E <4> The DFE timing and adder input signal waveform at the moment. The figure marks the process in which all 4-order feedback signals are balanced and compensated by the SUM1 adder during the high-level pulse stage of CK270. The input data D <3> ,correspond Figure 5 The sampler output of CK270 is S <3> The signal is fed back directly to the SUM1 adder through the first-order DFE feedback channel using the H1 feedback coefficient, and the input data D <2> ,correspond Figure 5The L of the SR latch output <2> The signal is connected to the SUM1 adder through the MUX selector driven by CK270 and the second-order DFE feedback channel using the H2 feedback coefficient. The input data D <1> ,correspond Figure 5 The L of the SR latch output <1> The signal is connected to the SUM1 adder through the MUX selector driven by CK270 and the third-order DFE feedback channel using the H3 feedback coefficient. The input data D <0> ,correspond Figure 5 The D of the latch output <0> The signal is connected to the SUM1 adder through the MUX selector driven by CK270 and the H4 feedback coefficient is used in the fourth-order DFE feedback channel. All DFE feedback signals of each order are added and compensated in the SUM1 adder with the signal input from the linear equalizer (CTLE) during the high-level pulse duration of the CK270 clock. Then, the sampler (RZ Sampler) driven by CK0 samples the data at the rising edge of the clock to obtain S <4> The data signal is then delayed by the SR latch and the latch to obtain the final data signal D. <4> Output; The sampler (RZ Sampler) driven by CK45 performs edge sampling at the rising edge of the clock to obtain the output edge signal, and then obtains the final edge signal E after the delay of the SR latch and the latch (Latch). <4> Output.

[0039] The sampling and DFE feedback timing waveforms on all clock phases are shown in Figure 1. Figure 6 Similarly, the eight clock phases and the even branches and the odd branches are cyclically fed back in sequence to form a time-continuous DFE equalization compensation structure, thereby achieving the effect described in this embodiment.

[0040] Figure 7 A circuit schematic diagram of a SUM adder that can be used in the technical solution of this embodiment is provided. The adder adopts a fully differential circuit structure and includes a 4th-order tap feedback coefficient branch. Figure 7 The differential pair composed of the M0 transistors is the main amplification branch of the adder, which amplifies the input differential signals Inp and Inn. The output load resistance is R, and the amplification factor of the adder is controlled by the current size of the tail current source H0; the two groups of differential pairs composed of the M1 transistors are the first-order feedback branches, and the first-order feedback coefficient is controlled by the tail current source H1. The input signals Tap0p, Tap0n and Tap1p, Tap1n of the two groups of differential pairs are connected to Figure 5 The S in the DFE structure shown <0> , S <2> or S <1> , S <3> It should be noted that S<0-3> must also be in differential signal form to accommodate Figure 7In the differential circuit structure shown in FIG, since the sampling clocks of the two groups of signals in the first-order feedback path are in anti-phase relationship, the two groups of differential signals Tap0p, Tap0n and Tap1p, Tap1n will not be valid at the same time. When one group of signals is valid, the other group of signals is in a reset state, that is, the positive and negative ends of the other group of differential signals are all 0; the differential pair composed of the M2 transistor is a second-order feedback branch, and the second-order feedback coefficient is controlled by the tail current source H2. The differential input signals Tap2p and Tap2n are connected Figure 5 The L<0-3> in the DFE structure shown in the figure is the second-order feedback path signal output after being selected by the MUX switch; the differential pair composed of the M3 transistor is the third-order feedback branch, and the third-order feedback coefficient is controlled by the tail current source H3. The differential input signals Tap3p and Tap3n are connected Figure 5 The L<0-3> in the DFE structure shown in the figure is the 3rd-order feedback path signal output after being selected by the MUX switch; the differential pair composed of the M4 transistor is the 4th-order feedback branch, and the 4th-order feedback coefficient is controlled by the tail current source H4. The differential input signals Tap4p and Tap4n are connected Figure 5 D<0-3> in the DFE structure shown in the figure is the output of the 4th order feedback path signal after being selected by the MUX switch. It is particularly important to note that the decision feedback equalizer circuit (DFE) is a negative feedback control circuit, so the feedback signals of the tap coefficients of each order need to form a negative feedback compensation effect when connected. Figure 7 The connection relationship between the differential pair transistor output terminals of each order feedback branch and the output signals Outp and Outn is exactly opposite to the connection mode of the differential pair transistors of the main amplifier circuit.

[0041] Figure 8 A circuit schematic diagram of a return-to-zero type sampler (RZ Sampler) that can be used in the technical solution of this embodiment is provided. The circuit is a dynamic comparator circuit driven by a CK clock signal. The magnitudes of the input signals Inp and Inn are compared at the rising edge of the CK clock, and the output comparison result is maintained during the duration of the CK signal being at a high level. The comparison result signal of the sampler is Figure 8 The inverter drives the output; when the CK signal becomes low, the RZ sampler resets the comparison result. Figure 8 The middle transistors M3 and M4 are turned on when the CK signal is at a low level, and the output differential signals A and An are all pulled up to the power supply voltage VDD, and the differential signals Outp and Outn driven by the inverters are all reset to a low level '0'.

[0042] Fig. 9A circuit structure diagram of an SR latch (SR Latch) that can be used in the technical solution of this embodiment is provided. The SR latch is composed of two cross-coupled NOR gates. The R and S terminals are signal input ports, and the Q and Qn terminals are signal output ports. When the R and S signals are '0' or '1' respectively, the SR latch will latch the input signal to the output Q and Qn terminals. When the R and S signals are '0' at the same time, the SR latch will keep the previous output result unchanged. Fig. 9 The SR latch provided in the Figure 8 The return-to-zero type sampler (RZ Sampler) provided in the cascade, when the CK signal is high, the return-to-zero type sampler outputs the comparison result, and the SR latch latches the result to the Q, Qn output. When the CK signal is low, the return-to-zero type sampler output result is reset, and the differential output ends all become '0' signals. At this time, the SR latch will keep the previous output result unchanged.

[0043] In order to better understand this embodiment, the following is given Figure 1-Figure 9 Specific instructions: Figure 1 Ain represents the input signal; Dout represents the output signal; F represents the filter in the feedback path; L represents the filter in the feedforward path; C1, C2, C3, …, Cn represent delay elements, which usually represent registers or storage units used to store the signal value at the previous moment; CK represents the clock signal, which is used to synchronize the operations of various parts of the system.

[0044] Figure 2 In the figure, From CTLE indicates that the input signal comes from a continuous time linear equalizer; +c1 and -c1 indicate that adders and subtractors with coefficients of +c1 and -c1 are used in the circuit to adjust the gain or phase of the signal; MUX indicates a multiplexer, which is used to select the path of the input signal; DFF indicates a D-type flip-flop, which is a digital storage element that can store one bit of data under the control of a clock signal (CK); CK and CK′ indicate the clock signal and its inverted signal; c2 and c3 indicate circuit coefficients; OUT indicates the output signal of the circuit.

[0045] Figure 3In the INPUT DATA SIGNAL, 1ST INPUT SIGNAL, 2ND INPUT SIGNAL: 1st input signal and 2nd input signal, representing different input data streams or signal channels; CLK1, CLK2, CLK3, CLK4: These usually represent clock signals, which are used to synchronize operations in the circuit. The numbers may represent different clock sources or phases of clock signals; LATCH: latch, used to store data until the next clock signal arrives; FTFS: circuit module abbreviation; 1ST, 2ND, 3RD, 4TH: represent first, second, third and fourth, used to distinguish different outputs or processing stages; OUTPUT: output signal, representing the processed data signal; Figure 4 In the part marked as (a): IN: indicates input signal; β1: indicates gain, which is used to adjust the strength of the input signal; FF: indicates flip-flop, which is a storage unit that can store one bit of binary information; Φ 1 / 4,j : represents the phase or clock signal, which is used to synchronize the operation of the trigger; OUT0, OUT1, OUT2, OUT3: represents the output signal of the trigger; The part marked as (b): T bit : represents the time period of a bit, that is, the duration of each bit signal; D0, D1, D2, D3: represent data input signals, which may be the input data of the trigger; A, B, C: represent output signals, which may correspond to the output of the trigger.

[0046] Figure 5In the diagram, VCC / VDD indicates the power supply voltage, VCC indicates the positive power supply, and VDD indicates the power supply voltage. GND indicates ground, which is the reference voltage point in the circuit. R indicates resistor. C indicates capacitor. Q indicates transistor, and in some cases may also indicate flip-flop. RZ Sampler RZ Sampler data signal sampler. IN indicates input signal. OUT indicates output signal. CLK: indicates clock signal, which is used to synchronize circuit operation. EN: usually indicates enable signal, which is used to control the activation state of the circuit. RST: indicates reset signal, which is used to restore the circuit to the initial state. I / O: indicates input / output, which refers to the input or output port of data. MUX: indicates multiplexer, which is used to select an output from multiple inputs. DE: indicates data enable. SR Latch indicates SR latch. Latch indicates latch.

[0047] Figure 6 In the D <0> ,D <1> ,...,D <9> : Indicates different bits on the data bus, usually used to indicate a 10-bit wide data bus. <0> ,E <1> , ...,E <9> : Indicates the signal (Enable), which is used to control the enable status of each bit on the data bus. <1> ,L <2> ,S <3> : Signals used to indicate different operations or states, CK0, CK45, CK90, ..., CK315: represent different clock signals. H0, H1, H2, H3, H4: represent tap feedback coefficients. SUM: represents the output of the adder (Sum), which may be the part of the circuit used to perform addition operations.

[0048] Figure 7In the diagram, VDD: represents the positive pole of the power supply voltage. GND: represents ground, the reference voltage point of the circuit. R: represents resistor. M0, M1, M2, M3, M4: represents transistors (MOSFET), usually used for amplification or switching. Inp: represents input signal (Input). Outp, Outn: represents output signal (Output), where Outp may be a positive output and Outn is a negative output. Inn: may represent an internal node or signal. Tap0p, Tap0n, Tap1p, Tap1n,..., Tap4n: represent different taps (Tap) or nodes, used to connect different circuit parts to achieve specific filtering or amplification functions. H0, H1, H2, H3, H4: represent tap feedback coefficients.

[0049] Figure 8 In the figure, VDD: represents the positive pole of the power supply voltage. GND: represents ground, the reference voltage point of the circuit, that is, the zero potential point. CK: represents the clock signal (Clock), which is used to synchronize circuit operation or control switching elements. Inp: represents the positive end of the input signal (Positive Input). Inn: represents the negative end of the input signal (Negative Input), which together with Inp constitutes a differential input. Outp: represents the positive end of the output signal (Positive Output). Outn: represents the negative end of the output signal (Negative Output), which together with Outp constitutes a differential output. M0, M1, M2, M3, M4, M5: represent MOSFET transistors, which are usually used to build amplifiers, switches or other functional modules in analog circuits. A, An: represent nodes or signal points, which are used to connect different components in the circuit or represent specific voltage points.

[0050] Fig. 9 In the figure, R is the abbreviation of Reset, which means reset input. When the R input is an activation signal, the flip-flop will be reset and the output will be forced to 0. S is the abbreviation of Set, which means set input. When the S input is an activation signal, the flip-flop will be set and the output will be forced to 1. Q: represents the output state of the flip-flop. When the flip-flop is set, the Q output is 1. Qn: represents the inverted output of Q (Not Q). When Q is 1, Qn is 0, and vice versa.

[0051] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A quarter rate 8 phase sampling and decision feedback equalizer circuit, characterized in that: include: MUX switches, multiple adders, and multiple sampling and delay branches; Each sampling and delay branch includes: a return-to-zero sampler, an SR latch and a clock-driven latch, the output of the return-to-zero sampler is connected to the SR latch, and the output of the SR latch is connected to the clock-driven latch; The outputs of the zeroing sampler, the SR latch and the clock-driven latch are respectively selected by the MUX switch and input into different adders as the feedback signals of each order of the decision feedback equalizer, thereby forming a multi-tap time-interleaved decision feedback equalizer circuit.

2. The quarter rate 8 phase sampling and decision feedback equalizer circuit according to claim 1, characterized in that: The sampling clock of the return-to-zero sampler includes at least 8 sampling clock signals, which are 0 degree phase clock CK0, 45 degree phase clock CK45, 90 degree phase clock CK90, 135 degree phase clock CK135, 180 degree phase clock CK180, 225 degree phase clock CK225, 270 degree phase clock CK270, and 315 degree phase clock CK315.

3. The quarter rate 8 phase sampling and decision feedback equalizer circuit according to claim 1, characterized in that: The output data signal of the return-to-zero sampler is S<0-3>, and the data signal S<0-3> outputs the data signal L<0-3> after passing through the SR latch, and the data signal L<0-3> outputs the final data signal D<0-3> after passing through the clock-driven latch.

4. The quarter rate 8 phase sampling and decision feedback equalizer circuit according to claim 2, characterized in that: The final output signals of the sampling and delay branches connected to the sampling clocks CK0, CK90, CK180, and CK270 are data signals D <0> , D <1> , D <2> , D <3> ; The final output signals of the sampling and delay branches connected to the sampling clocks CK45, CK135, CK225, and CK315 are edge signals E <0> , E <1> , E <2> , E <3> .

5. The quarter rate 8 phase sampling and decision feedback equalizer circuit according to claim 4, characterized in that: The sampling clock CK0 corresponds to the sampling and delay branches connected to the data signal D <0> sampling; The sampling clock CK45 corresponds to the sampling and delay branches connected to the edge signal E <0> sampling; The sampling clock CK180 corresponds to the sampling and delay branches connected to the data signal D <2> sampling; The sampling clock CK225 corresponds to the sampling and delay branches connected to the edge signal E <2> sampling; The sampling clock CK90 corresponds to the sampling and delay branches connected to the data signal D <1> sampling; The sampling clock CK135 corresponds to the sampling and delay branches connected to the edge signal E <1> sampling; The sampling clock CK270 corresponds to the sampling and delay branches connected to the data signal D <3> sampling; The sampling clock CK315 corresponds to the sampling and delay branches connected to the edge signal E <3> sampling.

6. A decision feedback equalization method, applied to the circuit according to any one of claims 1 to 5, characterized in that: The specific steps include: The output signal of the zeroing sampler is fed back to the adder of the complementary branch to form a first-order feedback path; The output signal of the SR latch is fed back to the adder of this branch after being selected by the MUX switch, forming a second-order feedback path; The output signal of the SR latch is fed back to the adder of the complementary branch after being selected by the MUX switch, forming a third-order feedback path; The output signal of the clock-driven latch is fed back to the adder of this branch after being selected by the MUX switch, forming a 4th-order feedback path; The sampling and delay branch includes an even branch and an odd branch. The even branch is connected to the adder SUM1, and the odd branch is connected to the adder SUM2. The even branch and the odd branch are complementary branches.

7. The decision feedback equalization method according to claim 6, characterized in that: The signal feedback process of the first-order feedback path specifically includes: The output signal S of the return-to-zero sampler of the even-numbered branch <0> and S <2> At the same time, it is directly fed back to the adder SUM2 of the odd-numbered branches to form the feedback path of the first-order tap DFE, and the feedback coefficient is H1; The zero sampler output signal S of the odd-numbered branches <1> and S <3> At the same time, it is directly fed back to the adder SUM1 of the even-numbered branches to form a complementary first-order tap DFE feedback path, and the feedback coefficient is H1; Among them, the even-numbered branch output signal S <0> and S <2> The return-to-zero sampler driving clocks are CK0 and CK180 respectively, and the odd-numbered branch output signal S <1> and S <3> The return-to-zero sampler driving clocks are CK90 and CK270 respectively.

8. The decision feedback equalization method according to claim 6, characterized in that: The signal feedback process of the second-order feedback path specifically includes: The output signal L of the SR latch of the even branch <0> and L <2> After being selected by the MUX switch driven by the CK270 clock signal, it is fed back to the SUM1 adder, and the feedback coefficient is H2; The output signal L of the SR latch of the odd branch <1> and L <3> The MUX switch driven by the CK180 clock signal selects and then feeds back to the SUM2 adder, with a feedback coefficient of H2.

9. The decision feedback equalization method according to claim 6, characterized in that: The signal feedback process of the third-order feedback path specifically includes: The output signal L of the SR latch of the even branch <0> and L <2> The MUX switch driven by the CK180 clock signal is selected and then fed back to the SUM2 adder, and the feedback coefficient is H3; The output signal L of the SR latch of the odd branch <1> and L <3> The MUX switch driven by the CK270 clock signal selects and then feeds back to the SUM1 adder, with a feedback coefficient of H3.

10. The decision feedback equalization method according to claim 6, characterized in that: The signal feedback process of the 4th-order feedback path specifically includes: The output signal D of the latch of the even branch <0> and D <2> After being selected by the MUX switch driven by the CK270 clock signal, it is fed back to the SUM1 adder, and the feedback coefficient is H4; The output signal D of the latch of the odd branch <1> and D <3> The MUX switch driven by the CK180 clock signal selects and then feeds back to the SUM2 adder, with a feedback coefficient of H4.

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