Two-dimensional semiconductor device and preparation method thereof

Abstract

The invention discloses a two-dimensional semiconductor device and a preparation method thereof, the device comprises a substrate, a two-dimensional semiconductor material layer and a gate structure, the gate structure comprises a gate dielectric layer and a gate layer, and the gate dielectric layer comprises a part covered by the bottom of the gate and a part not covered by the bottom of the gate. Parts which are not covered by the bottom of the grid respectively extend outwards along the surface of the semiconductor layer; side walls cover the part, not covered by the bottom of the grid electrode, of the grid dielectric layer and the two sides of the grid electrode; supporting layers are arranged on the surfaces of the side walls; and the side wall, the two-dimensional semiconductor material layer and the substrate penetrate through the active drain metal contact layer from top to bottom along the supporting layer. According to the invention, the metal yttrium is deposited on the two-dimensional semiconductor material layer and cleaned to leave the yttrium seed crystal, and the high-performance gate structure is obtained by taking the metal yttrium as the seed crystal, so that the sub-threshold swing and contact resistance of the device are remarkably reduced, the short channel effect is effectively inhibited, the channel defect is reduced, and the overall performance, yield and reliability of the device are remarkably improved.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure and a preparation method thereof, and in particular to a two-dimensional semiconductor device and a preparation method thereof. Background Art

[0002] With the continuous development of semiconductor technology, the process nodes of advanced silicon-based integrated circuit devices have challenged 2nm. However, as the process nodes continue to shrink, Moore's Law is gradually becoming invalid. Silicon-based integrated circuit technology is facing bottlenecks in process cost, physical limits, and yield. Especially with the continuous reduction of device size, the trade-off between power consumption, performance, and cost of traditional silicon-based technology has become more complex and difficult. Therefore, the semiconductor industry urgently needs new materials and processing technologies to promote the continued development of technology. Due to its unique physical properties, two-dimensional materials have become a very promising candidate material in the post-Moore era. They can effectively replace traditional silicon materials and solve many problems in current integrated circuit technology.

[0003] Two-dimensional materials such as molybdenum disulfide (MoS2) have excellent subthreshold swing characteristics and high electron mobility, and therefore have broad application prospects in future electronic devices. However, the traditional dry etching process technology has significant deficiencies in terms of etching depth control, sidewall steepness, and etching rate selectivity. Especially when processing two-dimensional materials, the existing etching methods are difficult to achieve high-precision control, which can easily cause material damage or uneven etching, affecting the final performance of the device. In addition, because the thickness of two-dimensional materials is particularly thin, existing doping technologies often damage the channel, and a new method for doping is needed.

[0004] Therefore, an improved process flow is urgently needed to reduce damage to materials and improve device yield. Summary of the invention

[0005] Purpose of the invention: The purpose of the present invention is to provide a two-dimensional material semiconductor device that can improve the overall performance, yield and reliability of the device;

[0006] The second object of the present invention is to provide a method for preparing the above-mentioned two-dimensional material semiconductor device.

[0007] Technical solution: The two-dimensional semiconductor device described in the present invention includes a substrate, a two-dimensional semiconductor material layer arranged on the substrate and a gate structure arranged on the two-dimensional semiconductor material layer, the gate structure includes a gate dielectric layer and a gate layer above the gate dielectric layer, the gate dielectric layer includes a portion covered by the bottom of the gate layer and a portion not covered by the bottom of the gate layer, the portions not covered by the bottom of the gate layer extend outward along the surface of the two-dimensional semiconductor material layer; the portion of the gate dielectric layer not covered by the bottom of the gate layer and both sides of the gate are covered with side walls; the surface of the side wall is provided with a supporting layer formed of a low dielectric constant material; the supporting layer, the side wall and the top of the gate are flush, and a source-drain metal contact layer is vertically penetrated along the supporting layer, the side wall located on the surface of the gate dielectric layer, the two-dimensional semiconductor material layer and the substrate.

[0008] The method for preparing the two-dimensional semiconductor device comprises the following steps:

[0009] (A) forming a two-dimensional semiconductor material layer on a substrate, depositing metal yttrium on the two-dimensional semiconductor material layer, and annealing in an inert atmosphere to perform yttrium sulfide metallization; after annealing, cleaning the metal yttrium layer and retaining the metal yttrium seed crystal;

[0010] (B) forming a gate dielectric layer on the surface of the two-dimensional semiconductor material layer retaining the metal yttrium seed crystal, and forming a gate layer on the surface of the gate dielectric layer to obtain a gate structure;

[0011] (C) using photolithography to divide the positions of the source and drain electrodes, then etching away the gate layer in the source and drain regions, etching the gate dielectric layer downward to a certain depth, and then forming a sidewall on the exposed surface;

[0012] (D) depositing a low dielectric constant material on the surface of the sidewall to form a support layer for the source and drain metal;

[0013] (E) planarizing the structure obtained in step (D) by CMP and stopping at the gate layer, removing the excess support layer, and exposing the gate layer;

[0014] (F) etching downwardly the unremoved support layer to form a recess, wherein the recess extends into the substrate;

[0015] (G) depositing source and drain metals into the recess to form an ohmic contact with the two-dimensional semiconductor material layer; after the deposition is completed, removing excess metal to expose the gate structure, thereby obtaining the two-dimensional semiconductor device.

[0016] Wherein, in step (A), yttrium metal is deposited by electron beam evaporation in a high vacuum environment, and the deposition thickness of the metal yttrium is 1 to 2 nm.

[0017] In step (A), a mixed gas of argon and hydrogen is used during the annealing process to prevent oxidation and improve the activity of the seed crystal.

[0018] Wherein, in step (A), the annealing temperature is 240-300° C. and the time is 20-40 min.

[0019] Wherein, in step (A), the metal yttrium layer is removed by pickling, and the metal yttrium seed crystals are retained.

[0020] Wherein, in step (A), before depositing metal yttrium, the patterned local contact area is treated with low-power argon soft plasma or electron beam irradiation to modify the surface of the two-dimensional semiconductor material and generate active sites.

[0021] In which, in step (A), the two-dimensional material is MoS2; before depositing metal yttrium, the surface of MoS2 is bombarded with low-power soft plasma to induce sulfur vacancy control on the surface of MoS2, the bombardment time is 5S to 30S, and the concentration is controlled between 5% and 20%.

[0022] Wherein, in step (G), the deposition temperature is 200-250°C.

[0023] Wherein, after step (G), the remaining photoresist or hard mask material is removed and the device is packaged.

[0024] Beneficial effects: Compared with the prior art, the present invention achieves the following significant effects:

[0025] (1) The present invention deposits metal yttrium on a two-dimensional semiconductor material layer, washes away the yttrium seed crystal, uses metal yttrium to dope the source and drain two-dimensional material, and uses metal yttrium as a seed crystal to obtain a high-performance gate structure, which significantly reduces the subthreshold swing and contact resistance of the device, effectively suppresses the short channel effect, and reduces channel defects, thereby significantly improving the overall performance, yield and reliability of the device. (2) The present invention etches vertically along the support layer, the sidewall located on the surface of the gate dielectric layer, the two-dimensional semiconductor layer, and the substrate to form a depression, and the depression extends into the substrate layer. The process effectively protects the channel two-dimensional material and solves the problem of the etching cutoff depth of the two-dimensional material. (3) The process is compatible with existing silicon-based processes and is suitable for large-scale production. Compared with traditional silicon-based field-effect transistors, the present invention can maintain excellent electrical properties at a smaller geometric size, thereby performing well in high-density integrated circuits. (4) The present invention is suitable for field-effect transistors (FETs) based on two-dimensional materials (such as molybdenum disulfide or carbon nanotubes). These devices can be used in high-performance, low-power integrated circuits, flexible electronic devices, sensors, and next-generation computing and communication equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a schematic structural diagram of a two-dimensional semiconductor device of the present invention;

[0027] Figure 2 It is a schematic flow chart of a method for preparing a two-dimensional semiconductor device of the present invention;

[0028] Figure 3 The performance of the two-dimensional semiconductor device of the present invention is compared with that of a two-dimensional semiconductor device obtained without any treatment on the surface of the two-dimensional semiconductor material layer. DETAILED DESCRIPTION

[0029] The present invention is described in further detail below.

[0030] like Figure 1 As shown, the present invention provides a two-dimensional semiconductor device, including a substrate 1, a two-dimensional semiconductor material layer 2 arranged on the substrate 1 and a gate structure arranged on the two-dimensional semiconductor material layer 2, the gate structure including a gate dielectric layer 3 and a gate layer 4 above the gate dielectric layer 3, the gate dielectric layer 3 including a portion covered by the bottom of the gate layer and a portion not covered by the bottom of the gate layer, the portions not covered by the bottom of the gate layer extend outward along the surface of the two-dimensional semiconductor material layer 2 respectively; the portion of the gate dielectric layer 3 not covered by the bottom of the gate and both sides of the gate are covered with side walls 5; the surface of the side wall 5 is provided with a supporting layer 6 formed of a low dielectric constant material; the supporting layer 6, the side wall 5 and the top of the gate are flush, and a source-drain metal contact layer 7 penetrates from top to bottom along the supporting layer 6, the side wall 5 located on the surface of the gate dielectric layer 3, the two-dimensional semiconductor material layer 2, and the substrate 1.

[0031] The method for preparing the above-mentioned two-dimensional semiconductor device, such as Figure 2 As shown, the following steps are included:

[0032] 1. Material stacking and layer structure preparation

[0033] (1) First, a two-dimensional semiconductor material layer 2 is grown on a silicon oxide substrate 1 by a CVD method. The two-dimensional semiconductor material in this embodiment is molybdenum disulfide MoS2, and the thickness can be 1 to 5 nm. The CVD method can also be replaced by PVD, mechanical transfer and other methods;

[0034] (2) Treating the patterned local contact area with low-power argon soft plasma to change the contact interface and generate active sites; this low-power soft plasma filters high-energy particles to induce trace sulfur vacancies on the surface of the top MoS2 without damaging the overall lattice of 2D MoS2; in the experiment, as the bombardment time increases, the concentration of sulfur vacancy defects increases and the crystal structure is gradually destroyed, so it is necessary to reasonably control the concentration of sulfur vacancy defects to achieve optimal doping; the bombardment intensity of this embodiment is 30w, and the bombardment is 20s;

[0035] (3) Depositing yttrium metal Y on the surface of the two-dimensional semiconductor material layer 2 by electron beam evaporation in a high vacuum environment. The deposition thickness of yttrium is maintained between 1 and 2 nanometers, and the deposition rate is 0.3A per second; a mixed gas of argon and hydrogen is used during the annealing process to prevent oxidation and improve the activity of the seed crystal;

[0036] (4) Yttrium sulfide metallization at 240 °C under inert gas to reduce defect formation and ensure the uniformity and quality of the 2D material layer, thereby forming an effective ohmic contact;

[0037] (5) Then, pickling is performed to remove the metal yttrium layer and retain the seed crystal; after the metal yttrium is deposited, the metal yttrium is cleaned with dilute hydrochloric acid; and the contamination on the surface of some channels can be removed at the same time;

[0038] In order to further optimize the deposition of yttrium as a seed, the deposition thickness and uniformity of yttrium can be controlled to ensure the subsequent growth of a high-quality top gate layer. During the annealing process, the temperature and atmosphere are appropriately adjusted to promote the uniform distribution of yttrium, reduce interface defects, and enhance the bonding strength between the top gate and the two-dimensional material. The time for pickling to remove the metal layer also needs to be adjusted according to the thickness of the yttrium deposition.

[0039] 2. Deposit a gate dielectric layer 3 and a metal gate layer 4 to obtain a gate structure:

[0040] (1) With the help of yttrium seed crystal, atomic layer deposition (ALD) technology is used to deposit high dielectric constant material, i.e., High-k material to obtain gate dielectric layer 3, which can reduce defects between the channel and the insulating layer; a precursor, tetraethylcyclopentadienyl hafnium (TEMAH for short), is used in combination with an oxidant, O3, for deposition, and the deposition temperature is controlled at 250°C to achieve atomic-level thickness control, ensure uniform coverage and reduce leakage current; the atomic layer deposition method is a prior art; the precursor can also be replaced by hafnium chloride (HfCl4), and the oxidant can be replaced by H2O.

[0041] (2) A metal gate is deposited on the surface of the gate dielectric layer 3 to form a gate stack dielectric layer, namely, a gate structure.

[0042] 3. Metal gate formation

[0043] The sample is patterned using photolithography to divide the positions of the source and drain. Then, a dry etching process is used to remove the metal gate and part of the gate dielectric layer 3 in the source and drain regions. The gate dielectric layer 3 plays a protective role in this process to prevent the two-dimensional material layer from being damaged. The etching process uses plasma-enhanced reactive ion etching (RIE) technology to control the gas flow and radio frequency power to achieve highly selective etching and reduce damage to the two-dimensional material.

[0044] 4. Spacer layer deposition

[0045] A low dielectric constant material, i.e., a low-k material, is deposited on the exposed surface of the structure obtained in step 3 to form a spacer 5 structure. This step helps to reduce parasitic capacitance and improve the switching speed and electrical performance of the device. The thickness of the deposited low-k material should be controlled within a suitable range to ensure the mechanical strength and electrical isolation effect of the spacer 5.

[0046] 5. Deposition of support layer

[0047] Silicon oxide is deposited on both sides of the source and drain regions to form a support layer 6 for the source and drain metals. This prevents the source and drain metals from collapsing during deposition. The deposition of silicon oxide can be carried out using a chemical vapor deposition (CVD) process with a thickness of 20-30 nanometers to achieve effective isolation without affecting the scalability of the device. Silicon oxide can be replaced with other low dielectric constant materials.

[0048] 6. CMP polishing to metal gate

[0049] The entire structure is flattened using CMP technology to remove the excess support layer 6 to ensure that the source and drain metal areas achieve consistent flatness, thereby improving the accuracy of subsequent deposition processes. During the CMP process, a soft pad is used and the polishing speed is optimized to reduce damage to the sensitive layer, ensure the flattening effect, and improve the manufacturing yield.

[0050] 7. Grooving and source / drain metal deposition

[0051] Using dry etching technology, deep grooves are formed along both sides of the gate and in the isolation layer, that is, the support layer 6, the sidewall 5 located on the surface of the gate dielectric layer 3, the two-dimensional semiconductor layer 2, and the substrate 1 are etched vertically to form grooves for the deposition of the source and drain metals; the grooves are inverted trapezoidal structures. Since the two-dimensional material layer is extremely thin, the etching depth is difficult to control, and the etching is carried out to the substrate 1 layer to achieve edge contact. During the etching process, real-time etching monitoring, such as optical emission spectroscopy OES technology, is used to accurately control the etching depth and reduce the impact of excessive etching on the two-dimensional material, thereby improving the yield of the device.

[0052] 8. Deposit metal to form ohmic contact

[0053] Source and drain metals are deposited in the grooved area to form a good ohmic contact with the two-dimensional material layer. The specific deposition method is a prior art. For example, it can be carried out by physical vapor deposition (PVD) technology, the deposition temperature is controlled at 200-250°C, and the gas flow rate is precisely controlled to ensure the uniformity and density of the metal film. After the metal deposition is completed, the excess metal is removed by photolithography and dry etching to ensure that the metal is retained only in the source and drain areas, reducing parasitic resistance and improving switching performance.

[0054] The material of the source-drain metal contact layer 7 is prior art, specifically, a single layer or multiple layers of metal or metal compound material, such as Ti, Al, TiN, Ta, TaN, TiAl, TiAlN, TiAlSc, AlSc, TiSc, TiPd, AlPd. The stacking combination of materials; its thickness is determined according to the needs of the device.

[0055] 9. Post-processing

[0056] After etching is completed, the remaining photoresist or hard mask material needs to be removed, and oxygen plasma cleaning technology is used to remove the residue. Oxygen plasma can effectively remove organic photoresist residues and ensure the smooth progress of subsequent processes.

[0057] 10. Packaging

[0058] Finally, the device is packaged to ensure its mechanical strength and electrical stability. The packaging material can be silicon oxide or polyimide to ensure the isolation of the device from the environment and provide mechanical support. This step ensures the compatibility of the device with other components in the back-end process and meets the integration requirements of advanced processes.

[0059] like Figure 3 As shown, Figure 3 The "after" represents the two-dimensional material semiconductor field effect transistor obtained by the method of the present invention, and the "befor" represents the two-dimensional material semiconductor field effect transistor obtained by omitting steps (2) to (5) in the above step 1 of the present invention, thereby making the surface of the two-dimensional semiconductor material layer without any treatment. By comparing the two, it can be seen that the subthreshold swing of the two-dimensional material semiconductor field effect transistor of the present invention is significantly improved.

Claims

1. A two-dimensional semiconductor device, comprising a substrate (1), a two-dimensional semiconductor material layer (2) provided on the substrate (1), and a gate structure provided on the two-dimensional semiconductor material layer (2), wherein the gate structure comprises a gate dielectric layer (3) and a gate layer (4) above the gate dielectric layer (3), characterized in that: The gate dielectric layer (3) comprises a portion covered by the bottom of the gate layer (4) and a portion not covered by the bottom of the gate layer (4), and the portions not covered by the bottom of the gate layer (4) extend outward along the surface of the two-dimensional semiconductor material layer (2); the portion of the gate dielectric layer (3) not covered by the bottom of the gate layer (4) and both sides of the gate are covered with side walls (5); the surface of the side wall (5) is provided with a support layer (6) formed of a low dielectric constant material; the support layer (6), the side wall (5) and the top of the gate are flush, and a source-drain metal contact layer (7) penetrates vertically along the support layer (6), the side wall (5) located on the surface of the gate dielectric layer (3), the two-dimensional semiconductor material layer (2) and the substrate (1).

2. A method for preparing a two-dimensional semiconductor device according to claim 1, characterized in that: The following steps are involved: (A) forming a two-dimensional semiconductor material layer (2) on a substrate (1), depositing metal yttrium on the two-dimensional semiconductor material layer (2), and annealing in an inert atmosphere to perform yttrium sulfide metallization; after annealing, cleaning the metal yttrium layer and retaining the metal yttrium seed crystal; (B) forming a gate dielectric layer (3) on the surface of the two-dimensional semiconductor material layer (2) retaining the metal yttrium seed crystal, and forming a gate layer (4) on the surface of the gate dielectric layer (3) to obtain a gate structure; (C) using photolithography to divide the positions of the source and drain, then etching away the gate layer (4) in the source and drain regions, and etching downwards the gate dielectric layer (3) to a certain depth, and then forming a sidewall (5) on the exposed surface; (D) depositing a low dielectric constant material on the surface of the sidewall (5) to form a support layer (6) for the source and drain metal; (E) using CMP to planarize the structure obtained in step (D) and stop at the gate layer (4), removing the excess support layer (6), and exposing the gate layer (4); (F) etching downwards the unremoved support layer (6) to form a recess, wherein the recess extends into the substrate (1); (G) depositing source and drain metals into the recess to form ohmic contacts with the two-dimensional semiconductor material layer (2); After the deposition is completed, the excess metal is removed to expose the gate structure, thereby obtaining the two-dimensional semiconductor device.

3. The method for preparing a two-dimensional semiconductor device according to claim 2, characterized in that: In step (A), yttrium metal is deposited by electron beam evaporation in a high vacuum environment, and the deposition thickness of the metal yttrium is 1 to 2 nm.

4. The method for preparing a two-dimensional semiconductor device according to claim 2, characterized in that: In step (A), a mixed gas of argon and hydrogen is used during the annealing process to prevent oxidation and improve the activity of the seed crystal.

5. The method for preparing a two-dimensional semiconductor device according to claim 2, characterized in that: In step (A), the annealing temperature is 240-300° C. and the time is 20-40 min.

6. The method for preparing a two-dimensional semiconductor device according to claim 2, characterized in that: In step (A), the metal yttrium layer is removed by pickling, and the metal yttrium seed crystals are retained.

7. The method for preparing a two-dimensional semiconductor device according to claim 2, characterized in that: In step (A), before depositing metal yttrium, the patterned local contact area is treated with low-power argon soft plasma or electron beam irradiation to modify the surface of the two-dimensional semiconductor material and generate active sites.

8. The method for preparing a two-dimensional semiconductor device according to claim 2, characterized in that: In step (A), the two-dimensional material is MoS2; before depositing metallic yttrium, the surface of MoS2 is bombarded with low-power soft plasma to induce sulfur vacancy control on the surface of MoS2, the bombardment time is 5S to 30S, and the concentration is controlled between 5% and 20%.

9. The method for preparing a two-dimensional semiconductor device according to claim 2, characterized in that: In step (G), the deposition temperature is 200-250°C.

10. The method for preparing a two-dimensional semiconductor device according to claim 2, characterized in that: After step (G), the remaining photoresist or hard mask material is removed and the device is packaged.

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