Preparation method of intrinsic passivation structure, intrinsic passivation structure and battery

Abstract

The invention discloses a preparation method of an intrinsic passivation structure, the intrinsic passivation structure and a battery, the intrinsic passivation structure comprises a base layer, the surface of which is provided with a first interface layer; the first intrinsic layer is arranged on the first interface layer, and a second interface layer is arranged on the surface of the first intrinsic layer; the second intrinsic layer is arranged on the second interface layer, and a third interface layer is arranged on the surface of the second intrinsic layer; and the doped microcrystalline silicon layer is arranged on the surface of the third interface layer. According to the invention, the surfaces of the base layer, the first intrinsic layer and the second intrinsic layer are treated, so that the contact between the intrinsic amorphous silicon and the crystalline silicon substrate is effectively improved, the generation of nano twin crystals is inhibited, the passivation effect is enhanced, and the minority carrier lifetime is prolonged.

Description

Technical Field

[0001] The present invention relates to the technical field of battery manufacturing, and more specifically, to a preparation method of an intrinsic passivation structure, an intrinsic passivation structure and a battery. Background Art

[0002] Currently, the key to achieving high performance in silicon heterojunction cells lies in the Si-H bonds of the intrinsic amorphous silicon film, which effectively passivates dangling defects on the crystalline silicon surface, reducing the interfacial recombination rate and increasing the cell's open-circuit voltage. Because intrinsic amorphous silicon has poor conductivity and absorbs visible light, only a thin layer (5-10nm) is typically deposited. Within this narrow process window, controlling relevant parameters is crucial to achieve optimal passivation.

[0003] In the existing technology, a stacked process is commonly used to prepare intrinsic amorphous silicon. The buffer layer in contact with the crystalline silicon is deposited via silane plasma. It has a high Si-H2 and Si-H3 content and a loose, porous structure that can inhibit the formation of nanocrystalline crystals. On this basis, a second layer is deposited using a certain mixing ratio of silane and hydrogen. Since hydrogen etching breaks the weaker silicon-hydrogen bonds, it ultimately forms a dense film dominated by Si-H and low in internal defects. However, this route still has unresolved issues, including poor interlayer contact, severe parasitic absorption in the passivation layer, and mismatched conductivity with the doped microcrystalline silicon. Summary of the Invention

[0004] One object of the present invention is to provide a method for preparing an intrinsic passivation structure, a new technical solution for an intrinsic passivation structure and a battery, which can at least solve the problems in the prior art such as poor contact between silicon heterojunction battery layers and interlayer interfaces, severe parasitic absorption of the passivation layer and mismatch with the conductivity of doped microcrystalline silicon.

[0005] The first aspect of the present invention provides an intrinsic passivation structure, comprising: a base layer, a first interface layer being provided on the surface of the base layer; a first intrinsic layer, the first intrinsic layer being provided on the first interface layer, and a second interface layer being provided on the surface of the first intrinsic layer; a second intrinsic layer, the second intrinsic layer being provided on the second interface layer, and a third interface layer being provided on the surface of the second intrinsic layer; and a doped microcrystalline silicon layer, the doped microcrystalline silicon layer being provided on the surface of the third interface layer.

[0006] Optionally, the first interface layer is a crystalline silicon oxide layer, the second interface layer is an amorphous silicon dense layer, and the third interface layer is a microcrystalline silicon oxide layer.

[0007] Optionally, the first intrinsic layer is an amorphous silicon thin film, and the second intrinsic layer is a dense amorphous silicon thin film.

[0008] Optionally, the thickness of the first intrinsic layer is 0.5-3 nm, the thickness of the second intrinsic layer is 2-7 nm, and the thickness of the third interface layer is 0.5-4 nm.

[0009] Optionally, the intrinsic passivation structure further includes: a conductive film layer and an electrode, wherein the conductive film layer is provided on the surface of the doped microcrystalline silicon layer, and the electrode is provided on the conductive film layer.

[0010] A second aspect of the present invention provides a method for preparing an intrinsic passivation structure, which is used to prepare the intrinsic passivation structure described in the above embodiment, and the preparation method comprises:

[0011] Immersing the silicon wafer in a first solution for cleaning to form a first interface layer on the surface of the silicon wafer, wherein the first solution is an oxidizing solution;

[0012] Depositing silicon on the first interface layer to form a first intrinsic layer;

[0013] performing hydrogen plasma etching on the first intrinsic layer to form a second interface layer on a surface of the first intrinsic layer;

[0014] depositing a second intrinsic layer on the second interface layer;

[0015] treating a surface of the second intrinsic layer to form a third interface layer on the surface of the second intrinsic layer;

[0016] Doped microcrystalline silicon is deposited on the third interface layer.

[0017] Optionally, the first solution is a mixed solution of hydrofluoric acid and hydrogen peroxide, and the first interface layer is an oxide layer.

[0018] Optionally, the step of depositing silicon on the first interface layer to form a first intrinsic layer includes:

[0019] sending the cleaned silicon wafer into a deposition device;

[0020] High-purity silane with a flow rate of 100-1200 sccm is introduced to form a hydrogen-rich amorphous silicon film on the surface of the first interface layer; the amorphous silicon film is the first intrinsic layer.

[0021] Optionally, the step of performing hydrogen plasma etching on the first intrinsic layer to form a second interface layer on the surface of the first intrinsic layer includes:

[0022] Plasma deposition is performed in a deposition device using pure hydrogen as hydrogen plasma to form the second interface layer; wherein the flow rate of the pure hydrogen is 500-3000sccm of high-purity hydrogen, the reaction temperature is 170-220°C, the pressure is 0.5-1.8mbar, the RF power is 100-2000W, and the reaction time is 10-45s.

[0023] Optionally, the step of depositing a second intrinsic layer on the second interface layer includes:

[0024] A mixture of silane and hydrogen is passed through a deposition device to form the second intrinsic layer on the second interface layer; wherein the total flow rate of the mixture of silane and hydrogen is 800-3000sccm, the flow ratio of silane to hydrogen is between 3:1-1:20, the reaction temperature is 170-220°C, the pressure is 0.7-2.1mbar, the RF power is 300-1800W, and the reaction time is 10-60s.

[0025] Optionally, the step of processing the surface of the second intrinsic layer to form a third interface layer on the surface of the second intrinsic layer includes:

[0026] Silane, hydrogen and carbon dioxide are introduced into a deposition device to form a microcrystalline silicon oxide layer, which serves as the third interface layer.

[0027] Optionally, the step of introducing silane, hydrogen and carbon dioxide into the deposition equipment to form a microcrystalline silicon oxide layer includes: the total flow rate of silane, hydrogen and carbon dioxide is 2000-20000sccm, the flow ratio of silane to hydrogen is between 1:10-1:200, carbon dioxide occupies 0.1%-2% of the total gas flow rate, the reaction temperature is 170-220°C, the pressure is 1.4-3.2mbar, the RF power is 500-2500W, and the reaction time is 30-120s.

[0028] Optionally, the method for preparing the intrinsic passivation structure further comprises:

[0029] A conductive film and an electrode are deposited on the residual microcrystalline silicon.

[0030] A third aspect of the present invention provides a battery comprising the intrinsic passivation structure described in the above embodiment.

[0031] The intrinsic passivation structure of the present invention effectively improves the contact between the intrinsic amorphous silicon and the crystalline silicon substrate by treating the surfaces of the base layer, the first intrinsic layer, and the second intrinsic layer, inhibits the generation of nanotwins, strengthens the passivation effect, and increases the minority carrier lifetime.

[0032] Further features and advantages of the present invention will become apparent from the following detailed description of exemplary embodiments of the present invention with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0034] Figure 1 is a flowchart of a method for preparing an intrinsic passivation structure according to an embodiment of the present invention;

[0035] Figure 2 is a schematic structural diagram of an intrinsic passivation structure according to an embodiment of the present invention;

[0036] Figure 3 is a scanning electron microscope image of the second interface layer before modification according to an embodiment of the present invention;

[0037] Figure 4 is a scanning electron microscope image of the modified second interface layer according to an embodiment of the present invention;

[0038] Figure 5 is a schematic diagram representing the structural factors of the first intrinsic layer and the second intrinsic layer according to an embodiment of the present invention;

[0039] Figure 6 3 is a schematic diagram of minority carrier lifetime characterization after interface treatment of the intrinsic passivation structure according to an embodiment of the present invention.

[0040] Reference numerals:

[0041] Base layer 11 ; first interface layer 12 ; first intrinsic layer 13 ; second interface layer 14 ; second intrinsic layer 15 ; third interface layer 16 ; doped microcrystalline silicon layer 17 ; conductive thin film layer 18 ; electrode 19 . DETAILED DESCRIPTION

[0042] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that unless otherwise specifically stated, the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present invention.

[0043] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

[0044] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered part of the specification.

[0045] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0046] It should be noted that like reference numerals and letters refer to like items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0047] In the specification and claims of the present invention, references to features using the terms "first" or "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, unless otherwise specified, "plurality" means two or more. Furthermore, in the specification and claims, "and / or" refers to at least one of the connected entities, and the character " / " generally indicates an "or" relationship between the connected entities.

[0048] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0049] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, these terms may refer to fixed, removable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediary; or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in the present invention based on the specific circumstances.

[0050] The following describes in detail the method for preparing the intrinsic passivation structure according to an embodiment of the present invention with reference to the accompanying drawings.

[0051] The intrinsic passivation structure according to the embodiment of the present invention is manufactured using the method for preparing the intrinsic passivation structure in the above embodiment, see Figure 2The intrinsic passivation structure includes a base layer 11, a first intrinsic layer 13, a second intrinsic layer 15 and a doped microcrystalline silicon layer 17. The base layer 11 can be a silicon wafer, and a first interface layer 12 is provided on the surface of the base layer 11. The first intrinsic layer 13 is provided on the first interface layer 12, and a second interface layer 14 is provided on the surface of the first intrinsic layer 13, which improves the substrate environment during the deposition of the second intrinsic layer 15. The second intrinsic layer 15 is provided on the second interface layer 14, and a third interface layer 16 is provided on the surface of the second intrinsic layer 15. The doped microcrystalline silicon layer 17 is provided on the surface of the third interface layer 16, which is conducive to the growth of the doped microcrystalline silicon 17. At the same time, it can effectively reduce the damage to the second intrinsic layer 15 caused by the high-power, high-voltage and high-intensity doped microcrystalline silicon process, and improve the electrochemical performance of the intrinsic passivation structure.

[0052] Therefore, the intrinsic passivation structure of the present invention effectively improves the contact between the intrinsic amorphous silicon and the crystalline silicon substrate by treating the surfaces of the base layer 11, the first intrinsic layer 13, and the second intrinsic layer 15, inhibits the generation of nanotwins, strengthens the passivation effect, and increases the minority carrier lifetime.

[0053] According to one embodiment of the present invention, Figure 2 As shown, the first interface layer 12 is a crystalline silicon oxide layer etched by an oxidizing solution, the second interface layer 14 is an amorphous silicon dense layer etched by hydrogen plasma, and the third interface layer 16 is a microcrystalline silicon oxide layer etched by a mixture of silane, hydrogen, and carbon dioxide.

[0054] Specifically, the base layer 11 can be a silicon wafer, and the surface of the silicon wafer is cleaned by a strong oxidizing mixed solution composed of hydrofluoric acid and hydrogen peroxide, which can effectively remove organic matter, dust and metal impurities remaining on the surface of the silicon wafer, improve the cleaning effect, and form a first interface layer 12 with a natural oxide layer on the surface of the silicon wafer to improve the minority carrier lifetime.

[0055] The surface of the first intrinsic layer 13 is etched with hydrogen plasma to form a second interface layer 14 on the surface of the first intrinsic layer 13. Specifically, plasma deposition can be performed in a deposition device using pure hydrogen as a hydrogen plasma to form the second interface layer 14; wherein the pure hydrogen flow rate is 500-3000 sccm of high-purity hydrogen, the reaction temperature is 170-220°C, the pressure is 0.5-1.8 mbar, the radio frequency power is 100-2000 W, and the reaction time is 10-45 seconds. Using hydrogen plasma to etch the first intrinsic layer 13 breaks weaker silicon-silicon bonds and silicon-hydrogen bonds, allowing subsequent thin film growth to form a dense layer, while also reducing interface defect states and minimizing charge recombination.

[0056] A third interface layer 16 is formed on the surface of the second intrinsic layer 15. During the surface treatment of the second intrinsic layer 15 to form the third interface layer 16, silane, hydrogen, and carbon dioxide can be introduced into the deposition apparatus to form a microcrystalline silicon oxide layer, which serves as the third interface layer 16. By further increasing the hydrogen dilution ratio, increasing the total gas flow rate, and introducing carbon dioxide, the intrinsic microcrystalline silicon oxide layer is deposited, thereby improving the overall conductivity of the passivation structure and reducing the interface contact resistance.

[0057] According to one embodiment of the present invention, the first intrinsic layer 13 is an amorphous silicon thin film deposited using pure silane. The second intrinsic layer 15 is a dense amorphous silicon thin film deposited using a mixture of silane and hydrogen. Specifically, in the present invention, the cleaned silicon wafer can be fed into a deposition device, which can be a PECVD (chemical vapor deposition) device. High-purity silane is introduced at a flow rate of 100-1200 sccm, the chamber temperature is set to 170-220°C, the pressure is controlled at 0.3-1.5 mbar, and the radio frequency power range is 100-2000 W. The process takes 1-60 seconds, and the final layer thickness is distributed in the range of 0.5-3 nm, thereby forming a hydrogen-rich amorphous silicon thin film on the surface of the first interface layer 12. The amorphous silicon thin film is the first intrinsic layer 13. The hydrogen-rich amorphous silicon thin film obtained by introducing pure silane effectively passivates the dangling bonds on the crystalline silicon surface and suppresses the occurrence of epitaxial growth.

[0058] The surface of the first intrinsic layer 13 is etched with hydrogen plasma to form a second interface layer 14 on the surface of the first intrinsic layer 13. Specifically, plasma deposition can be performed in a deposition device using pure hydrogen as a hydrogen plasma to form the second interface layer 14; wherein the pure hydrogen flow rate is 500-3000 sccm of high-purity hydrogen, the reaction temperature is 170-220°C, the pressure is 0.5-1.8 mbar, the radio frequency power is 100-2000 W, and the reaction time is 10-45 seconds. Using hydrogen plasma to etch the first intrinsic layer 13 breaks weaker silicon-silicon bonds and silicon-hydrogen bonds, allowing subsequent thin film growth to form a dense layer, while also reducing interface defect states and minimizing charge recombination.

[0059] The second intrinsic layer 15 is deposited on the second interface layer 14. During the deposition process, a mixture of silane and hydrogen is passed through the deposition equipment to form the second intrinsic layer 15 on the second interface layer 14. The presence of a large amount of hydrogen atoms effectively enhances the passivation effect, resulting in a dense film of good quality, low internal defect density, and improved minority carrier lifetime.

[0060] A third interface layer 16 is formed on the surface of the second intrinsic layer 15. During the surface treatment of the second intrinsic layer 15 to form the third interface layer 16, silane, hydrogen, and carbon dioxide can be introduced into the deposition apparatus to form a microcrystalline silicon oxide layer, which serves as the third interface layer 16. By further increasing the hydrogen dilution ratio, increasing the total gas flow rate, and introducing carbon dioxide, the intrinsic microcrystalline silicon oxide layer is deposited, thereby improving the overall conductivity of the passivation structure and reducing the interface contact resistance.

[0061] In the intrinsic passivation structure of the present invention, a mixed solution of H2O2 and HF is used to improve the effect of cleaning residual metal impurities, and the minority carrier lifetime is increased by more than 200μs. The crystalline silicon surface oxide layer and the hydrogen-rich amorphous silicon film synergistically suppress the formation of nano-luan crystals, thereby enhancing the passivation effect, increasing the open circuit voltage by 2mv, and increasing the minority carrier lifetime by more than 500μs. Hydrogen plasma treatment is added between the layers of the intrinsic passivation structure to improve the quality of the dense layer, and the minority carrier lifetime is further increased by 300μs. The overall conductivity of the passivation layer is improved, which improves charge transport and provides a short-circuit current gain of approximately 0.03A. Ultimately, the efficiency of the battery cell is increased by an average of 0.3-0.4%.

[0062] According to one embodiment of the present invention, the thickness of the first intrinsic layer 13 is 0.5-3 nm, the thickness of the second intrinsic layer 15 is 2-7 nm, and the thickness of the third interface layer 16 is 0.5-4 nm. By properly controlling the thickness of the first intrinsic layer 13, the second intrinsic layer 15, and the third interface layer 16, it is advantageous to perform surface treatment on the first intrinsic layer 13, the second intrinsic layer 15, etc., thereby improving the passivation effect and the minority carrier lifetime.

[0063] According to one embodiment of the present invention, Figure 2 As shown, the intrinsic passivation structure further includes: a conductive film layer 18 and an electrode 19. The conductive film layer 18 is disposed on the surface of the doped microcrystalline silicon layer 17, and the electrode 19 is disposed on the conductive film layer 18. The present invention undergoes interface treatment, and after depositing double-sided intrinsic amorphous silicon, and the subsequent n-doped layer and p-doped layer, the minority carrier lifetime is significantly improved. The double-layer structure composed of the first intrinsic layer 13 and the second intrinsic layer 15 significantly improves the passivation effect on the dangling bonds on the crystalline silicon surface, successfully achieving maximum passivation effect.

[0064] Of course, for those skilled in the art, other structures of the intrinsic passivation structure and its working principles are understandable and achievable, and will not be described in detail in the present invention.

[0065] According to the second aspect of the present invention, Figure 1 As shown, a method for preparing an intrinsic passivation structure is provided, which is used to prepare the intrinsic passivation structure in the above embodiment. The preparation method includes:

[0066] S1, immersing the silicon wafer in a first solution for cleaning to form a first interface layer 12 on the surface of the silicon wafer, wherein the first solution is an oxidizing solution;

[0067] S2, depositing silicon on the first interface layer 12 to form a first intrinsic layer 13;

[0068] S3, performing hydrogen plasma etching on the first intrinsic layer 13 to form a second interface layer 14 on the surface of the first intrinsic layer 13;

[0069] S4, depositing a second intrinsic layer 15 on the second interface layer 14;

[0070] S5, treating the surface of the second intrinsic layer 15 to form a third interface layer 16 on the surface of the second intrinsic layer 15;

[0071] S6 , depositing doped microcrystalline silicon on the third interface layer 16 .

[0072] In other words, if Figure 1 As shown, in the method for preparing an intrinsic passivation structure according to an embodiment of the present invention, a silicon wafer with texturing fillets is first immersed in a first solution for cleaning. The first solution is an oxidizing solution. Under the action of the oxidizing solution, the surface of the silicon wafer is corroded, causing the metal impurities and particles on the surface to fall off. At the same time, a natural oxide layer is formed on the surface of the silicon wafer. This natural oxide layer serves as the first interface layer 12, effectively improving the lifetime of minority carriers.

[0073] Silicon deposition can then be performed on the first interface layer 12 to form a first intrinsic layer 13. Next, the first intrinsic layer 13 can be etched by hydrogen plasma to break weaker silicon-silicon bonds and silicon-hydrogen bonds, allowing subsequent thin film growth to form a dense layer. This also reduces interface defect states and charge recombination, thereby forming a second interface layer 14 on the surface of the first intrinsic layer 13.

[0074] Then, a second intrinsic layer 15 can be deposited on the second interface layer 14. The surface of the second intrinsic layer 15 is treated to form a third interface layer 16 on the surface of the second intrinsic layer 15. Finally, doped microcrystalline silicon can be deposited on the third interface layer 16. By treating the surfaces of the silicon wafer, the first intrinsic layer 13, and the second intrinsic layer 15, the present invention effectively improves the contact between the intrinsic amorphous silicon and the crystalline silicon substrate, inhibits the formation of nanotwins, enhances the passivation effect, and increases the minority carrier lifetime.

[0075] Therefore, the preparation method of the intrinsic passivation structure of the present invention cleans the silicon wafer with a first easy solution having oxidizing properties to remove organic matter, dust, and metal impurities remaining on the surface of the silicon wafer, thereby improving the cleaning effect and forming a first interface layer 12 having a natural oxide layer on the surface of the silicon wafer to improve the minority carrier lifetime. Hydrogen plasma deposition is performed on the first intrinsic layer 13 to form a second interface layer 14 on the surface of the first intrinsic layer 13, thereby breaking the weaker silicon-silicon bonds and silicon-hydrogen bonds, allowing the subsequent thin film to grow into a dense layer, while reducing interface defect states and reducing charge recombination. The present invention effectively improves the contact between the intrinsic amorphous silicon and the crystalline silicon substrate by treating the surfaces of the silicon wafer, the first intrinsic layer 13, and the second intrinsic layer 15, thereby suppressing the generation of nanotwins, strengthening the passivation effect, and improving the minority carrier lifetime.

[0076] According to one embodiment of the present invention, the first solution is a mixture of hydrofluoric acid and hydrogen peroxide, and the first interface layer 12 is an oxide layer. This highly oxidizing mixture of hydrofluoric acid and hydrogen peroxide effectively removes residual organic matter, dust, and metallic impurities on the silicon wafer surface, improving the cleaning effect. It also forms a first interface layer 12 comprising a natural oxide layer on the silicon wafer surface, thereby increasing the minority carrier lifetime.

[0077] According to one embodiment of the present invention, the step of depositing silicon on the first interface layer 12 to form the first intrinsic layer 13 includes:

[0078] The cleaned silicon wafer is fed into the deposition equipment;

[0079] High-purity silane with a flow rate of 100-1200 sccm is introduced to form a hydrogen-rich amorphous silicon film on the surface of the first interface layer 12 ; the amorphous silicon film serves as the first intrinsic layer 13 .

[0080] That is to say, in the process of depositing silicon on the first interface layer 12 to form the first intrinsic layer 13, first, the cleaned silicon wafer can be sent to the deposition equipment, which can be a PECVD (chemical vapor deposition) equipment. High-purity silane with a flow rate of 100-1200sccm is introduced, the chamber temperature is set to 170-220°C, the pressure is controlled at 0.3-1.5mbar, and the RF power range is 100-2000W. The process takes 1-60s, and the final thickness of the layer is distributed in 0.5-3nm, thereby forming a hydrogen-rich amorphous silicon film on the surface of the first interface layer 12, and the amorphous silicon film is the first intrinsic layer 13. Pure silane is introduced to obtain a hydrogen-rich amorphous silicon film, which efficiently passivates the dangling bonds on the surface of the crystalline silicon and suppresses the occurrence of epitaxial growth.

[0081] The coating method adopted in the present invention is VHF-PECVD, which can also be RF-PECVD (radio frequency plasma enhanced chemical vapor deposition) and DC-PECVD (direct current plasma enhanced chemical vapor deposition), or it can be HWCVD (hot wire chemical vapor deposition), LPCVD (low pressure chemical vapor deposition), ECRCVD (electron cyclotron resonance chemical vapor deposition), ETP (expanding thermal plasma deposition), etc.

[0082] According to one embodiment of the present invention, the step of performing hydrogen plasma etching on the first intrinsic layer 13 to form the second interface layer 14 on the surface of the first intrinsic layer 13 includes:

[0083] In the deposition equipment, plasma deposition is performed using pure hydrogen as hydrogen plasma to form the second interface layer 14; wherein the flow rate of pure hydrogen is 500-3000sccm of high-purity hydrogen, the reaction temperature is 170-220°C, the pressure is 0.5-1.8mbar, the RF power is 100-2000W, and the reaction time is 10-45s.

[0084] In other words, during hydrogen plasma etching of the first intrinsic layer 13 to form the second interface layer 14 on the surface of the first intrinsic layer 13, plasma deposition can be performed in a deposition apparatus using pure hydrogen as a hydrogen plasma to form the second interface layer 14. The pure hydrogen gas flow rate is 500-3000 sccm of high-purity hydrogen, the reaction temperature is 170-220°C, the pressure is 0.5-1.8 mbar, the RF power is 100-2000 W, and the reaction time is 10-45 seconds. Using hydrogen plasma to etch the first intrinsic layer 13 breaks weak silicon-silicon bonds and silicon-hydrogen bonds, allowing subsequent thin film growth to form a dense layer. This also reduces interface defect states and minimizes charge recombination.

[0085] According to one embodiment of the present invention, the step of depositing the second intrinsic layer 15 on the second interface layer 14 includes:

[0086] A mixture of silane and hydrogen is passed through the deposition equipment to form a second intrinsic layer 15 on the second interface layer 14; wherein the total flow rate of the mixture of silane and hydrogen is 800-3000 sccm, the flow ratio of silane to hydrogen is between 3:1-1:20, the reaction temperature is 170-220°C, the pressure is 0.7-2.1 mbar, the RF power is 300-1800 W, and the reaction time is 10-60 s.

[0087] That is, during the deposition of the second intrinsic layer 15 on the second interface layer 14, a mixture of silane and hydrogen is passed through the deposition equipment to form the second intrinsic layer 15 on the second interface layer 14. A large number of hydrogen atoms can effectively enhance the passivation effect, resulting in a dense film with good quality, low internal defect density, and improved minority carrier lifetime. The total flow rate of the silane and hydrogen mixture is 800-3000 sccm, the flow ratio of silane to hydrogen is between 3:1-1:20, the reaction temperature is 170-220°C, the pressure is 0.7-2.1 mbar, the RF power is 300-1800 W, the reaction time is 10-60 seconds, and the thickness of the second intrinsic layer 15 is 2-7 nm.

[0088] According to one embodiment of the present invention, the step of processing the surface of the second intrinsic layer 15 to form the third interface layer 16 on the surface of the second intrinsic layer 15 includes:

[0089] Silane, hydrogen and carbon dioxide are introduced into the deposition equipment to form a microcrystalline silicon oxide layer, which serves as the third interface layer 16 .

[0090] That is, during the process of treating the surface of the second intrinsic layer 15 to form the third interface layer 16 on the surface of the second intrinsic layer 15, silane, hydrogen, and carbon dioxide can be introduced into the deposition apparatus to form a microcrystalline silicon oxide layer, which serves as the third interface layer 16. By further increasing the hydrogen dilution ratio, increasing the total gas flow rate, and introducing carbon dioxide, the intrinsic microcrystalline silicon oxide layer is deposited, thereby improving the overall conductivity of the passivation structure and reducing the interface contact resistance.

[0091] Optionally, silane, hydrogen and carbon dioxide are introduced into the deposition equipment to form a microcrystalline silicon oxide layer, including the following steps: the total flow rate of silane, hydrogen and carbon dioxide is 2000-20000sccm, the flow rate ratio of silane to hydrogen is between 1:10-1:200, carbon dioxide accounts for 0.1%-2% of the total gas flow rate, the reaction temperature is 170-220°C, the pressure is 1.4-3.2mbar, the RF power is 500-2500W, the reaction time is 30-120s, and the thickness of the third interface layer 16 is 0.5-4nm.

[0092] According to one embodiment of the present invention, the method for preparing the intrinsic passivation structure further includes:

[0093] A conductive film and an electrode 19 are deposited on the residual microcrystalline silicon.

[0094] Specifically, after the surface of the second intrinsic layer 15 is treated to form a third interface layer 16 on the surface of the second intrinsic layer 15, it can be transferred to another PECVD device and coated with 10-30nm of n-type microcrystalline silicon on the front side. After turning over, it is transferred to the next PECVD device and coated with 15-40nm of p-type microcrystalline silicon on the back side. Then, TCO thin film deposition is carried out, using an ITO target with an In2O3 / SnO2 mass ratio of 97:3 on the front side and an ITO with an In2O3 / SnO2 mass ratio of 90:10 on the back side. The chamber temperature is set to 25-200°C, the sputtering pressure is controlled at 0.1-0.5Pa, the sputtering power range is 2-6KW, and high-purity argon and oxygen are introduced, of which oxygen accounts for 2%-8%. The pre-sputtering time is 30s, and the carrier speed is adjusted to make the thickness distribution between 70-150nm.

[0095] Next, a thermal annealing process is performed, where the coated silicon wafer is placed in air, nitrogen, or a vacuum environment for annealing at a temperature of 150-200°C for 30-60 minutes. After annealing, a photovoltaic paste is screen-printed onto the TCO surface, dried, and sintered to form the electrodes 19 of the solar cell.

[0096] Next, light injection is performed, using laser light dozens of times brighter than sunlight to cause weak hydrogen atoms to jump or diffuse, reactivating the dopant atoms and increasing the conductivity of the doped layer. Finally, testing and sorting are performed, using an IV test system to measure the photoelectric conversion efficiency and electrical performance parameters. The solar cells are then graded and sorted based on the test results.

[0097] The oxygen doping source used in the present invention is carbon dioxide, and may also be oxygen, ozone, nitrous oxide, etc.

[0098] Since Si-H2 and Si-H bonds have different stretching vibration absorption, they can be analyzed by infrared spectroscopy. -1 and 2100cm -1 The two expansion modes are separated to obtain the Si-H2 and Si-H ratios in the film layer, and then the corresponding hydrogen content and structure factor (R*) are calculated. The structure factor is defined as:

[0099]

[0100] like Figure 5 As shown, the calculation results show that the structure factors of the modified first intrinsic layer 13 and the second intrinsic layer 15 are 0.50 and 0.27 respectively. The Si-H2 content of the first layer is higher, which is conducive to forming a loose and porous structure and inhibiting the generation of nano-Luan crystals.

[0101] like Figure 3 and Figure 4 As shown, after hydrogen plasma treatment, lines appear on the second intrinsic layer 15, the roughness increases, and the film thickness increases from 23.5nm to 25nm (test process). It can be considered that after hydrogen combines with dangling bonds, the film layer grows.

[0102] like Figure 6 As shown, after interface treatment, deposition of double-sided intrinsic amorphous silicon, and subsequent n-doped and p-doped layers, the minority carrier lifetime is significantly improved. The double-layer structure composed of the first intrinsic layer 13 and the second intrinsic layer 15 significantly improves the passivation effect on the dangling bonds on the crystalline silicon surface, successfully achieving maximum passivation effect. As shown in Table 1, Table 1 shows the improvement effect of battery efficiency:

[0103] Table 1 Cell efficiency improvement effect

[0104]

[0105] In the preparation method of the intrinsic passivation structure of the present invention, H2O2 improves the effectiveness of cleaning residual metal impurities, and the minority carrier lifetime is increased by more than 200μs. The crystalline silicon surface oxide layer and the hydrogen-rich amorphous silicon film synergistically suppress the formation of nano-crystals, enhancing the passivation effect, increasing the open-circuit voltage by 2mV, and increasing the minority carrier lifetime by more than 500μs. Hydrogen plasma treatment is added between the layers of the intrinsic passivation structure to improve the quality of the dense layer, and the minority carrier lifetime is further increased by 300μs. The overall conductivity of the passivation layer is improved, improving charge transport and providing a short-circuit current gain of approximately 0.03A. Ultimately, the efficiency of the battery cell is increased by an average of 0.3-0.4%.

[0106] According to a third aspect of the present invention, a battery is provided, comprising the intrinsic passivation structure of the above-described embodiment. The carrier of the battery of the present invention may be a plate or a tube. Since the intrinsic passivation structure according to the present invention has the above-described technical effects, the battery according to the embodiment of the present invention should also have the corresponding technical effects. That is, by adopting the intrinsic passivation structure, the battery of the present invention ensures that the overall conductivity of the passivation layer is improved, improves charge transport, provides a short-circuit current gain of approximately 0.03A, and ultimately increases the battery cell efficiency by an average of 0.3-0.4%.

[0107] Of course, for those skilled in the art, other structures of the battery and their working principles are understandable and achievable, and will not be described in detail in the present invention.

[0108] Although some specific embodiments of the present invention have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It should be understood by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. An intrinsic passivation structure, characterized in that: include: A base layer, wherein a first interface layer is disposed on the surface of the base layer; a first intrinsic layer, wherein the first intrinsic layer is disposed on the first interface layer, and a second interface layer is disposed on a surface of the first intrinsic layer; a second intrinsic layer, wherein the second intrinsic layer is disposed on the second interface layer, and a third interface layer is disposed on a surface of the second intrinsic layer; A doped microcrystalline silicon layer is disposed on the surface of the third interface layer.

2. The intrinsic passivation structure according to claim 1, characterized in that: The first interface layer is a crystalline silicon oxide layer, the second interface layer is an amorphous silicon dense layer, and the third interface layer is a microcrystalline silicon oxide layer.

3. The intrinsic passivation structure according to claim 1, characterized in that: The first intrinsic layer is an amorphous silicon thin film, and the second intrinsic layer is an amorphous silicon dense thin film.

4. The intrinsic passivation structure according to claim 1, characterized in that: The thickness of the first intrinsic layer is 0.5-3 nm, the thickness of the second intrinsic layer is 2-7 nm, and the thickness of the third interface layer is 0.5-4 nm.

5. The intrinsic passivation structure according to claim 1, characterized in that: Also includes: A conductive film layer and an electrode, wherein the conductive film layer is arranged on the surface of the doped microcrystalline silicon layer, and the electrode is arranged on the conductive film layer.

6. A method for preparing an intrinsic passivation structure, for preparing the intrinsic passivation structure according to any one of claims 1 to 5, characterized in that: The preparation method comprises: Immersing the silicon wafer in a first solution for cleaning to form a first interface layer on the surface of the silicon wafer, wherein the first solution is an oxidizing solution; Depositing silicon on the first interface layer to form a first intrinsic layer; Performing hydrogen plasma etching on the first intrinsic layer to form a second interface layer on the surface of the first intrinsic layer; depositing a second intrinsic layer on the second interface layer; Processing the surface of the second intrinsic layer to form a third interface layer on the surface of the second intrinsic layer; Doped microcrystalline silicon is deposited on the third interface layer.

7. The method for preparing an intrinsic passivation structure according to claim 6, characterized in that: The first solution is a mixed solution of hydrofluoric acid and hydrogen peroxide, and the first interface layer is an oxide layer.

8. The method for preparing an intrinsic passivation structure according to claim 6, characterized in that: The step of depositing silicon on the first interface layer to form a first intrinsic layer comprises: Sending the cleaned silicon wafer into a deposition device; High-purity silane with a flow rate of 100-1200 sccm is introduced to form a hydrogen-rich amorphous silicon film on the surface of the first interface layer; the amorphous silicon film is the first intrinsic layer.

9. The method for preparing an intrinsic passivation structure according to claim 6, characterized in that: The step of performing hydrogen plasma etching on the first intrinsic layer to form a second interface layer on the surface of the first intrinsic layer includes: In a deposition device, pure hydrogen gas is used as hydrogen plasma to perform plasma deposition to form the Second interface layer ; Wherein, the flow rate of pure hydrogen is 500-3000sccm of high-purity hydrogen, the reaction temperature is 170-220°C, the pressure is 0.5-1.8mbar, the RF power is 100-2000W, and the reaction time is 10-45s.

10. The method for preparing an intrinsic passivation structure according to claim 6, characterized in that: The step of depositing a second intrinsic layer on the second interface layer comprises: A mixture of silane and hydrogen is passed through a deposition device to form the second intrinsic layer on the second interface layer; wherein the total flow rate of the mixture of silane and hydrogen is 800-3000sccm, the flow rate ratio of silane to hydrogen is between 3:1-1:20, the reaction temperature is 170-220°C, the pressure is 0.7-2.1mbar, the RF power is 300-1800W, and the reaction time is 10-60s.

11. The method for preparing an intrinsic passivation structure according to claim 6, characterized in that: The step of processing the surface of the second intrinsic layer to form a third interface layer on the surface of the second intrinsic layer includes: Silane, hydrogen and carbon dioxide are introduced into the deposition equipment to form a microcrystalline silicon oxide layer, and the microcrystalline silicon oxide layer is the third interface layer.

12. The method for preparing an intrinsic passivation structure according to claim 11, characterized in that: The steps of introducing silane, hydrogen and carbon dioxide into a deposition device to form a microcrystalline silicon oxide layer include: The total flow rate of silane, hydrogen and carbon dioxide is 2000-20000sccm, the flow ratio of silane to hydrogen is between 1:10-1:200, carbon dioxide accounts for 0.1%-2% of the total gas flow rate, the reaction temperature is 170-220°C, the pressure is 1.4-3.2mbar, the RF power is 500-2500W, and the reaction time is 30-120s.

13. The method for preparing an intrinsic passivation structure according to claim 6, characterized in that: Also includes: A conductive film and an electrode are deposited on the residual microcrystalline silicon.

14. A battery, characterized in that: The invention comprises the intrinsic passivation structure according to any one of claims 1 to 5.

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