Semiconductor structure and forming method thereof

Abstract

The embodiment of the invention discloses a semiconductor structure and a forming method thereof. The semiconductor structure comprises a semiconductor substrate, a stacking structure and a bit line structure. The stack structure and the bit line structure are located on the semiconductor substrate. The stacked structure comprises separation layers and composite layers which are alternately stacked in the vertical direction. The bit line structure extends in the vertical direction and penetrates through the stacking structure. The semiconductor substrate comprises an array region and a peripheral region; the stacked structure located in the peripheral area comprises a capacitor area. A row of bit line structures are respectively formed outside two opposite sides of the capacitor area along the first direction. Wherein the composite layer of the capacitor region comprises a first polar plate. The first polar plates are distributed on the two opposite sides of the composite layer of the capacitor area at intervals in the first direction and protrude outwards. Each first polar plate is connected to a corresponding bit line structure.

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, a semiconductor structure and a method for forming the same. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor device commonly used in electronic devices such as computers. DRAM chips are divided into an array area and a peripheral area. The array area includes a memory cell array for storing data, and the peripheral area includes peripheral circuits located outside the memory cell array.

[0003] The capacitor in the peripheral area is usually called NICAP. NICAP needs a large capacity to be used as a power source or for signal processing in the peripheral area. However, in the prior art, the structure of NICAP is relatively complex and the process cost is high, which needs to be further optimized. Summary of the invention

[0004] In view of this, the embodiments of the present disclosure provide a semiconductor structure and a method for forming the same, which can save costs and improve performance.

[0005] The technical solution of the embodiment of the present disclosure is implemented as follows:

[0006] An embodiment of the present disclosure provides a semiconductor structure, which includes: a semiconductor substrate, a stacking structure and a bit line structure; the stacking structure and the bit line structure are located on the semiconductor substrate; the semiconductor substrate includes: an array area and a peripheral area; the stacking structure includes: separation layers and composite layers alternately stacked along a vertical direction; the bit line structure extends along the vertical direction and penetrates the stacking structure; the stacking structure located in the peripheral area includes: a capacitor area; a row of the bit line structures are respectively formed outside the two opposite sides of the capacitor area along a first direction; wherein the composite layer of the capacitor area includes: a first electrode plate; the first electrode plates are spaced apart and distributed on the two opposite sides of the composite layer of the capacitor area along the first direction, and protrude outward; each of the first electrode plates is connected to the corresponding bit line structure.

[0007] In some embodiments of the present disclosure, the composite layer of the capacitor region further includes: a dielectric layer and a second electrode plate; the second electrode plate is located on the inner side of the composite layer of the capacitor region; the dielectric layer is located between the first electrode plate and the second electrode plate; the inner side of the second electrode plate is filled with semiconductor material.

[0008] In some embodiments of the present disclosure, the composite layer of the capacitor region further includes: a contact plug; the contact plug is located between the first electrode plate and the bit line structure; each first electrode plate is connected to the corresponding bit line structure through the contact plug.

[0009] In some embodiments of the present disclosure, the stacked structure located in the array area includes: a storage cell area; array-arranged storage cells are arranged in the storage cell area; a bit line structure is formed between two storage cells opposite to each other along the first direction; two storage cells are connected to a corresponding bit line structure; the capacitor area and the storage cell area are both formed based on the first mask.

[0010] In some embodiments of the present disclosure, the semiconductor structure further includes: a back-end connection structure; the back-end connection structure extends along the vertical direction; and the back-end connection structure is located above the capacitor region and above the bit line structure.

[0011] The embodiment of the present disclosure also provides a method for forming a semiconductor structure, the method comprising: providing a semiconductor substrate; the semiconductor substrate comprising: an array area and a peripheral area; forming a stacking structure on the semiconductor substrate; the stacking structure comprising: separation layers and composite layers alternately stacked along a vertical direction; based on a first mask, forming a bit line structure in the stacking structure, and forming a capacitor area in the peripheral area; wherein the bit line structure extends along the vertical direction and runs through the stacking structure; a row of the bit line structures is formed outside the two opposite sides of the capacitor area along the first direction; the composite layer of the capacitor area comprises: a first electrode plate; the first electrode plates are spaced apart and distributed on the two opposite sides of the composite layer of the capacitor area along the first direction, and protrude outward; each of the first electrode plates is connected to the corresponding bit line structure.

[0012] In some embodiments of the present disclosure, the method for forming the bit line structure and the capacitor area includes: based on the first mask, forming a first cavity and a bit line hole in the stacked structure; the first cavity and the bit line hole both penetrate the stacked structure along the vertical direction; a row of the bit line holes are formed outside the two opposite sides of the first cavity along the first direction; protruding grooves distributed at intervals are formed at the intersection of the two opposite sides of the first cavity along the first direction and the composite layer; filling the first cavity and the bit line hole with sacrificial material; removing the sacrificial material in the bit line hole to form the bit line structure in the bit line hole; removing the sacrificial material in the first cavity to form the capacitor area in the first cavity; wherein the first electrode is formed in the protruding groove.

[0013] In some embodiments of the present disclosure, the capacitor region is formed in the first cavity, including: depositing a first conductive layer on the inner wall of the first cavity; etching in the first cavity to partially remove the first conductive layer, retaining and exposing the first conductive layer in the protruding groove to form the first electrode plate; depositing a dielectric layer on the inner wall of the first cavity; depositing a second conductive layer covering the dielectric layer on the inner wall of the first cavity to form a second electrode plate; and filling the first cavity with a semiconductor material.

[0014] In some embodiments of the present disclosure, etching is performed in the first cavity to partially remove the first conductive layer, retaining and exposing the first conductive layer in the protruding groove, including: filling the protruding groove with a sacrificial material; etching is performed in the first cavity to partially remove the first conductive layer, retaining the first conductive layer in the protruding groove; and expanding the size of the first cavity along the first direction to expose the first conductive layer in the protruding groove and remove the sacrificial material in the protruding groove.

[0015] In some embodiments of the present disclosure, after forming the bit line structure and the capacitor region, the method further includes: forming a back-end connection structure extending along the vertical direction above the capacitor region and above the bit line structure.

[0016] It can be understood that the first electrode plate protrudes outward, so that it is convenient to connect with the bit line structure located outside, thereby facilitating the processing and manufacturing of the semiconductor structure. At the same time, the first electrode plate protrudes outward to form a curved electrode shape, so that the area between the electrodes can be increased, thereby increasing the capacity of the capacitor NICAP. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure Figure 1 ;

[0018] Figure 2 A schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure Figure 2 ;

[0019] Figure 3A A schematic diagram of a method for forming a semiconductor structure according to an embodiment of the present disclosure Figure 1 ;

[0020] Figure 3B A schematic diagram of a method for forming a semiconductor structure according to an embodiment of the present disclosure Figure 2 ;

[0021] Figure 3C Structural schematic diagram 3 of the method for forming a semiconductor structure provided by an embodiment of the present disclosure;

[0022] Figure 4A Structural schematic diagram 4 of the method for forming a semiconductor structure provided by an embodiment of the present disclosure;

[0023] Figure 4B Structural schematic diagram 5 of a method for forming a semiconductor structure provided by an embodiment of the present disclosure;

[0024] Figure 4C Structural schematic diagram 6 of a method for forming a semiconductor structure provided in an embodiment of the present disclosure;

[0025] Figure 5A Structural schematic diagram 7 of a method for forming a semiconductor structure provided by an embodiment of the present disclosure;

[0026] Figure 5B Structural schematic diagram 8 of a method for forming a semiconductor structure provided by an embodiment of the present disclosure;

[0027] Figure 5C Structural schematic diagram 9 of a method for forming a semiconductor structure provided by an embodiment of the present disclosure;

[0028] Fig. 6A Structural schematic diagram 10 of a method for forming a semiconductor structure provided by an embodiment of the present disclosure;

[0029] Figure 6B A structural schematic diagram eleven of a method for forming a semiconductor structure provided by an embodiment of the present disclosure;

[0030] Figure 6C A structural schematic diagram 12 of a method for forming a semiconductor structure provided by an embodiment of the present disclosure;

[0031] Fig. 7A 13. Structural schematic diagram of a method for forming a semiconductor structure provided by an embodiment of the present disclosure;

[0032] Figure 7B Structural schematic diagram 14 of a method for forming a semiconductor structure provided by an embodiment of the present disclosure;

[0033] Figure 7C A structural schematic diagram 15 of a method for forming a semiconductor structure provided by an embodiment of the present disclosure;

[0034] Fig. 8A Structural schematic diagram 16 of a method for forming a semiconductor structure provided by an embodiment of the present disclosure;

[0035] Figure 8B Structural schematic diagram 17 of a method for forming a semiconductor structure provided by an embodiment of the present disclosure;

[0036] Figure 8CStructural schematic diagram 18 of a method for forming a semiconductor structure provided by an embodiment of the present disclosure;

[0037] Fig.9A Structural schematic diagram 19 of a method for forming a semiconductor structure provided by an embodiment of the present disclosure;

[0038] Fig. 9B A schematic diagram of a method for forming a semiconductor structure according to an embodiment of the present disclosure Figure 2 ten;

[0039] Fig. 9C A schematic diagram of a method for forming a semiconductor structure according to an embodiment of the present disclosure Figure 2 eleven;

[0040] Fig. 10A A schematic diagram of a method for forming a semiconductor structure according to an embodiment of the present disclosure Figure 2 twelve;

[0041] Fig. 10B A schematic diagram of a method for forming a semiconductor structure according to an embodiment of the present disclosure Figure 2 Thirteen;

[0042] Fig. 10C A schematic diagram of a method for forming a semiconductor structure according to an embodiment of the present disclosure Figure 2 fourteen;

[0043] Fig.11A A schematic diagram of a method for forming a semiconductor structure according to an embodiment of the present disclosure Figure 2 fifteen;

[0044] Fig. 11B A schematic diagram of a method for forming a semiconductor structure according to an embodiment of the present disclosure Figure 2 sixteen;

[0045] Fig. 11C A schematic diagram of a method for forming a semiconductor structure according to an embodiment of the present disclosure Figure 2 XVII;

[0046] Fig. 12A A schematic diagram of a method for forming a semiconductor structure according to an embodiment of the present disclosure Figure 2 eighteen;

[0047] Fig. 12B A schematic diagram of a method for forming a semiconductor structure according to an embodiment of the present disclosure Figure 2 nineteen;

[0048] Fig. 12C Structural schematic diagram 30 of the method for forming a semiconductor structure provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0049] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further elaborated in detail below in conjunction with the drawings and embodiments. The described embodiments should not be regarded as limiting the present disclosure. All other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present disclosure.

[0050] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0051] If similar descriptions of "first / second" appear in the application documents, the following description is added. In the following description, the terms "first / second / third" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It is understandable that "first / second / third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0052] In this document, when a layer / element is referred to as being "on" another layer / element, the layer / element can be directly on the other layer / element or there can be an intervening layer / element between them. In addition, if a layer / element is "on" another layer / element in one orientation, it may be "under" the other layer / element when the orientation is reversed.

[0053] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0054] It should be noted that Figure 1 and Figure 2 A schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure, wherein: Figure 1 and Figure 2 All of them are structural schematic diagrams from a three-dimensional perspective.

[0055] Figure 3A , Figure 3B and Figure 3C Until Fig. 12A , Fig. 12B and Fig. 12C, are all structural schematic diagrams of various steps in the method for forming a semiconductor structure provided by an embodiment of the present disclosure; wherein the schematic diagram numbered A is a structural schematic diagram of a three-dimensional perspective, the schematic diagram numbered B is a cross-sectional structural schematic diagram along the cutting line A-A1 direction in the schematic diagram numbered A, and the schematic diagram numbered C is a cross-sectional structural schematic diagram along the cutting line B-B1 direction in the schematic diagram numbered A. In addition, for the convenience of explanation, in the schematic diagram numbered A, the internal structure is cut open; in practice, the cut open position is filled with a corresponding structure.

[0056] The present disclosure provides a semiconductor structure, such as Figure 1 As shown, it includes: a semiconductor substrate 10 , a stack structure 20 and a bit line structure 30 .

[0057] In the embodiments of the present disclosure, reference Figure 1 , the stacking structure 20 and the bit line structure 30 are located on the semiconductor substrate 10. The stacking structure 20 includes: a separation layer and a composite layer alternately stacked along the vertical direction Z; wherein the composite layer forms a device and a circuit structure, and the separation layer is used to separate each composite layer. The bit line structure 30 extends along the vertical direction Z and penetrates the stacking structure 20. In this way, a 3D (three-dimensional) semiconductor structure is formed, thereby improving integration, enhancing performance, and reducing costs.

[0058] In the embodiment of the present disclosure, the semiconductor substrate 10 includes an array region and a peripheral region; wherein the array region includes a memory cell array for storing data, and the peripheral region includes a peripheral circuit located outside the memory cell array. The stacked structure 20 located in the peripheral region includes a capacitor region 40, and the capacitor region 40 is used to form a capacitor NICAP in the peripheral region. Figure 1 The area shown at the center of FIG. 1 is the capacitor region 40 .

[0059] It should be noted that in a memory chip (such as a DRAM chip), the capacitor NICAP in the peripheral area is used as a decoupling capacitor, and its main function is to provide a stable power supply, reduce power supply noise, and protect the chip from high-frequency electromagnetic interference. On the one hand, the decoupling capacitor can be set at the power supply end as a local source for providing transient current to maintain the stability of the power supply voltage; on the other hand, the decoupling capacitor can also bypass high-frequency noise and reduce high-frequency electromagnetic interference.

[0060] In the embodiments of the present disclosure, reference Figure 1 A row of bit line structures 30 is formed outside two opposite sides of the capacitor region 40 along the first direction X. The first direction X is located in a horizontal plane perpendicular to the vertical direction Z, that is, the first direction X is perpendicular to the vertical direction Z.

[0061] Continue to refer Figure 1The composite layer of the capacitor region 40 includes: first electrodes 41. The first electrodes 41 are spaced apart and distributed on two opposite sides of the composite layer of the capacitor region 40 along the first direction X, wherein adjacent first electrodes 41 are not directly connected.

[0062] Continue to refer Figure 1 Each first electrode plate 41 protrudes toward the outside of the capacitor region 40 , that is, each first electrode plate 41 protrudes toward the corresponding bit line structure 30 and is connected to the corresponding bit line structure 30 .

[0063] It can be understood that the first electrode plate 41 protrudes outward, so that it is convenient to connect with the bit line structure 30 located outside, thereby facilitating the processing and manufacturing of the semiconductor structure. At the same time, the first electrode plate 41 protrudes outward to form a curved electrode shape, so that the area between the electrodes can be increased, thereby increasing the capacity of the capacitor NICAP.

[0064] In some embodiments of the present disclosure, reference Figure 1 The composite layer of the capacitor region 40 further includes: a dielectric layer 43 and a second electrode plate 42. The second electrode plate 42 is located inside the composite layer of the capacitor region 40. The dielectric layer 43 is located between the first electrode plate and the second electrode plate.

[0065] The inner side of the second electrode plate 42 is filled with semiconductor material, which can play a supporting and isolating role. The semiconductor material may include polycrystalline silicon.

[0066] In the embodiment of the present disclosure, in the composite layer of each capacitor region 40, the second electrode plate 42 is an integral electrode plate, that is, the same second electrode plate 42 and multiple first electrodes 41 form a capacitor. In this way, it is equivalent to connecting multiple capacitors in parallel, so that a capacitor with a larger capacity can be realized.

[0067] At the same time, in the composite layer of each capacitor region 40, the second electrode plate 42 is located inside to form a closed structure, which can effectively reduce the size of the capacitor, thereby facilitating the improvement of integration.

[0068] In the embodiments of the present disclosure, reference Figure 1 The surface of the bit line structure 30 along the vertical direction Z is wavy, wherein the bit line structure 30 protrudes outward at the position connected with the contact structure (congtact). In this way, on the one hand, the contact area with the contact structure can be increased, thereby reducing the contact resistance; on the other hand, the cross-sectional area of ​​the bit line structure 30 is enlarged, thereby reducing the resistance of the bit line structure 30.

[0069] In the embodiments of the present disclosure, reference Figure 1The bit line structure 30 may be formed of one or more layers of conductive material, wherein the conductive material may include one or more of titanium (Ti), titanium nitride (TiN) and tungsten (W). The etching selectivity ratio between the conductive material and the dielectric material of the bit line structure 30 has a large difference, so that the conductive material can be selectively etched to form the bit line structure 30; wherein the dielectric material may be silicon nitride (SiN) or silicon oxide (SiO).

[0070] In the embodiments of the present disclosure, reference Figure 1 The materials of the first electrode plate 41 and the second electrode plate 42 may include titanium (Ti) and / or titanium nitride (TiN). The material of the dielectric layer 43 may include a high-k material. The use of the high-k material may increase the capacitance of the capacitor.

[0071] In some embodiments of the present disclosure, reference Figure 1 The composite layer of the capacitor region 40 further includes a contact plug 44. The contact plug 44 is located between the first electrode plate 41 and the bit line structure 30. Each first electrode plate 41 is connected to the corresponding bit line structure 30 through the contact plug 44.

[0072] It is understandable that the contact plug 44 can establish a good electrical connection between the first electrode plate 41 and the bit line structure 30 to avoid a circuit break due to poor contact. Wherein, at the connection position between the contact plug 44 and the bit line structure 30, the bit line structure 30 protrudes outward, thereby increasing the contact area and reducing the contact resistance.

[0073] In some embodiments of the present disclosure, Figure 2 As shown, the stacked structure in the array area includes a storage unit area 50. The storage unit area 50 is provided with storage units 51 arranged in an array.

[0074] In the embodiments of the present disclosure, reference Figure 2 A bit line structure 30 is formed between two memory cells 51 that are opposite to each other along the first direction X, and the two memory cells 51 are connected to a corresponding bit line structure 30 (ie, the bit line structure 30 between the two memory cells 51 ).

[0075] In the embodiments of the present disclosure, reference Figure 2 , an isolation structure 60 may be formed on a side of the memory cell 51 away from the bit line structure 30. The isolation structure 60 penetrates the stacked structure and extends along the second direction Y. Figure 2 In the figure, the dielectric material filled in the isolation structure 60 is not shown, and it is shown as a cavity. The second direction Y is located in a horizontal plane perpendicular to the vertical direction Z, that is, the second direction Y is perpendicular to the vertical direction Z. At the same time, the first direction X intersects with the second direction Y, and the angle is not limited.

[0076] In some embodiments of the present disclosure, Figure 1 and Figure 2 The capacitor region 40 and the memory cell region 50 are both formed based on the first photomask.

[0077] exist Figure 2 In FIG. 1 , the horizontal projection of the memory cell 51 and the isolation structure 60 between the two rows of bit line structures 30 is Figure 1 The projection of the capacitor area 40 on the horizontal plane is consistent; at the same time, Figure 2 The memory cell 51 shown may be a capacitor in the memory cell, and the capacitor in the memory cell and the capacitor in the peripheral region (i.e., the capacitor region 40) are formed in the same layer. Therefore, the same photomask may be used to form the capacitor region 40 and the memory cell region 50, thus reducing the number of photomasks required and saving costs.

[0078] In some embodiments of the present disclosure, reference Figure 2 The semiconductor structure further includes a word line structure 70 . The word line structure 70 extends along the second direction Y and is located between the memory cell 51 and the bit line structure 30 .

[0079] In some embodiments of the present disclosure, reference Fig. 12A , Fig. 12B and Fig. 12C The semiconductor structure further includes a back-end interconnect 80. The back-end interconnect 80 extends along a vertical direction Z. The back-end interconnect 80 is located above the capacitor region 40 and above the bit line structure 30. The material of the back-end interconnect 80 includes a metal material, such as tungsten (W).

[0080] The embodiment of the present disclosure further provides a method for forming a semiconductor structure, including steps S101 to S103.

[0081] S101 , providing a semiconductor substrate 10 .

[0082] In the embodiments of the present disclosure, reference Figure 1 The semiconductor substrate 10 is divided into an array area and a peripheral area. The array area can be used to form a memory cell array to store data, and the peripheral area can be used to form a peripheral circuit located outside the memory cell array.

[0083] S102 , forming a stacked structure 20 on the semiconductor substrate 10 .

[0084] In the embodiments of the present disclosure, reference Figure 1The stacked structure 20 includes: a separation layer and a composite layer alternately stacked in a vertical direction. The composite layer forms a device and a circuit structure, and the separation layer is used to separate each composite layer. Through the stacked structure 20, a 3D semiconductor structure can be formed, thereby improving integration, enhancing performance, and reducing costs.

[0085] In the embodiments of the present disclosure, reference Figure 1 The stacked structure 20 can be generated layer by layer through an epitaxial growth process; the stacked structure 20 can also be generated by alternately stacking ONO (silicon oxide-silicon nitride-silicon oxide).

[0086] S103 , based on the first photomask, forming a bit line structure 30 in the stacked structure 20 , and forming a capacitor region 40 in the peripheral region.

[0087] refer to Figure 1 The bit line structure 30 extends along the vertical direction Z and penetrates the stack structure 20. A row of bit line structures 30 is formed outside two opposite sides of the capacitor region 40 along the first direction X.

[0088] Continue to refer Figure 1 The composite layer of the capacitor region 40 includes: first electrodes 41. The first electrodes 41 are spaced apart and distributed on two opposite sides of the composite layer of the capacitor region 40 along the first direction X, wherein adjacent first electrodes 41 are not directly connected.

[0089] Continue to refer Figure 1 Each first electrode plate 41 protrudes toward the outside of the capacitor region 40 , that is, each first electrode plate 41 protrudes toward the corresponding bit line structure 30 and is connected to the corresponding bit line structure 30 .

[0090] It can be understood that the first electrode plate 41 protrudes outward, so that it is convenient to connect with the bit line structure 30 located outside, thereby facilitating the processing and manufacturing of the semiconductor structure. At the same time, the first electrode plate 41 protrudes outward to form a curved electrode shape, so that the area between the electrodes can be increased, thereby increasing the capacity of the capacitor NICAP.

[0091] In some embodiments of the present disclosure, Figure 1 and Figure 2 Based on the first photomask, a memory cell region 50 of the array region can also be formed.

[0092] exist Figure 2 In FIG. 1 , the horizontal projection of the memory cell 51 and the isolation structure 60 between the two rows of bit line structures 30 is Figure 1 The projection of the capacitor area 40 on the horizontal plane is consistent; at the same time, Figure 2The memory cell 51 shown may be a capacitor in the memory cell, and the capacitor in the memory cell and the capacitor in the peripheral region (i.e., the capacitor region 40) are formed in the same layer. Therefore, the same photomask may be used to form the capacitor region 40 and the memory cell region 50, thus reducing the number of photomasks required and saving costs.

[0093] In some embodiments of the present disclosure, the method of forming the bit line structure 30 and the capacitor region 40 includes steps S201 to S204 .

[0094] S201 , forming a first cavity 401 and a bit line hole 301 in a stacked structure based on a first photomask.

[0095] S202 , filling the first cavity 401 and the bit line hole 301 with a sacrificial material.

[0096] Figure 3A , Figure 3B and Figure 3C In the embodiment, the first cavity 401 and the bit line hole 301 are filled with sacrificial materials. The first cavity 401 and the bit line hole 301 both penetrate the stack structure 20 along the vertical direction Z. A row of bit line holes 301 are formed outside the two opposite sides of the first cavity 401 along the first direction X. Protruding grooves 402 distributed at intervals are formed at the intersection of the two opposite sides of the first cavity 401 along the first direction X and the composite layer.

[0097] S203 , removing the sacrificial material in the bit line hole 301 , and forming a bit line structure 30 in the bit line hole 301 .

[0098] refer to Figure 4A and Figure 5A After the sacrificial material in the bit line hole 301 is removed, one or more layers of conductive material may be sequentially deposited in the bit line hole 301 to form a bit line structure 30. The conductive material may include one or more of titanium (Ti), titanium nitride (TiN) and tungsten (W). The etching selectivity ratio between the conductive material and the dielectric material of the bit line structure 30 has a large difference, so that the conductive material can be selectively etched to form the bit line structure 30; the dielectric material may be silicon nitride (SiN) or silicon oxide (SiO).

[0099] S204 , removing the sacrificial material in the first cavity 401 , and forming a capacitor region 40 in the first cavity 401 ; wherein the first electrode plate 41 is formed in the protruding groove 402 .

[0100] It should be noted that, in the process of forming the bit line structure 30 in the bit line hole 301, a protective layer can be formed above the first cavity 401 to prevent the first cavity 401 from being affected; correspondingly, in the process of forming the capacitor area 40 in the first cavity 401, a protective layer can be formed above the bit line structure 30 to prevent the bit line structure 30 from being affected.

[0101] In some embodiments of the present disclosure, the above step S204 may be implemented through steps S301 to S305.

[0102] S301 , depositing a first conductive layer on the inner wall of the first cavity 401 .

[0103] Combination Fig. 6A and Fig. 7A After the sacrificial material in the first cavity 401 is removed, a conductive layer (i.e., a first conductive layer) may be deposited on the inner sidewall of the first cavity 401. The first conductive layer covers the inner sidewall of the protruding groove 402 and the inner sidewall of other regions in the first cavity 401. The material of the first conductive layer may include titanium (Ti) and / or titanium nitride (TiN).

[0104] S302 , performing etching in the first cavity 401 to partially remove the first conductive layer, retaining and exposing the first conductive layer in the protruding groove 402 , and forming a first electrode plate 41 .

[0105] Combination Fig. 8A and Fig.9A , etching can be performed in the first cavity 401, only the first conductive layer covering the inner side wall of the protruding groove 402 is retained, the rest of the first conductive layer is removed, and the first conductive layer in the protruding groove 402 is exposed, thus forming the first electrode plates 41 arranged at intervals. Since the protruding grooves 402 are arranged at intervals, adjacent first electrode plates 41 are not directly connected.

[0106] S303 , depositing a dielectric layer 43 on the inner sidewall of the first cavity 401 .

[0107] refer to Fig. 10A , Fig. 10B and Fig. 10C The dielectric layer 43 covers the inner sidewall of the first cavity 401 and also covers the exposed surface of the first electrode 41. The material of the dielectric layer 43 may include a high-k material, and the use of the high-k material can increase the capacity of the capacitor.

[0108] S304 , depositing a second conductive layer covering the dielectric layer 43 on the inner side wall of the first cavity 401 to form a second electrode 42 .

[0109] refer to Fig.11A , Fig. 11B and Fig. 11C The second electrode plate 42 covers the surface of the dielectric layer 43 on the inner sidewall of the first cavity 401, thereby forming a capacitor NICAP. The material of the second electrode plate 42 may include titanium (Ti) and / or titanium nitride (TiN).

[0110] In the embodiment of the present disclosure, in the composite layer of each capacitor region 40, the second electrode plate 42 is an integral electrode plate, that is, the same second electrode plate 42 and multiple first electrodes 41 form a capacitor. In this way, it is equivalent to connecting multiple capacitors in parallel, so that a capacitor with a larger capacity can be realized.

[0111] At the same time, in the composite layer of each capacitor region 40, the second electrode plate 42 is located inside to form a closed structure. In this way, compared with sleeve capacitors or flat plate capacitors, the size of the capacitor can be effectively reduced, thereby facilitating the improvement of integration.

[0112] S305, filling the first cavity 401 with semiconductor material. The semiconductor material filled in the first cavity 401 can play a supporting and isolating role. The semiconductor material can include polysilicon.

[0113] In some embodiments of the present disclosure, the above step S302 may be implemented through steps S401 to S403.

[0114] S401 , filling the protruding groove 402 with a sacrificial material.

[0115] In the embodiment of the present disclosure, a sacrificial material can be filled in the first cavity 401 (including the protruding groove 402 and other areas); then, etching is performed to retain only the sacrificial material in the protruding groove 402 and remove the sacrificial material in other areas, thus obtaining Fig. 8A , Figure 8B and Figure 8C Since the protruding groove 402 protrudes toward the outside of the first cavity 401, the sacrificial material in the protruding groove 402 can be retained during the etching process.

[0116] S402 , performing etching in the first cavity 401 to partially remove the first conductive layer and retain the first conductive layer in the protruding groove 402 .

[0117] In the embodiment of the present disclosure, since the protruding groove 402 is filled with a sacrificial material, during the process of etching the first conductive layer, the first conductive layer in the protruding groove 402 is protected by the sacrificial material and is retained.

[0118] S403 , enlarging the size of the first cavity 401 along the first direction X, exposing the first conductive layer in the protruding groove 402 , and removing the sacrificial material in the protruding groove 402 .

[0119] In the embodiment of the present disclosure, the exposed sidewall of the first cavity 401 may be etched, thereby expanding the size of the first cavity 401 along the first direction X. For example, an etching solution with a certain etching selectivity ratio may be injected into the first cavity 401 to selectively etch the sidewall of the first cavity 401. For another example, the sidewall of the first cavity 401 may be etched by bombarding the sidewall of the first cavity 401 with a plasma beam.

[0120] In some embodiments of the present disclosure, after the above step S103 , the method for forming a semiconductor structure further includes step S104 .

[0121] S104 , forming a back-end connection structure 80 extending along a vertical direction Z above the capacitor region 40 and above the bit line structure 30 .

[0122] refer to Fig. 12A , Fig. 12B and Fig. 12C The material of the rear-end connection structure 80 includes a metal material, such as tungsten (W).

[0123] It should be noted that the semiconductor structure and the method for forming the same provided by the embodiments of the present disclosure can be applied to dynamic random access memory DRAM, providing a new solution for three-dimensional memory products. The capacitor NICAP in the peripheral area (i.e., capacitor area 40) is in the same composite layer as the memory cell; the capacitor NICAP in the peripheral area is used as a power source or for signal processing in the peripheral area, and can modulate frequency to reduce noise, increase capacitance, and realize a separate IC test structure.

[0124] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0125] The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in the several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in the several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in the several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0126] The above description is only a specific implementation mode of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure.

Claims

1. A semiconductor structure, characterized in that: The semiconductor structure comprises: a semiconductor substrate, a stacking structure and a bit line structure; The stack structure and the bit line structure are located on the semiconductor substrate; The semiconductor substrate comprises: an array region and a peripheral region; The stack structure comprises: a separation layer and a composite layer alternately stacked in a vertical direction; the bit line structure extends in the vertical direction and penetrates the stack structure; The stacked structure located in the peripheral area includes: a capacitor area; a row of bit line structures is formed outside two opposite sides of the capacitor area along the first direction; The composite layer of the capacitor region includes: first plates; the first plates are spaced apart on two opposite sides of the composite layer of the capacitor region along the first direction and protrude outward; each of the first plates is connected to the corresponding bit line structure.

2. The semiconductor structure according to claim 1, characterized in that: The composite layer of the capacitor region further includes: a dielectric layer and a second electrode plate; The second electrode plate is located inside the composite layer of the capacitor region; the dielectric layer is located between the first electrode plate and the second electrode plate; The inner side of the second electrode plate is filled with semiconductor material.

3. The semiconductor structure according to claim 1, characterized in that: The composite layer in the capacitor region further includes: a contact plug; The contact plug is located between the first electrode plate and the bit line structure; each of the first electrode plates is connected to the corresponding bit line structure through the contact plug.

4. The semiconductor structure according to claim 1, characterized in that: The stacked structure located in the array area includes: a storage unit area; The storage unit area is provided with storage units arranged in an array; A bit line structure is formed between two memory cells that are opposite to each other along the first direction; the two memory cells are connected to a corresponding bit line structure; The capacitor region and the memory cell region are both formed based on a first photomask.

5. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure further includes: a back-end connection structure; The rear end connection structure extends along the vertical direction; The back-end connection structure is located above the capacitor region and above the bit line structure.

6. A method for forming a semiconductor structure, characterized in that: The method comprises: A semiconductor substrate is provided; the semiconductor substrate comprises: an array region and a peripheral region; A stacking structure is formed on the semiconductor substrate; the stacking structure comprises: a separation layer and a composite layer alternately stacked in a vertical direction; Based on the first mask, a bit line structure and a capacitor area are formed in the stacked structure in the peripheral area; wherein the bit line structure extends along the vertical direction and penetrates the stacked structure; a row of the bit line structures is formed outside the two opposite sides of the capacitor area along the first direction; the composite layer of the capacitor area includes: a first electrode plate; the first electrode plates are spaced apart and distributed on the two opposite sides of the composite layer of the capacitor area along the first direction and protrude outward; each of the first electrode plates is connected to the corresponding bit line structure.

7. The method for forming a semiconductor structure according to claim 6, wherein: The method of forming the bit line structure and the capacitor region includes: Based on the first photomask, a first cavity and a bit line hole are formed in the stacked structure; the first cavity and the bit line hole both penetrate the stacked structure along the vertical direction; a row of the bit line holes is formed outside two opposite sides of the first cavity along the first direction; protruding grooves distributed at intervals are formed at the intersection of two opposite sides of the first cavity along the first direction and the composite layer; Filling the first cavity and the bit line hole with a sacrificial material; removing the sacrificial material in the bit line hole to form the bit line structure in the bit line hole; The sacrificial material in the first cavity is removed to form the capacitor region in the first cavity; wherein the first electrode plate is formed in the protruding groove.

8. The method for forming a semiconductor structure according to claim 7, characterized in that: forming the capacitor region in the first cavity, comprising: Depositing a first conductive layer on the inner sidewall of the first cavity; Performing etching in the first cavity to partially remove the first conductive layer, retaining and exposing the first conductive layer in the protruding groove, and forming the first electrode plate; Depositing a dielectric layer on the inner sidewall of the first cavity; Depositing a second conductive layer covering the dielectric layer on the inner side wall of the first cavity to form a second electrode plate; The first cavity is filled with a semiconductor material.

9. The method for forming a semiconductor structure according to claim 8, characterized in that: Etching is performed in the first cavity to partially remove the first conductive layer and retain and expose the first conductive layer in the protruding groove, comprising: Filling the protruding groove with sacrificial material; Performing etching in the first cavity to partially remove the first conductive layer and retain the first conductive layer in the protruding groove; The size of the first cavity along the first direction is enlarged to expose the first conductive layer in the protruding groove, and the sacrificial material in the protruding groove is removed.

10. The method for forming a semiconductor structure according to claim 6, wherein: After forming the bit line structure and the capacitor region, the method further includes: A back-end connection structure extending along the vertical direction is formed above the capacitor region and above the bit line structure.

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