Silicon optical chip platform and manufacturing method

Abstract

The invention provides a silicon optical chip platform and a manufacturing method, and relates to the technical field of semiconductor processing, and the silicon optical chip platform comprises a silicon substrate, a buried oxide BOX layer and a SiO2 cladding which are sequentially arranged from bottom to top; the functional device is embedded in the SiO2 cladding layer; the third metal electrode is arranged in the SiO2 cladding and is positioned below the bonding region; the dielectric waveguide comprises a multi-layer waveguide structure, and the dielectric waveguide is arranged in the SiO2 cladding and is located between the two third metal electrodes; and the heterogeneous bonding layer is bonded at the bonding area of the SiO2 cladding, and the third metal electrode, the heterogeneous bonding layers made of different materials and the dielectric waveguide form devices with different functions. The silicon optical chip platform in the scheme is based on a CMOS (complementary metal oxide semiconductor) process, so that the purpose of large-scale mass production is achieved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor processing technology, and in particular to a silicon photonic chip platform and a manufacturing method thereof. Background Art

[0002] Existing silicon photonic chips based on silicon-on-insulator (SOI) technology generally include Si waveguides, SiN waveguides, grating couplers, end couplers, Si modulators, Ge detectors, and thermal modulators.

[0003] However, due to the natural properties of Si materials, on the one hand, the modulation bandwidth of the modulator is limited and difficult to improve further, and on the other hand, Si has an indirect bandgap and is difficult to emit light, requiring an external light source. Therefore, a new type of silicon photonic chip is needed to achieve more functions. Summary of the invention

[0004] In view of this, the embodiments of this specification provide a silicon photonic chip platform and a manufacturing method to achieve the purpose of integrating multiple functional devices based on SOI process.

[0005] The embodiments of this specification provide the following technical solutions:

[0006] A silicon photonic chip platform, comprising:

[0007] The silicon substrate, the buried oxide BOX layer and the SiO2 cladding layer are arranged in sequence from bottom to top;

[0008] Functional devices, the functional devices are embedded in the SiO2 cladding;

[0009] a third metal electrode in the SiO2 cladding layer and below the bonding region;

[0010] A dielectric waveguide, the dielectric waveguide comprises a multilayer waveguide structure, the dielectric waveguide is in a SiO2 cladding and is located between two third metal electrodes;

[0011] The heterogeneous bonding layer is bonded to the bonding area of ​​the SiO2 cladding layer. The third metal electrode, the heterogeneous bonding layer of different materials and the dielectric waveguide constitute devices with different functions.

[0012] Furthermore, if the material of the heterogeneous bonding layer is a high-speed modulation material, the heterogeneous bonding layer and the dielectric waveguide form a composite waveguide, and form a high-speed modulator with the third metal electrode;

[0013] If the material of the heterogeneous bonding layer is a light-emitting material, the heterogeneous bonding layer and the third metal electrode constitute a light source, and the light source is coupled into the interior of the silicon photonic chip platform through a dielectric waveguide.

[0014] Furthermore, the bonding area is located on the top surface of the SiO2 cladding layer, and the dielectric waveguide includes a Si waveguide, a lower silicon nitride waveguide, an intermediate transition optical waveguide and a silicon nitride waveguide arranged from bottom to top.

[0015] Furthermore, the thickness of the intermediate transition optical waveguide is 200nm~400nm, the width of the intermediate transition optical waveguide is 100nm~5um, the vertical spacing between the intermediate transition optical waveguide and the silicon nitride waveguide is 100nm~500nm, and the vertical spacing between the lower silicon nitride waveguide and the Si waveguide is 200nm~800nm; the top surface of the silicon nitride waveguide is flush with the top surface of the third metal electrode.

[0016] Furthermore, the silicon nitride waveguide is multi-layered, and the multi-layer silicon nitride waveguide is arranged in a vertical direction.

[0017] Furthermore, the silicon photonic chip platform further includes:

[0018] The first etched groove is formed by etching the SiO2 cladding layer located above the dielectric waveguide and the third metal electrode, the bonding area is located at the bottom of the first etched groove, the heterogeneous bonding layer is bonded to the bottom of the first etched groove, and the upper surface of the waveguide structure of the top layer in the dielectric waveguide is flush with the upper surface of the third metal electrode.

[0019] Furthermore, the dielectric waveguide includes a Si waveguide and a silicon nitride waveguide arranged from bottom to top, and the upper surface of the third metal electrode is flush with the upper surface of the silicon nitride waveguide.

[0020] Furthermore, the silicon photonic chip platform also includes:

[0021] A second etched groove, the second etched groove is located above the dielectric waveguide and the third metal electrode, the heterogeneous bonding layer is bonded to the bottom of the second etched groove, and the upper surface of the waveguide structure at the top layer in the dielectric waveguide is flush with the upper surface of the third metal electrode;

[0022] Two first metal electrodes are located below the non-bonding region in the SiO2 cladding layer;

[0023] The two layers of second metal electrodes are located below the non-bonding area in the SiO2 cladding layer, and the third metal electrode, the bottom first metal electrode and the bottom second metal electrode are located at the same layer in the SiO2 cladding layer.

[0024] A method for manufacturing a silicon photonic chip platform, the manufacturing method comprising the following steps:

[0025] Processing and preparing silicon substrate, buried oxide BOX layer and SiO2 cladding layer, and processing and preparing functional devices in the SiO2 cladding layer to generate multifunctional SOI wafers;

[0026] If the heterogeneous bonding layer is bonded on the top surface of the SiO2 cladding layer or in the second etched groove in the SiO2 cladding layer, a dielectric waveguide and a metal electrode are prepared by the first processing method based on the multifunctional SOI wafer to construct a silicon photonic chip platform;

[0027] If the heterogeneous bonding layer is bonded in the first etched groove in the SiO2 cladding layer, a dielectric waveguide and a metal electrode are prepared by a second processing method based on the multifunctional SOI wafer to construct a silicon photonic chip platform.

[0028] Furthermore, based on the multifunctional SOI wafer, dielectric waveguides and metal electrodes are processed and prepared by the first processing method to form a silicon photonic chip platform, including:

[0029] Processing and preparing the lower silicon nitride waveguide on the multifunctional SOI wafer;

[0030] Depositing a titanium nitride resistance layer on the multifunctional SOI wafer, etching the titanium nitride resistance layer, filling a second filling medium SiO2 layer and performing a planarization process;

[0031] Etching and depositing metal vias on the multifunctional SOI wafer and performing planarization processing;

[0032] Depositing an intermediate transition optical medium on the multifunctional SOI wafer, etching the intermediate transition optical medium to form an intermediate transition optical waveguide, depositing a first filling medium SiO2 layer on the intermediate transition optical waveguide, and flattening the first filling medium SiO2 layer;

[0033] Depositing silicon nitride on the first filling dielectric SiO2 layer, etching the silicon nitride to form a silicon nitride waveguide, depositing a second filling dielectric SiO2 layer on the silicon nitride waveguide, and performing a planarization process on the second filling dielectric SiO2 layer, wherein the first filling dielectric SiO2 layer and the second filling dielectric SiO2 layer constitute a SiO2 cladding layer;

[0034] Etching a metal groove above the metal via Via in the SiO2 cladding layer, and filling the metal in the metal groove to generate a first metal electrode, a second metal electrode, and a third metal electrode, and performing a planarization process on all the metal electrodes until the upper surface of the metal electrode is flush with the upper surface of the silicon nitride waveguide;

[0035] Depositing a first bonding SiO2 layer on the upper surface of the metal electrode and the silicon nitride waveguide and performing a planarization process on the first bonding SiO2 layer;

[0036] If the heterogeneous bonding layer is bonded to the first bonding SiO2 layer, the heterogeneous bonding layer is bonded by the first sub-method;

[0037] If the heterogeneous bonding layer is bonded to the bottom of the second etching groove, the heterogeneous bonding layer is bonded by the second sub-method and the metal electrode is processed.

[0038] Further, bonding the heterogeneous bonding layer by a first sub-method includes:

[0039] Etching above the metal electrode to expose the pin pad PAD;

[0040] The heterogeneous bonding layer is processed and bonded to the first bonding SiO2 layer.

[0041] Furthermore, the heterogeneous bonding layer is bonded by a second sub-method, and the metal electrode is processed, including:

[0042] Depositing a sacrificial layer on the top surface of the first bonding SiO2 layer, etching the sacrificial layer, depositing a sixth filling dielectric SiO2 layer on the sacrificial layer and performing a planarization process on the sixth filling dielectric SiO2 layer, wherein the first bonding SiO2 layer and the sixth filling dielectric SiO2 layer constitute a SiO2 cladding layer;

[0043] Etching and depositing metal vias Via on the SiO2 cladding layer, and performing a planarization process on the metal vias Via;

[0044] Depositing a seventh filling dielectric SiO2 layer on the metal via hole Via;

[0045] Etching a metal groove on the seventh filling dielectric SiO2 layer, and filling the metal in the metal groove to generate a second layer of first metal electrode and a second layer of second metal electrode, and performing a planarization process on the second layer of first metal electrode and the second layer of second metal electrode, wherein the sixth filling dielectric SiO2 layer and the seventh filling dielectric SiO2 layer constitute a SiO2 cladding layer;

[0046] Etching above the second layer first metal electrode and the second layer second metal electrode to expose the pin pad PAD;

[0047] Etching a second etching groove in an area of ​​the SiO2 cladding layer that does not include a metal electrode, exposing the sacrificial layer, stopping the etching, and removing the sacrificial layer;

[0048] A heterogeneous bonding layer is processed and bonded to the first bonding SiO2 layer at the bottom of the second etched groove.

[0049] Furthermore, based on the multifunctional SOI wafer, metal electrodes and dielectric waveguides are prepared by a second processing method to form a silicon photonic chip platform, including:

[0050] Processing and preparing Si waveguide on multifunctional SOI wafer, filling the third filling medium SiO2 layer and performing planarization treatment;

[0051] Depositing silicon nitride on the third filling dielectric SiO2 layer, etching the silicon nitride to form a silicon nitride waveguide (6), depositing a third filling dielectric SiO2 layer on the silicon nitride waveguide, and flattening the third filling dielectric SiO2 layer;

[0052] Etching a metal groove on the SiO2 cladding layer of the multifunctional SOI wafer, and filling the metal in the metal groove to generate a third metal electrode, and performing a planarization process on the third metal electrode until the upper surface of the third metal electrode is flush with the upper surface of the silicon nitride waveguide;

[0053] depositing a second bonding SiO2 layer on the upper surface of the third metal electrode and the silicon nitride waveguide;

[0054] Depositing a sacrificial layer on the top surface of the second bonding SiO2 layer, etching the sacrificial layer, depositing a fourth filling dielectric SiO2 layer on the sacrificial layer and performing a planarization process on the fourth filling dielectric SiO2 layer, depositing a titanium nitride resistance layer, and etching the titanium nitride resistance layer;

[0055] Filling a fourth filling dielectric SiO2 layer and performing a planarization process, wherein the second bonding SiO2 layer and the fourth filling dielectric SiO2 layer constitute a SiO2 cladding layer;

[0056] Etching and depositing metal vias Via on the SiO2 cladding layer, and performing a planarization process on the metal vias Via;

[0057] Depositing a fifth filling dielectric SiO2 layer on the metal via hole Via;

[0058] Etching a metal groove on the fifth filling dielectric SiO2 layer, and filling the metal in the metal groove to generate a first metal electrode and a second metal electrode, and performing a planarization process on the first metal electrode and the second metal electrode;

[0059] Etching above the first metal electrode and the second metal electrode to expose the pin pad PAD;

[0060] Etching a first etching groove on the fifth filling dielectric SiO2 layer, exposing the sacrificial layer, stopping etching, and removing the sacrificial layer;

[0061] A heterogeneous bonding layer is processed and bonded to the second bonding SiO2 layer at the bottom of the first etched groove.

[0062] Compared with the prior art, the at least one technical solution adopted in the embodiments of this specification can achieve the following beneficial effects:

[0063] The new silicon photonic chip platform is based on CMOS technology and integrates a variety of heterogeneous functional devices, which is conducive to achieving more functions and better performance, and realizing large-scale mass production. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0065] Figure 1 is a schematic structural diagram of a silicon photonic chip according to a first embodiment of the present invention;

[0066] Figure 2 is a schematic structural diagram of a silicon photonic chip according to a second embodiment of the present invention;

[0067] Figure 3 It is a schematic diagram of the structure of a silicon photonic chip according to the third embodiment of the present invention.

[0068] Reference numerals in the figure: 1, silicon substrate; 2, buried oxide BOX layer; 3, SiO2 cladding layer; 301, first filling dielectric SiO2 layer; 302, second filling dielectric SiO2 layer; 303, first bonding SiO2 layer; 304, third filling dielectric SiO2 layer; 305, second bonding SiO2 layer; 306, fourth filling dielectric SiO2 layer; 307, fifth filling dielectric SiO2 layer; 308, sixth filling dielectric SiO2 layer; 309, seventh filling dielectric SiO2 layer; 4, germanium detector; 5, nitrogen nitride layer; 501, grating coupler; 502, end coupler; 503, Si waveguide; 504, Si modulator; 6, silicon nitride waveguide; 601, lower silicon nitride waveguide; 602, intermediate transition optical waveguide; 7, metal electrode; 701, first metal electrode; 702, second metal electrode; 703, third metal electrode; 704, fourth metal electrode; 8, pin pad PAD; 9, through silicon via TSV; 10, titanium nitride resistor layer; 11, heterogeneous bonding layer; 12, covering material layer; 13, metal via Via. DETAILED DESCRIPTION

[0069] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0070] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0071] like Figure 1 , Figure 2 and Figure 3 As shown, the silicon photonic chip platform includes:

[0072] A silicon substrate 1, a buried oxide BOX layer 2 and a SiO2 cladding layer 3 are sequentially arranged from bottom to top;

[0073] Functional devices (such as silicon nitride end couplers (arranged in the silicon nitride layer 5), grating couplers 501, end couplers 502, Si modulators 504 and germanium detectors 4, etc.), the functional devices are embedded in the SiO2 cladding layer 3;

[0074] A third metal electrode 703, in the SiO2 cladding layer 3 and below the bonding region;

[0075] A dielectric waveguide, the dielectric waveguide includes a multilayer waveguide structure, the dielectric waveguide is in the SiO2 cladding layer 3 and is located between two third metal electrodes 703;

[0076] The heterogeneous bonding layer 11 is bonded to the bonding area of ​​the SiO2 cladding layer 3. The third metal electrode 703, the heterogeneous bonding layer 11 of different materials and the dielectric waveguide constitute a composite waveguide, and constitute a high-speed modulator together with the third metal electrode 703.

[0077] In specific implementation, the silicon photonic chip platform also includes a titanium nitride resistor layer 10, a pin pad PAD8 and a through silicon via TSV9. The first metal electrode 701 and the second metal electrode 702 are connected to the pin pad PAD8. The first metal electrodes 701 are connected to the titanium nitride resistor layer 10 through the metal via Via13. The second metal electrodes 702 are connected to the Si modulator 504, the germanium detector 4, the third metal electrode 703, etc. through the metal via Via13.

[0078] In a specific implementation, if the material of the heterogeneous bonding layer 11 is a high-speed modulation material, the heterogeneous bonding layer 11 and the dielectric waveguide constitute a composite waveguide, and constitute a high-speed modulator with the third metal electrode 703; if the material of the heterogeneous bonding layer 11 is a luminescent material, the heterogeneous bonding layer 11 and the third metal electrode 703 constitute a light source, and the light source is coupled into the interior of the silicon photonic chip platform through the dielectric waveguide.

[0079] In a specific implementation, the covering material layer 12 is disposed above the heterogeneous bonding layer 11, and the material of the covering material layer 12 includes air, silicon dioxide SiO2 and silicon Si. The material of the heterogeneous bonding layer 11 is a high-speed modulation material or a luminescent material. The high-speed modulation material is lithium niobate LN, etc. The luminescent material is indium phosphide InP.

[0080] In a specific implementation, the silicon nitride waveguide 6 can be a single layer or a multilayer, and the multilayer silicon nitride waveguide 6 is arranged in the vertical direction and is located between the third metal electrodes 703. The thickness of the silicon nitride waveguide 6 is about 200nm to 800nm, and the width is about 300nm to 5um. The SiO2 cladding layer 3 on the upper surface of the lower silicon nitride waveguide 601 in the bonding region bonded to the heterogeneous bonding layer 11 has a thickness of about 50nm to 300nm.

[0081] In a specific implementation, the metal electrode 7 includes a first metal electrode 701 , a second metal electrode 702 , a third metal electrode 703 and a fourth metal electrode 704 disposed below the silicon substrate 1 .

[0082] The first metal electrode 701 is connected to the titanium nitride resistor layer 10 through the metal via Via13 and is used for thermal modulation, and the second metal electrode 702 is connected to the Si modulator 504 through the metal via Via13 to form the Si modulator 504 and / or the germanium detector 4. The third metal electrode 703 is directly led out or connected to the second metal electrode 702 through the metal via Via13 or connected to the fourth metal electrode 704 through the silicon through hole TSV9 (i.e., connected to the substrate metal line).

[0083] The thickness of the metal electrode 7 (including the first metal electrode 701 , the second metal electrode 702 , the third metal electrode 703 and the fourth metal electrode 704 ) is about 500 nm to 3 um.

[0084] The third metal electrode 703 located in the bonding area plays the role of loading the modulated signal onto the optical waveguide or providing power for the light source. The fourth metal electrode 704 arranged below the silicon substrate 1 is used to arrange more metal electrodes 7 below the silicon substrate 1 to achieve more functions when there are too many metal electrodes 7 above the wafer to be arranged.

[0085] like Figure 1 As shown, in the first embodiment of the present invention, the top surface of the SiO2 cladding 3 is an overall plane, the bonding area is located on the top surface of the SiO2 cladding 3, the dielectric waveguide includes a Si waveguide 503, a lower silicon nitride waveguide 601, an intermediate transition optical waveguide 602 and a silicon nitride waveguide 6 arranged in sequence from bottom to top, the thickness of the Si waveguide 503 is 210nm-230nm, and the width of the Si waveguide 503 is 300nm-5um. The thickness of the intermediate transition optical waveguide 602 is 200nm-400nm, the width of the intermediate transition optical waveguide 602 is 100nm-5um, the vertical spacing between the intermediate transition optical waveguide 602 and the lower silicon nitride waveguide 601 is 100nm-500nm, and the vertical spacing between the intermediate transition optical waveguide 602 and the Si waveguide 503 is 200nm-800nm. The top surface of the lower silicon nitride waveguide 601 is flush with the top surfaces of the first metal electrode 701 , the second metal electrode 702 and the third metal electrode 703 .

[0086] Compared with the existing SOI chip, the first embodiment of the present invention realizes new functions by changing the position of the optical waveguide, increasing the number of layers and bonding heterogeneous materials. The silicon photonic chip platform of the first embodiment of the present invention requires at least 4 layers of dielectric waveguides, including Si waveguide 503 (of the existing SOI chip) at the bottom, lower silicon nitride waveguide 601 (low-loss SiN waveguide) at the top, intermediate transition optical waveguide 602 in the middle and silicon nitride waveguide 6 (low-loss SiN waveguide) at the top. The third metal electrode 703, the lower silicon nitride waveguide 601 and the bonded heterogeneous bonding layer 11 together constitute the core device area. When the bonding material of the heterogeneous bonding layer 11 is a high-speed modulation material such as lithium niobate, the silicon nitride waveguide 6 is less than 150nm away from the bonding surface, and together with the high-speed modulation material, it forms a composite waveguide to achieve light modulation; when the bonding material of the heterogeneous bonding layer 11 is a luminescent material such as InP, the silicon nitride waveguide 6 is less than 300nm away from the bonding surface, and is used to achieve interlayer light coupling with the light source waveguide. The intermediate transition optical waveguide 602 is used to achieve the optical coupling transition between the silicon nitride waveguide 6 and the Si waveguide 503, and the material of the intermediate transition optical waveguide 602 can be silicon Si or silicon nitride SiN.

[0087] like Figure 2 As shown, in the second embodiment, the top surface of the SiO2 cladding layer 3 can also be a plane with a first etched groove, and the bonding area is located at the bottom of the first etched groove. In this case, the dielectric waveguide includes a Si waveguide 503 and a silicon nitride waveguide 6 arranged in sequence from bottom to top, and the dielectric waveguide can achieve optical coupling. The thickness of the Si waveguide 503 is 210nm to 230nm, and the width of the Si waveguide 503 is 300nm to 5um.

[0088] The second embodiment is processed with a first etched groove, which is formed by etching the SiO2 cladding 3 located above the dielectric waveguide and the third metal electrode 703. The bonding area is located at the bottom of the first etched groove, and the heterogeneous bonding layer 11 is bonded to the bottom of the first etched groove. The upper surface of the waveguide structure of the top layer in the dielectric waveguide is flush with the upper surface of the third metal electrode 703. The upper surface of the third metal electrode 703 is flush with the upper surface of the silicon nitride layer 5 in the functional device (the silicon nitride layer 5 can be used as a coupler or waveguide to achieve multiple functions) (that is, the upper surface of the third metal electrode 703 and the upper surface of the silicon nitride layer 5 in the functional device are located at the same layer in the SiO2 cladding 3). Specifically, the upper surface of the third metal electrode 703 is flush with the upper surface of the silicon nitride waveguide 6.

[0089] Compared with the existing SOI chip, the second embodiment realizes new functions by changing the position of the metal electrode and bonding the heterogeneous material through the first etched groove. The third metal electrode 703 is moved down to the upper surface and flush with the upper surface of the silicon nitride waveguide 6. The heterogeneous bonding layer 11 and the silicon nitride waveguide 6 and the third metal electrode 703 are bonded by slots to form a core device area. When the bonding material of the heterogeneous bonding layer 11 is a high-speed modulation material such as lithium niobate, the silicon nitride waveguide 6 is less than 150nm away from the bonding surface, and together with the high-speed modulation material, it forms a composite waveguide to realize light modulation; when the bonding material of the heterogeneous bonding layer 11 is a luminescent material such as InP, the silicon nitride waveguide 6 is less than 300nm away from the bonding surface, which is used to realize interlayer optical coupling with the light source waveguide.

[0090] like Figure 3 As shown, in the third embodiment of the present invention, the top surface of the SiO2 cladding layer 3 can also be a plane with a second etching groove, the bonding area is located at the bottom of the second etching groove, the first metal electrode 701 and the second metal electrode 702 are two-layer or multi-layer structures respectively, and the dielectric waveguide includes Si waveguide 503, lower silicon nitride waveguide 601, intermediate transition optical waveguide 602 and silicon nitride waveguide 6 arranged in sequence from bottom to top, the thickness of Si waveguide 503 is 210nm~230nm, and the width of Si waveguide 503 is 300nm~5um. The thickness of the intermediate transition optical waveguide 602 is 200nm~400nm, the width of the intermediate transition optical waveguide 602 is 100nm~5um, the vertical spacing between the intermediate transition optical waveguide 602 and the lower silicon nitride waveguide 601 is 100nm~500nm, and the vertical spacing between the intermediate transition optical waveguide 602 and the Si waveguide 503 is 200nm~800nm. The top surface of the lower silicon nitride waveguide 601 is flush with the top surfaces of the lower layer of the first metal electrode 701, the second metal electrode 702 and the lower layer of the third metal electrode 703 (i.e., the top surface of the lower silicon nitride waveguide 601 and the top surfaces of the first metal electrode 701, the second metal electrode 702 and the third metal electrode 703 are located at the same layer in the SiO2 cladding 3).

[0091] The third embodiment is processed with a second etched groove, which is located above the dielectric waveguide and the third metal electrode 703, and the heterogeneous bonding layer 11 is bonded to the bottom of the second etched groove. The upper surface of the waveguide structure of the top layer in the dielectric waveguide is flush with the upper surface of the third metal electrode 703 (that is, the upper surface of the waveguide structure of the top layer in the dielectric waveguide and the upper surface of the third metal electrode 703 are located at the same layer in the SiO2 cladding 3).

[0092] The first metal electrode 701 of the third embodiment may be a multi-layer first metal electrode 701 , and the second metal electrode 702 may be a multi-layer second metal electrode 702 .

[0093] Specifically, two layers of first metal electrodes 701 are located below the non-bonding region in the SiO2 cladding layer 3. Two layers of second metal electrodes 702 are located below the non-bonding region in the SiO2 cladding layer 3, and the third metal electrode 703, the bottom first metal electrode 701, and the bottom second metal electrode 702 are located at the same layer in the SiO2 cladding layer 3.

[0094] In the third embodiment, the upper and lower layers of first metal electrodes 701 are connected via a metal via Via13, and the upper and lower layers of second metal electrodes 702 are connected via a metal via Via13.

[0095] Compared with the existing SOI chip, the third embodiment of the present invention realizes new functions by increasing the number of metal electrode layers and bonding heterogeneous materials through the second etched groove. The silicon photonic chip platform of the third embodiment of the present invention requires at least 4 layers of dielectric waveguides, including Si waveguide 503 (of the existing SOI chip) at the bottom, lower silicon nitride waveguide 601 (low-loss SiN waveguide) at the top, intermediate transition optical waveguide 602 in the middle, and silicon nitride waveguide 6 (low-loss SiN waveguide) at the top. The third metal electrode 703, the lower silicon nitride waveguide 601, and the bonded heterogeneous bonding layer 11 together constitute the core device area. When the bonding material of the heterogeneous bonding layer 11 is a high-speed modulation material such as lithium niobate, the silicon nitride waveguide 6 is less than 150nm away from the bonding surface, and together with the high-speed modulation material, it forms a composite waveguide to achieve optical modulation; when the bonding material of the heterogeneous bonding layer 11 is a luminescent material such as InP, the silicon nitride waveguide 6 is less than 300nm away from the bonding surface, and is used to achieve interlayer optical coupling with the light source waveguide. The intermediate transition optical waveguide 602 is used to achieve the optical coupling transition between the silicon nitride waveguide 6 and the Si waveguide 503, and the material of the intermediate transition optical waveguide 602 can be silicon Si or silicon nitride SiN. The upper and lower layers of the first metal electrode 701 and the upper and lower layers of the second metal electrode 702 improve the wiring density and performance, and also support high-density integration, complex circuit design, and the development of new device architectures, and can be used in high-performance electrochemistry.

[0096] The silicon photonic chip of the embodiment of the present invention is based on the SOI process of the CMOS platform.

[0097] A method for manufacturing a silicon photonic chip platform, the manufacturing method comprising the following steps:

[0098] 1. Processing and preparing silicon waveguide on SOI according to conventional processes (processing and preparing silicon substrate 1, buried oxide BOX layer 2, SiO2 cladding layer 3, and processing and preparing silicon nitride layer 5, grating coupler 501, end face coupler 502, Si waveguide 503, Si modulator 504 and germanium detector 4 in SiO2 cladding layer 3 to generate multifunctional SOI wafer;

[0099] 2. If the heterogeneous bonding layer 11 is bonded on the top surface of the SiO2 cladding layer 3 or in the second etched groove in the SiO2 cladding layer 3, a dielectric waveguide and a metal electrode 7 are prepared by the first processing method based on the multifunctional SOI wafer to construct a silicon photonic chip platform;

[0100] 3. If the heterogeneous bonding layer 11 is bonded in the first etched groove in the SiO2 cladding layer 3, based on the multifunctional SOI wafer, the dielectric waveguide and the metal electrode 7 are prepared by the second processing method to construct a silicon photonic chip platform.

[0101] Specifically, based on the multifunctional SOI wafer, a dielectric waveguide and a metal electrode 7 are prepared by a first processing method to construct the silicon photonic chip platform, including:

[0102] 2.1. Processing and preparing a lower silicon nitride waveguide 601 on a multifunctional SOI wafer;

[0103] 2.2. Depositing a titanium nitride resistor layer 10 on the multifunctional SOI wafer, etching the titanium nitride resistor layer 10, filling a second filling dielectric SiO2 layer 302 and performing a planarization process;

[0104] 2.3. Etching and depositing metal vias Via13 on the multifunctional SOI wafer and performing planarization processing;

[0105] 2.4. Depositing an intermediate transition optical medium on the multifunctional SOI wafer, etching the intermediate transition optical medium to form an intermediate transition optical waveguide 602, depositing a first filling medium SiO2 layer 301 on the intermediate transition optical waveguide 602, and performing a planarization process on the first filling medium SiO2 layer 301;

[0106] 2.5. Depositing silicon nitride on the first filling dielectric SiO2 layer 301, etching the silicon nitride to form a silicon nitride waveguide 6, depositing a second filling dielectric SiO2 layer 302 on the silicon nitride waveguide 6, and performing a planarization process on the second filling dielectric SiO2 layer 302, wherein the first filling dielectric SiO2 layer 301 and the second filling dielectric SiO2 layer 302 constitute a SiO2 cladding layer 3;

[0107] 2.6. Etching a metal groove above the metal via Via13 in the SiO2 cladding layer 3 and filling the metal in the metal groove to generate a first metal electrode 701, a second metal electrode 702 and a third metal electrode 703. Flattening all the metal electrodes 7 by chemical mechanical polishing technology until the upper surface of the metal electrode 7 is flush with the upper surface of the silicon nitride waveguide 6;

[0108] 2.7. Depositing a first bonding SiO2 layer 303 on the upper surface of the metal electrode 7 and the silicon nitride waveguide 6 and performing a planarization process on the first bonding SiO2 layer 303, wherein the thickness of the first bonding SiO2 layer 303 is controlled by a deposition time or a chemical mechanical polishing technique;

[0109] 2.8. If the heterogeneous bonding layer 11 is bonded to the first bonding SiO2 layer 303, the heterogeneous bonding layer 11 is bonded by the first sub-method; if the heterogeneous bonding layer 11 is bonded to the bottom of the second etching groove, the heterogeneous bonding layer 11 is bonded by the second sub-method and the metal electrode 7 is processed.

[0110] Bonding the heterogeneous bonding layer 11 by a first sub-method includes:

[0111] 2.8.1. Etching the top of the metal electrode 7 to expose the pin pad PAD8;

[0112] 2.8.2. Processing to form a heterogeneous bonding layer 11, and bonding the heterogeneous bonding layer 11 to the first bonding SiO2 layer 303.

[0113] The second sub-method is used to bond the heterogeneous bonding layer 11 and process the metal electrode 7, including:

[0114] 2.8.1. Depositing a sacrificial layer on the top surface of the first bonding SiO2 layer 303, etching the sacrificial layer, depositing a sixth filling dielectric SiO2 layer 308 on the sacrificial layer, and performing a planarization process on the sixth filling dielectric SiO2 layer 308, wherein the first bonding SiO2 layer 303 and the sixth filling dielectric SiO2 layer 308 constitute a SiO2 cladding layer 3;

[0115] 2.8.2. Etching and depositing metal vias Via13 on the SiO2 cladding layer 3, and performing a planarization process on the metal vias Via13;

[0116] 2.8.3. Depositing a seventh filling dielectric SiO2 layer 309 on the metal via Via13;

[0117] 2.8.4, etching a metal groove on the seventh filling dielectric SiO2 layer 309, and filling the metal in the metal groove to generate a second layer of first metal electrode 701 and a second layer of second metal electrode 702, and performing a planarization process on the second layer of first metal electrode 701 and the second layer of second metal electrode 702, wherein the sixth filling dielectric SiO2 layer 308 and the seventh filling dielectric SiO2 layer 309 constitute a SiO2 cladding layer 3;

[0118] 2.8.5. Etching is performed above the second-layer first metal electrode 701 and the second-layer second metal electrode 702 to expose the pin pad PAD8;

[0119] 2.8.6, etching a second etching groove in the area of ​​the SiO2 cladding layer 3 that does not include the metal electrode 7, exposing the sacrificial layer, stopping the etching, and removing the sacrificial layer;

[0120] 2.8.7. Processing to form a heterogeneous bonding layer 11, and bonding the heterogeneous bonding layer 11 to the first bonding SiO2 layer 303 at the bottom of the second etched groove.

[0121] Specifically, based on the multifunctional SOI wafer, the metal electrode 7 and the dielectric waveguide are prepared by the second processing method, and the silicon photonic chip platform is processed, including:

[0122] 3.1. Processing and preparing Si waveguide 503 on multifunctional SOI wafer, filling the third filling medium SiO2 layer 304 and performing planarization treatment;

[0123] 3.2. Depositing silicon nitride on the third filling dielectric SiO2 layer 304, etching the silicon nitride to form a silicon nitride waveguide 6, depositing a third filling dielectric SiO2 layer 304 on the silicon nitride waveguide 6, and performing a planarization process on the third filling dielectric SiO2 layer 304;

[0124] 3.3. Etching a metal groove on the SiO2 cladding layer 3 of the multifunctional SOI wafer and filling the metal in the metal groove to generate a third metal electrode 703. The third metal electrode 703 is planarized by chemical mechanical polishing technology until the upper surface of the third metal electrode 703 is flush with the upper surface of the silicon nitride waveguide 6.

[0125] 3.4. Depositing a second bonding SiO2 layer 305 on the upper surface of the third metal electrode 703 and the silicon nitride waveguide 6, wherein the thickness of the second bonding SiO2 layer 305 is controlled by deposition time or chemical mechanical polishing technology;

[0126] 3.5. Depositing a sacrificial layer on the second bonding SiO2 layer 305, etching the sacrificial layer, depositing a fourth filling dielectric SiO2 layer 306 on the sacrificial layer and performing a planarization process on the fourth filling dielectric SiO2 layer 306, depositing a titanium nitride resistor layer 10, and etching the titanium nitride resistor layer 10;

[0127] 3.6. Filling a fourth filling dielectric SiO2 layer 306 and performing a planarization process, wherein the second bonding SiO2 layer 305 and the fourth filling dielectric SiO2 layer 306 constitute a SiO2 cladding layer 3;

[0128] 3.7, etching a metal via Via13 on the SiO2 cladding layer 3, filling the metal via Via13 with metal, and flattening the metal via Via13 by chemical mechanical polishing technology;

[0129] 3.8. Depositing a fifth filling dielectric SiO2 layer 307 on the metal via Via13;

[0130] 3.9, etching a metal groove on the fifth filling dielectric SiO2 layer 307, and filling the metal groove with metal to generate a first metal electrode 701 and a second metal electrode 702, and flattening the first metal electrode 701 and the second metal electrode 702 by chemical mechanical polishing technology;

[0131] 3.10. Etching is performed above the first metal electrode 701 and the second metal electrode 702 to expose the pin pad PAD8;

[0132] 3.11, etching a first etching groove on the fifth filling dielectric SiO2 layer 307, exposing the sacrificial layer, stopping etching, and removing the sacrificial layer;

[0133] 3.12. Processing to form a heterogeneous bonding layer 11, and bonding the heterogeneous bonding layer 11 to the second bonding SiO2 layer 305 at the bottom of the first etched groove.

[0134] Beneficial effects of the embodiments of the present invention:

[0135] The silicon photonic chip platform of the embodiment of the present invention achieves the purpose of adding new functions (high-speed modulator and light source composed of composite waveguides) to the silicon photonic chip processed by the SOI process of the traditional COMS platform by changing the position of the optical waveguide, increasing the number of layers and bonding heterogeneous materials, and bonding heterogeneous materials in the etching groove; the silicon photonic chip platform of the embodiment of the present invention solves the problem of ultra-high-speed modulator and light source on the SOI platform, and the structure of the silicon photonic chip platform is based on the CMOS process, which is conducive to large-scale mass production; the silicon photonic chip platform of the embodiment of the present invention can realize the integration of multiple functions such as modulators, detectors, light sources, etc. on a single platform. In addition, back-side routing or pin pads PAD can be achieved through silicon through vias, avoiding the problem that it is inconvenient to open pin pads PAD on the bonding surface.

[0136] The above is only a specific embodiment of the present invention, and cannot be used to limit the scope of the invention. Therefore, the replacement of equivalent components, or equivalent changes and modifications made according to the scope of protection of the patent of the present invention, should still fall within the scope of this patent. In addition, the technical features of the present invention can be freely combined with each other, with each other, and with each other.

Claims

1. A silicon photonic chip platform, characterized in that: include: A silicon substrate (1), a buried oxide BOX layer (2) and a SiO2 cladding layer (3) are arranged in sequence from bottom to top; A functional device, wherein the functional device is embedded in the SiO2 cladding layer (3); A third metal electrode (703) is located in the SiO2 cladding layer (3) and below the bonding region; A dielectric waveguide, the dielectric waveguide comprising a multilayer waveguide structure, the dielectric waveguide being in the SiO2 cladding (3) and located between two third metal electrodes (703); A heterogeneous bonding layer (11), wherein the heterogeneous bonding layer (11) is bonded to the bonding region of the SiO2 cladding layer (3), and the third metal electrode (703), the heterogeneous bonding layer (11) of different materials and the dielectric waveguide constitute devices with different functions.

2. The silicon photonic chip platform according to claim 1, characterized in that: If the material of the heterogeneous bonding layer (11) is a high-speed modulation material, the heterogeneous bonding layer (11) and the dielectric waveguide form a composite waveguide, and form a high-speed modulator with the third metal electrode (703); If the material of the heterogeneous bonding layer (11) is a luminescent material, the heterogeneous bonding layer (11) and the third metal electrode (703) constitute a light source, and the light source is coupled into the interior of the silicon photonic chip platform through the dielectric waveguide.

3. The silicon photonic chip platform according to claim 1, characterized in that: The bonding area is located on the top surface of the SiO2 cladding layer (3), and the dielectric waveguide includes a Si waveguide (503), a lower silicon nitride waveguide (601), an intermediate transition optical waveguide (602), and a silicon nitride waveguide (6) arranged from bottom to top.

4. The silicon photonic chip platform according to claim 3, characterized in that: The thickness of the intermediate transition optical waveguide (602) is 200nm-400nm, the width of the intermediate transition optical waveguide (602) is 100nm-5um, the vertical spacing between the intermediate transition optical waveguide (602) and the silicon nitride waveguide (6) is 100nm-500nm, and the vertical spacing between the lower silicon nitride waveguide (601) and the Si waveguide (503) is 200nm-800nm; the top surface of the silicon nitride waveguide (6) is flush with the top surface of the third metal electrode (703).

5. The silicon photonic chip platform according to claim 3, characterized in that: The silicon nitride waveguide (6) is multi-layered, and the multi-layered silicon nitride waveguide (6) is arranged in a vertical direction.

6. The silicon photonic chip platform according to claim 1, characterized in that: The silicon photonic chip platform further includes: A first etching groove is formed by etching the SiO2 cladding layer (3) located above the dielectric waveguide and the third metal electrode (703), the bonding area is located at the bottom of the first etching groove, the heterogeneous bonding layer (11) is bonded to the bottom of the first etching groove, and the upper surface of the waveguide structure at the top layer in the dielectric waveguide is flush with the upper surface of the third metal electrode (703).

7. The silicon photonic chip platform according to claim 6, characterized in that: The dielectric waveguide comprises a Si waveguide (503) and a silicon nitride waveguide (6) arranged from bottom to top, and the upper surface of the third metal electrode (703) is flush with the upper surface of the silicon nitride waveguide (6).

8. The silicon photonic chip platform according to claim 3, characterized in that: The silicon photonic chip platform further includes: A second etching groove, wherein the second etching groove is located above the dielectric waveguide and the third metal electrode (703), the heterogeneous bonding layer (11) is bonded to the bottom of the second etching groove, and the upper surface of the waveguide structure at the top layer in the dielectric waveguide is flush with the upper surface of the third metal electrode (703); Two layers of first metal electrodes (701) are located below the non-bonding area in the SiO2 cladding layer (3); Two layers of second metal electrodes (702) are located below the non-bonding area in the SiO2 cladding (3); the third metal electrode (703), the bottom layer of the first metal electrode (701) and the bottom layer of the second metal electrode (702) are located in the same layer in the SiO2 cladding (3).

9. A method for manufacturing a silicon photonic chip platform according to any one of claims 1 to 8, characterized in that: The manufacturing method comprises the following steps: Processing and preparing the silicon substrate (1), the buried oxide BOX layer (2) and the SiO2 cladding layer (3), and processing and preparing the functional device in the SiO2 cladding layer (3) to generate a multifunctional SOI wafer; If the heterogeneous bonding layer (11) is bonded to the top surface of the SiO2 cladding (3) or in the second etched groove in the SiO2 cladding (3), the dielectric waveguide and the metal electrode (7) are prepared by a first processing method based on the multifunctional SOI wafer to construct the silicon photonic chip platform; If the heterogeneous bonding layer (11) is bonded in the first etched groove in the SiO2 cladding (3), the dielectric waveguide and the metal electrode (7) are prepared by a second processing method based on the multifunctional SOI wafer to construct the silicon photonic chip platform.

10. The manufacturing method according to claim 9, characterized in that: Based on the multifunctional SOI wafer, the dielectric waveguide and the metal electrode (7) are processed and prepared by a first processing method to manufacture the silicon photonic chip platform, including: Processing and preparing a lower silicon nitride waveguide (601) on the multifunctional SOI wafer; Depositing a titanium nitride resistance layer (10) on the multifunctional SOI wafer, etching the titanium nitride resistance layer (10), filling a second filling medium SiO2 layer (302) and performing a planarization process; Etching and depositing metal vias Via (13) on the multifunctional SOI wafer, and performing a planarization process; Depositing an intermediate transition optical medium on the multifunctional SOI wafer, etching the intermediate transition optical medium to form an intermediate transition optical waveguide (602), depositing a first filling medium SiO2 layer (301) on the intermediate transition optical waveguide (602), and performing a planarization process on the first filling medium SiO2 layer (301); Depositing silicon nitride on the first filling dielectric SiO2 layer (301), etching the silicon nitride to form a silicon nitride waveguide (6), depositing a second filling dielectric SiO2 layer (302) on the silicon nitride waveguide (6), and performing a planarization process on the second filling dielectric SiO2 layer (302), wherein the first filling dielectric SiO2 layer (301) and the second filling dielectric SiO2 layer (302) constitute the SiO2 cladding layer (3); Etching a metal groove above the metal via hole Via (13) in the SiO2 cladding layer (3), and filling the metal groove with metal to generate a first metal electrode (701), a second metal electrode (702) and the third metal electrode (703), and performing a planarization process on all the metal electrodes (7) until the upper surface of the metal electrode (7) is flush with the upper surface of the silicon nitride waveguide (6); Depositing a first bonding SiO2 layer (303) on the upper surfaces of the metal electrode (7) and the silicon nitride waveguide (6) and performing a planarization process on the first bonding SiO2 layer (303); If the heterogeneous bonding layer (11) is bonded to the first bonding SiO2 layer (303), bonding the heterogeneous bonding layer (11) is performed by a first sub-method; If the heterogeneous bonding layer (11) is bonded to the bottom of the second etching groove, the heterogeneous bonding layer (11) is bonded by a second sub-method, and the metal electrode (7) is processed.

11. The manufacturing method according to claim 10, characterized in that: Bonding the heterogeneous bonding layer (11) by a first sub-method comprises: Etching above the metal electrode (7) to expose a pin pad PAD (8); The heterogeneous bonding layer (11) is processed and bonded to the first bonding SiO2 layer (303).

12. The manufacturing method according to claim 10, characterized in that: Bonding the heterogeneous bonding layer (11) and processing the metal electrode (7) by a second sub-method includes: Depositing a sacrificial layer on the top surface of the first bonding SiO2 layer (303), etching the sacrificial layer, depositing a sixth filling dielectric SiO2 layer (308) on the sacrificial layer and performing a planarization process on the sixth filling dielectric SiO2 layer (308), wherein the first bonding SiO2 layer (303) and the sixth filling dielectric SiO2 layer (308) constitute the SiO2 cladding layer (3); Etching and depositing a metal via (13) on the SiO2 cladding layer (3), and performing a planarization process on the metal via (13); Depositing a seventh filling dielectric SiO2 layer (309) on the metal via hole Via (13); Etching a metal groove on the seventh filling dielectric SiO2 layer (309), and filling the metal in the metal groove to generate a second layer of the first metal electrode (701) and a second layer of the second metal electrode (702), and performing a planarization process on the second layer of the first metal electrode (701) and the second layer of the second metal electrode (702), wherein the sixth filling dielectric SiO2 layer (308) and the seventh filling dielectric SiO2 layer (309) constitute the SiO2 cladding layer (3); Etching above the first metal electrode (701) of the second layer and the second metal electrode (702) of the second layer to expose a pin pad PAD (8); Etching the second etching groove in the area of ​​the SiO2 cladding layer (3) that does not include the metal electrode (7), exposing the sacrificial layer, stopping etching, and removing the sacrificial layer; The heterogeneous bonding layer (11) is processed and bonded to the first bonding SiO2 layer (303) at the bottom of the second etching groove.

13. The manufacturing method according to claim 9, characterized in that: Based on the multifunctional SOI wafer, the metal electrode (7) and the dielectric waveguide are prepared by a second processing method, and processed into the silicon photonic chip platform, including: Processing and preparing a Si waveguide (503) on the multifunctional SOI wafer, filling a third filling medium SiO2 layer (304) and performing a planarization process; Depositing silicon nitride on the third filling dielectric SiO2 layer (304), etching the silicon nitride to form a silicon nitride waveguide (6), depositing the third filling dielectric SiO2 layer (304) on the silicon nitride waveguide (6), and performing a planarization process on the third filling dielectric SiO2 layer (304); Etching a metal groove on the SiO2 cladding layer (3) of the multifunctional SOI wafer, and filling the metal in the metal groove to generate a third metal electrode (703), and performing a planarization process on the third metal electrode (703) until the upper surface of the third metal electrode (703) is flush with the upper surface of the silicon nitride waveguide (6); Depositing a second bonding SiO2 layer (305) on the upper surface of the third metal electrode (703) and the silicon nitride waveguide (6); Depositing a sacrificial layer on the top surface of the second bonding SiO2 layer (305), etching the sacrificial layer, depositing a fourth filling dielectric SiO2 layer (306) on the sacrificial layer and performing a planarization process on the fourth filling dielectric SiO2 layer (306), depositing a titanium nitride resistance layer (10), and etching the titanium nitride resistance layer (10); Filling the fourth filling dielectric SiO2 layer (306) and performing a planarization process, wherein the second bonding SiO2 layer (305) and the fourth filling dielectric SiO2 layer (306) constitute the SiO2 cladding layer (3); Etching and depositing a metal via (13) on the SiO2 cladding layer (3), and performing a planarization process on the metal via (13); Depositing a fifth filling dielectric SiO2 layer (307) on the metal via hole Via (13); Etching a metal groove on the fifth filling dielectric SiO2 layer (307), filling the metal groove with metal to generate a first metal electrode (701) and a second metal electrode (702), and performing a planarization process on the first metal electrode (701) and the second metal electrode (702); Etching above the first metal electrode (701) and the second metal electrode (702) to expose a pin pad PAD (8); Etching the first etching groove on the fifth filling dielectric SiO2 layer (307) to expose the sacrificial layer, stop etching, and remove the sacrificial layer; The heterogeneous bonding layer (11) is processed and bonded to the second bonding SiO2 layer (305) at the bottom of the first etching groove.

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