A phase change memory material, device, and in-memory computing array with wide temperature range and low resistance drift

Abstract

This invention discloses a phase change memory material, device, and in-memory computing array with wide temperature range and low resistance drift. The phase change memory material contains chromium (Cr) and tellurium (Te), with the chemical formula Cr. x Te 100‑x Where 0 < x < 100; the resistivity drift coefficients of both the amorphous and crystalline thin films of the phase change memory material are ≤0.002 in the temperature range of -200 to 200℃. The local structure of the amorphous phase of the phase change memory material of the present invention is mainly octahedral, without obvious Pell's distortion, and can maintain an ultra-low resistivity drift coefficient over a wide temperature range, overcoming the resistivity drift problem in existing phase change memory technologies, especially the problem of complicated resistivity drift behavior under wide temperature range operating conditions.

Description

Technical Field

[0001] This invention relates to the field of non-volatile memory technology, specifically to a phase change memory material, device, and in-memory computing array with wide temperature range and low resistance drift. Background Technology

[0002] Phase-change memory (PCM) technology utilizes the rapid, reversible phase transition between the amorphous and crystalline phases of a phase-change material and the significant resistance difference to switch between logic values ​​"0" (RESET state) and "1" (SET state) for data storage. Furthermore, the large resistance window between the SET and RESET states in PCM (e.g., the resistance window of commercially available germanium-antimony-tellurium PCM can reach 3-6 orders of magnitude) allows multiple identifiable resistance values ​​to be obtained within the same storage cell through gradual phase transitions. This breaks through the limitations of binary storage, enabling "multi-value storage" and "in-memory computing" technologies. In-memory computing refers to constructing a storage cell array and directly solving matrix-vector multiplication using electrical measurements, which can significantly improve computing power. The more identifiable logic values ​​a single storage cell has, the higher the array's computational efficiency.

[0003] However, the spontaneous structural relaxation of amorphous phase change materials causes the resistance of the device to continuously increase over time, i.e., resistance drift. The amorphous germanium-antimony-tellurium alloy exhibits a drift coefficient as high as 0.11 at room temperature. This phenomenon severely affects the coding accuracy of in-memory computing devices, leading to a high bit error rate. It also limits the number of logic values ​​that a single memory node can recognize, making it one of the main bottlenecks for improving the computing power of phase change in-memory computing chips. Furthermore, memory chips operate over extremely wide temperature ranges in different service environments. For example, the operating temperature of chips in servers and data centers is typically 60–80°C, while in automotive embedded environments it ranges from -40 to 165°C. In the external environment of the International Space Station, the operating temperature needs to cycle between -120°C and 120°C 16 times per day. This wide and diverse operating temperature range makes the resistance drift phenomenon of phase change memories more complex and difficult to compensate for through external conditions such as software algorithms and circuit design. Therefore, there is an urgent need to develop a phase change memory material with intrinsically low resistance drift characteristics over a wide temperature range. Summary of the Invention

[0004] To overcome the shortcomings of the existing technologies, this invention proposes a phase change memory material, device, and in-memory computing array with low resistance drift over a wide temperature range. The amorphous phase local structure of this phase change memory material is mainly octahedral, and there is no obvious Pearse distortion. It can maintain an ultra-low resistance drift coefficient over a wide temperature range, overcoming the resistance drift problem in existing phase change memory technologies, especially the problem of complicated resistance drift behavior under wide temperature operating conditions.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0006] A phase change memory material with a wide temperature range and low resistance drift, chemical formula Cr x Te 100-x , where 0 < x < 100;

[0007] The resistivity drift coefficients of both the amorphous and crystalline thin films of the phase change storage material are ≤0.002 in the temperature range of -200 to 200℃.

[0008] The crystal phase structure of the phase change storage material has a layered structure feature. In the intralayer structure, Cr atoms and Te atoms form a local [CrTe6] octahedral structure, and the octahedral structures are connected by sharing corners and edges. The interlayer structure is mainly connected by van der Waals forces.

[0009] In the amorphous phase structure of the phase change storage material, most Cr atoms form a [CrTe6] octahedral local structure with Te atoms, and the remaining Cr atoms form a defective octahedral local structure. The octahedral or defective octahedral structures are randomly distributed and connected to each other.

[0010] The local structures of both the crystalline and amorphous phase change storage materials are dominated by [CrTe6] octahedra. The [CrTe6] octahedra have stable Cr-Te chemical bonds, and the bond lengths of the Cr-Te bonds along the same direction are basically the same, without obvious Pearce distortion.

[0011] The preparation methods of the phase change storage material include, but are not limited to, magnetron sputtering, chemical vapor deposition, atomic layer deposition, or electron beam evaporation.

[0012] The amorphous thin film of the phase change storage material has a crystallization temperature of 250–300°C and a data retention temperature of 130–190°C for ten years.

[0013] The amorphous phase of the phase change storage material is a high-resistivity state, with a resistance value typically around 5 × 10⁻⁶ at room temperature. 4 Ω ~ Approximately 1×10 6 Ω; the crystalline phase is a low-resistivity state, with a typical resistance of about 1 × 10⁻⁶ at room temperature. 3 Ω ~ Approximately 5 × 10 4 Ω; the resistance value varies with temperature and film thickness.

[0014] The phase change storage material can be applied to phase change memory and phase change memory-integrated arrays.

[0015] The phase-change memory device may employ a confined structure, including a substrate, which is a SiO2 / Si substrate, and on the substrate, a bottom electrode layer, an oxide dielectric layer, a phase-change memory material layer, and a top electrode layer are sequentially arranged; the bottom electrode layer and the top electrode layer are made of TiN or W, Cr, Cu, which are high electrical and thermal conductivity materials; the oxide dielectric layer is made of SiO2, which is a low electrical and thermal conductivity material.

[0016] The thickness of the bottom electrode layer, oxide dielectric layer, phase change storage material layer and top electrode layer is between 10 nm and 1000 nm. The phase change storage material layer is located in the middle of the through hole of the oxide dielectric layer. The through hole is cylindrical or columnar and is concentrically arranged with the oxide dielectric layer. The corresponding diameter or side length is between 10 nm and 1000 nm.

[0017] The device may be a T-type structure, including a substrate, which is a SiO2 / Si substrate, and on the substrate are, in sequence, a bottom electrode layer, an oxide dielectric layer, a heating electrode layer, a phase change storage material layer and a top electrode layer.

[0018] The bottom electrode layer, top electrode layer, and heating electrode layer are made of TiN or W, Cr, Cu, which are high electrical and thermal conductivity materials. The oxide dielectric layer is made of SiO2, which is low electrical and thermal conductivity material. The thickness of the bottom electrode layer, oxide dielectric layer, phase change storage material layer, top electrode layer, and heating electrode layer is between 10 nm and 1000 nm. The heating electrode layer is located in the middle of the through hole in the oxide dielectric layer. The through hole is cylindrical or columnar and is concentric with the oxide dielectric layer. The corresponding diameter or side length is between 10 nm and 1000 nm.

[0019] The functional layer material of the device is Cr. x Te 100-x Materials; Reversible SET and RESET operations of the device are achieved by applying current or voltage pulses, corresponding to the crystallization and amorphization processes of the phase change storage material thin film, respectively; Partial crystallization or partial amorphization of the functional layer thin film is achieved by adjusting the amplitude and pulse width of the pulse, resulting in different resistance states and corresponding to different logic values;

[0020] The resistance drift coefficient of the device is ≤0.002 for different resistance states within the temperature range of -200 to 200℃. The resistance drift coefficient can be expressed by the formula R=R0(t / t0). v An evaluation is performed, where R0 is the resistance at time t0, t is the test time, and v is the resistance drift coefficient.

[0021] The electrical pulse width range of the SET operation of the device is typically about 1 ns to 1000 ns, and the amplitude range is typically about 0.5 V to 7 V; the electrical pulse width range of the RESET operation is typically about 0.1 ns to 100 ns, and the amplitude range is typically about 3 V to 10 V; partial SET operation is performed when the device is in the RESET state, and its parameters can be adjusted proportionally according to the required number of intermediate resistance states; partial RESET operation is performed when the device is in the SET state, and its parameters can be adjusted proportionally according to the required number of intermediate resistance states; the phase change storage film in the device in both partial SET and partial RESET states is composed of a mixture of crystalline and amorphous phases, and different volume ratios of the two correspond to different resistance states.

[0022] A 4.5V electrical pulse with a pulse width of 80ns was applied to perform a RESET operation on the device unit, and the measured resistance of the device was approximately 2 × 10⁻⁶. 3 Ω, at this point it is in a low-resistance state; a partial SET operation is performed by applying an electrical pulse with a pulse width of 80ns and a voltage of 2.7V, and the measured resistance of the device is approximately 3×10 Ω. 4 Ω, at this point it is the first intermediate resistance state; a partial RESET operation is performed by applying an electrical pulse with a pulse width of 80ns and a voltage of 4V, and the measured resistance of the device is approximately 7×10 Ω. 4 Ω, at this point is the second intermediate resistance state.

[0023] The in-memory computing array is one of the following: crossbar structure, transistor-memristor cascade structure or three-dimensional stacked structure. The device unit structure in the array is one of the following: confined structure, T-structure or bridge structure.

[0024] The functional layer material of the device units in the array is Cr. x Te 100-x Materials; the logic state programming of the device units in the array is achieved by loading a current or voltage pulse of a certain amplitude and pulse width, which corresponds to the partial crystallization or partial amorphization of the functional layer film; the logic state reconstruction of the device units in the array can be achieved by SET or RESET operations, which corresponds to the complete crystallization or complete amorphization of the functional layer film;

[0025] The resistance drift coefficient of different logic states of the device units in the array is ≤0.002 in the temperature range of -200 to 200℃. The resistance drift coefficient can be expressed by the formula R=R0(t / t0). v An evaluation is performed, where R0 is the resistance at time t0, t is the test time, and v is the resistance drift coefficient.

[0026] The beneficial effects of this invention are:

[0027] Traditional phase change material germanium-antimony-tellurium (CHT) contains numerous germanium tetrahedral defects in its amorphous structure, and the bond lengths of chemical bonds along the same direction vary in local structures, forming long and short bonds. During structural relaxation, significant Pell's distortion occurs, leading to substantial resistivity drift. This invention proposes a Cr... x Te 100-x The phase change material does not contain germanium, and the local structural units in its amorphous phase are basically the same as those in the crystalline phase, both being dominated by [CrTe6] octahedra. The bond lengths of the Cr-Te bonds along the same direction are essentially the same, and there is no obvious Pearse distortion. This effectively decouples the direct relationship between structural relaxation and resistivity drift, therefore its amorphous thin film resistivity drift coefficient is ≤0.002. Furthermore, Cr... x Te 100-x The crystallization temperature of amorphous thin films of phase change materials can reach 250-300℃, which is much higher than that of germanium, antimony and tellurium at ~150℃. Therefore, their amorphous thin films have excellent thermal stability, and the resistance drift coefficient is ≤0.002 in the temperature range of -200 to 200℃.

[0028] Phase-change memory devices and in-memory computing arrays achieve multi-logic value programming by adjusting the volume ratio of crystalline to amorphous components in the functional layer thin film. However, resistance drift in the amorphous portion can lead to decoding errors in the logic values. The device and array proposed in this invention utilize Cr... x Te 100-x As a functional layer material, the amorphous thin film of the material has an ultra-low resistance drift coefficient over a wide temperature range. Therefore, the resistance drift coefficient of different logic states of the device unit is ≤0.002 in the temperature range of -200 to 200℃, which effectively improves the programming and read / write accuracy of the logic state. It is expected to expand the storage density of phase change devices and the array scale of in-memory computing, while also widening the operating temperature range of the device and array, and maintaining high accuracy and consistency of operation programming and data recognition under various service temperatures.

[0029] The Cr proposed in this invention x Te 100-x Phase change memory materials, devices, and in-memory computing arrays can be fabricated using methods including, but not limited to, magnetron sputtering, chemical vapor deposition, atomic layer deposition, or electron beam evaporation. The fabrication methods for devices and arrays can include, but are not limited to, ultraviolet exposure, electron beam lithography, dry etching, or wet etching. All of these methods are compatible with existing mature CMOS semiconductor processing technologies, making it easy to achieve large-scale integration and engineering fabrication. They have broad application prospects and significant application value in the fields of data-intensive multi-value storage, embedded non-volatile storage, in-memory computing, and neuron-inspired brain-like computing. Attached Figure Description

[0030] Figure 1 For Cr x Te 100-xThe atomic model of the crystal structure.

[0031] Figure 2 For Cr x Te 100-x The amorphous atomic model.

[0032] Figure 3 For Cr x Te 100-x Resistance-temperature curves of phase change thin films.

[0033] Figure 4 For Cr x Te 100-x Resistance drift curves of phase change thin films were measured in multiple temperature regions.

[0034] Figure 5 For Cr x Te 100-x Ten years of data retention temperature testing for phase change thin films.

[0035] Figure 6 For Cr x Te 100-x A cross-sectional schematic diagram of a restricted electronic device unit.

[0036] Figure 7 For Cr x Te 100-x A cross-sectional schematic diagram of a T-shaped electronic device unit.

[0037] Figure 8 For Cr x Te 100-x Schematic diagram of a phase change device array.

[0038] 1—Top electrode layer of the confined phase change device; 2—Phase change material layer; 3—Oxide dielectric layer; 4—Bottom electrode layer; 5—Heating electrode layer. Detailed Implementation

[0039] The present invention will now be described in further detail with reference to the accompanying drawings.

[0040] Figure 1 For Cr x Te 100-x The atomic model of the crystal structure is shown, where the basic unit of the local structure is the [CrTe6] octahedron, and the crystal structure is composed of multiple [CrTe6] octahedron structures connected in a shared corner and shared edge manner. The bond lengths of Cr-Te bonds along the same direction are basically the same, and there is no obvious Pell's distortion.

[0041] Figure 2 For Cr x Te 100-xThe amorphous atomic model shows that most Cr atoms form a local structure of [CrTe6] octahedron with Te, and the bond lengths of Cr-Te bonds along the same direction are basically the same, with no obvious Pearce distortion.

[0042] Figure 3 For Cr x Te 100-x Resistance-temperature curves of phase change thin films, using Cr prepared by magnetron sputtering. 25 Te 75 The phase change thin film is in a low-resistivity state upon deposition. When the heating temperature reaches approximately 270°C, the resistance increases sharply, indicating the film begins to crystallize. The temperature drops to room temperature when heated to 350°C. Comparing the resistance values ​​before and after annealing, the difference between the crystalline and amorphous states is approximately one order of magnitude, indicating that the crystalline state exhibits high resistance. The entire test was conducted using a two-point method with a heating rate of 10°C / min.

[0043] Figure 4 For Cr x Te 100-x Resistance drift curves of phase change thin films in multiple temperature regions. For deposited Cr... 25 Te 75 The phase change thin film was subjected to resistance-time testing to monitor the change in resistance over time and fit the results. It was confirmed that its drift coefficient was ≤0.002 in multiple temperature ranges, including -150 to 150℃, which is about two orders of magnitude lower than the drift coefficient of the traditional germanium-antimony-tellurium alloy amorphous state, proving that the material has extremely low resistance drift.

[0044] Figure 5 For Cr x Te 100-x Ten years of data on phase change thin films were maintained using temperature profiles. Resistance-time tests were performed at four known temperature points below the crystallization temperature to obtain the relationship between resistance failure time and temperature. Resistance failure time refers to the time required for the material's resistance to decrease to half its initial value when held at a constant temperature. The resistance failure time and temperature were fitted using the Arrhenius equation to obtain the Cr... x Te 100-x The phase change thin film maintained a temperature of approximately 162°C over ten years, which is about 70°C higher than the amorphous drift coefficient of traditional germanium-antimony-tellurium alloys, demonstrating that the material has high amorphous thermal stability.

[0045] Figure 6 For Cr x Te 100-xA cross-sectional schematic diagram of the confinement device unit. The substrate is a SiO2 / Si substrate. Above the substrate, in sequence, are a bottom electrode layer 1, an oxide dielectric layer 2, a phase change memory material layer 3, and a top electrode layer 4. The bottom electrode layer 1 and the top electrode layer 4 are typically made of high-conductivity and high-thermal-conductivity materials such as TiN, W, Cr, and Cu; the oxide dielectric layer 2 is typically made of low-conductivity and low-thermal-conductivity materials such as SiO2. The thickness of these materials is typically between 10 nm and 1000 nm. The diameter of the phase change memory material layer 3 is typically between 10 nm and 1000 nm.

[0046] Figure 7 For Cr x Te 100-x A cross-sectional schematic diagram of a T-type device unit. The substrate is a SiO2 / Si substrate. Above the substrate, in sequence, are a bottom electrode layer 1, an oxide dielectric layer 2, a heating electrode layer 5, a phase change storage material layer 3, and a top electrode layer 4. The materials of the bottom electrode layer 1, top electrode layer 4, and heating electrode layer 5 are typically high-conductivity and high-thermal-conductivity materials such as TiN, W, Cr, and Cu; the oxide dielectric layer 2 is typically a low-conductivity and low-thermal-conductivity material such as SiO2. The thickness of the bottom electrode layer 1, oxide dielectric layer 2, phase change storage material layer 3, and top electrode layer 4 is typically between 10 nm and 1000 nm. The diameter of the heating electrode layer 5 is typically between 10 nm and 1000 nm.

[0047] Figure 8 For Cr x Te 100-x A schematic diagram illustrating phase-change memory materials suitable for in-memory computing arrays. The top and bottom electrodes of the device cells are arranged in a cross pattern, forming word lines, bit lines, and source lines. The array size can be expanded in a planar direction.

[0048] The phase change memory material is stored in the device array as conductivity information through a write operation. Voltage is used as the input quantity, and according to Kirchhoff's laws, the final current output value is the result of matrix-vector multiplication. Since Cr... x Te 100-x Phase change storage materials possess the characteristics of low drift across multiple temperature zones, thereby enabling high-precision edge computing and storage applications.

[0049] The present invention will be further illustrated below with specific embodiments.

[0050] Example 1

[0051] This embodiment uses Cr 30 Te 70 Taking the magnetron sputtering preparation and electrical property measurement of phase change thin films as an example, the specific process is as follows:

[0052] The chemical formula Cr was prepared by dual-target co-sputtering using Cr and Te elemental targets.30 Te 70 Phase change thin films were obtained. The Cr elemental target was sputtered using a DC power supply of 20W, while the Te elemental target was sputtered using an RF power supply of 37W for 20 minutes, resulting in a film thickness of ~200nm. Subsequently, a protective layer of approximately 10nm thickness was uniformly sputtered onto the film surface using a ZnS-SiO2 target to prevent damage to the film introduced during subsequent testing.

[0053] The resistance-temperature (RTT) of the thin film was performed using a digital source meter and an in-situ hot-cold stage. Resistance was measured by applying a voltage and measuring the current using the digital source meter; the test voltage was 0.1V. Temperature was controlled using the in-situ hot-cold stage, with a heating rate of 10℃ / min, heating to 350℃, and then cooling to room temperature at a cooling rate of 20℃ / min. The measured RTT curves are shown below. Figure 3 As shown, the crystallization temperature of the thin film is approximately 270℃, and the resistivity of the deposited and annealed states are approximately 8 × 10⁻⁶. 3 Ω and ~9×10 4 Ω, the resistance value changes in the reverse direction during crystallization. Subsequently, the same batch of films were used to conduct a ten-year data retention test. Resistance-time tests were performed at 245℃, 250℃, 255℃ and 260℃ respectively. The resistance failure was judged by a 50% change in resistance. The Arrhenius formula was used for fitting, and the ten-year data retention of the film was found to be ~162℃.

[0054] Example 2

[0055] This embodiment uses Cr 30 Te 70 Taking the fabrication and electrical performance testing of a restricted phase-change memory device cell as an example, the specific process is as follows:

[0056] The phase-change memory device cell is fabricated on a substrate (SiO2 / Si, SiO2 thickness approximately 300 nm), including a bottom electrode layer (W, approximately 200 nm thick), a dielectric layer (SiO2, approximately 100 nm thick), and a functional layer (Cr). 30 Te 70 The top electrode layer (W, approximately 50 nm thick) and the top electrode layer (W, approximately 200 nm thick), as shown in the attached diagram. Figure 6 As shown. All the above layers were deposited using magnetron sputtering. W was deposited using a DC power supply of 80W for 80 minutes; SiO2 was deposited using an RF power supply of 50W for 92 minutes; Cr... 30 Te 70 The Cr and Te targets were co-sputtered, with Cr using a DC power supply of 20W and Te using an RF power supply of 37W. The preparation time was 5 minutes.

[0057] The electrical performance of the above-mentioned device unit was tested using an electrical test probe station, a digital source meter, and a pulse signal generator. First, a DC test was performed on the device unit in its initial state to perform a SET operation, and the measured resistance value was approximately 3 × 10⁻⁶. 5 Ω, at this point the phase change storage film in the device is an amorphous phase. Comparing the resistance values ​​before and after the operation, it is confirmed that the initial state is a low-resistance state and the SET state is a high-resistance state. An electrical pulse with a pulse width of 80ns and a voltage of 4.5V is applied to the device unit for a RESET operation, and the measured device resistance is approximately 2 × 10⁻⁶. 3 Ω, at this point the phase change storage film in the device is a crystalline phase, and the RESET state is a low-resistance state; if an electrical pulse with a pulse width of 80ns and a voltage of 2.7V is applied in the RESET state to perform a partial SET operation, the measured resistance of the device is approximately 3×10 Ω. 4 Ω, at this point the phase change storage film in the device is in the first intermediate resistance state; if a partial RESET operation is performed in the SET state by applying an electrical pulse with a pulse width of 80ns and a voltage of 4V, the measured resistance of the device is approximately 7 × 10 Ω. 4 Ω, at this point, is the second intermediate resistance state. After partial SET and partial RESET operations, the phase change storage film in the device exists as a mixture of crystalline and amorphous phases, but with different volume ratios, thus resulting in different resistance states. The resistance values ​​of the SET state, RESET state, and two intermediate resistance states were measured at room temperature using an electrical probe station and a digital source meter for 1 hour. Based on the measurement results, the resistance drift coefficients of the four resistance states were all ≤0.002.

[0058] Example 3

[0059] This embodiment uses Cr-based 30 Te 70 The fabrication of a reconfigurable phase-change memory-computing array based on a T-structure device unit and its electrical performance testing at different temperatures are illustrated in the following details:

[0060] The device units in the reconfigurable phase-change in-memory computing array have a T-shaped structure and are fabricated on a substrate (SiO2 / Si, SiO2 thickness approximately 300 nm). They include a bottom electrode layer (W, approximately 200 nm thick), a heating electrode layer (W, via diameter approximately 200 nm), a dielectric layer (SiO2, approximately 100 nm thick), and a functional layer (Cr). 30 Te 70 The top electrode layer (W, approximately 50 nm thick) and the top electrode layer (W, approximately 200 nm thick) are shown in the attached diagram. Figure 7 As shown. Devices are interconnected via an array of word lines, bit lines, and source lines, as detailed in the attached diagram. Figure 8 As shown.

[0061] The fabricated device array was placed in an environment of 200°C, and SET, partial SET, RESET, and partial RESET operations were performed on the device cells at specified sites in the device array. The resistance values ​​of the SET state and RESET state of the device differed by more than an order of magnitude, and the resistance values ​​of the partial SET state and partial RESET state were between the SET state and RESET state. The resistance drift coefficient of all four resistance states was ≤0.002 within one hour.

[0062] The fabricated device array was placed in an environment of -200℃, and SET, partial SET, RESET, and partial RESET operations were performed on the device cells at specified sites in the device array. The resistance values ​​of the SET state and RESET state of the device differed by more than an order of magnitude, and the resistance values ​​of the partial SET state and partial RESET state were between the SET state and RESET state. The resistance drift coefficient of all four resistance states was ≤0.002 within one hour.

Claims

1. A phase change memory material with wide temperature range and low resistance drift, characterized in that, The chemical formula is Cr x Te 100-x , where 0 < x < 100; The resistivity drift coefficients of the amorphous and crystalline thin films of the phase change storage material are both ≤0.002 in the temperature range of -200~200℃. The crystal phase structure of the phase change storage material has a layered structure feature. In the intralayer structure, Cr atoms and Te atoms form a [CrTe6] octahedral local structure, and the octahedral structures are connected by sharing corners and edges; the interlayer structure is connected by van der Waals forces. In the amorphous phase structure of the phase change storage material, most Cr atoms form a [CrTe6] octahedral local structure with Te atoms, and the remaining Cr atoms form a defective octahedral local structure. The octahedral or defective octahedral structures are randomly distributed and connected to each other. The local structures of both the crystalline and amorphous phase change storage materials are dominated by [CrTe6] octahedra. The [CrTe6] octahedra have stable Cr-Te chemical bonds, and the bond lengths of the Cr-Te bonds are the same along the same direction, without obvious Pearce distortion. The amorphous thin film of the phase change storage material has a crystallization temperature of 250~300℃ and a data retention temperature of 130~190℃ for ten years.

2. The phase change memory material with wide temperature range and low resistance drift according to claim 1, characterized in that, The amorphous phase of the phase change memory material is a high-resistivity state, with a resistance of 5 × 10⁻⁶ at room temperature. 4 Ω~1×10 6 Ω; the crystalline phase is a low-resistivity state, with a resistance of 1×10⁻⁶ at room temperature. 3 Ω~5×10 4 Ω; the resistance value varies with temperature and film thickness.

3. A phase-change memory, characterized in that, The phase change storage material layer (3) of the device is the phase change storage material described in claim 1; When the device is selected as a confined structure, it includes a substrate, and on the substrate are, in sequence, a bottom electrode layer (1), an oxide dielectric layer (2), a phase change storage material layer (3) and a top electrode layer (4). The thickness of the bottom electrode layer (1), oxide dielectric layer (2), phase change storage material layer (3) and top electrode layer (4) is between 10 nm and 1000 nm. The phase change storage material layer (3) is located in the middle of the through hole of the oxide dielectric layer (2). The through hole is cylindrical or columnar and is concentrically set with the oxide dielectric layer (2). The corresponding diameter or side length is between 10nm and 1000nm. When the device adopts a T-type structure, it includes a substrate, which is a SiO2 / Si substrate, and on the substrate are, in sequence, a bottom electrode layer (1), an oxide dielectric layer (2), a heating electrode layer (5), a phase change storage material layer (3), and a top electrode layer (4). The thicknesses of the bottom electrode layer (1), oxide dielectric layer (2), phase change storage material layer (3), top electrode layer (4) and heating electrode layer (5) are between 10 nm and 1000 nm, respectively. The heating electrode layer (5) is disposed in the middle of the through hole of the oxide dielectric layer (2). The through hole is cylindrical or columnar and is concentric with the oxide dielectric layer (2). The corresponding diameter or side length is between 10 nm and 1000 nm.

4. The phase-change memory according to claim 3, characterized in that, The device's SET and RESET reversible operations are achieved by applying current or voltage pulses, corresponding to the crystallization and amorphization processes of the phase change storage material thin film, respectively; by adjusting the pulse amplitude and pulse width, the functional layer thin film is partially crystallized or partially amorphized, resulting in different resistance states corresponding to different logic values. The resistance drift coefficient of the device is ≤0.002 for all different resistance states within the temperature range of -200~200℃. The resistance drift coefficient is expressed by the formula R=R0(t / t0). v An evaluation is performed, where R0 is the resistance at time t0, t is the test time, and v is the resistance drift coefficient.

5. A storage-computing integrated array, characterized in that, The functional layer material of the in-memory computing array is the phase change storage material described in claim 1; it is one of a crossbar structure, a transistor-memristor cascade structure, or a three-dimensional stacked structure, and the device unit structure in the array is one of a confined structure, a T-structure, or a bridge structure. The logic state programming of the device units in the array is achieved by applying current or voltage pulses with varying amplitudes and pulse widths, which corresponds to the partial crystallization or partial amorphization of the functional layer thin film; the logic state reconstruction of the device units in the array is achieved by SET or RESET operations, and the logic state programming process corresponds to the complete crystallization or complete amorphization of the functional layer thin film. The resistance drift coefficients of different logic states of the device units in the array are all ≤0.002 in the temperature range of -200~200℃. The resistance drift coefficient is expressed by the formula R=R0(t / t0). v An evaluation is performed, where R0 is the resistance at time t0, t is the test time, and v is the resistance drift coefficient.

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