Verification method and device, electronic equipment and storage medium
By dividing the code file to be verified into two parts with different module timing requirements, and verifying them in software and hardware simulation environments respectively, the problems of low verification accuracy and long verification cycle in the existing technology are solved, and efficient and accurate simulation verification is achieved.
CN119862826AActive Publication Date: 2025-04-22BEIJING INSTITUTE OF OPEN SOURCE CHIP
6 Cites 1 Cited by
Patent Information
- Application Number
- CN202510350529.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-24
- Publication Date
- 2025-04-22
- Estimated Expiration
- 2045-03-24
AI Technical Summary
Technical Problem
In the simulation verification of chip codes in the prior art, the verification accuracy of timing problems is low, the verification cycle is long, and the debugging performance is poor.
Method used
By dividing the code file to be verified into the first code file and the second code file according to the module timing requirements, it is verified in the software simulation environment and the hardware simulation environment respectively, and the flexibility of software simulation verification and the high precision of hardware simulation verification are used.
Benefits of technology
High-precision verification of timing problems is achieved, debugging process is simplified, verification efficiency is improved, and the limitations of a single verification method are avoided.
✦ Generated by Eureka AI based on patent content.
Abstract
The embodiment of the invention provides a verification method and device, electronic equipment and a storage medium, and the method comprises the steps: dividing a to-be-verified code file into a first code file and a second code file based on a module time sequence requirement corresponding to each module in the to-be-verified code file; the module time sequence requirement of the first module contained in the first code file is lower than the module time sequence requirement of the second module contained in the second code file; compiling the first code file into an executable file, and performing software simulation verification in a software simulation environment based on the executable file; deploying a target bit file corresponding to the second code file to a specified chip, and performing hardware simulation verification in a hardware simulation environment based on the specified chip; and the software simulation environment and the hardware simulation environment perform bidirectional data synchronization based on the target communication interface. A software and hardware combined verification mode is adopted, the verification effect is improved, the verification advantages of the two verification modes are considered at the same time, and the method has the advantages of being convenient to debug and high in verification precision.
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