Semiconductor manufacturing method and semiconductor structure

Abstract

The invention relates to a semiconductor manufacturing method and a semiconductor structure, and belongs to the technical field of semiconductors. The semiconductor manufacturing method comprises the following steps: providing a first semiconductor substrate; forming a first dielectric layer over the first semiconductor substrate; patterning the first dielectric layer to form a first groove; depositing metal on the first dielectric layer to form a metal filling part filled in the first groove and a metal covering layer higher than the plane where the top of the first dielectric layer is located; executing a planarization process to remove the metal covering layer, and enabling the top of the metal filling part to be flush with the top of the first dielectric layer; and forming a first hard mask layer covering the first dielectric layer and the metal filling part. By optimizing the manufacturing process, the defects such as surface depression are avoided, meanwhile, the risk of cracking caused by mismatching of thermal expansion is reduced, and the reliability of the semiconductor device is improved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a semiconductor manufacturing method and a semiconductor structure. Background Art

[0002] Since the advent of Moore's Law, the density of microelectronic devices has developed almost in line with the predictions of Moore's Law. In order to increase circuit density, microelectronics manufacturing has developed from two-dimensional to three-dimensional. One of the methods is to stack chips and then package them, which has led to the emergence of three-dimensional circuit packaging technology (3D IC packaging).

[0003] With the help of three-dimensional packaging technology, the top wafer (Top Wafer) and the bottom wafer (Bottom Wafer) are bonded and connected, and the top metal (Top Metal) is electrically connected to the outside world through TSV technology. In the existing technology, first, a top metal is formed on the substrate, and a dielectric layer is deposited on the top metal, and then a planarization process is performed to form a flat surface to facilitate subsequent bonding with the upper wafer.

[0004] However, since the top metal layer is usually several microns in height, there is a large height difference between the top metal layer and the substrate. During the dielectric layer deposition process, the dielectric layer deposited on the top metal layer will form a large step. During the subsequent planarization of the dielectric layer, an oxide recess will be formed, resulting in defects such as bubbles (Bonding bubbles) on the bonding surface. In addition, the top metal layer and the oxide dielectric layer have different thermal expansion coefficients (Coefficient of Thermal Expansion). During the heating process, the sharper part where the top of the top metal layer contacts the surrounding oxide dielectric layer is prone to metal / oxide thermal expansion mismatch (Metal / Oxide CTE mismatch), resulting in cracking and other problems, which in turn affects the reliability of semiconductor devices. Summary of the invention

[0005] In view of the shortcomings existing in the related art, the present invention provides a semiconductor manufacturing method and a semiconductor structure. By optimizing the manufacturing process, a flat surface can be obtained even if a top metal layer is formed and there is a height difference. The risk of cracking due to thermal expansion mismatch is reduced, thereby improving the reliability of semiconductor devices.

[0006] The present application provides a semiconductor manufacturing method, comprising at least the following steps: providing a first semiconductor substrate; forming a first dielectric layer over the first semiconductor substrate; patterning the first dielectric layer to form a first trench; Depositing metal on the first dielectric layer to form a metal filling portion filled in the first trench and a metal capping layer higher than the plane where the top of the first dielectric layer is located; performing a planarization process to remove the metal capping layer and make the top of the metal filling part flush with the top of the first dielectric layer; A first hard mask layer is formed overlying the first dielectric layer and the metal filling portion.

[0007] In some embodiments, the manufacturing method further comprises the following steps: forming a second dielectric layer over the first hard mask layer; Performing a patterning process to form a second trench penetrating to the metal filling portion; Filling the second trench with metal to form a first metal external connection portion.

[0008] In some embodiments, the manufacturing method further comprises the following steps: providing a second semiconductor substrate; forming a third dielectric layer over the second semiconductor substrate; performing a patterning process to form a third trench; Filling metal into the third trench to form a second metal external connection portion; The first semiconductor substrate and the second semiconductor substrate are bonded and connected, and the first metal external connection portion is butted against the second metal external connection portion.

[0009] In some embodiments, before forming the second trench, the method further includes: forming a first bonding layer on the second dielectric layer, wherein the second trench penetrates from the first bonding layer to the metal filling portion; Before forming the third trench, the method further includes: forming a second bonding layer on the third dielectric layer, wherein the third trench extends from the second bonding layer to the third dielectric layer; The first bonding layer and the second bonding layer are bonded to connect the first semiconductor substrate to the second semiconductor substrate.

[0010] In some embodiments, before forming a third dielectric layer on the second semiconductor substrate, the method further includes: forming a fourth dielectric layer over the second semiconductor substrate; forming a bonding pad in the fourth dielectric layer; forming a second hard mask layer over the fourth dielectric layer; The third dielectric layer is formed on the second hard mask layer, and the third trench passes through to the bonding pad.

[0011] In some embodiments, the manufacturing method further comprises: forming a fourth trench penetrating to the bonding pad on a side of the second semiconductor substrate away from the second metal external connection portion; The fourth trench is filled with metal to form a third metal external connection.

[0012] In some embodiments, the materials of the first dielectric layer, the second dielectric layer, the third dielectric layer, and the fourth dielectric layer are all silicon dioxide.

[0013] In some embodiments, materials of the first bonding layer and the second bonding layer are both nitride-doped silicon carbide.

[0014] The present application also provides a semiconductor structure, which is manufactured by using any of the semiconductor manufacturing methods described above, and the semiconductor structure includes: a first semiconductor substrate; forming a first dielectric layer over a first semiconductor substrate; A metal filling portion is formed in the first dielectric layer, wherein a top of the metal filling portion is flush with a top of the first dielectric layer; A first hard mask layer is formed over the first dielectric layer.

[0015] In some embodiments, a second dielectric layer is further formed on the first hard mask layer, and a first metal external connection portion extending to the metal filling portion is formed in the second dielectric layer; It also includes a second semiconductor substrate bonded to the first semiconductor substrate, a fourth dielectric layer, a second hard mask layer and a third dielectric layer are sequentially formed on the side of the second semiconductor substrate facing the first semiconductor substrate, a bonding pad is formed in the fourth dielectric layer, and a second metal external portion connecting the first metal external portion and the bonding pad is formed in the third dielectric layer.

[0016] Compared with the prior art, the advantages and positive effects of the present invention are: (1) The semiconductor manufacturing method provided in at least one embodiment of the present application improves the process to planarize the metal covering layer, thereby avoiding the problem of depression caused by directly planarizing the first dielectric layer with a large height difference. Since the metal planarization process is easier to control and implement, after the planarization process, the top of the metal filling part and the top of the first dielectric layer are basically flush, and no defects such as depressions will occur.

[0017] (2) The semiconductor manufacturing method provided in at least one embodiment of the present application adjusts the process so that the metal filling portion and the top of the first dielectric layer are located on the same plane, without the phenomenon of the top metal protruding into the dielectric layer as in the prior art, thereby reducing the probability of cracking in this portion and improving the reliability of the semiconductor device.

[0018] (3) The semiconductor structure provided by at least one embodiment of the present application has a flat top surface, which avoids the formation of bonding bubble defects in the subsequent packaging process and improves the strength and reliability of the bonding connection; moreover, the metal filling portion and the top of the first dielectric layer are located on the same plane and are covered with a first hard mask layer. The first hard mask layer can absorb part of the deformation and offset part of the expansion difference, thereby reducing the probability of cracking problems in this part and improving the reliability of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of this application. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings: Figure 1 is a schematic diagram of a semiconductor structure in the prior art; Figure 2 A flow chart of each step for a first semiconductor substrate in a semiconductor manufacturing method provided in an embodiment of the present application; Figure 3 A flow chart of the steps of the second semiconductor substrate and its bonding with the first semiconductor substrate in the semiconductor manufacturing method provided in the embodiment of the present application; Figure 4a is a cross-sectional view of a semiconductor structure after the semiconductor manufacturing method provided in an embodiment of the present application performs step S103; Figure 4b is a cross-sectional view of a semiconductor structure after the semiconductor manufacturing method provided in an embodiment of the present application performs step S104; Figure 4c is a cross-sectional view of a semiconductor structure after the semiconductor manufacturing method provided in an embodiment of the present application performs step S105; Figure 4d is a cross-sectional view of a semiconductor structure after the semiconductor manufacturing method provided in an embodiment of the present application performs step S106; Figure 4e is a cross-sectional view of a semiconductor structure after the semiconductor manufacturing method provided by an embodiment of the present application executes step S107; Figure 4f is a cross-sectional view of a semiconductor structure after the semiconductor manufacturing method provided in an embodiment of the present application performs step S108; Figure 4g is a cross-sectional view of a semiconductor structure after the semiconductor manufacturing method provided in an embodiment of the present application performs step S109; Figure 5 A cross-sectional view of a second semiconductor substrate obtained by the semiconductor manufacturing method provided in an embodiment of the present application; Figure 6This is a cross-sectional view of a first semiconductor substrate and a second semiconductor substrate bonded together according to the semiconductor manufacturing method provided in an embodiment of the present application.

[0020] In the figure: 100', top metal layer; 200', dielectric layer; 300, first semiconductor substrate; 301, first dielectric layer; 302, first trench; 303, metal filling part; 304, metal covering layer; 305, first hard mask layer; 306, second dielectric layer; 307, second trench; 308, first metal external part; 309, first bonding layer; 400, second semiconductor substrate; 401, third dielectric layer; 402, second metal external part; 403, second bonding layer; 404, fourth dielectric layer; 405, bonding pad; 406, second hard mask layer; 407, third metal external part. DETAILED DESCRIPTION

[0021] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0022] Obviously, the drawings described below are only some examples or embodiments of the present application. For ordinary technicians in this field, the present application can also be applied to other similar scenarios based on these drawings without creative work. In addition, it can also be understood that although the efforts made in this development process may be complicated and lengthy, for ordinary technicians in this field related to the content disclosed in this application, some changes in design, manufacturing or production based on the technical content disclosed in this application are just conventional technical means, and should not be understood as insufficient content disclosed in this application.

[0023] Reference to "embodiments" in this application means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those of ordinary skill in the art that the embodiments described in this application may be combined with other embodiments without conflict.

[0024] It is worth to be understood that, although the accompanying drawings may show the specific order of method steps, the order of steps may be different from the order depicted. In addition, two or more steps may be performed simultaneously or partially simultaneously. All such variations are within the scope of the present disclosure.

[0025] The terms "first", "second", "third", "fourth" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. When a layer is referred to as being on another layer or "on" a substrate, it can be directly on the other layer or on the substrate, or intervening layers may also be present.

[0026] In the existing 3D packaging process, Figure 1 As shown, the usual manufacturing method is: first, a layer of metal is deposited on the semiconductor substrate; an etching process is performed to pattern the metal layer, and the patterned metal is used as the top metal 100' (Top Metal) for electrical connection with other wafers; then a dielectric layer 200' is deposited on the patterned metal layer; and a planarization process is performed on the surface of the dielectric layer 200', and then it is connected with other wafers.

[0027] However, since the top metal layer 100' is usually relatively high, about several microns, a large height difference occurs on the surface of the dielectric layer 200' deposited on the top metal layer 100'. Due to the characteristics of the dielectric material itself, it is very sensitive to polishing conditions and difficult to control by chemical reactions. The formation of such a height difference in the dielectric layer 200' makes it difficult to eliminate it during the subsequent flattening process of the dielectric layer 200', thereby forming uneven recesses on the surface of the dielectric layer 200', making it difficult to obtain a flat surface. These recesses can easily form bonding bubble defects on the bonding surface during the back-end bonding process, affecting the bonding effect and the performance of the semiconductor device.

[0028] In addition, the top metal layer 100' encapsulated in the dielectric layer 200' has a portion of the top thereof in contact with the surrounding dielectric layer 200' formed as a protruded metal protruding into the dielectric layer 200', such as Figure 1 As shown in the area circled by the oval in the middle. Since the metal and the oxide material constituting the dielectric layer 200' have different thermal expansion coefficients, the top metal 100' and the oxide material of the dielectric layer expand to different degrees during the heating process of the semiconductor device, resulting in the generation of internal stress, and then cracking, which affects the reliability of the semiconductor device.

[0029] Based on this, the present application proposes a semiconductor manufacturing method and a semiconductor structure. By optimizing the manufacturing process, the direct flattening process on the dielectric layer is avoided, and a flat surface can be obtained even without reducing the height difference of the front-end process. At the same time, the semiconductor structure is optimized to avoid the problem of cracking caused by the mismatch of thermal expansion of metal and oxide, thereby improving the electrical performance and reliability of semiconductor devices.

[0030] In an exemplary embodiment of the semiconductor manufacturing method provided in the present application, Figure 2 As shown, the semiconductor manufacturing method comprises at least the following steps: S101, providing a first semiconductor substrate; S102, forming a first dielectric layer on the first semiconductor substrate; S103, patterning the first dielectric layer to form a first trench; S104, depositing metal on the first dielectric layer to form a metal filling portion filled in the first trench and a metal covering layer higher than the plane where the top of the first dielectric layer is located; wherein the metal filling portion can function as a top metal; S105, performing a planarization process to remove the metal cover layer and make the top of the metal filling part flush with the top of the first dielectric layer; S106 , forming a first hard mask layer covering the first dielectric layer and the metal filling part.

[0031] The semiconductor manufacturing method provided in the above-mentioned embodiments of the present application changes the traditional process flow by first forming a patterned first dielectric layer, then filling the grooves with metal and covering the first dielectric layer, and then flattening the metal covering layer, so that the first dielectric layer itself has a flat surface without forming a height difference, thereby avoiding the problem of depression caused by directly flattening the first dielectric layer with a large height difference; because the metal flattening process is easier to control and implement, after the flattening process, the top of the metal filling part and the top of the first dielectric layer are basically flush, and no defects such as depressions will occur.

[0032] In addition, in the semiconductor structure after the above process, the metal filling part and the top of the first dielectric layer are located on the same plane, and the phenomenon of the top metal protruding into the dielectric layer in the prior art does not occur, thereby reducing the probability of cracking in this part and improving the reliability of the semiconductor device.

[0033] It can be understood that in the above method, only the steps related to the improvement of the present application are shown instead of all the steps. Therefore, the steps are not seamlessly connected, and other necessary or unnecessary steps may be interspersed between two steps according to needs and designer choices.

[0034] Hereinafter, each step of the semiconductor manufacturing method provided in the embodiment of the present application will be described in detail in conjunction with a cross-sectional view of a semiconductor structure during the semiconductor manufacturing process.

[0035] In step S101, a first semiconductor substrate 300 is provided. The semiconductor substrate is a bulk silicon substrate, and alternatively, it can also be a semiconductor substrate on an insulating layer, such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. A chip component may also be formed in the semiconductor substrate. The chip component may include a plurality of individual circuit elements, such as transistors (such as MOS), diodes, resistors, capacitors and / or other active or passive semiconductor devices formed by a variety of integrated circuit manufacturing processes. The specific method for forming the chip component is not described in detail in this application, and reference may be made to any prior art method capable of forming the chip component.

[0036] Through step S102, a first dielectric layer 301 is formed on the first semiconductor substrate 300. The first dielectric layer 301 is used to isolate different conductive layers to ensure the normal operation of the circuit and the stability of the device. In some embodiments, the first dielectric layer 301 can be made of materials such as silicon dioxide (SiO2), silicon nitride (Si3N4) or silicon oxynitride (SiON). The first dielectric layer 301 can be formed by methods such as chemical vapor deposition (CVD), physical vapor deposition (PVD) or atomic layer deposition (ALD).

[0037] In step S103, the first dielectric layer 301 is patterned to form a first trench 302, such as Figure 4a As shown. By patterning the first dielectric layer 301, the pattern of the top metal can be defined to prepare for subsequent metal filling. The first groove 302 can be realized by photolithography and etching technology. Specifically, a photoresist is coated with fluorine on the surface of the first dielectric layer 301, and the desired pattern is transferred to the photoresist through steps such as exposure and development; an etching process (such as dry etching or wet etching) is used to remove the dielectric material not protected by the photoresist, thereby forming the first groove 302. The selection of the etching process depends on the properties of the dielectric material and the required pattern accuracy.

[0038] Then, by executing step S104, metal is deposited on the first dielectric layer 301, and the deposited metal is higher than the top of the first dielectric layer 301, so as to form a metal filling portion 303 filled in the first trench 302 and a metal covering layer 304 covering the first dielectric layer 301. Figure 4bAs shown. The metal filling portion 303 is subsequently used as the top metal to achieve external electrical connection, and the metal covering layer 304 is higher than the plane where the top of the first dielectric layer 301 is located, thereby ensuring that the first trench 302 is filled with metal, but the protruding portion needs to be removed in the subsequent process. Optionally, the top metal is aluminum, and the metal deposited in this step is aluminum.

[0039] In step S105, a planarization process is performed to remove the metal cover layer 304 that is higher than the first dielectric layer 301, so that the top of the metal filling part 303 is flush with the top of the first dielectric layer 301. Figure 4c The planarization process can be achieved by using processes such as Chemical Mechanical Polishing (CMP) and Plasma Planarization, depending on the specific process conditions.

[0040] It is understandable that, since there is a height difference in the first dielectric layer 301 before deposition, after the metal covering layer 304 is formed by deposition in step S104, there will inevitably still be a certain height difference. However, based on the characteristics of the material itself, it is much easier to flatten the metal than to flatten the dielectric material. For example, in the CMP process of the metal material, the flattening process can be accurately controlled by adjusting the composition of the polishing liquid, the hardness of the polishing pad, and the polishing pressure. Therefore, even if there is a height difference in the metal, a surface with high flatness can be obtained through the flattening process. However, due to its high hardness and brittleness, the dielectric material may cause defects such as scratches and pits on the surface. Based on this, the present application flattens the metal deposited on the first dielectric layer 301 through step S105, and finally achieves a flattening effect on the entire top surface (the top surface of the metal filling portion 303 and the top surface of the first dielectric layer 301), and basically no concave defects will occur.

[0041] Through step S106, a first hard mask layer 305 is formed on the planarized surface. That is, the first hard mask layer 305 covers the first dielectric layer and the metal filling portion 303. Figure 4d As shown. The first hard mask layer 305 is located on the top and can protect the first dielectric layer and the metal filling part 303 from damage. In addition, during the heating process of the semiconductor device, the metal filling part 303 and the first dielectric layer expand to different degrees due to different thermal expansion coefficients. Due to the existence of the first hard mask layer 305, part of the deformation of the metal filling part 303 and the first dielectric layer can be absorbed, and part of the expansion difference can be offset, thereby reducing the probability of cracking problems in this part and improving the reliability of the semiconductor device.

[0042] In some embodiments, the material of the first hard mask layer 305 is silicon nitride. Silicon nitride material has high hardness and good mechanical strength, and can effectively protect the first dielectric layer 301 and the metal filling part 303. In addition, silicon nitride has high thermal stability, can maintain the stability of structure and performance under high temperature conditions, can effectively absorb and offset the thermal expansion difference between the metal filling part 303 and the first dielectric layer, and reduce the risk of cracking.

[0043] In some embodiments, the semiconductor manufacturing method of the present application further includes the following steps: S107, forming a second dielectric layer 306 on the first hard mask layer 305, such as Figure 4e S108, performing a patterning process to form a second groove 307 that penetrates the metal filling portion 303, such as Figure 4f S109, fill the second groove 307 with metal to form a first metal external connection portion 308, such as Figure 4g shown.

[0044] In the above embodiment, a second dielectric layer 306 is continuously formed on the first semiconductor substrate 300, and a first metal external connection portion 308 is formed in the second dielectric layer 306. The first metal external connection portion 308 is directly connected to the metal filling portion 303, thereby forming a channel for the metal filling portion 303 to be connected to the outside, providing a basis for the subsequent realization of three-dimensional packaging.

[0045] In some embodiments, the semiconductor manufacturing method of the present application further includes the following steps: S201, providing a second semiconductor substrate 400; S202, forming a third dielectric layer 401 on the second semiconductor substrate 400; S203, performing a patterning process to form a third trench; S204, filling the third trench with metal to form a second metal external connection 402; S205, bonding the first semiconductor substrate 300 and the second semiconductor substrate 400, and the first metal external connection 308 is connected to the second metal external connection 402. The cross-sectional view of the second semiconductor substrate 400 and the layers formed thereon is shown in FIG. Figure 5 As shown, the cross-sectional view after the first semiconductor substrate and the second semiconductor substrate are bonded together is as shown Figure 6 shown.

[0046] In the above embodiment, a second semiconductor substrate 400 for packaging is provided, and a third dielectric layer 401 and a second metal external connection portion 402 located in the third dielectric layer 401 are formed on the second semiconductor substrate 400, and the first semiconductor substrate 300 and the second semiconductor substrate 400 are bonded and connected. During the bonding process, due to the optimization of the manufacturing process of the first semiconductor substrate 300, the surface of the first semiconductor substrate 300 no longer has concave defects, thereby avoiding the problem of bonding bubbles forming on the bonding surface, achieving high-quality packaging of a multi-layer semiconductor structure, and ensuring the electrical interconnection and structural stability between the layers.

[0047] In some embodiments, the semiconductor manufacturing method in the present application, before forming the second groove 307, further includes: the step of forming a first bonding layer 309 on the second dielectric layer 306, and the second groove 307 is connected from the first bonding layer 309 to the metal filling part 303; before forming the third groove, it also includes: the step of forming a second bonding layer 403 on the third dielectric layer 401, and the third groove extends from the second bonding layer 403 to the third dielectric layer 401; the first bonding layer 309 and the second bonding layer 403 are bonded to connect the first semiconductor substrate 300 and the second semiconductor substrate 400.

[0048] In the above embodiment, the first bonding layer 309 and the second bonding layer 403 are respectively formed on the structure of the first semiconductor substrate 300 and the second semiconductor substrate 400. The connection of the two semiconductor substrates is achieved through the first bonding layer 309 and the second bonding layer 403, which can improve the strength and reliability of the bonding connection and reduce the risk of delamination or cracking due to mechanical stress or thermal stress in subsequent processes. Optionally, the first bonding layer 309 and the second bonding layer 403 are made of the same material. In some embodiments, the first bonding layer 309 and the second bonding layer 403 are both made of nitride-doped silicon carbide.

[0049] In some embodiments, Figure 5 As shown, before forming the third dielectric layer 401 on the second semiconductor substrate 400, it also includes: S211, forming a fourth dielectric layer 404 on the second semiconductor substrate 400; S212, forming a bonding pad 405 in the fourth dielectric layer 404; S213, forming a second hard mask layer 406 on the fourth dielectric layer 404; and, in step S202, the third dielectric layer 401 is formed on the second hard mask layer 406, and the third trench passes through to the bonding pad 405.

[0050] In the above embodiment, in addition to the second metal external connection 402 connected to the first semiconductor substrate 300, a bonding pad 405 is formed in the second semiconductor substrate 400. The bonding pad 405 is formed in the fourth dielectric layer 404 to avoid current leakage and other problems, and ensure the electrical performance and reliability of the bonding pad 405. The bonding pad 405 can be made of metal copper, which has good conductivity. In some embodiments, the bonding pad 405 can be formed by an electrochemical plating process (Electrical Chemical Plating, ECP).

[0051] In some embodiments, Figure 6As shown, the semiconductor manufacturing method of the present application also includes: S231, forming a fourth groove penetrating to the bonding pad 405 on the side of the second semiconductor substrate 400 away from the second metal external portion 402 (which can be understood as the back side of the second semiconductor substrate 400); S232, filling metal into the fourth groove to form a third metal external portion 407.

[0052] In the above embodiment, by forming a third metal external portion 407 on the back side of the second semiconductor substrate 400, the third metal external portion 407 is connected to the bonding pad 405, so that the second semiconductor substrate 400 can be further interconnected with other semiconductor structures, so that the semiconductor device can achieve higher integration.

[0053] In some embodiments, the first dielectric layer 301, the second dielectric layer 306, the third dielectric layer 401, and the fourth dielectric layer 404 are made of the same material. Using the same dielectric material can simplify the process flow, reduce the complexity of the process, and reduce costs. In addition, the same dielectric material ensures the consistency of electrical performance between layers and improves the stability of semiconductor devices. For example, the first dielectric layer 301, the second dielectric layer 306, the third dielectric layer 401, and the fourth dielectric layer 404 are all made of silicon dioxide.

[0054] The present application also provides a semiconductor structure, which is manufactured using the above semiconductor manufacturing method. Figure 4d As shown, the semiconductor structure includes: a first semiconductor substrate 300; a first dielectric layer 301 formed on the first semiconductor substrate 300; a metal filling part 303 formed in the first dielectric layer 301, and the top of the metal filling part 303 is flush with the top of the first dielectric layer 301; and a first hard mask layer 305 formed on the first dielectric layer 301.

[0055] The semiconductor structure is manufactured by the improved manufacturing method described above in the present application, so that the metal filling portion 303 and the top of the first dielectric layer 301 are formed into a flat surface, thereby avoiding the formation of bonding bubble defects in the subsequent packaging process and improving the strength and reliability of the bonding connection.

[0056] In addition, the metal filling part 303 and the top of the first dielectric layer 301 are located on the same plane and are covered with a first hard mask layer 305. The first hard mask layer 305 can absorb part of the deformation of the metal filling part 303 and the first dielectric layer and offset part of the expansion difference, thereby reducing the probability of cracking problems occurring in this part and improving the reliability of the semiconductor device.

[0057] In some embodiments, a second dielectric layer 306 is further formed on the first hard mask layer 305 , and a first metal external portion 308 extending to the metal filling portion 303 is formed in the second dielectric layer 306 .

[0058] In some embodiments, the semiconductor structure also includes a second semiconductor substrate 400 bonded to the first semiconductor substrate 300, a fourth dielectric layer 404, a second hard mask layer 406 and a third dielectric layer 401 are sequentially formed on the side of the second semiconductor substrate 400 facing the first semiconductor substrate 300, a bonding pad 405 is formed in the fourth dielectric layer 404, and a second metal external portion 402 connecting the first metal external portion 308 and the bonding pad 405 is formed in the third dielectric layer 401.

[0059] In the above embodiment, the first semiconductor substrate 300 and the second semiconductor substrate 400 are bonded to form a semiconductor stacking structure, and the two are electrically connected through the first metal external connection part 308 and the second metal external connection part 402. Due to the optimization of the manufacturing process of the first semiconductor substrate 300, there is no longer any concave defect on its surface, thereby avoiding the problem of bonding bubbles forming on the bonding surface, realizing high-quality packaging of the multi-layer semiconductor structure, and ensuring the electrical interconnection and structural stability between the layers.

[0060] Finally, it should be noted that: the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0061] The above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, ordinary technicians in the field should understand that the specific implementation methods of the present invention can still be modified or some technical features can be replaced by equivalents without departing from the spirit of the technical solution of the present invention, which should be included in the scope of the technical solution for protection of the present invention.

Claims

1. A semiconductor manufacturing method, characterized in that: At least the following steps are included: providing a first semiconductor substrate; forming a first dielectric layer over the first semiconductor substrate; patterning the first dielectric layer to form a first trench; Depositing metal on the first dielectric layer to form a metal filling portion filled in the first trench and a metal covering layer higher than the plane where the top of the first dielectric layer is located; performing a planarization process to remove the metal capping layer and make the top of the metal filling part flush with the top of the first dielectric layer; A first hard mask layer is formed covering the first dielectric layer and the metal filling part.

2. The semiconductor manufacturing method according to claim 1, characterized in that: The following steps are also included: forming a second dielectric layer over the first hard mask layer; Performing a patterning process to form a second trench penetrating to the metal filling portion; Filling the second trench with metal to form a first metal external connection portion.

3. The semiconductor manufacturing method according to claim 2, characterized in that: The following steps are also included: providing a second semiconductor substrate; forming a third dielectric layer on the second semiconductor substrate; performing a patterning process to form a third trench; Filling metal into the third trench to form a second metal external connection portion; The first semiconductor substrate and the second semiconductor substrate are bonded and connected, and the first metal external connection portion is butted against the second metal external connection portion.

4. The semiconductor manufacturing method according to claim 3, characterized in that: Before forming the second trench, the method further includes: forming a first bonding layer on the second dielectric layer, wherein the second trench is connected from the first bonding layer to the metal filling portion; Before forming the third trench, the method further includes: forming a second bonding layer on the third dielectric layer, wherein the third trench extends from the second bonding layer to the third dielectric layer; The first bonding layer and the second bonding layer are bonded to connect the first semiconductor substrate and the second semiconductor substrate.

5. The semiconductor manufacturing method according to claim 4, characterized in that: Before forming a third dielectric layer on the second semiconductor substrate, the method further includes: forming a fourth dielectric layer on the second semiconductor substrate; forming a bonding pad in the fourth dielectric layer; forming a second hard mask layer over the fourth dielectric layer; The third dielectric layer is formed on the second hard mask layer, and the third trench passes through to the bonding pad.

6. The semiconductor manufacturing method according to claim 5, characterized in that: Also includes: forming a fourth groove penetrating to the bonding pad on a side of the second semiconductor substrate away from the second metal external connection portion; Filling the fourth trench with metal to form a third metal external connection portion.

7. The semiconductor manufacturing method according to claim 5, characterized in that: The materials of the first dielectric layer, the second dielectric layer, the third dielectric layer and the fourth dielectric layer are all silicon dioxide.

8. The semiconductor manufacturing method according to claim 5, characterized in that: The materials of the first bonding layer and the second bonding layer are both nitride-doped silicon carbide.

9. A semiconductor structure, characterized in that: The semiconductor structure is manufactured by the semiconductor manufacturing method according to any one of claims 1 to 8, wherein the semiconductor structure comprises: a first semiconductor substrate; forming a first dielectric layer over the first semiconductor substrate; A metal filling portion formed in the first dielectric layer, wherein a top of the metal filling portion is flush with a top of the first dielectric layer; A first hard mask layer is formed over the first dielectric layer.

10. The semiconductor structure according to claim 9, characterized in that: A second dielectric layer is formed on the first hard mask layer, and a first metal external connection portion extending to the metal filling portion is formed in the second dielectric layer; It also includes a second semiconductor substrate bonded to the first semiconductor substrate, wherein a fourth dielectric layer, a second hard mask layer and a third dielectric layer are sequentially formed on a side of the second semiconductor substrate facing the first semiconductor substrate, a bonding pad is formed in the fourth dielectric layer, and a second metal external portion connecting the first metal external portion and the bonding pad is formed in the third dielectric layer.

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