Memory data migration method, memory management system, and memory tracking circuit

Abstract

An apparatus for executing a software program, comprising: a processing unit; at least one memory component, each memory component connected to the processing unit and mapped to a memory address range of the processing unit; a memory mapping circuit connected to the processing unit and the memory component and configured to: in each of a plurality of iterations: access a statistical counter collected while the processing unit executes the software program; in a case where a first range and a second range are identified according to an analysis of the statistical counter, generate a mapping between the first memory address range and the second memory address range; in response to a memory access command including a first memory address within the first range received from the processing unit, replace the first memory address in the memory access command with a second memory address within the second range according to the mapping.

Description

[0001] This application is a divisional application of the original application with the application number 202280092124.X and the original filing date of February 23, 2022, the entire contents of the original application are incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the field of computers, and in particular to a memory data migration method, a memory management system and a memory tracking circuit. BACKGROUND

[0003] The present application relates to a computerized device, and more particularly, but not exclusively, to a computerized device having more than one memory component.

[0004] For brevity, the term "system" is used hereinafter to refer to a computerized system, and these terms are used interchangeably.

[0005] There are numerous metrics used to measure the performance of a computerized system, such as throughput, i.e., the amount of tasks performed in a determined time interval, and latency, i.e., the amount of time a task is delayed before being executed. Improving the performance of a system, for example, by increasing the throughput of the system and / or reducing the latency of the system, depends, among other factors, on the amount of computer resources available in the system and on how well the various components of the system work together. For example, reducing the latency of accessing a memory and / or increasing the throughput of memory accesses can improve the performance of a system.

[0006] Memory components with relatively high performance access characteristics, such as low latency memory components or high throughput memory components, such as static RAM (SRAM), are typically more expensive than memory components with lower performance access characteristics, such as dynamic RAM (DRAM). It is a common practice to design the memory of a system using more than one type of memory component to balance the cost and performance of the system. Some common system designs organize multiple memory components in multiple memory tiers, where small and fast tiers are above larger and slower tiers as a cache for the larger tiers. In some designs, there is a hierarchy of tiers, where only the largest tier is available to software programs, i.e., application memory addresses are addressable using software programs, and the other tiers in the hierarchy are used as hierarchical caches.

[0007] Some other system designs enable all memory tiers to be addressed using application memory addresses of software programs. In such systems, the performance of the system is affected by the distribution of the application memory of the software programs among the multiple memory tiers (i.e., among one or more memory components of the system). When the application memory of the software programs includes multiple application memory regions, performance can be improved when frequently accessed application memory regions are stored in one or more high performance memory components, while lower performance memory components are used to store less frequently accessed application memory regions.

[0008] The term non-uniform memory access (NUMA) refers to computerized systems having more than one memory component, where some characteristics of memory accesses from processing units to the memory components (e.g., latency and / or throughput) depend on the topology of the system, e.g., the location of the memory components relative to the processing units. In a manner similar to the above-described systems, in systems having NUMA, the performance of the system can be affected by the distribution of the application memory of the software programs among one or more memory components. SUMMARY

[0009] The present invention includes a description of an apparatus and a method for memory management. In some embodiments described herein, a memory mapping circuit is used to map the application memory of a software program executed by a processing unit among one or more memory components connected to the processing unit, without requiring computation by the processing unit, and without affecting the memory mapping table used by an operating system executed by the processing unit. Furthermore, in these embodiments, the memory mapping circuit is used to replace, in a memory access command received from the processing unit, a first memory address in a first memory address range with a second memory address in a second memory address range, according to a mapping between the first memory address range and the second memory address range, where the mapping between the first memory address range and the second memory address range is generated according to an analysis of one or more statistical counters collected while the software program is executed by the processing unit. Using the memory mapping circuit to generate the mapping between the first memory address range and the second memory address range, and to replace the memory addresses in the memory access command according to the generated mapping, reduces the processing overhead required by the processing unit to update the distribution of multiple application memory regions of the software program among the one or more memory components, thereby improving the performance of the apparatus.

[0010] The above and other objects are achieved by the features of the independent claims. Other implementations are apparent from the dependent claims, the description and the accompanying drawings.

[0011] According to a first aspect, there is provided an apparatus for executing a software program, the apparatus comprising: a processing unit; at least one memory component, each memory component connected to the processing unit and mapped to at least one memory address range of a plurality of memory address ranges of the processing unit; a memory mapping circuit connected to the processing unit and the at least one memory component, the memory mapping circuit configured to: in each management iteration of a plurality of management iterations: access one or more of a plurality of statistical counters collected while the processing unit executes the software program; in case a first memory address range of the plurality of memory address ranges and a second memory address range of the plurality of memory address ranges are identified based on an analysis of the one or more statistical counters, generate a mapping between the first memory address range and the second memory address range; in response to receiving at least one memory access command comprising a first memory address in the first memory address range from the processing unit, replace the first memory address in the at least one memory access command to a second memory address in the second memory address range according to the mapping.

[0012] According to a second aspect, there is provided a method for managing memory in an apparatus for executing one or more software programs, the method comprising: in each management iteration of a plurality of management iterations, performing, by a memory mapping circuit connected to a processing unit and to at least one memory component connected to the processing unit, wherein each of the at least one memory component is mapped to at least one memory address range of a plurality of memory address ranges of the processing unit: accessing one or more of a plurality of statistical counters collected while the processing unit executes at least one of the one or more software programs; in case a first memory address range of the plurality of memory address ranges and a second memory address range of the plurality of memory address ranges are identified based on an analysis of the one or more statistical counters, generating a mapping between the first memory address range and the second memory address range; in response to receiving at least one memory access command comprising a first memory address in the first memory address range from the processing unit, replacing the first memory address in the at least one memory access command to a second memory address in the second memory address range according to the mapping.

[0013] According to a third aspect, there is provided a software program product for memory management, the software program product comprising: a non-transitory computer readable storage medium; first program instructions for: in each management iteration of a plurality of management iterations, performing the following operations by a memory mapping circuit connected to a processing unit and to at least one memory component connected to the processing unit, wherein each of the at least one memory component is mapped to at least one memory address range of a plurality of memory address ranges of the processing unit: accessing one or more of a plurality of statistical counters collected when the processing unit executes at least one of one or more software programs; in case a first memory address range of the plurality of memory address ranges and a second memory address range of the plurality of memory address ranges are identified based on an analysis of the one or more statistical counters, generating a mapping between the first memory address range and the second memory address range; second program instructions for: in response to receiving at least one memory access command comprising a first memory address in the first memory address range from the processing unit, replacing the first memory address in the at least one memory access command to a second memory address in the second memory address range according to the mapping. According to the third aspect, the first program instructions and the second program instructions are executed by at least one computerized processor from the non-transitory computer readable storage medium.

[0014] In an implementation form of the first and second aspects, the plurality of statistical counters comprises a high access counter, a low access counter, and a plurality of range access counters, each range access counter being associated with one of the plurality of memory address ranges. Optionally, accessing the one or more statistical counters comprises: accessing at least one of the low access counter and the high access counter; performing a further analysis comprising the at least one of the low access counter and the high access counter; accessing at least one range access counter according to a further result of the further analysis. Using a watermark counter (e.g. the high access counter or the low access counter) in addition to the plurality of range access counters helps to reduce the amount of accesses to the plurality of range access counters, and to reduce the amount of computational resources required for memory mapping compared to approaches where all the plurality of range access counters are accessed.

[0015] In a further implementation form of the first aspect and the second aspect, the apparatus further includes at least one memory tracking circuit connected to the processing unit and the at least one memory component. Optionally, at least one of the plurality of statistical counters is implemented in the at least one memory tracking circuit, and the at least one memory tracking circuit is configured to update the at least one of the plurality of statistical counters in each of a plurality of tracking iterations in response to memory access commands received from the processing unit. Implementing the statistical counters in the memory tracking circuit reduces the amount of computational resources required to track one or more memory accesses as compared to a method of implementing the statistical counters in a page table of an operating system executed by the processing unit executing the software program. Optionally, the memory mapping circuit is further configured to access one or more of the plurality of statistical counters by accessing the at least one memory tracking circuit. Optionally, the memory mapping circuit is further configured to configure at least one of a low access threshold and a high access threshold in the at least one memory tracking circuit. Optionally, the memory mapping circuit configures at least one of the low access threshold and the high access threshold in the at least one memory tracking circuit according to a further result of a further analysis including the one or more statistical counters. Configuring the low access threshold and / or the high access threshold improves the accuracy of the high access counter and the low access counter, and improves the accuracy of the memory mapping calculated from the one or more statistical counters.

[0016] In a further implementation form of the first aspect and the second aspect, the memory mapping circuit further includes a plurality of address mappings, each address mapping mapping one of the plurality of memory address ranges to a media address range, wherein the media address range is another of the plurality of memory address ranges. Mapping one of the plurality of memory address ranges to a media address range that is another of the plurality of memory address ranges enables moving an application memory region of the software program from one memory component to another memory component without modifying a page table of an operating system mapping application addresses of the software program to physical addresses of the processing unit, reducing the amount of interruption to one or more services provided by the apparatus executing the software program. Optionally, generating the mapping between the first memory address range and the second memory address range includes updating a respective media address range of a respective address mapping of the first memory address range to the second memory address range. Optionally, the memory mapping circuit is configured to perform the plurality of management iterations while the processing unit executes the software program. Performing the plurality of management iterations generating the memory mapping while the processing unit executes the software program improves the performance of the apparatus executing the software program without increasing the amount of interruption to one or more services provided by the apparatus executing the software program.

[0017] In a further implementation form of the first and second aspects, the memory mapping circuitry is further configured to, in case the first memory address range and the second memory address range are identified based on the analysis of the plurality of statistical counters, copy at least one data value stored in a first one of the at least one memory component associated with the first memory address range to a second one of the at least one memory component associated with the second memory address range. Optionally, the application memory of the software program comprises a plurality of application memory regions, each application memory region being stored in one of the at least one memory component. Optionally, the at least one data value is part of at least one of the plurality of application memory regions. Copying one or more data values that are part of the application memory of the software program improves the performance of the apparatus executing the software program without increasing the amount of interruptions to one or more services provided by the apparatus executing the software program.

[0018] In yet a further implementation form of the first and second aspects, the processing unit executes the software program by executing an operating system having an operating system page size for memory management. Optionally, at least one of the plurality of memory address ranges addresses a different amount of memory than the operating system page size. Using memory address ranges having a range size that is not equal to any one of a set of page sizes of an operating system improves the accuracy of the analysis of the one or more statistical counters, thereby improving the performance of the apparatus executing the software program.

[0019] Other systems, methods, features, and advantages of the application will be or become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional systems, methods, features, and advantages be included within this description, be within the scope of the application, and be protected by the accompanying claims.

[0020] Unless otherwise defined, all technical and / or scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the implementations belong. The BRIEF DESCRIPTION OF DRAWINGS

[0021] Some embodiments are herein described, by way of example only, with the understanding that they will vary with respective changes and modifications, the illustrations being the only examples of the application and therefore not limiting. Thus, persons skilled in the art and technology concerned have the full support from this detailed description and drawings and also from the claims to realize the application in all its developments.

[0022] In the drawings:

[0023] Figure 1 is a schematic block diagram of an exemplary device provided by some embodiments;

[0024] Figure 2 is a schematic block diagram of an exemplary address mapping provided by some embodiments;

[0025] Figure 3 is a schematic block diagram of an exemplary content mapping provided by some embodiments;

[0026] Figure 4 is a schematic block diagram of another exemplary content mapping provided by some embodiments;

[0027] Figure 5 is a flowchart schematically representing an optional operational flow for memory mapping provided by some embodiments. DETAILED DESCRIPTION

[0028] As used herein, the term "processing unit" refers to any type of programmable or non- programmable circuitry for performing the operations described below. The processing unit can include hardware and software. For example, the processing unit can include one or more processors and a transitory or non-transitory memory carrying a program that, when executed by the one or more processors, causes the processing unit to perform the corresponding operations.

[0029] Further, as used herein, the term "physical address" refers to an address used by the processing unit in a memory access request to access a memory component. Further, as used herein, the term "application address" refers to an address used in an application. The application address can be a virtual address, in which case the application address needs to be converted to a physical address in order to access one or more memory components. Further, as used herein, the term "media address" refers to an address recognized by a memory component. The processing unit can use the media address in a memory access request. Optionally, a memory address in a memory access request is mapped to a media address. As used herein, the term "memory mapping" refers to mapping of application memory addresses of a software program to physical addresses in memory access requests sent by the processing unit. Such mapping can be used to convert an application address to a physical address that identifies a location in a memory component where the application data or instructions are stored.

[0030] Further, as used herein, the terms "memory access request" and "memory access command" are both used to refer to a request to access a memory component in order to read from and / or write to the memory component, and the terms are used interchangeably. A memory access request can be generated when a computer instruction of a software program that includes a memory access computer instruction is executed.

[0031] Furthermore, the terms "range of memory addresses" and "memory address range" are both used herein to mean a range of memory addresses, and are used interchangeably.

[0032] To allocate each of the plurality of application memory regions to one or more memory components connected to the processing unit, thereby improving performance of the system, some systems track accesses to the one or more memory components and use the collected tracking information to identify application memory regions that should be moved from one memory component to another. Some existing tracking methods maintain access counters in page tables used by an operating system executed by the processing unit to map application addresses of software programs to physical addresses of the processing unit. Some such methods update the counters in the page tables each time memory is accessed. Analyzing the plurality of counters in the page tables requires consolidating counters for a plurality of virtual pages that map to a common physical page. Some methods require sorting the plurality of counters to categorize the page table entries, for example to identify page table entries that describe highly accessed application memory regions. Furthermore, moving an application memory region from one memory component to another requires computational resources of the processing unit to update the page tables, and can also require copying the application memory region from one memory component to another. Such methods reduce performance of the system because they require computational resources of the processing unit. Furthermore, one or more services provided by the system executing the software programs can be interrupted while the page tables are updated.

[0033] To reduce the amount of computer resources used by a processing unit to map application memory to one or more memory components, in some embodiments described herein, the inventors suggest using a memory mapping circuit coupled to the processing unit and the one or more memory components to generate a mapping between one or more physical addresses of the processing unit and one or more media addresses of the one or more memory components, and to replace, in a memory access command received from the processing unit, a memory address of the memory access command with a media address of one of the memory components according to the generated mapping. Optionally, the memory address of the memory access command is a first physical memory address in a first memory address range of the processing unit, and the memory address range is one of a plurality of memory address ranges of the processing unit. Optionally, the media address is a second physical memory address in a second memory address range of the plurality of memory address ranges. Such a mapping between one or more physical addresses used by the processing unit and one or more media addresses identified by the one or more memory components enables moving an application memory region from one memory component to another memory component without modifying a page table of an operating system that maps application addresses of a software program to physical addresses of the processing unit. Avoiding modification of the page table reduces the amount of interruption to one or more services provided by a system executing the software program. Optionally, the memory mapping circuit generates the mapping in each of a plurality of management iterations. Optionally, the memory mapping circuit generates the mapping while the processing unit executes the software program.

[0034] Optionally, the mapping is generated according to an analysis of one or more statistical counters collected while the processing unit executes the software program. Optionally, the statistical counter is indicative of a plurality of memory access commands. For example, when the processing unit has a plurality of memory address ranges, and each of the one or more memory components is mapped to one or more of the plurality of memory address ranges, the statistical counter can be a range access counter associated with a memory address range, indicative of a number of memory access commands that access the memory address range. Optionally, the statistical counter is indicative of an amount of range access counters that satisfy an identified criterion. For example, the statistical counter can be a watermark counter, indicative of an amount of range access counters that exceed a high access threshold, where the high access threshold is indicative of an amount of access to a memory address range deemed high. Or, the watermark counter can be indicative of an amount of range access counters that are less than a low access threshold, where the low access threshold is indicative of another amount of access to a memory address range deemed low. Optionally, the statistical counter is indicative of an amount of memory access commands received from the processing unit. Optionally, the one or more processing circuits receive the memory access commands in each of a plurality of iterations, and update at least one of the plurality of statistical counters in each of the plurality of iterations.

[0035] Compared to performing the analysis by the processing unit, performing the analysis by the memory mapping circuit reduces the amount of computing resources of the processing unit required to perform the analysis, improves the performance of the system when executing the software program, e.g., increases throughput and / or reduces latency when performing one or more tasks of the software program.

[0036] Optionally, the memory mapping circuit is further configured to copy one or more data values stored in a first memory component of the one or more memory components into a second memory component of the one or more memory components, wherein the first memory component is associated with a first memory address range and the second memory component is associated with a second memory address range. Optionally, the one or more data values are copied from the first memory component to the second memory component in accordance with the analysis of the one or more statistical counters identifying the first memory address range and the second memory address range. Compared to copying the one or more data values by the processing unit, copying the one or more data values by the memory mapping circuit reduces the amount of interruption to one or more services provided by the system executing the software program.

[0037] Optionally, at least one of the one or more statistical counters is implemented in one or more tracking circuits connected to the processing unit and the one or more memory components. Implementing the statistical counter in the tracking circuit reduces the amount of resources of the processing unit used for tracking the plurality of memory accesses, e.g., reduces the amount of memory accesses performed by the processing unit and / or reduces the amount of processor cycles of the processing unit used for computing the memory mapping. Optionally, the memory mapping circuit is further configured to configure the one or more tracking circuits.

[0038] When the processing unit executes the operating system, the operating system can address the plurality of memory components using a plurality of operating system memory pages. It is a common practice to use an arbitrary page size for the plurality of operating system memory pages, i.e., each of the plurality of operating system memory pages has one of a set of identified page sizes. When memory access tracking is done using a page table of the operating system, the granularity of the memory access tracking is according to the respective page size of each of the plurality of operating system memory pages. In some embodiments described herein, at least one of the plurality of memory address ranges has a range size that is not equal to any of the set of page sizes. Tracking the plurality of memory access commands according to the plurality of memory address ranges using one or more range access counters supports tracking the plurality of memory access commands at a granularity different from the page size of the operating system, improves the accuracy of the memory mapping computed according to the plurality of statistical counters compared to a memory mapping computed when tracking according to the page size of the operating system, and thus improves the accuracy of allocating the plurality of application memory regions to the one or more memory components, and improves the performance of the system.

[0039] Before at least one embodiment is explained in detail, it is to be understood that the embodiments are not limited in their application to the details of construction and the arrangement of the components and / or methods set forth in the following description and / or illustrated in the drawings and / or examples. The implementations described herein are applicable to other embodiments or of being practiced or carried out in various ways.

[0040] Embodiments can be a system, a method, and / or a computer program product. The computer program product can include one or more computer readable storage media (storage media) having computer readable program instructions stored therein, the computer readable program instructions being executable by a processor to carry out various aspects of the embodiments.

[0041] The computer readable storage media can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage media can be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer readable storage media includes the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, and any suitable combination of the foregoing. Computer readable storage media used in the description herein can not be a transitory signal per se but can be a computer readable medium having a transitory signal embodied therein. For example, transmission of a computer readable program over the Internet, over a local area network, over a wide area network, and / or over a wireless network, and / or in other formats is not included within the definition of computer readable storage media described herein.

[0042] The computer readable program instructions described herein can be downloaded to respective computing / processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and / or a wireless network. The network can comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and / or edge servers. A network adapter card or network interface in each computing / processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing / processing device.

[0043] Computer readable program instructions for carrying out operations of an embodiment can be in assembly code, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or source code or object code written in any combination of one or more programming languages, including an object-oriented programming language such as Smalltalk, C++, Java, or Visual Basic, and conventional procedural programming languages, such as the "C" programming language, Fortran or similar programming languages, an interpretive programming language such as JavaScript, Python, or similar programming languages. The computer readable program instructions can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), and the connection can be made through external computer or through an Internet service provider (ISP). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) can execute the computer readable program instructions by utilizing state information of the computer readable program instructions to customize the electronic circuitry, in order to perform aspects of embodiments.

[0044] Aspects of the embodiments are provided herein with reference to the flow diagrams and / or block diagrams of the methods, apparatuses (systems) and computer program products according to this disclosure. It is understood that each block of the flow diagrams and / or block diagrams, and combinations of blocks in the flow diagrams and / or block diagrams, can be implemented by computer readable program instructions.

[0045] These computer readable program instructions can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks. These computer readable program instructions can also be stored in a computer readable storage medium that can direct a computer, a programmable data processing apparatus, and / or other devices to function in a particular manner, such that the computer readable storage medium having instructions for causing an apparatus to implement various aspects of the functions / acts specified in the flowchart and / or block diagram block or blocks is produced. The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0046] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0047] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0048] Reference will now be made to the Figure 1 which shows a schematic block diagram of an exemplary apparatus provided by some embodiments. In these embodiments, a processing unit 101 is connected to at least one memory component 120.

[0049] For brevity, hereafter, the term "memory component 120" is used to mean "at least one memory component 120" and these terms are used interchangeably. Optionally, the memory component 120 comprises one memory component, such as memory component 120C. Optionally, the memory component 120 comprises more than one memory component, such as memory component 120A, memory component 120B and memory component 120C. The memory component can be a random access memory (RAM) component, such as a SRAM component or a DRAM component. Other examples of memory components include read only memory (ROM) components, electrically erasable programmable ROM (EEPROM) and non-volatile RAM (NVRAM). Optionally, one or more of the memory components 120 are electrically coupled to the processing unit 101. Optionally, one or more of the memory components 120 are connected to the processing unit 101 through a host memory controller (not shown).

[0050] Optionally, one or more of the memory components 120 are cache memory components of the processing unit 101. Optionally, one or more of the memory components 120 are connected to another cache memory component (not shown) that is additionally connected to the processing unit 101.

[0051] Optionally, one or more memory tracking circuits 130 are connected to the processing unit 101 and the memory components 120. Optionally, each memory component 120 is mapped to at least one of a plurality of memory address ranges of the processing unit 101.

[0052] Reference is now made to Fig. 2, Figure 2 which shows a schematic block diagram of an exemplary address mapping 200 provided by some embodiments. In this example, the memory component 120A is mapped to memory address range 201A, memory address range 201B and memory address range 201C of the plurality of memory address ranges 201. Thus, when the processing unit 101 accesses a memory address in one of the memory address range 201A, memory address range 201B and memory address range 201C, the processing unit 101 accesses the memory component.

[0053] Similarly, the memory component 120B is mapped to memory address range 201D of the plurality of memory address ranges 201, the memory component 120C is mapped to memory address range 201E and memory address range 201F of the plurality of memory address ranges 201.

[0054] Optionally, the processing unit 101 executes an operating system that uses multiple operating system memory pages to address the memory component 120. Optionally, each of the multiple operating system memory pages has a page size that is one of the identified set of page sizes. Optionally, a size of at least one of the multiple memory address ranges 201 is not a member of the identified set of page sizes.

[0055] Reference is now again made to Figure 1 Optionally, the memory mapping circuit 110 is connected to the processing unit 101 and the memory component 120.

[0056] Optionally, the memory mapping circuit 110 includes multiple address mappings. Optionally, each of the multiple address mappings maps one of the multiple memory address ranges 201 to a media address range, where the media address range is another one of the multiple memory address ranges 201.

[0057] Reference is now again made to Figure 3 which shows a schematic block diagram of an exemplary memory mapping 300 provided by some embodiments. In this example, the multiple address mappings 321 include an address mapping 321A that maps the memory address range 201A to a media address range that is the memory address range associated with the memory component 120A, e.g., the memory address range 201A.

[0058] Similarly, in this example, the multiple address mappings 321 include an address mapping 321D that maps the memory address range 201D to another media address range that is another memory address range associated with the memory component 120B, e.g., the memory address range 201D.

[0059] Further, in this example, the multiple address mappings 321 include an address mapping 321E that maps the memory address range 201E to an additional media address range that is an additional memory address range associated with the memory component 120C, e.g., the memory address range 201E.

[0060] Further, in this example, the multiple address mappings 321 include an address mapping 321B that maps the memory address range 201B, an address mapping 321C that maps the memory address range 201C, and an address mapping 321F that maps the memory address range 201F.

[0061] When the application memory of the software program executed by the processing unit 101 includes multiple application memory regions 301, one or more of the multiple memory regions can be stored in one of the memory components and associated with one of the multiple memory address ranges 201. In the present example, an application memory region 301 A of the multiple application memory regions 301 is stored in the memory component 120A and is associated with the memory address range 201 A. When the processing unit 101 sends a memory access command to access the application memory region 301 A, the memory access command includes a first memory address in the memory address range 201 A. When the address mapping 321 A maps the memory address range 201 A to a media address range that is the memory address range 201 A, the memory component 120A responds to the memory address command.

[0062] Similarly, an application memory region 301B of the multiple application memory regions 301 is stored in the memory component 120B and is associated with the memory address range 201D, and an application memory region 301C of the multiple application memory regions 301 is stored in the memory component 120C and is associated with the memory address range 201E.

[0063] According to some embodiments, the memory mapping circuit 110 optionally generates a new mapping for a memory address range of the multiple memory address ranges 201.

[0064] Reference is now made to Figure 4 which shows a schematic block diagram of another example memory mapping 400 provided by some embodiments. In the present example, a new memory mapping 421 A is generated instead of the memory mapping 321 A, mapping the memory address range 201 A to a new media address range that is a memory address range in the memory component 120C, such as the memory address range 201F. Optionally, the application memory region 301 A associated with the memory address range 201 A is now stored in the memory component 120C instead of the memory component 120A. In the present example, when the processing unit 101 sends a new memory access command to access the application memory region 301 A, the new memory access command includes a first memory address in the memory address range 201 A. Since in the present example the address mapping 421 A maps the memory address range 201 A to a new media address range that is the memory address range 201F, in some embodiments the memory mapping circuit 120 replaces the first memory address with a second memory address in the memory address range 201F in the new memory access command, so that the memory component 120C responds to the new memory address command instead of the memory component 120A.

[0065] Thus, in this example, the processing unit 101 accesses the application memory region 301 A using the memory address range 201 A without modifying the page table that maps the plurality of application memory regions 301 to the plurality of memory address ranges 201, even though the application memory region 301 A is now stored in the memory component 120C instead of the memory component 120A as before.

[0066] To manage memory, the memory mapping circuit 110 in the system 100 can implement the following optional methods.

[0067] Reference is now also made to Figure 5 which shows a flowchart schematically representing an optional operational flow 500 for memory mapping provided by some embodiments.

[0068] For brevity, hereafter the term "mapping circuit" is used to mean "memory mapping circuit" and these terms can be used interchangeably.

[0069] In these embodiments, in 501, the mapping circuit 110 accesses one or more of a plurality of statistical counters collected while the processing unit 101 executes a software program. Optionally, the plurality of statistical counters includes a plurality of range access counters, each associated with one of the plurality of memory address ranges 201. Optionally, the plurality of statistical counters includes one or more watermark counters, each associated with a frequency of access to a memory component. A watermark counter can indicate an amount of memory access ranges accessed at the frequency associated with the watermark counter. A watermark counter can be a high access counter indicating an amount of range access counters of the plurality of range access counters that exceed a high access threshold, thereby indicating frequent access to the respective memory component associated with the range access counters that exceed the high access threshold. For example, the range access counter of the memory address range 201 A that exceeds the high access threshold can indicate frequent access to the memory component 120A associated with the memory address range 201 A. Another example of a watermark counter is a low access counter indicating an amount of range access counters of the plurality of range access counters that exceed a low access threshold. There can be more than two watermark counters, each associated with one of a plurality of frequencies of access to a memory component. Each of the more than two watermark counters can be associated with an access threshold indicating the frequency of access thereby associated, i.e., indicating an amount of range access counters of the plurality of range access counters that exceed the threshold associated with the watermark counter.

[0070] Optionally, accessing the one or more statistical counters includes the mapping circuit accessing at least one of a low access counter and a high access counter. Optionally, accessing the one or more statistical counters includes the mapping circuit performing an initial analysis, the initial analysis including accessing the low access counter and / or the high access counter. Optionally, accessing the one or more statistical counters includes the mapping circuit accessing at least one range access counter in accordance with an initial result of the initial analysis.

[0071] Optionally, in each of the one or more access iterations, the mapping circuit 110 accesses one of the one or more range access counters at a time. Optionally, in each of the one or more access iterations, the mapping circuit 110 accesses a subset of the plurality of range access counters. Optionally, the management component 110 denies access to at least one range access counter in the event of identifying a stopping condition, for example, an amount of range access counters received exceeds a threshold value equal to a value of a previously accessed watermark counter.

[0072] Optionally, at least one of the plurality of statistical counters is implemented in one or more memory tracking circuits 130. Optionally, the one or more memory tracking circuits 130 are configured to update at least one of the plurality of statistical counters in each of a plurality of tracking iterations in response to memory access commands received from the processing unit 101. Optionally, the memory mapping circuit accesses the one or more statistical counters by accessing the one or more memory tracking circuits 130.

[0073] Optionally, at least one other of the plurality of statistical counters is implemented in one of the memory components 120. Optionally, the one memory component implementing the at least one other statistical counter is a cache memory component of the processing unit 101. Optionally, at least one other of the plurality of statistical counters is implemented in another cache memory component connected to the one or more memory components 120.

[0074] Optionally, the memory mapping circuit 110 accesses the one or more statistical counters while the processing unit 101 executes a software program.

[0075] In 502, the mapping circuit 110 optionally performs an analysis of the one or more statistical counters. Optionally, in 507, the mapping circuit 110 identifies a first memory address range (e.g., memory address range 201A) and a second memory address range (e.g., memory address range 201F). Optionally, the mapping circuit 110 identifies the first memory address range and the second memory address range based on the analysis of the one or more statistical counters. For example, when the results of the analysis indicate that the application memory region 301A is accessed with high frequency using the memory address range 201A, the mapping circuit 110 can identify the memory address range 201A as the first memory address range.

[0076] In 510, the mapping circuit 110 optionally generates a mapping between the first memory address range and the second memory address range, e.g., the mapping 421A between the memory address range 201A and the memory address range 201F. Optionally, the mapping 421A is generated by updating the media address range of the mapping 321A from the memory address range 210A to the memory address range 201F.

[0077] Optionally, the mapping circuit 110 generates the mapping while the processing unit 101 is executing the software program.

[0078] Optionally, in 520, the mapping circuit 110 copies one or more data values (e.g., at least a portion of the application memory region 301A) from the memory component 120A associated with the memory address range 201A to the memory component 120C associated with the memory address range 201F.

[0079] Optionally, the mapping circuit 110 stops access to the memory component 120A and the memory component 120C from the processing unit 101 prior to generating the mapping 421A and prior to copying the one or more data values. Optionally, the mapping circuit 110 re-enables access to the memory component 120A and the memory component 120C from the processing unit 101 after copying the one or more data values.

[0080] Optionally, copying the one or more data values from the memory component 120A to the memory component 120C includes swapping the one or more data values with one or more other data values stored in the memory component 120C such that, after the swapping, the one or more data values are stored in the memory component 120C and the one or more other data values are stored in the memory component 120A. Optionally, the swapping between the one or more data values and the one or more other data values includes using one or more intermediate memory regions. Optionally, the one or more intermediate memory regions are located in one of the memory components 120. Optionally, the one or more intermediate memory regions are located in the mapping circuit 110.

[0081] Optionally, the mapping circuit 110 repeats one or more of 501, 502, 507, 510, and 520 in each of the plurality of management iterations. Optionally, the mapping circuit 110 performs the plurality of management iterations while the processing unit 101 executes the software program.

[0082] Optionally, in 540, the memory mapping circuit 110 receives one or more memory access commands from the processing unit 101. Optionally, the one or more memory access commands include a first memory address in the memory address range 201A. Optionally, in response to the received one or more memory access commands, in 541, the mapping circuit 110 replaces the first memory address in the one or more memory access commands with a second memory address in the memory address range 201F, according to the memory mapping 421A.

[0083] Optionally, the processing unit 101 sends the one or more memory access commands while executing the software program, optionally accessing the application memory of the software program, for example, the application memory region 301A.

[0084] Optionally, the memory mapping circuit 110 configures one or more of the plurality of thresholds, for example, the low access threshold or the high access threshold, in the one or more memory tracking circuits 130. Optionally, the memory mapping circuit 110 performs a further analysis including one or more statistical counters. Optionally, the memory mapping circuit 110 configures the one or more thresholds according to a further result of the further analysis.

[0085] Optionally, the memory mapping circuit 110 configures the low access threshold and / or configures the high access threshold in at least one of the plurality of management iterations while the processing unit 101 executes the software program.

[0086] The description of the various embodiments is merely meant to be illustrative and not exhaustive or limiting to the disclosed embodiments. Many modifications and variations of the described embodiments will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The choice of words in using the terminology used herein is best suited to explain the principles, practical application, or technological advance of the described embodiments, or to enable other skilled artisans to understand the described embodiments disclosed herein.

[0087] It is expected that during the life of a patent maturing from this application many relevant memory mapping circuits and memory tracking circuits will be developed and the scope of the memory mapping circuit and memory tracking circuit is intended to include all such new technologies a priori.

[0088] As used herein, the term "about" means ± 10%.

[0089] The terms "comprises", "comprising", "includes", "including" and "has" or "having", etc., are inclusive and therefore specify the presence of stated features, integers, steps, operations, objects, or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, objects, components, or groups thereof. The term "consisting of" means an exclusive inclusion, such that the composition of matter or process only includes the listed features, integers, steps, operations, objects, or components, and excludes all other features, integers, steps, operations, objects, components or groups thereof. The term "consisting essentially of" means an inclusive inclusion, such that the composition of matter or process includes the listed features, integers, steps, operations, objects, or components, and any additional features, integers, steps, operations, objects, components or groups thereof that do not materially affect the basic and novel characteristics of the claimed composition of matter or process.

[0090] The phrase "consisting essentially of" indicates that the composition or process can include additional ingredients and / or steps, but only if the additional ingredients and / or steps do not materially alter the basic and novel characteristics of the claimed composition or process.

[0091] As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. For example, the terms "a compound" or "at least one compound" can include more than one compound, including mixtures thereof.

[0092] As used herein, the term "exemplary" means "serving as an example, instance, or illustration." Any implementation described as "exemplary" is not necessarily to be construed as preferred or advantageous over other implementations.

[0093] As used herein, the term "optionally" means "in some embodiments provided, and in other embodiments not provided." Any particular embodiment can include multiple "optional" features unless such features conflict.

[0094] In this application, various embodiments can be presented through a range format. It should be understood that the description in range format is merely for convenience and brevity and is to be interpreted -in the context of the specification as a whole. Therefore, this description of a range should be considered as specifically and individually disavowing any endpoint in the described range except the specifically recited endpoint(s). Furthermore, it must be understood that the described ranges are not to be construed as being bound by the minimum and maximum values. Unless otherwise indicated, each numerical limitation disclosed herein includes every whole number and fraction within the range, up to the property limit of the respective range. For example, a range of "1 to 10" should be interpreted to include single integer values between 1 and 10, such as 1, 2, 3, 4, 5, 6, 7, 8, 9, and 10, as well as sub-ranges within the range, such as 1-6.1, 2-8.7, 3-6.6, 4-10, etc.

[0095] When a range of numbers is indicated herein, any recited number (fraction or integer) within the indicated range is included. The phrases "a range between a first indicated number and a second indicated number" and "a range from a first indicated number to a second indicated number" are used interchangeably herein to mean that the first and second indicated numbers are included and all fractions and integers between them.

[0096] It is to be understood that certain features of the embodiments described in the context of separate embodiments can also be provided in combination in a single embodiment. Conversely, various features of the embodiments described in the context of a single embodiment can also be provided separately or in any appropriate

[0097] Although the embodiments have been described in conjunction with specific embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, it is intended to embrace all such alternatives, modifications and variations as fall within the spirit and broad scope of the appended claims.

[0098] It is the intent of the Applicant that all publications, patents and patent applications referred to in this specification be incorporated in their entirety by reference into the specification, as if each individual publication, patent or patent application was specifically and individually indicated to be incorporated by reference. In addition, any reference to the application that could incorporate by reference any patent or patent application is not construed as an admission that such patent or patent application is prior art with respect to the instant application. To the extent that section headings are used, they should not be construed as necessarily limiting the subject matter described. In addition, any priority document(s) of this application is / are hereby incorporated by reference in its / their entirety.

Claims

1. A method for migrating data in a memory, the method comprising: The method is applied to a memory system, the memory system comprising a memory tracking circuit, a memory mapping circuit, a first memory component and a second memory component, the method comprising: The memory tracking circuit tracks a memory access command sent from a processing unit, the memory access command comprising a first address; Based on the first address, updating a first statistical counter corresponding to a first memory address range, wherein the first memory address range comprises the first address, and a size of the first memory address range is not equal to a size of any one page size in a set of page sizes; The memory tracking circuit provides the first statistical counter to the memory mapping circuit; The memory mapping circuit exchanges data between the first memory component and the second memory component based on statistical data in the first statistical counter, wherein the second memory component has higher performance access characteristics than the first memory component.

2. The method of claim 1, wherein, The memory mapping circuit manages a plurality of application memory regions corresponding to a plurality of memory address ranges.

3. The method of claim 1, wherein, The first memory address range corresponds to the first memory component.

4. The method of claim 2, wherein, The exchanging data between the first memory component and the second memory component based on statistical data in the first statistical counter comprises: The memory mapping circuit performs analysis of the first statistical counter; The memory mapping circuit moves data of at least one application memory region in the plurality of application memory regions from the first memory component to the second memory component based on a result of the analysis, wherein the plurality of application memory regions are memory regions accessible by a software program.

5. The method of claim 4, wherein, The memory mapping component maps the plurality of application memory regions when the processing unit executes the software program.

6. The method of claim 1, wherein, Comprises: The memory mapping circuit replaces the first address with a second address, the second address being an address on the second memory component.

7. A method for migrating data in a memory, the method comprising: The method is performed by a memory tracking circuit, comprising: Tracking a memory access command sent from a processing unit, the memory access command comprising a first address; Based on the first address, updating a first statistical counter corresponding to a first memory address range, wherein the first memory address range comprises the first address, and a size of the first memory address range is not equal to a size of any one page size in a set of page sizes; Providing the first statistical counter to a memory mapping circuit to instruct the memory mapping circuit to move an application memory region between a first memory component and a second memory component, wherein the second memory component has higher performance access characteristics than the first memory component, and the application memory region is a region frequently accessed by a software program.

8. The method of claim 7, wherein, The first memory address range corresponds to the first memory component.

9. The method according to any one of claims 7-8, characterized in that, Comprises: Replacing the first address with a second address, the second address being an address on the second memory component.

10. A memory management system, characterized by, Comprises a processing unit, a memory tracking circuit, a memory mapping circuit and a plurality of memory components, the memory components comprising a first memory component and a second memory component, wherein the memory tracking circuit is connected to the processing unit, the first memory component and the second memory component: The memory tracking circuit is configured to track a memory access command sent from the processing unit, the memory access command comprising a first address, and update a first statistical counter corresponding to a first memory address range based on the first address, wherein the first memory address range comprises the first address, and a size of the first memory address range is not equal to a size of any page size in a set of page sizes. The memory tracking circuit is further configured to provide the first statistical counter to the memory mapping circuit. The memory mapping circuit is configured to access the first statistical counter, and move data in an application memory region between the first memory component and the second memory component according to the first statistical counter, wherein the second memory component has a higher performance access characteristic than the first memory component, and the application memory region is a memory region frequently accessed by a software program.

11. The memory management system of claim 10, wherein, The first statistical counter is located in the memory tracking circuit. The first statistical counter is located in the first memory component or the second memory component.

12. The memory management system of claim 10, wherein, The memory mapping circuit is further configured to manage a plurality of application memory regions, the plurality of application memory regions comprising the application memory region, and the plurality of application memory regions corresponding to a plurality of memory address ranges. The first memory address range corresponds to the first memory component.

13. The memory management system according to any one of claims 10-12, wherein, The moving data in the application memory region between the first memory component and the second memory component according to the first statistical counter specifically comprises:

14. The memory management system of claim 10, wherein, The memory mapping circuit performs analysis of the first statistical counter; 15. The memory management system of claim 14, wherein, Based on a result of the analysis, moving at least one application memory region in the plurality of application memory regions from the first memory component to the second memory component, wherein the plurality of application memory regions are memory regions accessible by the software program. The memory management system further comprises a memory mapping component configured to map the plurality of application memory regions when the processing unit executes the software program. The memory mapping circuit replaces the first address with a second address, the second address being an address on the second memory component.

16. The memory management system of claim 15, wherein, The memory tracking circuit is configured to perform the method of any one of claims 7-9.

17. The memory management system of claim 10, wherein, ​ ​ 18. A memory trace circuit, comprising: ​

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