Back contact battery and photovoltaic module

Abstract

The invention discloses a back contact battery and a photovoltaic module, and relates to the technical field of photovoltaics. The back contact cell comprises a silicon substrate which comprises a first surface and a second surface which are oppositely arranged, and a side surface which connects the first surface and the second surface; the first interface passivation layer, the first doped silicon layer, the intrinsic silicon layer, the second doped silicon layer and the transparent conducting layer are sequentially arranged on the side face in the direction away from the side face. On the side surface of the silicon substrate, the first doped silicon layer is in direct contact with the intrinsic silicon layer; wherein the conduction types of the first doped silicon layer and the second doped silicon layer are opposite. On the side face of the silicon substrate, the first doped silicon layer can be electrically connected with the second doped silicon layer with the conduction type opposite to that of the first doped silicon layer through the intrinsic silicon layer, so that a diode structure with low reverse breakdown voltage is formed on the side face of the silicon substrate, and the hot spot risk of the back contact battery is reduced.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of the Chinese patent application filed with the China Patent Office on September 14, 2024, with application number 202411295529.0 and title “A Back-Contact Cell and Photovoltaic Module”, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present invention relates to the field of photovoltaic technology, and in particular to a back contact cell and a photovoltaic module. Background Art

[0004] A solar cell is a device that can convert sunlight into electrical energy. Specifically, when the solar cell is in operation, sunlight shines on the semiconductor pn junction of the solar cell, forming new hole-electron pairs. Under the action of the built-in electric field of the pn junction, photogenerated holes flow to the p region, and photogenerated electrons flow to the n region. When the circuit is connected, current can be generated. Among them, a solar cell in which both the positive electrode and the negative electrode are on the back of the cell is a back-contact cell. Compared with a double-sided contact solar cell, the front of the back-contact cell is not blocked by a metal electrode, so that the light-facing side of the back-contact cell has a higher light utilization rate. Therefore, the back-contact cell has a higher short-circuit current and photoelectric conversion efficiency, and is one of the current technical directions for achieving high-efficiency crystalline silicon cells.

[0005] However, existing back-contact cells passivate the front and back sides of the silicon substrate, while the sides of the silicon substrate are directly exposed. This causes severe side recombination and the risk of damage, thereby reducing the efficiency of the back-contact cell. Summary of the invention

[0006] The purpose of the present invention is to provide a back-contact cell and a photovoltaic module, which can protect the side of the silicon substrate by a film layer arranged on the side of the silicon substrate, thereby reducing the risk of damage to the side. At the same time, the side of the silicon substrate can be passivated to reduce carrier recombination on the side of the silicon substrate and improve the conversion efficiency of the back-contact cell.

[0007] In order to achieve the above-mentioned purpose, in a first aspect, the present invention provides a back-contact battery, which includes: a silicon substrate, a first interface passivation layer, a first doped silicon layer, a surface passivation layer, an anti-reflection layer, an intrinsic silicon layer, a second doped silicon layer and a transparent conductive layer. The silicon substrate includes a first surface and a second surface arranged opposite to each other, and a side surface connecting the first surface and the second surface. In a direction away from the side surface, the first interface passivation layer, the first doped silicon layer, the surface passivation layer, the anti-reflection layer, the intrinsic silicon layer, the second doped silicon layer and the transparent conductive layer are sequentially arranged on the side surface. The first doped silicon layer and the second doped silicon layer have opposite conductivity types. Among them, along the thickness direction of the silicon substrate, the surface passivation layer and the anti-reflection layer are also sequentially arranged on the second surface, and the surface passivation layer and the anti-reflection layer extend from the second surface to the side surface.

[0008] In the case of adopting the above technical solution, on the side of the silicon substrate and in the direction away from the side, a first interface passivation layer, a first doped silicon layer, a surface passivation layer, an anti-reflection layer, an intrinsic silicon layer, a second doped silicon layer and a transparent conductive layer are sequentially arranged. The presence of the above film layers can isolate the side of the silicon substrate from the external environment, reducing the risk of damage such as scratches on the side of the silicon substrate due to extrusion, collision and other factors after transportation or packaging. At the same time, it can also reduce the risk of water vapor and the like entering the battery from the side of the battery to cause battery failure, thereby increasing the service life of the back contact battery. In addition, the above surface passivation layer and anti-reflection layer are not only located on the second surface of the silicon substrate, but also extend to the side of the silicon substrate. At this time, on the side of the silicon substrate, the first doped silicon layer and the second doped silicon layer of opposite conductivity types can be isolated by the surface passivation layer and the anti-reflection layer to prevent the two from being turned on and leaking electricity, so that the back contact battery has a higher conversion efficiency. In addition, the surface passivation layer and the anti-reflection layer are arranged on the part of the second surface to reduce carrier recombination and surface reflectivity. The two layers are then extended to the side of the silicon substrate, and can also be used to isolate the first doped silicon layer and the second doped silicon layer. There is no need to form other insulating layers through other deposition steps to prevent leakage between the first doped silicon layer and the second doped silicon layer, which can simplify the manufacturing process of the back contact battery. At the same time, there is no need to consider the compatibility between the film layer that isolates the first doped silicon layer and the second doped silicon layer and other structures in the back contact battery, ensuring that the back contact battery has a high yield. At the same time, not only the first interface passivation layer and the first doped silicon layer arranged on the side of the silicon substrate have a passivation effect on the silicon substrate, but the surface passivation layer that achieves insulation isolation between the first doped silicon layer and the second doped silicon layer on the side can also passivate the side of the silicon substrate, further reducing the carrier recombination rate on the side of the silicon substrate and improving the conversion efficiency of the back contact battery.

[0009] In addition, in the actual manufacturing process, the order in which the corresponding film layers are formed on the first and second surfaces of the silicon substrate affects the order in which the corresponding film layers are formed on the side surfaces of the silicon substrate. Since the order in which the film layers are formed on the first and second surfaces of the silicon substrate is closely related to the process, battery structure, equipment, etc., the order in which the film layers are formed on the first and second surfaces of the silicon substrate cannot be adjusted arbitrarily, that is, the order in which the film layers are formed on the side surfaces of the silicon substrate cannot be adjusted arbitrarily, and needs to be comprehensively considered based on the requirements for the order in which the film layers are formed on the side surfaces of the silicon substrate, the technical problems to be solved, as well as the requirements for the order in which the film layers are formed on the front and back surfaces, the technical problems to be solved, etc.

[0010] As a possible implementation scheme, the first interface passivation layer and the first doped silicon layer arranged on the side are only located on a local area of ​​the side and close to the first surface. Wherein, along the thickness direction of the silicon substrate, the ratio between the maximum extension length of the first interface passivation layer and the first doped silicon layer on the side and the thickness of the silicon substrate is greater than or equal to 70%; and / or, the surface of the area on the side that is not covered by the first interface passivation layer and the first doped silicon layer is velvet, and the ratio between the maximum extension length of the velvet on the side and the thickness of the silicon substrate is less than or equal to 30%; and / or, the surface reflectivity of the area on the side that is not covered by the first interface passivation layer and the first doped silicon layer is less than the surface reflectivity of the area covering the first interface passivation layer and the first doped silicon layer; and / or, the surface of the area on the side that is not covered by the first interface passivation layer and the first doped silicon layer is velvet; and / or, the surface of the area on the side that covers the first interface passivation layer and the first doped silicon layer is a polished surface.

[0011] In the case of adopting the above technical solution, as mentioned above, the first interface passivation layer and the first doped silicon layer have a passivation effect on the side of the silicon substrate. Therefore, when the ratio between the maximum extension length of the first interface passivation layer and the first doped silicon layer on the side and the thickness of the silicon substrate is greater than or equal to 70%, it is ensured that the first interface passivation layer and the first doped silicon layer have a larger formation range on the side of the silicon substrate, so that more areas of the surface in the side have a lower carrier recombination rate, further improving the conversion efficiency of the back contact battery. In addition, most areas of the side of the silicon substrate are covered with the first interface passivation layer and the first doped silicon layer. At this time, the first interface passivation layer and the first doped silicon layer have a protective effect on most areas of the side of the silicon substrate, and when preventing the intrusion of water vapor, etc., it is ensured that the side of the silicon substrate has a thicker stacking protection, further improving the protection effect of the side of the silicon substrate. The surface of the area on the side that is not covered with the first interface passivation layer and the first doped silicon layer is velvet, and the application principle of the beneficial effect of the ratio between the maximum extension length of the velvet on the side and the thickness of the silicon substrate is less than or equal to 30% can be referred to the above, and will not be repeated here. In addition, compared with the area on the side that is covered with the first interface passivation layer and the first doped silicon layer, the surface reflectivity of the area on the side of the silicon substrate that is not covered with the first interface passivation layer and the first doped silicon layer is smaller. At this time, although the passivation effect of the surface of the area on the side of the silicon substrate that is not covered with the first interface passivation layer and the first doped silicon layer is relatively low, the surface of this area has a relatively high light trapping effect, which is conducive to more light being refracted from the side of the side of the silicon substrate close to the second surface into the silicon substrate, which is conducive to improving the conversion efficiency of the back contact battery. In addition, there is no need to strictly control the manufacturing conditions in order to retain all the first interface passivation layer and the first doped silicon layer on the side in the process of removing the first interface passivation layer and the first doped silicon layer plated on the second surface, thereby reducing the difficulty of manufacturing the back contact battery. Furthermore, when the surface of the area covering the first interface passivation layer and the first doped silicon layer in the side surface is a polished surface, the surface of the area covering the first interface passivation layer and the first doped silicon layer in the side surface is relatively flat, which is conducive to forming a thicker first interface passivation layer and first doped silicon layer in this area, thereby enhancing the passivation effect of the first interface passivation layer and the first doped silicon layer on the corresponding area of ​​the side surface, and further improving the conversion efficiency of the back contact battery.

[0012] As a possible implementation scheme, the thickness of each part of the first interface passivation layer and / or the first doped silicon layer is the same. In this case, it is beneficial to make each part of the first interface passivation layer and / or the first doped silicon layer have a higher passivation effect, so that each region in the silicon substrate corresponding to the first interface passivation layer and / or the first doped silicon layer in the silicon substrate has a relatively low carrier recombination rate, further improving the conversion efficiency of the back contact battery.

[0013] As a possible implementation scheme, the thickness of the surface passivation layer is equal on the side surfaces of the silicon substrate, or the thickness of the surface passivation layer gradually increases from the first surface to the second surface.

[0014] When the above technical solution is adopted, within a certain range, the thickness of the surface passivation layer is proportional to its own passivation effect and insulation isolation effect. Based on this, when the thickness of the surface passivation layer is equal on the side of the silicon substrate, each part of the surface passivation layer has a higher passivation effect and a higher insulation isolation characteristic, which is conducive to making each area covered with the surface passivation layer on the side of the silicon substrate have a lower number of surface defects, and is also conducive to better realizing the electrical isolation effect of the first doped silicon layer and the second doped silicon layer through the surface passivation layer with uniform thickness, thereby reducing forward leakage. When the thickness of the surface passivation layer gradually increases from the first surface to the second surface, the part of the surface passivation layer on the side close to the second surface has a higher passivation effect and better insulation isolation characteristics, further reducing the number of surface defects in the area close to the second surface on the side of the silicon substrate, while further reducing the leakage risk between the first doped silicon layer and the second doped silicon layer, which is conducive to increasing the open circuit voltage and fill factor of the back contact battery.

[0015] As a possible implementation scheme, on the side of the silicon substrate, the thickness of the anti-reflection layer gradually increases from the first surface to the second surface. In this case, the portion of the surface passivation layer on the side close to the second surface has better insulation isolation characteristics, further reducing the leakage risk between the first doped silicon layer and the second doped silicon layer, which is beneficial to increase the open circuit voltage and fill factor of the back contact battery.

[0016] As a possible implementation scheme, on the side surface of the silicon substrate, the thickness of at least one of the intrinsic silicon layer, the second doped silicon layer and the transparent conductive layer gradually increases along the direction from the second surface to the first surface.

[0017] When the above technical solution is adopted, on the side of the silicon substrate, at least one of the intrinsic silicon layer, the second doped silicon layer and the transparent conductive layer has a larger thickness close to the first surface, which is beneficial to improving the protective effect of the film layer on the area close to the first surface on the side of the silicon substrate, and can further improve the structural reliability of the side of the back contact battery.

[0018] As a possible implementation scheme, the surface passivation layer and the anti-reflection layer disposed on the side surface are located on a local area of ​​the side surface and close to the second surface. Along the thickness direction of the silicon substrate, the ratio between the maximum extension length of the surface passivation layer and the anti-reflection layer on the side surface and the thickness of the silicon substrate is less than or equal to 80%.

[0019] In the case of adopting the above technical solution, when a surface passivation layer and an anti-reflection layer are formed on the second surface and the side of the silicon substrate, a surface passivation layer and an anti-reflection layer may also be formed on the side of the first surface due to the coating. In order to eliminate the influence of the surface passivation layer and the anti-reflection layer of the first surface on the carrier collection efficiency of the second interface passivation layer and the second doped silicon layer, it is necessary to remove the part of the two that are coated around the first surface. Based on this, when the surface passivation layer and the anti-reflection layer arranged on the side can be located on the local area of ​​the side, the difficulty of removing the part of the surface passivation layer and the anti-reflection layer that are coated around the first surface can be reduced, and the manufacturing precision requirements can be reduced. In addition, in the area of ​​the side of the silicon substrate that is not covered with the surface passivation layer and the anti-reflection layer, the first doped silicon layer can be electrically contacted with the second doped silicon layer of the opposite conductivity type to itself through the second interface passivation layer, thereby forming a diode structure with a lower reverse breakdown voltage on the side of the silicon substrate, which is conducive to reducing the risk of hot spots of the back contact battery and improving the anti-burning ability of the back contact battery.

[0020] As a possible implementation scheme, the above-mentioned first surface includes a first area and a second area distributed at intervals. The first interface passivation layer and the first doped silicon layer are arranged on the first area. The intrinsic silicon layer and the second doped silicon layer are arranged in the second area, and extend from the second area to the first area, and cover part of the first interface passivation layer and the first doped silicon layer. In addition, the back contact battery also includes an insulating mask layer. The insulating mask layer is arranged between the first doped silicon layer and the surface passivation layer located on the side, and the insulating mask layer is also arranged between the intrinsic silicon layer and the first doped silicon layer located on the first surface along the thickness direction of the silicon substrate.

[0021] In the case of adopting the above technical solution, on the first surface of the silicon substrate, the intrinsic silicon layer and the second doped silicon layer are not only stacked in sequence in the second region along the thickness direction of the silicon substrate, but also cover part of the first interface passivation layer and the first doped silicon layer. At this time, the formation range of the intrinsic silicon layer and the second doped silicon layer on the first surface side of the silicon substrate is relatively large, which is conducive to reducing the etching range of the intrinsic silicon layer and the second doped silicon layer set in the whole layer during the manufacturing process, and is conducive to improving the etching capacity. In addition, the part of the intrinsic silicon layer and the second doped silicon layer covering the first doped silicon layer can protect the edge of the first doped silicon layer, prevent the etchant from affecting the edge of the first doped silicon layer, and ensure that the edge of the first doped silicon layer has a higher carrier collection efficiency. The insulating mask layer can separate the first doped silicon layer and the second doped silicon layer on the side together with the surface passivation layer and the anti-reflection layer, further suppressing the side leakage. At the same time, the side of the silicon substrate can also be passivated to further reduce the number of defects on the side of the silicon substrate. In addition, an insulating mask layer is also formed on the side, which helps to reduce the thickness requirement for the intrinsic silicon layer. While ensuring a lower forward leakage between the first doped silicon layer and the second doped silicon layer, the intrinsic silicon layer has a lower tunneling resistance, which helps to improve the carrier collection efficiency of the second doped silicon layer on the first side.

[0022] As a possible implementation scheme, on the side of the silicon substrate, the thickness of the insulating mask layer gradually increases from the second surface to the first surface. The application principle of the beneficial effect in this case is similar to the application principle of the beneficial effect of the thickness of the surface passivation layer gradually increasing from the first surface to the second surface on the side of the silicon substrate as described above, and will not be repeated here.

[0023] As a possible implementation scheme, the insulating mask layer arranged on the side is located on a local area of ​​the side; along the thickness direction of the silicon substrate, the ratio between the maximum extension length of the insulating mask layer on the side and the thickness of the silicon substrate is less than or equal to 80%.

[0024] In the case of adopting the above technical solution, it can be understood that the greater the extension length of the insulating mask layer on the side, the first doped silicon layer and the second doped silicon layer in the side of the silicon substrate can be isolated by forming a larger insulating mask layer, the lower the forward leakage of the back contact battery, and the stronger the protective effect of the insulating mask layer on the side of the silicon substrate. The smaller the extension length of the insulating mask layer on the side, the larger the range of the reverse leakage area formed between the first doped silicon layer and the second doped silicon layer in the side of the silicon substrate, and the lower the hot spot risk of the back contact battery. Based on this, when the ratio between the maximum extension length of the insulating mask layer on the side and the thickness of the silicon substrate is less than or equal to 80%, the forward leakage, hot spot risk and side protection of the back contact battery can be regulated by adjusting the maximum extension length of the insulating mask layer on the side according to the actual application scenario requirements of the back contact battery, which is conducive to achieving a balance between the forward leakage, hot spot risk and side protection of the back contact battery.

[0025] As a possible implementation solution, the material of the surface passivation layer includes at least one of aluminum oxide, intrinsic amorphous silicon, and doped silicon glass.

[0026] In the case of the above technical solution, aluminum oxide and intrinsic amorphous silicon contain hydrogen. When the material of the surface passivation layer includes aluminum oxide and / or intrinsic amorphous silicon, the silicon substrate and the first doped silicon layer can be hydrogen passivated to further improve the passivation effect of the surface passivation layer. The doped silicon glass is doped with impurities of the corresponding conductive type, and the silicon substrate and the first doped silicon layer can also be field passivated, which can also further improve the passivation effect of the surface passivation layer. Secondly, the manufacturing process of the surface passivation layer made of doped silicon glass is also relatively simple, which is conducive to reducing the difficulty of manufacturing back-contact batteries.

[0027] As a possible implementation solution, the thickness of the first doped silicon layer is greater than or equal to 30 nm and less than or equal to 140 nm.

[0028] When the above technical solution is adopted, the presence of the transparent conductive layer can improve the carrier collection efficiency and leave room for thinning the first doped silicon layer. In other words, without reducing the carrier collection efficiency, the thickness of the first doped silicon layer can be appropriately reduced due to the presence of the transparent conductive layer. Based on this, when the thickness of the first doped silicon layer is within the above range, the thickness of the first doped silicon layer is small, which is conducive to reducing its own parasitic absorption and further improving the working efficiency of the back contact battery. In addition, the deposition time of the first doped silicon layer can be reduced, and the production efficiency of the first doped silicon layer can be improved.

[0029] As a possible implementation scheme, the thickness of the intrinsic silicon layer is greater than or equal to 8 nm and less than or equal to 14 nm. In this case, the thickness of the intrinsic silicon layer is relatively large, which is conducive to enhancing the isolation effect of the intrinsic silicon layer on the first doped silicon layer and the second doped silicon layer, and reducing the risk of forward leakage.

[0030] As a possible implementation scheme, in the side of the silicon substrate, the surface of the region where the first interface passivation layer and the first doped silicon layer are provided has a tower-like texture structure. Moreover, the thickness of the first interface passivation layer located at the bottom surface of the tower-like texture structure is less than the thickness of the first interface passivation layer located on the side wall of the tower-like texture structure.

[0031] In the case of adopting the above technical solution, it can be understood that the bottom surface of the tower-shaped texture structure and the side wall of the tower-shaped texture structure have different crystal orientations. Specifically, the bottom surface of the tower-shaped texture structure is the

[110] crystal orientation, and the number of dangling bonds on the surface of the

[110] crystal orientation is relatively small; while the side wall of the tower-shaped texture structure is the

[111] crystal orientation, and the number of dangling bonds in the

[111] crystal orientation is relatively large. Based on this, when the thickness of the first interface passivation layer located on the bottom surface of the tower-shaped texture structure is less than the thickness of the first interface passivation layer located on the side wall of the tower-shaped texture structure, it is beneficial to make the thickness of the first interface passivation layer located on the side wall of the tower-shaped texture structure have a relatively high passivation effect, meet the demand for high passivation effect of the side wall of the tower-shaped texture structure, reduce the carrier recombination rate of the side wall of the tower-shaped texture structure, and further improve the working efficiency of the back contact battery.

[0032] As a possible implementation scheme, the side of the silicon substrate has a tower-shaped texture structure. The thickness of the first interface passivation layer at the bottom surface of the tower-shaped texture structure is less than the thickness of the first interface passivation layer at the side wall of the tower-shaped texture structure. The thickness of the intrinsic silicon layer at the bottom surface of the tower-shaped texture structure is greater than the thickness of the intrinsic silicon layer at the side wall of the tower-shaped texture structure; and / or the thickness of the second doped silicon layer at the bottom surface of the tower-shaped texture structure is greater than the thickness of the second doped silicon layer at the side wall of the tower-shaped texture structure.

[0033] When the above technical solution is adopted, the thickness relationship of the first interface passivation layer at the bottom surface and the side wall of the tower-shaped texture structure is opposite to the thickness relationship of the intrinsic silicon layer and / or the second doped silicon layer at the bottom surface and the side wall of the tower-shaped texture structure. At this time, the thickness of the first interface passivation layer at the side wall of the tower-shaped texture structure is relatively large, which can make up for the fact that the thickness of the intrinsic silicon layer and / or the second doped silicon layer at the side wall of the tower-shaped texture structure is relatively small, resulting in weaker passivation effect and protection effect of the first interface passivation layer; and, the thickness of the intrinsic silicon layer and / or the second doped silicon layer at the bottom surface of the tower-shaped texture structure is relatively large, which can make up for the fact that the thickness of the first interface passivation layer at the bottom surface of the tower-shaped texture structure is relatively small, resulting in weaker passivation effect and protection effect of the first interface passivation layer, thereby ensuring that under the common passivation effect and protection effect of the first interface passivation layer, and the intrinsic silicon layer and / or the second doped silicon layer, the bottom and side surfaces of the tower-shaped texture structure corresponding to the side surface of the silicon substrate have a higher passivation effect and protection strength.

[0034] As a possible implementation scheme, a doping layer is formed in the side surface of the silicon substrate, and the dopant in the doping layer includes the dopant in the first doped silicon layer.

[0035] When the above technical solution is adopted, the doped layer can form a high-low junction with the first doped silicon layer, so that the energy band between the first doped silicon layer and the side of the silicon substrate is more matched, thereby improving the passivation effect of the first doped silicon layer on the side of the silicon substrate and increasing the open circuit voltage of the back contact battery.

[0036] In a second aspect, the present invention provides another back-contact battery, which includes: a silicon substrate, a first interface passivation layer, a first doped silicon layer, an intrinsic silicon layer, a second doped silicon layer and a transparent conductive layer. The silicon substrate includes a first surface and a second surface arranged opposite to each other, and a side surface connecting the first surface and the second surface. In a direction away from the side surface, the first doped silicon layer, the intrinsic silicon layer, the second doped silicon layer and the transparent conductive layer are sequentially arranged on the side surface. On the side surface of the silicon substrate, the first doped silicon layer and the intrinsic silicon layer are in direct contact. The conductivity types of the first doped silicon layer and the second doped silicon layer are opposite.

[0037] When the above technical solution is adopted, on the side of the silicon substrate, the first doped silicon layer can be electrically connected through the intrinsic silicon layer and the second doped silicon layer of the opposite conductivity type to itself, thereby forming a diode structure with a lower reverse breakdown voltage on the side of the silicon substrate, reducing the risk of hot spots in the back contact battery. At the same time, the first doped silicon layer, the intrinsic silicon layer, and the second doped silicon layer arranged on the side of the silicon substrate can also passivate the side of the silicon substrate, reduce the carrier recombination rate on the side of the silicon substrate, and improve the conversion efficiency of the back contact battery. Secondly, the first doped silicon layer, the intrinsic silicon layer, and the second doped silicon layer arranged on the side of the silicon substrate can also protect the side of the silicon substrate, reduce the risk of damage and leakage due to the side of the silicon substrate being directly exposed to the outside, and improve the structural reliability of the back contact battery. In addition, in the actual manufacturing process, the order in which the corresponding film layers are formed on the first and second surfaces of the silicon substrate affects the order in which the corresponding film layers are formed on the side surfaces of the silicon substrate. Since the order in which the film layers are formed on the first and second surfaces of the silicon substrate is closely related to the process, battery structure, equipment, etc., the order in which the film layers are formed on the first and second surfaces of the silicon substrate cannot be adjusted arbitrarily, that is, the order in which the film layers are formed on the side surfaces of the silicon substrate cannot be adjusted arbitrarily, and needs to be comprehensively considered based on the requirements for the order in which the film layers are formed on the side surfaces of the silicon substrate, the technical problems to be solved, as well as the requirements for the order in which the film layers are formed on the front and back surfaces, the technical problems to be solved, etc.

[0038] As a possible implementation scheme, the back contact battery includes a surface passivation layer disposed on the second surface, and the surface passivation layer extends from the second surface to the side surface. In addition, the back contact battery also includes a second interface passivation layer disposed on the first surface and located between the silicon substrate and the second doped silicon layer, and the second interface passivation layer extends from the first surface to the side surface. Based on this, on the side surface, the intrinsic silicon layer includes a surface passivation layer and a second interface passivation layer stacked in a direction away from the side surface.

[0039] When the above technical solution is adopted, on the side of the silicon substrate, there are two film layers, a surface passivation layer and a second interface passivation layer, between the first doped silicon layer and the second doped silicon layer. At this time, the intrinsic silicon layer has a certain transmission resistance, which is beneficial to reduce the forward leakage of the back contact battery and balance the conversion efficiency and hot spot risk of the back contact battery. In addition, while obtaining lower forward leakage, there is no need to form a thicker intrinsic silicon layer, which results in a single second interface passivation layer or a larger surface passivation layer, ensuring that the second interface passivation layer has a lower tunneling resistance and the surface passivation layer has a lower barrier effect on light transmission, ensuring that the back contact battery has a higher conversion efficiency.

[0040] As a possible implementation scheme, the thickness of each part of the intrinsic silicon layer is the same on the side of the silicon substrate. In this case, each part of the intrinsic silicon layer disposed on the side of the silicon substrate has a high passivation performance and protective effect, which can further reduce the carrier recombination rate on the side of the silicon substrate and improve the structural reliability of the back contact battery.

[0041] As a possible implementation solution, on the side of the silicon substrate, the thickness of the intrinsic silicon layer is greater than or equal to 5 nm and less than or equal to 30 nm.

[0042] When the above technical solution is adopted, the thickness of the intrinsic silicon layer on the side of the silicon substrate is within the above range, which is conducive to preventing the intrinsic silicon layer from having poor passivation performance and protection due to its small thickness, ensuring that the side has a low carrier recombination rate and high structural reliability, and also helping to reduce the forward leakage loss of the back contact battery. It can also prevent the thickness of the second interface passivation layer (or the second interface passivation layer and the surface passivation layer) from being large due to the large thickness of the intrinsic silicon layer, ensuring that the second interface passivation layer has a low tunneling resistance, and the surface passivation layer has a low barrier effect on light transmission, ensuring that the back contact battery has a high conversion efficiency.

[0043] As a possible implementation scheme, the back contact cell further includes an anti-reflection layer. On the second surface, the anti-reflection layer is arranged on the side of the surface passivation layer away from the silicon substrate. The anti-reflection layer extends from the second surface to the side surface, and on the side surface, the anti-reflection layer is arranged between the second doped silicon layer and the transparent conductive layer.

[0044] In the case of adopting the above technical solution, an anti-reflection layer is added to the film layer arranged on the side of the silicon substrate, which can further improve the protection of the side of the silicon substrate, reduce the risk of damage to the side of the silicon substrate, and reduce the forward leakage loss. In addition, in this case, the anti-reflection layer is directly formed on the side of the second doped silicon layer away from the silicon substrate. Because there is a difference between the materials of the surface passivation layer and the second doped silicon layer, and the anti-reflection layer is more easily deposited on the surface passivation layer. Based on this, compared with the anti-reflection layer being directly formed on the surface passivation layer, when the anti-reflection layer is directly formed on the side of the second doped silicon layer away from the silicon substrate, the coating range of the anti-reflection layer on one side of the first surface can be reduced, thereby reducing the etching amount when removing the anti-reflection layer when coating on the first surface, and improving manufacturing efficiency.

[0045] As a possible implementation scheme, the above-mentioned back contact cell further includes a surface passivation layer and an anti-reflection layer sequentially arranged on the second surface along the thickness direction of the silicon substrate, and the surface passivation layer and the anti-reflection layer extend from the second surface to the side surface. Moreover, on the side surface, and in the direction away from the side surface, the surface passivation layer and the anti-reflection layer are sequentially stacked and arranged between the second doped silicon layer and the transparent conductive layer. In this case, the presence of the surface passivation layer and the anti-reflection layer can further enhance the protective effect on the side surface of the silicon substrate and reduce the risk of damage to the side surface of the silicon substrate.

[0046] As a possible implementation scheme, a doping layer is formed in the side surface of the silicon substrate, and the dopant in the doping layer includes the dopant in the first doped silicon layer.

[0047] As a possible implementation scheme, the first interface passivation layer and the first doped silicon layer arranged on the side are only located on a local area of ​​the side and close to the first surface. Wherein, along the thickness direction of the silicon substrate, the ratio between the maximum extension length of the first interface passivation layer and the first doped silicon layer on the side and the thickness of the silicon substrate is greater than or equal to 70%; and / or, the surface of the area on the side that is not covered by the first interface passivation layer and the first doped silicon layer is velvet, and the ratio between the maximum extension length of the velvet on the side and the thickness of the silicon substrate is less than or equal to 30%; and / or, the surface reflectivity of the area on the side that is not covered by the first interface passivation layer and the first doped silicon layer is less than the surface reflectivity of the area covering the first interface passivation layer and the first doped silicon layer; and / or, the surface of the area on the side that is not covered by the first interface passivation layer and the first doped silicon layer is velvet; and / or, the surface of the area on the side that covers the first interface passivation layer and the first doped silicon layer is a polished surface.

[0048] As a possible implementation scheme, the thicknesses of various parts of the first interface passivation layer and / or the first doped silicon layer are the same.

[0049] As a possible implementation scheme, the thickness of the surface passivation layer is equal on the side surfaces of the silicon substrate, or the thickness of the surface passivation layer gradually increases from the first surface to the second surface.

[0050] As a possible implementation scheme, on the side surface of the silicon substrate, the thickness of the anti-reflection layer gradually increases along the direction from the first surface to the second surface.

[0051] As a possible implementation scheme, on the side surface of the silicon substrate, the thickness of the second doped silicon layer and / or the transparent conductive layer gradually increases along the direction from the second surface to the first surface.

[0052] As a possible implementation scheme, the surface passivation layer and the anti-reflection layer arranged on the side are located on a local area of ​​the side and close to the second surface; along the thickness direction of the silicon substrate, the ratio between the maximum extension length of the surface passivation layer and the anti-reflection layer on the side and the thickness of the silicon substrate is less than or equal to 80%.

[0053] As a possible implementation scheme, the surface passivation layer arranged on the side is located on a local area of ​​the side and close to the second surface; along the thickness direction of the silicon substrate, the ratio between the maximum extension length of the surface passivation layer on the side and the thickness of the silicon substrate is less than or equal to 80%.

[0054] As a possible implementation, the anti-reflection layer disposed on the side is located on a local area of ​​the side and close to the second surface; along the thickness direction of the silicon substrate, the ratio between the maximum extension length of the anti-reflection layer on the side and the thickness of the silicon substrate is less than or equal to 80%. As a possible implementation, the material of the surface passivation layer includes at least one of aluminum oxide, intrinsic amorphous silicon, and doped silicon glass. As a possible implementation, the thickness of the first doped silicon layer is greater than or equal to 30nm and less than or equal to 140nm.

[0055] As a possible implementation scheme, in the side of the silicon substrate, the surface of the region where the first interface passivation layer and the first doped silicon layer are provided has a tower-like texture structure. Moreover, the thickness of the first interface passivation layer located at the bottom surface of the tower-like texture structure is less than the thickness of the first interface passivation layer located on the side wall of the tower-like texture structure.

[0056] As a possible implementation scheme, in the side of the silicon substrate, the surface of the region where the first interface passivation layer and the first doped silicon layer are provided has a tower-like texture structure. Moreover, the thickness of the first interface passivation layer located at the bottom surface of the tower-like texture structure is greater than the thickness of the first interface passivation layer located on the side wall of the tower-like texture structure.

[0057] As a possible implementation scheme, the side of the silicon substrate has a tower-like texture structure; wherein the thickness of the first interface passivation layer located at the bottom surface of the tower-like texture structure is less than the thickness of the first interface passivation layer located at the side wall of the tower-like texture structure; the thickness of the intrinsic silicon layer located at the bottom surface of the tower-like texture structure is greater than the thickness of the intrinsic silicon layer located at the side wall of the tower-like texture structure; and / or the thickness of the second doped silicon layer located at the bottom surface of the tower-like texture structure is greater than the thickness of the second doped silicon layer located at the side wall of the tower-like texture structure.

[0058] It should be understood that in the second aspect and the first aspect, the same or similar possible implementation schemes have the same or similar technical effects, which will not be described in detail here.

[0059] In a third aspect, the present invention provides another back contact battery. The back contact battery comprises: a silicon substrate, a first interface passivation layer, a first doped silicon layer, an insulating mask layer, an intrinsic silicon layer, a second doped silicon layer and a transparent conductive layer. The silicon substrate comprises a first surface and a second surface arranged opposite to each other, and a side surface connecting the first surface and the second surface. In a direction away from the side surface, the first interface passivation layer, the first doped silicon layer, the insulating mask layer, the intrinsic silicon layer, the second doped silicon layer and the transparent conductive layer are sequentially arranged on the side surface. The first doped silicon layer and the second doped silicon layer have opposite conductivity types. Among them, the back contact battery comprises a surface passivation layer arranged on the second surface, and the surface passivation layer extends from the second surface to the side surface; the back contact battery also comprises a second interface passivation layer arranged on the first surface and located between the silicon substrate and the second doped silicon layer, and the second interface passivation layer extends from the above-mentioned first surface to the side surface; on the side surface, the intrinsic silicon layer comprises a surface passivation layer and a second interface passivation layer stacked in a direction away from the side surface.

[0060] In the case of adopting the above technical solution, in addition to the intrinsic silicon layer disposed between the first doped silicon layer and the second doped silicon layer, an insulating mask layer is also disposed. While ensuring the reduction of forward leakage loss, the thickness requirement of the intrinsic silicon layer can also be reduced, and the tunneling resistance of the intrinsic silicon layer can be reduced, which is conducive to improving the hand collection efficiency of the second doped silicon layer disposed on the side of the first surface of the silicon substrate for carriers, and further improving the conversion efficiency of the back contact battery. In addition, the presence of the insulating mask layer can also enhance the protection of the side surface of the silicon substrate, and further improve the side structure reliability of the back contact battery. In addition, in the actual manufacturing process, the order of formation of the corresponding film layers disposed on the first surface and the second surface of the silicon substrate affects the order of formation of the corresponding film layers on the side surface of the silicon substrate. Since the order of formation of the film layers on the first surface and the second surface of the silicon substrate is closely related to the process, the battery structure, the equipment, etc., the order of formation of the film layers on the first surface and the second surface of the silicon substrate cannot be adjusted arbitrarily, that is, the order of film layers formed on the side surface of the silicon substrate cannot be adjusted arbitrarily, and needs to be comprehensively considered according to the requirements for the order of formation of the film layers on the side surface of the silicon substrate, the technical problems to be solved, and the requirements for the order of formation of the front and back film layers, and the technical problems to be solved.

[0061] As a possible implementation scheme, the back contact cell further includes an anti-reflection layer disposed on the second surface, the anti-reflection layer extending from the second surface to the side surface. On the side surface, the anti-reflection layer is disposed between the second doped silicon layer and the transparent conductive layer in a direction away from the side surface.

[0062] In the case of adopting the above technical solution, an anti-reflection layer is added to the film layer arranged on the side of the silicon substrate, which can further improve the protection of the side of the silicon substrate, reduce the risk of damage to the side of the silicon substrate, and reduce the forward leakage loss. In addition, in this case, the anti-reflection layer is directly formed on the side of the second doped silicon layer away from the silicon substrate. Because there is a difference between the materials of the surface passivation layer and the second doped silicon layer, and the anti-reflection layer is more easily deposited on the surface passivation layer. Based on this, compared with the anti-reflection layer being directly formed on the surface passivation layer, when the anti-reflection layer is directly formed on the side of the second doped silicon layer away from the silicon substrate, the coating range of the anti-reflection layer on one side of the first surface can be reduced, thereby reducing the etching amount when removing the anti-reflection layer when coating on the first surface, and improving manufacturing efficiency.

[0063] As a possible implementation scheme, a doping layer is formed in the side surface of the silicon substrate, and the dopant in the doping layer includes the dopant in the first doped silicon layer.

[0064] As a possible implementation scheme, the first interface passivation layer and the first doped silicon layer arranged on the side are only located on a local area of ​​the side and close to the first surface. Wherein, along the thickness direction of the silicon substrate, the ratio between the maximum extension length of the first interface passivation layer and the first doped silicon layer on the side and the thickness of the silicon substrate is greater than or equal to 70%; and / or, the surface of the area on the side that is not covered by the first interface passivation layer and the first doped silicon layer is velvet, and the ratio between the maximum extension length of the velvet on the side and the thickness of the silicon substrate is less than or equal to 30%; and / or, the surface reflectivity of the area on the side that is not covered by the first interface passivation layer and the first doped silicon layer is less than the surface reflectivity of the area covering the first interface passivation layer and the first doped silicon layer; and / or, the surface of the area on the side that is not covered by the first interface passivation layer and the first doped silicon layer is velvet; and / or, the surface of the area on the side that covers the first interface passivation layer and the first doped silicon layer is a polished surface.

[0065] As a possible implementation scheme, the thicknesses of various parts of the first interface passivation layer and / or the first doped silicon layer are the same.

[0066] As a possible implementation scheme, the thickness of the surface passivation layer is equal on the side surfaces of the silicon substrate, or the thickness of the surface passivation layer gradually increases from the first surface to the second surface.

[0067] As a possible implementation scheme, on the side surface of the silicon substrate, the thickness of the anti-reflection layer gradually increases along the direction from the first surface to the second surface.

[0068] As a possible implementation scheme, on the side surface of the silicon substrate, the thickness of the second doped silicon layer and / or the transparent conductive layer gradually increases along the direction from the second surface to the first surface.

[0069] As a possible implementation solution, the thickness of the first doped silicon layer is greater than or equal to 30 nm and less than or equal to 140 nm.

[0070] As a possible implementation scheme, in the side of the silicon substrate, the surface of the region where the first interface passivation layer and the first doped silicon layer are provided has a tower-like texture structure. Moreover, the thickness of the first interface passivation layer located at the bottom surface of the tower-like texture structure is less than the thickness of the first interface passivation layer located on the side wall of the tower-like texture structure.

[0071] As a possible implementation scheme, in the side of the silicon substrate, the surface of the region where the first interface passivation layer and the first doped silicon layer are provided has a tower-like texture structure. Moreover, the thickness of the first interface passivation layer located at the bottom surface of the tower-like texture structure is greater than the thickness of the first interface passivation layer located on the side wall of the tower-like texture structure.

[0072] In a fourth aspect, the present invention provides a photovoltaic module, comprising: a back-contact cell as provided in the first aspect and its various implementations, or a back-contact cell as provided in the second aspect and its various implementations, or a back-contact cell as provided in the third aspect and its various implementations.

[0073] The beneficial effects of the fourth aspect of the present invention and its various implementations may refer to the analysis of the beneficial effects in the first aspect and its various implementations, or may refer to the analysis of the beneficial effects in the second aspect and its various implementations, or may refer to the analysis of the beneficial effects in the third aspect and its various implementations, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0074] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0075] Figure 1 A schematic longitudinal cross-sectional view of the structure of a back contact battery provided in an embodiment of the present invention Figure 1 ;

[0076] Figure 2 A schematic longitudinal cross-sectional view of the structure of a back contact battery provided in an embodiment of the present invention Figure 2 ;

[0077] Figure 3 A schematic longitudinal cross-sectional view of the structure of a back contact battery provided in an embodiment of the present invention Figure 3 ;

[0078] Figure 4 A schematic longitudinal cross-sectional view of the structure of a back contact battery provided in an embodiment of the present invention Figure 4 ;

[0079] Figure 5 A schematic longitudinal cross-sectional view of the structure of a back contact battery provided in an embodiment of the present invention Figure 5 ;

[0080] Figure 6 A schematic longitudinal cross-sectional view of the structure of a back contact battery provided in an embodiment of the present invention Figure 6 ;

[0081] Figure 7 A schematic longitudinal cross-sectional view of the structure of a back contact battery provided in an embodiment of the present invention Figure 7 ;

[0082] Figure 8 A schematic longitudinal cross-sectional view of the structure of a back contact battery provided in an embodiment of the present invention Figure 8 ;

[0083] Fig. 9 A schematic longitudinal cross-sectional view of the structure of a back contact battery provided in an embodiment of the present invention Figure 9 ;

[0084] Fig.10 A schematic longitudinal cross-sectional view of the structure of a back contact battery provided in an embodiment of the present invention Figure 10 ;

[0085] Fig.11 A schematic longitudinal cross-sectional view of the structure of a back contact battery provided in an embodiment of the present invention Figure 10 one.

[0086] Figure numerals: 11 is a silicon substrate, 12 is a first doped silicon layer, 13 is a surface passivation layer, 14 is an anti-reflection layer, 15 is an intrinsic silicon layer, 16 is a second doped silicon layer, 17 is a transparent conductive layer, 18 is a first region, 19 is a second region, 20 is a first interface passivation layer, 21 is an insulating mask layer, and 22 is a second interface passivation layer. DETAILED DESCRIPTION

[0087] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present invention. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of the concept of the present invention.

[0088] Various structural schematic diagrams according to embodiments of the present invention are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for a clearer expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0089] In the context of the present invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. In addition, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "under" the other layer / element. In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0090] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. The meaning of "several" is one or more, unless otherwise clearly and specifically defined.

[0091] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0092] A solar cell is a device that can convert sunlight into electrical energy. Specifically, when the solar cell is in operation, sunlight shines on the semiconductor pn junction of the solar cell, forming new hole-electron pairs. Under the action of the built-in electric field of the pn junction, photogenerated holes flow to the p region, and photogenerated electrons flow to the n region. When the circuit is connected, current can be generated. Among them, a solar cell in which both the positive electrode and the negative electrode are on the back of the cell is a back-contact cell. Compared with a double-sided contact solar cell, the front of the back-contact cell is not blocked by a metal electrode, so that the light-facing side of the back-contact cell has a higher light utilization rate. Therefore, the back-contact cell has a higher short-circuit current and photoelectric conversion efficiency, and is one of the current technical directions for achieving high-efficiency crystalline silicon cells.

[0093] However, existing back-contact cells passivate the front and back sides of the silicon substrate, while the sides of the silicon substrate are directly exposed. This causes severe side recombination and the risk of damage, thereby reducing the efficiency of the back-contact cell.

[0094] In order to solve the above technical problems, in the first aspect, an embodiment of the present invention provides a back contact battery. Figure 1 As shown, the back contact cell provided by the embodiment of the present invention includes: a silicon substrate 11, a first interface passivation layer 20, a first doped silicon layer 12, a surface passivation layer 13, an anti-reflection layer 14, an intrinsic silicon layer 15, a second doped silicon layer 16 and a transparent conductive layer 17. The silicon substrate 11 includes a first surface and a second surface arranged opposite to each other, and a side surface connecting the first surface and the second surface. In the direction away from the side surface, the first interface passivation layer 20, the first doped silicon layer 12, the surface passivation layer 13, the anti-reflection layer 14, the intrinsic silicon layer 15, the second doped silicon layer 16 and the transparent conductive layer 17 are sequentially arranged on the side surface. The first doped silicon layer 12 and the second doped silicon layer 16 have opposite conductivity types. Among them, along the thickness direction of the silicon substrate 11, the surface passivation layer 13 and the anti-reflection layer 14 are also sequentially arranged on the second surface, and the surface passivation layer 13 and the anti-reflection layer 14 extend from the second surface to the side surface.

[0095] When the above technical solution is adopted, Figure 1As shown, on the side of the silicon substrate 11, and in the direction away from the side, a first interface passivation layer 20, a first doped silicon layer 12, a surface passivation layer 13, an anti-reflection layer 14, an intrinsic silicon layer 15, a second doped silicon layer 16 and a transparent conductive layer 17 are sequentially arranged. The presence of the above-mentioned film layers can isolate the side of the silicon substrate 11 from the external environment, and reduce the risk of damage such as scratches on the side of the silicon substrate 11 due to factors such as extrusion and collision after transportation or packaging. At the same time, it can also reduce the risk of water vapor entering the battery from the side of the battery to cause battery failure, and improve the service life of the back contact battery. In addition, the above-mentioned surface passivation layer 13 and anti-reflection layer 14 are not only located on the second surface of the silicon substrate 11, but also extend to the side of the silicon substrate 11. At this time, on the side of the silicon substrate 11, the first doped silicon layer 12 and the second doped silicon layer 16 of opposite conductivity types can be isolated by the surface passivation layer 13 and the anti-reflection layer 14 to prevent the two from conducting and leaking, reduce the forward leakage loss, and make the back contact battery have a higher conversion efficiency. In addition, the surface passivation layer 13 and the anti-reflection layer 14 are arranged on the part of the second surface to reduce carrier recombination and surface reflectivity. The two are then extended to the side of the silicon substrate 11, and can also be used to isolate the first doped silicon layer 12 and the second doped silicon layer 16. There is no need to form other insulating layers through other deposition steps to prevent leakage between the first doped silicon layer 12 and the second doped silicon layer 16. The manufacturing process of the back contact battery can be simplified. At the same time, there is no need to consider the compatibility between the film layer that isolates the first doped silicon layer 12 and the second doped silicon layer 16 and other structures in the back contact battery, ensuring that the back contact battery has a high yield. At the same time, not only the first interface passivation layer 20 and the first doped silicon layer 12 arranged on the side of the silicon substrate 11 have a passivation effect on the silicon substrate 11, but the surface passivation layer 13 that realizes the insulation isolation of the first doped silicon layer 12 and the second doped silicon layer 16 on the side can also passivate the side of the silicon substrate 11, further reducing the carrier recombination rate on the side of the silicon substrate 11 and improving the conversion efficiency of the back contact battery.

[0096] In addition, it is worth noting that in the actual manufacturing process, the order in which the corresponding film layers are formed on the first and second surfaces of the silicon substrate affects the order in which the corresponding film layers are formed on the side surfaces of the silicon substrate. Since the order in which the film layers are formed on the first and second surfaces of the silicon substrate is closely related to the process, battery structure, equipment, etc., the order in which the film layers are formed on the first and second surfaces of the silicon substrate cannot be adjusted arbitrarily, that is, the order in which the film layers are formed on the side surfaces of the silicon substrate cannot be adjusted arbitrarily, and needs to be comprehensively considered based on the requirements for the order in which the film layers are formed on the side surfaces of the silicon substrate, the technical problems to be solved, as well as the requirements for the order in which the film layers are formed on the front and back surfaces, the technical problems to be solved, etc.

[0097] In actual application, the embodiment of the present invention does not specifically limit the conductivity type of the silicon substrate. The conductivity type of the silicon substrate can be N-type, P-type, or intrinsic type.

[0098] In addition, the first surface of the silicon substrate corresponds to the backlight side of the back contact cell, and the second surface of the silicon substrate corresponds to the light-facing side of the silicon substrate. Figure 1 As shown, the back contact cell includes a first interface passivation layer 20, a first doped silicon layer 12, an intrinsic silicon layer 15, a second doped silicon layer 16 and a transparent conductive layer 17 which are not only arranged on the side of the silicon substrate 11, but also arranged on the first surface of the silicon substrate 11. Specifically, on the side of the first surface of the silicon substrate 11, the transparent conductive layer 17 covers the side of the first doped silicon layer 12 and the second doped silicon layer 16 away from the silicon substrate 11, and a penetrating isolation groove is arranged in the transparent conductive layer 17 to disconnect the part of the transparent conductive layer 17 corresponding to the first doped silicon layer 12 from the part of the transparent conductive layer 17 corresponding to the second doped silicon layer 16 to prevent short circuit. As for the distribution of the above-mentioned first interface passivation layer 20, the first doped silicon layer 12, the intrinsic silicon layer 15 and the second doped silicon layer 16 on the side of the first surface of the silicon substrate 11, it can be set according to actual needs and is not specifically limited here.

[0099] For example, the first surface may include a first region and a second region that do not overlap each other, the first interface passivation layer and the first doped silicon layer are arranged on the first region, and the intrinsic silicon layer and the second doped silicon layer are sequentially stacked on the second region in a direction away from the silicon substrate. In this case, the distribution range of the first region and the second region on the first surface can be determined according to the distribution of the first doped silicon layer and the second doped silicon layer on the first surface in an actual application scenario.

[0100] Exemplarily, the first surface may include a first region and a second region that are spaced apart, and a third region between the first region and the second region. The first interface passivation layer and the first doped silicon layer are disposed on the first region, and the intrinsic silicon layer and the second doped silicon layer are sequentially stacked on the second region in a direction away from the silicon substrate. In this case, the distribution range of the first region and the second region on the first surface can be determined according to the distribution of the first doped silicon layer and the second doped silicon layer on the first surface in an actual application scenario. The third region is an area of ​​the first surface where the first doped silicon layer and the second doped silicon layer are not disposed.

[0101] For example, Figure 1As shown, the first surface includes a first area 18 and a second area 19 that are spaced apart. The first interface passivation layer 20 and the first doped silicon layer 12 are disposed on the first area 18. The intrinsic silicon layer 15 and the second doped silicon layer 16 are disposed in the second area 19, and extend from the second area 19 to the first area 18, and cover a portion of the first interface passivation layer 20 and the first doped silicon layer 12. In this case, on the first surface of the silicon substrate 11, the intrinsic silicon layer 15 and the second doped silicon layer 16 are not only stacked in sequence in the second area 19 along the thickness direction of the silicon substrate 11, but also cover a portion of the first interface passivation layer 20 and the first doped silicon layer 12. At this time, the formation range of the intrinsic silicon layer 15 and the second doped silicon layer 16 on one side of the first surface of the silicon substrate 11 is relatively large, which is conducive to reducing the etching range of the entire layer of the intrinsic silicon layer 15 and the second doped silicon layer 16 during the manufacturing process, and is conducive to improving the etching capacity. Moreover, the portion where the intrinsic silicon layer 15 and the second doped silicon layer 16 cover the first doped silicon layer 12 can protect the edge of the first doped silicon layer 12, prevent the etchant from affecting the edge of the first doped silicon layer 12, and ensure that the edge of the first doped silicon layer 12 has a higher carrier collection efficiency. In addition, no isolation groove is provided between the first interface passivation layer 20, the first doped silicon layer, the second interface passivation layer, and the second doped silicon layer, so the contact area between the first interface passivation layer, the first doped silicon layer 12 and the silicon substrate 11, and the contact area between the intrinsic silicon layer 15, the second doped silicon layer 16 and the silicon substrate 11 can be maximized, thereby improving the utilization rate of the silicon substrate 11, and further improving the photoelectric conversion efficiency. Specifically, in this case, the distribution range of the first region 18 on the first surface can be determined according to the distribution of the first doped silicon layer 12 on the first surface in the actual application scenario. The distribution range of the second region 19 on the first surface can be determined according to the distribution of the portion of the second doped silicon layer 16 that does not overlap the first doped silicon layer 12 in the actual application scenario.

[0102] As for the surface morphology of the silicon substrate, the second surface of the silicon substrate can be a polished surface or a velvet surface. Among them, when the second surface of the silicon substrate is a velvet surface, it can improve its own light trapping effect and further improve the conversion efficiency of the back contact battery. Secondly, the first surface of the silicon substrate can be a polished surface; or, in the first surface of the silicon substrate, the surface of the area corresponding to the first interface passivation layer and the first doped silicon layer can be a polished surface, and the surface in contact with the intrinsic silicon layer and the second doped silicon layer can be a velvet surface. At this time, after at least removing the first interface passivation layer and the first doped silicon layer covering the area corresponding to the intrinsic silicon layer and the second doped silicon layer in the first surface, the second surface is subjected to a velvet treatment, and the surface of the area corresponding to the intrinsic silicon layer and the second doped silicon layer in the first surface is also subjected to a velvet treatment, so as to increase the contact area between the second doped silicon layer and the transparent conductive layer and reduce the contact loss between the two.

[0103] In addition, the side morphology of the silicon substrate can be determined according to the formation range of the first interface passivation layer and the first doped silicon layer on the side of the silicon substrate and the actual manufacturing process, and is not specifically limited here. Figure 1 As shown, the first interface passivation layer 20 and the first doped silicon layer 12 disposed on the side cover the entire area of ​​the side. Figure 2 As shown, the first interface passivation layer 20 and the first doped silicon layer 12 disposed on the side may be located on a local area of ​​the side and close to the first surface; in this case, it can be understood that in the actual manufacturing process, when the first doped silicon layer 12 is formed on the first surface and the side of the silicon substrate 11, the first doped silicon layer 12 may be plated on the second surface. The first doped silicon layer 12 located on the second surface has parasitic absorption and needs to be removed to improve the utilization rate of light by the silicon substrate. Based on this, when the first interface passivation layer 20 and the first doped silicon layer 12 disposed on the side are located on a local area of ​​the side, there is no need to strictly control the manufacturing conditions in order to retain all the first doped silicon layer 12 formed on the side in the process of removing the first interface passivation layer 20 and the first doped silicon layer 12 plated on the second surface, thereby reducing the manufacturing difficulty of the back contact battery.

[0104] Among them, Figure 1 As shown, when the first interface passivation layer 20 and the first doped silicon layer 12 disposed on the side cover the entire area of ​​the side, the surface reflectivity and / or surface morphology of each partial area of ​​the side of the silicon substrate 11 can be substantially the same. At this time, the surface of each area of ​​the side of the silicon substrate 11 can be a polished surface, or can be a suede surface or the like.

[0105] For example, Figure 3 As shown, when the first interface passivation layer 20 and the first doped silicon layer 12 disposed on the side are located on a local area of ​​the side and close to the first surface, the surface reflectivity of the area on the side not covered with the first doped silicon layer 12 can be less than the surface reflectivity of the area on the side covered with the first interface passivation layer 20 and the first doped silicon layer 12. At this time, although the passivation effect of the surface of the area on the side of the silicon substrate 11 not covered with the first interface passivation layer 20 and the first doped silicon layer 12 is relatively low, the surface of this area has a relatively high light trapping effect, which is conducive to refracting more light from the side of the side of the silicon substrate 11 close to the second surface into the silicon substrate 11, which is conducive to improving the conversion efficiency of the back contact battery.

[0106] Among them, when the surface reflectivity of the area on the side not covered by the first interface passivation layer and the first doped silicon layer is less than the surface reflectivity of the area on the side covered with the first interface passivation layer and the first doped silicon layer, the surface morphology of the area on the side not covered by the first interface passivation layer and the first doped silicon layer can be the same as the surface morphology of the area on the side covered with the first interface passivation layer and the first doped silicon layer, while the size of the texture structure on the surface of the area on the side not covered by the first interface passivation layer and the first doped silicon layer is different from the size of the texture structure on the surface of the area on the side covered with the first interface passivation layer and the first doped silicon layer.

[0107] For example: the surface of the area on the side that is not covered by the first interface passivation layer and the first doped silicon layer and the surface of the area on the side that is covered by the first interface passivation layer and the first doped silicon layer can both have a tower-like texture structure, and the side length of the tower-like texture structure on the surface of the area on the side that is not covered by the first interface passivation layer and the first doped silicon layer is smaller than the side length of the tower-like texture structure on the surface of the area on the side that is covered by the first interface passivation layer and the first doped silicon layer, and / or the height of the tower-like texture structure on the surface of the area on the side that is not covered by the first interface passivation layer and the first doped silicon layer is greater than the height of the tower-like texture structure on the surface of the area on the side that is covered by the first interface passivation layer and the first doped silicon layer.

[0108] For another example: the surface of the area on the side not covered by the first interface passivation layer and the first doped silicon layer and the surface of the area on the side covered by the first interface passivation layer and the first doped silicon layer may both have a pyramid-shaped texture structure, and the side length (or diagonal, height) of the bottom of the pyramid-shaped texture structure on the surface of the area on the side not covered by the first interface passivation layer and the first doped silicon layer is greater than the side length (or diagonal, height) of the pyramid-shaped texture structure on the surface of the area on the side covered by the first interface passivation layer and the first doped silicon layer.

[0109] Alternatively, when the surface reflectivity of the area on the side surface not covered with the first interface passivation layer and the first doped silicon layer is less than the surface reflectivity of the area on the side surface covered with the first interface passivation layer and the first doped silicon layer, the surface morphology of the area on the side surface not covered with the first interface passivation layer and the first doped silicon layer may also be different from the surface morphology of the area on the side surface covered with the first interface passivation layer and the first doped silicon layer. In this case, the surface morphologies of the two areas on the side surface may be determined based on the reflectivity relationship and the actual manufacturing process, and are not specifically limited here.

[0110] For example, Figure 3As shown, the surface of the area on the side that is not covered by the first interface passivation layer 20 and the first doped silicon layer 12 can be a velvet surface. In this case, the surface of the area on the side that is not covered by the first interface passivation layer 20 and the first doped silicon layer 12 has a relatively high light trapping effect, which is conducive to refracting more light from the side of the side of the silicon substrate 11 close to the second surface into the silicon substrate 11, which is conducive to improving the conversion efficiency of the back contact cell.

[0111] For example, Figure 3 As shown, the surface of the area covered with the first interface passivation layer 20 and the first doped silicon layer 12 in the side surface is a polished surface. In this case, the surface of the area covered with the first interface passivation layer 20 and the first doped silicon layer 12 in the side surface is relatively flat, which is conducive to forming a thicker first interface passivation layer 20 and the first doped silicon layer 12 in the area, enhancing the passivation effect of the first interface passivation layer 20 and the first doped silicon layer 12 on the corresponding area of ​​the side surface, and further improving the conversion efficiency of the back contact battery.

[0112] For the above-mentioned first doped silicon layer, from the aspect of the arrangement of the material, the crystal phase of the first doped silicon layer can be amorphous, microcrystalline, nanocrystalline, single crystal or polycrystalline, etc. The specific crystal phase of the first doped silicon layer can be determined according to the type of the first interface passivation layer. Among them, the first interface passivation layer can be a tunneling passivation layer such as a tunneling oxide layer. In this case, the first doped silicon layer is a doped crystalline silicon layer, and the material of the doped crystalline silicon layer may include polycrystalline silicon and / or single crystal silicon. Alternatively, the first interface passivation layer may also be an intrinsic silicon passivation layer such as intrinsic amorphous silicon. In this case, the materials of the first interface passivation layer and the first doped silicon layer may include at least one of amorphous silicon, nanocrystalline silicon and microcrystalline silicon.

[0113] It is worth noting that when the first interface passivation layer is a tunneling passivation layer and the first doped silicon layer is a doped crystalline silicon layer, the first interface passivation layer has a higher film density, which further enhances its passivation effect on the silicon substrate, thereby further reducing the surface defects of the silicon substrate and improving the conversion efficiency of the back contact battery.

[0114] In terms of thickness, Figure 1 As shown, the thickness of each part of the first doped silicon layer 12 can be the same; Figure 2 As shown, or the thickness of the first doped silicon layer 12 disposed on one side of the first surface may be greater than the thickness of the first doped silicon layer 12 disposed on the side surface. When the thickness of each part of the first doped silicon layer 12 is the same, it is beneficial for each part of the first doped silicon layer 12 to have a higher passivation effect, so that each region corresponding to the first doped silicon layer 12 in the silicon substrate 11 has a relatively low carrier recombination rate, further improving the conversion efficiency of the back contact battery.

[0115] As for the specific thickness of the first doped silicon layer, it can be determined according to actual needs and the material of the first doped silicon layer, and no specific limitation is made here. For example, the thickness of the first doped silicon layer can be greater than or equal to 30nm and less than or equal to 140nm. For example: the thickness of the first doped silicon layer can be 30nm, 40nm, 50nm, 60nm, 80nm, 100nm, 120nm, 130nm or 140nm, etc. In this way, the presence of the transparent conductive layer can improve the collection efficiency of carriers and leave a margin for thinning the first doped silicon layer. In other words, without reducing the carrier collection efficiency, the thickness of the first doped silicon layer can be appropriately reduced due to the presence of the transparent conductive layer. Based on this, when the thickness of the first doped silicon layer is within the above range, the thickness of the first doped silicon layer is small, which is conducive to reducing its own parasitic absorption and further improving the working efficiency of the back contact battery; and the deposition time of the first doped silicon layer can also be reduced to improve the production efficiency of the first doped silicon layer. In addition, the thickness of the first doped silicon layer cannot be too small to avoid affecting the collection of carriers.

[0116] For the first interface passivation layer, Figure 1 As shown, the thickness of each part of the first interface passivation layer 20 can be the same; or, the thickness of the first interface passivation layer disposed on one side of the first surface can be greater than the thickness of the first interface passivation layer disposed on the side surface. When the thickness of each part of the first interface passivation layer is the same, it is beneficial for each part of the first interface passivation layer 20 to have a higher passivation effect, so that each area corresponding to the first interface passivation layer 20 in the silicon substrate 11 has a relatively low carrier recombination rate, further improving the conversion efficiency of the back contact battery.

[0117] As for the specific thickness of the first interface passivation layer, it can be determined according to actual needs and the material of the first interface passivation layer, and is not specifically limited here.

[0118] In addition, in the side of the silicon substrate, when the surface of the region where the first interface passivation layer and the first doped silicon layer are provided has a tower-like texture structure, the thickness of the first interface passivation layer located at the bottom surface of the tower-like texture structure can be equal to the thickness of the first interface passivation layer located on the side wall of the tower-like texture structure. In this case, the first interface passivation layer has a high passivation effect on both the bottom surface and the side wall of the tower-like texture structure.

[0119] Alternatively, the thickness of the first interface passivation layer located on the bottom surface of the tower-shaped texture structure may also be less than the thickness of the first interface passivation layer located on the side wall of the tower-shaped texture structure. In this case, it can be understood that the bottom surface of the tower-shaped texture structure and the side surface of the tower-shaped texture structure have different crystal orientations. Specifically, the bottom surface of the tower-shaped texture structure is the

[110] crystal orientation, and the number of dangling bonds on the surface of the

[110] crystal orientation is relatively small; while the side surface of the tower-shaped texture structure is the

[111] crystal orientation, and the number of dangling bonds in the

[111] crystal orientation is relatively large. Based on this, when the thickness of the first interface passivation layer located on the bottom surface of the tower-shaped texture structure is less than the thickness of the first interface passivation layer located on the side wall of the tower-shaped texture structure, it is beneficial to make the thickness of the first interface passivation layer located on the side wall of the tower-shaped texture structure have a relatively high passivation effect, meet the demand for high passivation effect on the side surface of the tower-shaped texture structure, reduce the carrier recombination rate on the side surface of the tower-shaped texture structure, and further improve the working efficiency of the back contact battery.

[0120] The thickness of the first interface passivation layer at the bottom surface of the tower-shaped texture structure and the thickness of the first interface passivation layer on the side wall of the tower-shaped texture structure can be determined according to the requirements for the passivation effect of different areas of the tower-shaped texture structure and the actual manufacturing process, and are not specifically limited here.

[0121] Exemplarily, the thickness of the first interface passivation layer located at the bottom surface of the tower-shaped texture structure can be greater than or equal to 0.5nm and less than or equal to 1.5nm. For example: the thickness of the first interface passivation layer located at the bottom surface of the tower-shaped texture structure can be 0.5nm, 0.6nm, 0.8nm, 1nm, 1.2nm, 1.3nm or 1.5nm, etc. In this case, the thickness of the first interface passivation layer located at the bottom surface of the tower-shaped texture structure is within the above range, which is beneficial to prevent the first interface passivation layer from being located at the bottom surface of the tower-shaped texture structure. The thickness is small and the passivation effect of the part on the silicon substrate is relatively low, while reducing the carrier recombination rate on the side of the tower-shaped texture structure.

[0122] Exemplarily, the thickness of the first interface passivation layer located on the side wall of the tower-shaped texture structure can be greater than or equal to 0.5nm and less than or equal to 2nm. For example, the thickness of the first interface passivation layer located on the side wall of the tower-shaped texture structure can be 0.5nm, 0.8nm, 1nm, 1.2nm, 1.5nm, 1.8nm or 2nm, etc. In this case, the thickness of the first interface passivation layer located on the side wall of the tower-shaped texture structure is within the above range, which is conducive to preventing the passivation effect of the part from being low due to the small thickness, and reducing the carrier recombination rate on the side of the tower-shaped texture structure.

[0123] As for the formation range of the first interface passivation layer and the first doped silicon layer on the side of the silicon substrate, as mentioned above, the first interface passivation layer and the first doped silicon layer disposed on the side may cover the entire area of ​​the side. Alternatively, the first interface passivation layer and the first doped silicon layer disposed on the side may also be located only on a local area of ​​the side and close to the first surface; in this case, the extension range of the first interface passivation layer and the first doped silicon layer on the side may be set according to the actual manufacturing process and actual needs, and is not specifically limited here.

[0124] For example, Figure 3 As shown, along the thickness direction of the silicon substrate 11, the ratio between the maximum extension length of the first interface passivation layer 20 and the first doped silicon layer 12 on the side and the thickness of the silicon substrate 11 can be greater than or equal to 70%. For example, the ratio between the maximum extension length of the first interface passivation layer 20 and the first doped silicon layer 12 on the side and the thickness of the silicon substrate 11 can be 70%, 75%, 80%, 85%, 90%, 95% or 98%, etc. In this case, as mentioned above, the first interface passivation layer 20 and the first doped silicon layer 12 have a passivation effect on the side of the silicon substrate 11. Therefore, when the ratio between the maximum extension length of the first interface passivation layer 20 and the first doped silicon layer 12 on the side and the thickness of the silicon substrate 11 is greater than or equal to 70%, it is ensured that the first interface passivation layer 20 and the first doped silicon layer 12 have a larger formation range on the side of the silicon substrate 11, so that more areas of the surface in the side have a lower carrier recombination rate, further improving the conversion efficiency of the back contact battery. Moreover, most of the side surface of the silicon substrate 11 is covered with the first interface passivation layer 20 and the first doped silicon layer 12. At this time, the first interface passivation layer 20 and the first doped silicon layer 12 have a protective effect on most of the side surface of the silicon substrate 11 to prevent the intrusion of water vapor and the like, thereby ensuring that the side surface of the silicon substrate 11 has a thicker laminated protection, thereby further improving the protection effect of the side surface of the silicon substrate 11.

[0125] Exemplarily, in the case where the first interface passivation layer and the first doped silicon layer disposed on the side are only located on a local area of ​​the side and close to the first surface, the surface of the area of ​​the side not covered by the first interface passivation layer and the first doped silicon layer is velvet, and the ratio between the maximum extension length of the velvet on the side and the thickness of the silicon substrate can be less than or equal to 30%. For example: the ratio between the maximum extension length of the above-mentioned velvet on the side and the thickness of the silicon substrate can be 1%, 5%, 10%, 15%, 20%, 25% or 30%, etc. The application principle of the beneficial effect in this case can refer to the application principle of the beneficial effect of the ratio between the maximum extension length of the first interface passivation layer and the first doped silicon layer on the side and the thickness of the silicon substrate being greater than or equal to 70% as described above, which will not be repeated here.

[0126] For the above-mentioned surface passivation layer and anti-reflection layer, the embodiment of the present invention does not specifically limit the materials of the surface passivation layer and the anti-reflection layer, as long as they can be applied to the back contact battery provided by the embodiment of the present invention.

[0127] Exemplarily, the material of the surface passivation layer may include at least one of aluminum oxide, intrinsic amorphous silicon, and doped silicon glass. Among them, the conductivity type of the doped silicon glass is the same as or opposite to the conductivity type of the first doped silicon layer. Specifically, the material of the surface passivation layer may include only aluminum oxide, intrinsic amorphous silicon, or doped silicon glass. Alternatively, the material of the surface passivation layer may include any two of aluminum oxide, intrinsic amorphous silicon, and doped silicon glass. Alternatively, the material of the surface passivation layer may also include aluminum oxide, intrinsic amorphous silicon, and doped silicon glass at the same time. Specifically, when the material of the surface passivation layer includes at least two types, the distribution between different materials can be determined according to actual needs and the actual manufacturing process, and is not specifically limited here. In this case, aluminum oxide and intrinsic amorphous silicon contain hydrogen. When the material of the surface passivation layer includes aluminum oxide and / or intrinsic amorphous silicon, the silicon substrate and the first doped silicon layer can be hydrogen passivated to further improve the passivation effect of the surface passivation layer. The doped silicon glass is doped with impurities of the corresponding conductive type, which can also perform field passivation on the silicon substrate and the first doped silicon layer, and can further improve the passivation effect of the surface passivation layer. Secondly, the manufacturing process of the surface passivation layer made of doped silicon glass is also relatively simple, which helps to reduce the difficulty of manufacturing back contact batteries.

[0128] By way of example, the material of the anti-reflection layer may include silicon nitride and / or silicon oxynitride, etc.

[0129] As for the formation range of the surface passivation layer and the anti-reflection layer on the side of the silicon substrate, Figures 1 to 3 As shown, along the thickness direction of the silicon substrate 11, the surface passivation layer 13 and the anti-reflection layer 14 can cover various areas on the side of the silicon substrate 11, that is, cover the entire side. Figure 4As shown, the surface passivation layer 13 and the anti-reflection layer 14 arranged on the side surface may also be located on a local area of ​​the side surface and close to the second surface. In this case, it can be understood that in the actual manufacturing process, when the surface passivation layer 13 and the anti-reflection layer 14 are formed on the second surface and the side surface of the silicon substrate 11, in order to ensure that a surface passivation layer 13 and an anti-reflection layer 14 with a larger coverage area are formed on the side surface, the surface passivation layer 13 and the anti-reflection layer 14 may be plated around the first side surface. The surface passivation layer 13 and the anti-reflection layer 14 on the first surface will affect the carrier collection effect of the intrinsic silicon layer 15 and the second doped silicon layer 16 formed later, so it is necessary to remove the surface passivation layer 13 and the anti-reflection layer 14 on the first surface. Based on this, when the surface passivation layer 13 and the anti-reflection layer 14 arranged on the side surface are located on a local area of ​​the side surface, it is not necessary to strictly control the manufacturing conditions in order to retain all the surface passivation layer 13 and the anti-reflection layer 14 on the side surface in the process of removing the surface passivation layer 13 and the anti-reflection layer 14 plated around the first surface, thereby reducing the manufacturing difficulty of the back contact battery.

[0130] Specifically, it can be understood that the greater the extension length of the surface passivation layer and the anti-reflection layer on the side, the first doped silicon layer and the second doped silicon layer in the side of the silicon substrate can be separated by forming a larger surface passivation layer and anti-reflection layer, and the forward leakage of the back contact battery is lower. At the same time, the surface passivation layer and the anti-reflection layer have the largest protection range for the side of the silicon substrate. The smaller the extension length of the surface passivation layer and the anti-reflection layer on the side, the larger the range of the reverse leakage area formed between the first doped silicon layer and the second doped silicon layer in the side of the silicon substrate, and the lower the hot spot risk of the back contact battery. Based on this, the extension range of the surface passivation layer and the anti-reflection layer on the side can be determined according to the forward leakage loss, side protection, hot spot risk of the back contact battery in the actual application scenario, and the actual manufacturing process, and is not specifically limited here.

[0131] Exemplarily, along the thickness direction of the silicon substrate, the ratio between the maximum extension length of the surface passivation layer and the anti-reflection layer on the side and the thickness of the silicon substrate can be less than or equal to 80%. For example, the ratio between the maximum extension length of the surface passivation layer and the anti-reflection layer on the side and the thickness of the silicon substrate can be 5%, 10%, 15%, 20%, 30%, 40%, 50%, 60%, 70% or 80%, etc. In this case, the difficulty of removing the surface passivation layer and the anti-reflection layer around the first surface can be reduced, and the manufacturing precision requirements can be reduced. In addition, in the area of ​​the side of the silicon substrate that is not covered with the surface passivation layer and the anti-reflection layer, the first doped silicon layer can be electrically contacted with the second doped silicon layer of the opposite conductivity type to itself through the intrinsic silicon layer, thereby forming a diode structure with a lower reverse breakdown voltage on the side of the silicon substrate, which is conducive to reducing the risk of hot spots of the back contact battery and improving the anti-burning ability of the back contact battery. In addition, according to the actual application scenario requirements of the back-contact battery, the forward leakage, hot spot risk and side protection of the back-contact battery can be regulated by adjusting the maximum extension length of the surface passivation layer and the anti-reflection layer on the side, which is conducive to achieving a balance between the forward leakage, hot spot risk and side protection of the back-contact battery.

[0132] As for the thickness of the surface passivation layer and the anti-reflection layer, the thickness of the surface passivation layer and / or the anti-reflection layer on the second side of the silicon substrate can be roughly the same, so that each area on the second side of the silicon substrate corresponds to a higher passivation effect, and it is beneficial for each area on the second side of the back contact battery to have a relatively low reflectivity, thereby further improving the conversion efficiency of the back contact battery.

[0133] As for the thickness of the surface passivation layer and the anti-reflection layer on the side of the silicon substrate, the thickness of the surface passivation layer and / or the anti-reflection layer on each part of the side of the silicon substrate can be the same. In this case, within a certain range, the thickness of the surface passivation layer is proportional to its own passivation effect and insulation isolation effect. Based on this, when the thickness of the surface passivation layer is equal on the side of the silicon substrate, each part of the surface passivation layer has a higher passivation effect and a higher insulation isolation characteristic, which is conducive to making each area covered with the surface passivation layer on the side of the silicon substrate have a lower number of surface defects, and is also conducive to better realizing the electrical isolation effect of the first doped silicon layer and the second doped silicon layer through the surface passivation layer with uniform thickness, reducing forward leakage. Secondly, when the thickness of the anti-reflection layer on each part of the side of the silicon substrate is the same, it is conducive to making each part of the anti-reflection layer in the side have a higher insulation characteristic and protective effect, which is conducive to better realizing the electrical isolation effect of the first doped silicon layer and the second doped silicon layer through the anti-reflection layer with uniform thickness, reducing forward leakage, and improving the structural reliability of the side of the back contact battery.

[0134] Or, if Figure 4As shown, on the side of the silicon substrate 11, the thickness of the surface passivation layer 13 and / or the anti-reflection layer 14 can be gradually increased in the direction from the first surface to the second surface. In this case, it can be understood that when the thickness of the surface passivation layer 13 gradually increases in the direction from the first surface to the second surface, the portion of the surface passivation layer 13 on the side close to the second surface has a higher passivation effect and better insulation isolation characteristics, further reducing the number of surface defects in the area close to the second surface of the side of the silicon substrate 11, while further reducing the leakage risk between the first doped silicon layer 12 and the second doped silicon layer 16, which is conducive to increasing the open circuit voltage and fill factor of the back contact battery. When the thickness of the anti-reflection layer 14 gradually increases in the direction from the first surface to the second surface, the portion of the surface passivation layer 13 on the side close to the second surface has better insulation isolation characteristics, further reducing the leakage risk between the first doped silicon layer 12 and the second doped silicon layer 16, which is conducive to increasing the open circuit voltage and fill factor of the back contact battery.

[0135] Among them, on the side of the silicon substrate, the thickness of the surface passivation layer and / or the anti-reflection layer gradually increases from the first surface to the second surface, and the thickness of the surface passivation layer and / or the anti-reflection layer close to the first surface or the second surface can be set according to actual needs and are not specifically limited here.

[0136] For the intrinsic silicon layer and the second doped silicon layer, from the material aspect, the material of the intrinsic silicon layer and / or the second doped silicon layer may include at least one of amorphous silicon, microcrystalline silicon and nanocrystalline silicon. Secondly, the conductivity type of the second doped silicon layer and the first doped silicon layer can be determined according to the material of the first doped silicon layer and the actual application scenario, as long as the conductivity types of the first doped silicon layer and the second doped silicon layer are opposite. Specifically, the conductivity type of the first doped silicon layer can be N-type, in which case the conductivity type of the second doped silicon layer is P-type. Alternatively, the conductivity type of the first doped silicon layer can also be P-type, in which case the conductivity type of the second doped silicon layer is N-type.

[0137] Optionally, when the material of the first doped silicon layer includes polycrystalline silicon, the conductivity type of the first doped silicon layer may be N-type, and the conductivity type of the second doped silicon layer may be P-type. In this case, compared with P-type doped amorphous silicon, P-type doped microcrystalline silicon and P-type doped nanocrystalline silicon materials, the contact resistance between the P-type doped polycrystalline silicon material and the electrode is higher and the field passivation effect is poorer. Therefore, when the conductivity type of the first doped silicon layer is set to N-type and the conductivity type of the second doped silicon layer is set to P-type, the field passivation effect of the first doped silicon layer can be further improved, and at the same time, the contact resistance between the first doped silicon layer and the electrode can be reduced, which is beneficial to improving the electrical performance of the back contact battery.

[0138] As for the formation range of the intrinsic silicon layer and the second doped silicon layer on the side of the silicon substrate, Figures 1 to 3As shown, along the thickness direction of the silicon substrate 11, the intrinsic silicon layer 15 and the second doped silicon layer 16 can cover various regions of the side surface of the silicon substrate 11, that is, the entire side surface. Figure 5 As shown, the intrinsic silicon layer 15 and the second doped silicon layer 16 disposed on the side may also be located on a local area of ​​the side and close to the first surface. In this case, it can be understood that in the actual manufacturing process, when the intrinsic silicon layer 15 and the second doped silicon layer 16 are formed on the first surface and the side of the silicon substrate 11, in order to ensure that the intrinsic silicon layer 15 and the second doped silicon layer 16 with a larger coverage area are formed on the side, the intrinsic silicon layer 15 and the second doped silicon layer 16 may be plated around the second surface. However, the intrinsic silicon layer 15 and the second doped silicon layer 16 on the second surface have parasitic absorption, so it is necessary to remove the intrinsic silicon layer 15 and the second doped silicon layer 16 on the second surface. Based on this, when the intrinsic silicon layer 15 and the second doped silicon layer 16 disposed on the side are located on a local area of ​​the side, it is not necessary to strictly control the manufacturing conditions in order to retain all the intrinsic silicon layer 15 and the second doped silicon layer 16 on the side in the process of removing the intrinsic silicon layer 15 and the second doped silicon layer 16 plated around the second surface, thereby reducing the manufacturing difficulty of the back contact battery. Specifically, in this case, the extension range of the intrinsic silicon layer 15 and the second doped silicon layer 16 on the side can be determined based on the passivation and protection requirements for the side of the silicon substrate 11 in the actual application scenario, the anti-leakage requirements between the first doped silicon layer 12 and the second doped silicon layer 16 arranged on the side of the silicon substrate 11, and the actual manufacturing process, and no specific limitation is made here.

[0139] As for the thickness of the intrinsic silicon layer and the second doped silicon layer on the side of the silicon substrate, the thickness of the two on the side of the silicon substrate along the direction from the first surface to the second surface can be substantially the same. Figure 5 As shown, on the side of the silicon substrate 11, the thickness of the intrinsic silicon layer 15 and / or the second doped silicon layer 16 gradually increases from the second surface to the first surface. In this case, it is beneficial to improve the protective effect of the intrinsic silicon layer 15 and / or the second doped silicon layer 16 on the area near the first surface of the side of the silicon substrate 11, and the structural reliability of the side in the back contact battery can be further improved.

[0140] Exemplarily, the thickness of the intrinsic silicon layer may be greater than or equal to 8 nm and less than or equal to 14 nm. For example, the thickness of the intrinsic silicon layer may be 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm or 14 nm. In this case, the thickness of the intrinsic silicon layer is relatively large, which is conducive to enhancing the isolation effect of the intrinsic silicon layer on the first doped silicon layer and the second doped silicon layer, and reducing the risk of forward leakage.

[0141] In addition, in the side of the silicon substrate, when the surface of the region covered with the intrinsic silicon layer and / or the second doped silicon layer has a tower-shaped texture structure, the thickness of the intrinsic silicon layer and / or the second doped silicon layer located at the bottom of the tower-shaped texture structure can be equal to the thickness of the intrinsic silicon layer and / or the second doped silicon layer located at the side wall of the tower-shaped texture structure; or, the thickness of the intrinsic silicon layer and / or the second doped silicon layer located at the bottom of the tower-shaped texture structure can also be greater than the thickness of the intrinsic silicon layer and / or the second doped silicon layer located at the side wall of the tower-shaped texture structure. It can be understood that the portion of the intrinsic silicon layer and / or the second doped silicon layer located at the bottom of the tower-shaped texture structure accounts for a large proportion of the side, so when the thickness of the intrinsic silicon layer and / or the second doped silicon layer located at the bottom of the tower-shaped texture structure is large, the portion of the intrinsic silicon layer and / or the second doped silicon layer that accounts for a large proportion can have a higher passivation and protection effect, which can further reduce the number of defects on the side of the back contact battery and improve the protection of the side of the silicon substrate. Of course, the thickness of the intrinsic silicon layer and / or the second doped silicon layer located on the bottom surface of the tower-shaped texture structure can also be smaller than the thickness of the intrinsic silicon layer and / or the second doped silicon layer located on the side wall of the tower-shaped texture structure, so as to improve the applicability of the back-contact battery provided by the embodiment of the present invention in different application scenarios.

[0142] The above “thickness of the intrinsic silicon layer and / or the second doped silicon layer at the bottom surface of the tower-shaped texture structure” may refer to the thickness of the intrinsic silicon layer at the bottom surface of the tower-shaped texture structure, or the thickness of the second doped silicon layer at the bottom surface of the tower-shaped texture structure; of course, it may also refer to the sum of the thicknesses of the intrinsic silicon layer and the second doped silicon layer at the bottom surface of the tower-shaped texture structure. The above “thickness of the intrinsic silicon layer and / or the second doped silicon layer at the side wall of the tower-shaped texture structure” is the same as the above explanation and will not be repeated here.

[0143] In addition, when comparing the thickness at the bottom surface of the tower-shaped texture structure and the thickness at the side wall of the tower-shaped texture structure, the same film layer should be compared, for example, the intrinsic silicon layer, or the second doped silicon layer, or the sum of the thicknesses of the intrinsic silicon layer and the second doped silicon layer.

[0144] As a possible implementation scheme, in the case where the side of the above-mentioned silicon substrate has a tower-shaped texture structure, the thickness of the first interface passivation layer at the bottom surface of the tower-shaped texture structure can be less than the thickness of the first interface passivation layer at the side wall of the tower-shaped texture structure. In addition, the thickness of the intrinsic silicon layer at the bottom surface of the tower-shaped texture structure is greater than the thickness of the intrinsic silicon layer at the side wall of the tower-shaped texture structure; and / or, the thickness of the second doped silicon layer at the bottom surface of the tower-shaped texture structure is greater than the thickness of the second doped silicon layer at the side wall of the tower-shaped texture structure. "The thickness of the intrinsic silicon layer at the bottom surface of the tower-shaped texture structure is greater than the thickness of the intrinsic silicon layer at the side wall of the tower-shaped texture structure; and the thickness of the second doped silicon layer at the bottom surface of the tower-shaped texture structure is greater than the thickness of the second doped silicon layer at the side wall of the tower-shaped texture structure." refers to the sum of the thicknesses of the intrinsic silicon layer and the second doped silicon layer at the bottom surface of the tower-shaped texture structure, which is greater than the sum of the thicknesses of the intrinsic silicon layer and the second doped silicon layer at the side wall of the tower-shaped texture structure. Specifically, in the intrinsic silicon layer and the second doped silicon layer, only the thickness of the intrinsic silicon layer at the bottom of the tower-shaped texture structure may be greater than the thickness of the intrinsic silicon layer at the sidewall of the tower-shaped texture structure, and the thickness of the second doped silicon layer at the bottom of the tower-shaped texture structure is less than or equal to the thickness of the second doped silicon layer at the sidewall of the tower-shaped texture structure; or in the intrinsic silicon layer and the second doped silicon layer, the thickness of the intrinsic silicon layer at the bottom of the tower-shaped texture structure is less than or equal to the thickness of the intrinsic silicon layer at the sidewall of the tower-shaped texture structure, and the thickness of the second doped silicon layer at the bottom of the tower-shaped texture structure is greater than the thickness of the second doped silicon layer at the sidewall of the tower-shaped texture structure. It is also possible that in the intrinsic silicon layer and the second doped silicon layer, the thickness of the intrinsic silicon layer at the bottom of the tower-shaped texture structure is greater than the thickness of the intrinsic silicon layer at the sidewall of the tower-shaped texture structure, and the thickness of the second doped silicon layer at the bottom of the tower-shaped texture structure is also greater than the thickness of the second doped silicon layer at the sidewall of the tower-shaped texture structure.

[0145] When the above technical solution is adopted, the thickness relationship of the first interface passivation layer at the bottom surface and the side wall of the tower-shaped texture structure is opposite to the thickness relationship of the intrinsic silicon layer and / or the second doped silicon layer at the bottom surface and the side wall of the tower-shaped texture structure. At this time, the thickness of the first interface passivation layer at the side wall of the tower-shaped texture structure is relatively large, which can make up for the fact that the thickness of the intrinsic silicon layer and / or the second doped silicon layer at the side wall of the tower-shaped texture structure is relatively small, resulting in weaker passivation effect and protection effect of the first interface passivation layer; and, the thickness of the intrinsic silicon layer and / or the second doped silicon layer at the bottom surface of the tower-shaped texture structure is relatively large, which can make up for the fact that the thickness of the first interface passivation layer at the bottom surface of the tower-shaped texture structure is relatively small, resulting in weaker passivation effect and protection effect of the first interface passivation layer, thereby ensuring that under the common passivation effect and protection effect of the first interface passivation layer, and the intrinsic silicon layer and / or the second doped silicon layer, the bottom and side surfaces of the tower-shaped texture structure corresponding to the side surface of the silicon substrate have a higher passivation effect and protection strength.

[0146] For the above transparent conductive layer, Figure 1 As shown, along the thickness direction of the silicon substrate 11, the transparent conductive layer 17 can cover various areas on the side of the silicon substrate 11. Alternatively, as shown in FIG. Figure 5 As shown, the transparent conductive layer 17 disposed on the side may also be located on a local area of ​​the side and close to the first surface. In this case, it is not necessary to strictly control the manufacturing conditions in order to retain all the transparent conductive layer 17 on the side in the process of removing the transparent conductive layer 17 plated on the second surface, thereby reducing the difficulty of manufacturing the back contact battery. Specifically, in this case, the extension range of the transparent conductive layer 17 on the side can be determined based on the protection requirements for the side of the silicon substrate 11 in the actual application scenario, the anti-leakage requirements between the first doped silicon layer 12 and the second doped silicon layer 16 disposed on the side of the silicon substrate 11, and the actual manufacturing process, and is not specifically limited here.

[0147] As for the thickness of the transparent conductive layer on the side of the silicon substrate, the thickness of the transparent conductive layer on the side of the silicon substrate may be substantially the same along the direction from the first surface to the second surface. Figure 5 As shown, on the side of the silicon substrate 11, the thickness of the transparent conductive layer 17 gradually increases from the second surface to the first surface. In this case, it is beneficial to improve the protective effect of the transparent conductive layer 17 on the area near the first surface of the side of the silicon substrate 11, and the structural reliability of the side of the back contact battery can be further improved.

[0148] In addition, the material of the transparent conductive layer may include indium tin oxide, aluminum-doped zinc oxide, fluorine-doped tin oxide, antimony-doped tin oxide, or the like.

[0149] As a possible implementation, Figure 6 As shown, the above-mentioned back contact cell may also include an insulating mask layer 21. The insulating mask layer 21 is arranged between the first doped silicon layer 12 and the surface passivation layer 13 located on the side, and the insulating mask layer 21 is also arranged between the intrinsic silicon layer 15 and the first doped silicon layer 12 on the first surface along the thickness direction of the silicon substrate 11. In this case, the insulating mask layer 21 can separate the first doped silicon layer 12 and the second doped silicon layer 16 on the side together with the surface passivation layer 13 and the anti-reflection layer 14, further suppressing the side leakage. At the same time, the side of the silicon substrate 11 can also be passivated to further reduce the number of defects on the side of the silicon substrate 11. In addition, the insulating mask layer 21 is also formed on the side, which is also conducive to reducing the thickness requirement of the intrinsic silicon layer 15. While ensuring that there is a lower forward leakage between the first doped silicon layer 12 and the second doped silicon layer 16, the thickness of the intrinsic silicon layer 15 is smaller to have a lower tunneling resistance, which is conducive to improving the carrier collection efficiency of the second doped silicon layer 16 on one side of the first surface.

[0150] In terms of materials, the material of the insulating mask layer may include any insulating material with a mask protection function, and is not specifically limited here. For example, the insulating mask layer may include at least one of a doped silicon glass layer, an aluminum oxide layer, and a silicon nitride layer. The conductivity type of the doped silicon glass layer is opposite to the conductivity type of the first doped silicon layer.

[0151] In terms of side coverage, Figure 6 As shown, along the thickness direction of the silicon substrate 11, the insulating mask layer 21 can cover various areas on the side of the silicon substrate 11. Alternatively, as shown in FIG. Figure 7 As shown, the insulating mask layer 21 disposed on the side surface may also be located on a local area of ​​the side surface. The application principle of the beneficial effect in this case can refer to the application principle of the beneficial effect of the transparent conductive layer 17 being located on a local area of ​​the side surface and close to the first surface as described above, and will not be repeated here. Among them, when the insulating mask layer 21 disposed on the side surface is located on a local area of ​​the side surface, the insulating mask layer 21 located on the side surface may be close to one side of the first surface, may be close to one side of the second surface, or may be located in the middle area of ​​the side surface.

[0152] Specifically, when an insulating mask layer is formed on the first surface and the side surface of the silicon substrate, an insulating mask layer may also be plated on the second surface. In this case, when removing the insulating mask layer plated on the second surface, if the portion of the insulating mask layer located on the side and close to the second surface is also removed together, and when removing the surface passivation layer and the anti-reflection layer plated on the first surface, the etchant has no effect or little effect on the insulating mask layer, the insulating mask layer located on the side surface of the back contact battery is close to the first surface. Alternatively, when removing the insulating mask layer plated on the second surface, the insulating mask layer on the side surface is not affected; and when removing the surface passivation layer and the anti-reflection layer plated on the first surface, the etchant removes the portion of the insulating mask layer on the side surface close to the first surface together, the insulating mask layer located on the side surface of the back contact battery is close to the second surface. Alternatively, when removing the insulating mask layer that is plated around the second surface, the corresponding etchant removes the portion of the insulating mask layer located on the side and close to the second surface; and when removing the surface passivation layer and the anti-reflection layer that are plated around the first surface, the etchant removes the portion of the insulating mask layer on the side close to the first surface. In this case, the insulating mask layer on the side of the back contact battery may be located in the middle area of ​​the side.

[0153] In addition, in this case, the extension range of the insulating mask layer on the side can be determined based on the passivation and protection requirements for the side of the silicon substrate in the actual application scenario, the anti-leakage requirements between the first doped silicon layer and the second doped silicon layer arranged on the side of the silicon substrate, and the actual manufacturing process, and no specific limitation is made here.

[0154] Exemplarily, the ratio between the maximum extension length of the insulating mask layer on the side and the thickness of the silicon substrate can be less than or equal to 80%. For example, the ratio between the maximum extension length of the insulating mask layer on the side and the thickness of the silicon substrate can be 5%, 10%, 20%, 30%, 40%, 50%, 60%, 70% or 80%, etc. In this case, it can be understood that the greater the extension length of the insulating mask layer on the side, the first doped silicon layer and the second doped silicon layer in the side of the silicon substrate can be separated by forming a larger insulating mask layer, the lower the forward leakage of the back contact battery, and the stronger the protective effect of the insulating mask layer on the side of the silicon substrate. The smaller the extension length of the insulating mask layer on the side, the larger the range of the reverse leakage area formed between the first doped silicon layer and the second doped silicon layer in the side of the silicon substrate, and the lower the risk of hot spots of the back contact battery. Based on this, when the ratio of the maximum extension length of the insulating mask layer on the side to the thickness of the silicon substrate is less than or equal to 80%, the forward leakage, hot spot risk and side protection of the back contact battery can be regulated by adjusting the maximum extension length of the insulating mask layer on the side according to the actual application scenario requirements of the back contact battery, which is conducive to achieving a balance between the forward leakage, hot spot risk and side protection of the back contact battery.

[0155] As for the thickness of the insulating mask layer on the side of the silicon substrate, the thickness of the insulating mask layer on the side of the silicon substrate may be substantially the same along the direction from the first surface to the second surface. Figure 7 As shown, on the side of the silicon substrate 11, the thickness of the insulating mask layer 21 gradually increases from the second surface to the first surface. The application principle of the beneficial effect in this case is similar to the application principle of the beneficial effect of the thickness of the surface passivation layer 13 gradually increasing from the first surface to the second surface on the side of the silicon substrate 11 as described above, and will not be repeated here.

[0156] As a possible implementation scheme, a doping layer may also be formed in the side of the silicon substrate. The dopant in the doping layer includes the dopant in the first doped silicon layer. In this case, the doping layer is formed by controlling the manufacturing process, the concentration of the dopant in the first doped silicon layer, the thickness of the first doped silicon layer, and the thickness and compactness of the first interface passivation layer when forming the first doped silicon layer, so that part of the dopant in the first doped silicon layer passes through the first interface passivation layer and enters the side area of ​​the silicon substrate; or the doping layer and the first doped silicon layer may be formed separately. Based on this, the doping layer may form a high-low junction with the first doped silicon layer, so that the energy band between the first doped silicon layer and the side of the silicon substrate is more matched, the passivation effect of the first doped silicon layer on the side of the silicon substrate is improved, and the open circuit voltage of the back contact battery is increased. Specifically, the formation range of the doping layer, the doping concentration of the dopant in the doping layer, etc. can be determined according to the formation range of the first interface passivation layer and the first doped silicon layer on the side, the thickness and compactness of the first interface passivation layer, and the doping concentration of the first doped silicon layer, or according to actual needs, and no specific limitation is made here.

[0157] In a second aspect, an embodiment of the present invention provides another back contact battery. Figure 8 As shown, the back contact cell includes: a silicon substrate 11, a first interface passivation layer 20, a first doped silicon layer 12, an intrinsic silicon layer 15, a second doped silicon layer 16 and a transparent conductive layer 17. The silicon substrate 11 includes a first surface and a second surface arranged opposite to each other, and a side surface connecting the first surface and the second surface. In the direction away from the side surface, the first doped silicon layer 12, the intrinsic silicon layer 15, the second doped silicon layer 16 and the transparent conductive layer 17 are sequentially arranged on the side surface. On the side surface of the silicon substrate 11, the first doped silicon layer 12 and the intrinsic silicon layer 15 are in direct contact. Among them, the conductivity types of the first doped silicon layer 12 and the second doped silicon layer 16 are opposite.

[0158] When the above technical solution is adopted, Figure 8 As shown, on the side of the silicon substrate 11, the first doped silicon layer 12 can be electrically connected through the intrinsic silicon layer 15 and the second doped silicon layer 16 of the opposite conductivity type to itself, so as to form a diode structure with a lower reverse breakdown voltage on the side of the silicon substrate 11, reducing the risk of hot spots of the back contact battery. At the same time, the first doped silicon layer 12, the intrinsic silicon layer 15 and the second doped silicon layer 16 arranged on the side of the silicon substrate 11 can also passivate the side of the silicon substrate 11, reduce the carrier recombination rate on the side of the silicon substrate 11, and improve the conversion efficiency of the back contact battery. Secondly, the first doped silicon layer 12, the intrinsic silicon layer 15 and the second doped silicon layer 16 arranged on the side of the silicon substrate 11 can also protect the side of the silicon substrate 11, reduce the risk of damage and leakage due to the side of the silicon substrate 11 being directly exposed to the outside, and improve the structural reliability of the back contact battery.

[0159] In actual application, the first side of the silicon substrate corresponds to the backlight side of the back contact cell, and the second side of the silicon substrate corresponds to the light-facing side of the silicon substrate. Figure 8 As shown, the back contact cell includes a first interface passivation layer 20, a first doped silicon layer 12, an intrinsic silicon layer 15, a second doped silicon layer 16 and a transparent conductive layer 17 which are not only arranged on the side of the silicon substrate 11, but also arranged on the first surface of the silicon substrate 11. Specifically, on the first surface side of the silicon substrate 11, the transparent conductive layer 17 covers the first doped silicon layer 12 and the second doped silicon layer 16 on the side away from the silicon substrate 11, and a through isolation groove is arranged in the transparent conductive layer 17 to disconnect the part of the transparent conductive layer 17 corresponding to the first doped silicon layer 12 from the part of the transparent conductive layer 17 corresponding to the second doped silicon layer 16 to prevent short circuit. As for the distribution of the first interface passivation layer 20, the first doped silicon layer 12, the intrinsic silicon layer 15 and the second doped silicon layer 16 on the first surface side of the silicon substrate 11, reference can be made to the distribution of the first interface passivation layer 20, the first doped silicon layer 12, the intrinsic silicon layer 15 and the second doped silicon layer 16 on the first surface side of the silicon substrate 11 in the first aspect described above, and no specific limitation is made here.

[0160] It should be noted that the following is only used to illustrate the difference between the back contact cell provided in the second aspect of the embodiment of the present invention and the contact cell provided in the first aspect. The similarities between the back contact cell provided in the second aspect and the contact cell provided in the first aspect, such as the conductivity type of the silicon substrate, the formation range and thickness of the first doped silicon layer on the side, and the formation range and thickness of the intrinsic silicon layer and the second doped silicon layer on the side, can refer to the corresponding description in the first aspect, and will not be repeated here.

[0161] For the above intrinsic silicon layer, the intrinsic silicon layer can be a single-layer structure. At this time, each part of the intrinsic silicon layer can form a selective contact structure with the second doped silicon layer to achieve selective absorption of carriers and passivate the surface in contact with the silicon substrate.

[0162] Or, if Fig. 9As shown, the above-mentioned back contact battery includes a surface passivation layer 13 arranged on the second surface, and the surface passivation layer 13 extends from the second surface to the side. In addition, the back contact battery also includes a second interface passivation layer 22 arranged on the first surface and located between the silicon substrate 11 and the second doped silicon layer 16, and the second interface passivation layer 22 extends from the above-mentioned first surface to the side. Based on this, on the side, the above-mentioned intrinsic silicon layer 15 includes a surface passivation layer 13 and a second interface passivation layer 22 stacked in a direction away from the side. In this case, on the side of the silicon substrate 11, there are two film layers, the surface passivation layer 13 and the second interface passivation layer 22, between the first doped silicon layer 12 and the second doped silicon layer 16. At this time, the intrinsic silicon layer 15 has a certain transmission resistance, which is beneficial to reduce the forward leakage of the back contact battery and to balance the conversion efficiency and hot spot risk of the back contact battery. In addition, while obtaining lower forward leakage, there is no need to form a thicker intrinsic silicon layer 15, which results in a single second interface passivation layer 22 or a surface passivation layer 13 having a larger thickness. This ensures that the second interface passivation layer 22 has a lower tunneling resistance and that the surface passivation layer 13 has a lower barrier effect on light transmission, thereby ensuring that the back-contact battery has a higher conversion efficiency.

[0163] Among them, the formation order of the surface passivation layer and the second interface passivation layer included in the intrinsic silicon layer in the back contact battery provided by the embodiment of the present invention is not specifically limited. The surface passivation layer may be formed first, and then the second interface passivation layer is formed. In this case, the intrinsic silicon layer includes the surface passivation layer and the second interface passivation layer, which are sequentially arranged in a direction away from the side. Alternatively, the second interface passivation layer may be formed first, and then the surface passivation layer is formed. In this case, the intrinsic silicon layer includes the second interface passivation layer and the surface passivation layer, which are sequentially arranged in a direction away from the side.

[0164] As for the thickness of the intrinsic silicon layer on the side of the silicon substrate, Figure 8 and Fig. 9 As shown, the thickness of each part of the intrinsic silicon layer 15 is the same on the side of the silicon substrate 11. In this case, each part of the intrinsic silicon layer 15 disposed on the side of the silicon substrate 11 has a high passivation performance and protective effect, which can further reduce the carrier recombination rate on the side of the silicon substrate 11 and improve the structural reliability of the back contact battery.

[0165] Or, if Fig.10 As shown, on the side of the silicon substrate 11, the thickness of the intrinsic silicon layer 15 can also gradually increase from the second surface to the first surface. The application principle of the beneficial effect in this case can be referred to above and will not be repeated here.

[0166] The specific thickness of the intrinsic silicon layer disposed on the side of the silicon substrate can be determined according to the anti-leakage requirements of the first doped silicon layer and the second doped silicon layer disposed on the side of the silicon substrate in actual application scenarios, and is not specifically limited here.

[0167] Exemplarily, on the side of the silicon substrate, the thickness of the intrinsic silicon layer can be greater than or equal to 5nm and less than or equal to 30nm. In this case, on the side of the silicon substrate, the thickness of the intrinsic silicon layer is within the above range, which is conducive to preventing the poor passivation performance and protection of the intrinsic silicon layer due to its small thickness, ensuring that the side has a lower carrier recombination rate and higher structural reliability, and at the same time, it is also conducive to reducing the forward leakage loss of the back contact battery. It can also prevent the thickness of the second interface passivation layer (or the second interface passivation layer and the surface passivation layer) from being large due to the large thickness of the intrinsic silicon layer, ensuring that the second interface passivation layer has a lower tunneling resistance, and the surface passivation layer has a lower barrier effect on light transmission, ensuring that the back contact battery has a higher conversion efficiency.

[0168] As a possible implementation, Fig. 9 As shown, the above-mentioned back contact cell may also include an anti-reflection layer 14. On the second surface, the anti-reflection layer 14 is arranged on the side of the surface passivation layer 13 away from the silicon substrate 11. The anti-reflection layer 14 extends from the second surface to the side, and the anti-reflection layer 14 on the side is arranged between the second doped silicon layer 16 and the transparent conductive layer 17. In this case, an anti-reflection layer 14 is added to the film layer arranged on the side of the silicon substrate 11, which can further improve the protection of the side of the silicon substrate 11, reduce the risk of damage to the side of the silicon substrate 11, and reduce the forward leakage loss. In addition, in this case, the anti-reflection layer 14 is directly formed on the side of the second doped silicon layer 16 away from the silicon substrate 11. Compared with the anti-reflection layer 14 being directly formed on the surface passivation layer 13, when the anti-reflection layer 14 is directly formed on the side of the second doped silicon layer 16 away from the silicon substrate 11, the coating range of the anti-reflection layer 14 on one side of the first surface can be reduced, thereby reducing the etching amount when removing the anti-reflection layer 14 on the first surface, thereby improving the manufacturing efficiency.

[0169] As another possible implementation, Fig.10 As shown, the above-mentioned back contact cell further includes a surface passivation layer 13 and an anti-reflection layer 14 sequentially arranged on the second surface along the thickness direction of the silicon substrate, and the surface passivation layer 13 and the anti-reflection layer 14 extend from the second surface to the side surface. Moreover, on the side surface, and in the direction away from the side surface, the surface passivation layer 13 and the anti-reflection layer 14 are sequentially stacked and arranged between the second doped silicon layer 16 and the transparent conductive layer 17. In this case, the presence of the surface passivation layer 13 and the anti-reflection layer 14 can further enhance the protective effect on the side surface of the silicon substrate 11, and reduce the risk of damage to the side surface of the silicon substrate 11.

[0170] In a third aspect, an embodiment of the present invention provides another back contact battery. Fig.11As shown, the back contact cell includes: a silicon substrate, a first interface passivation layer 20, a first doped silicon layer 12, an insulating mask layer 21, an intrinsic silicon layer 15, a second doped silicon layer 16 and a transparent conductive layer 17. The silicon substrate includes a first surface and a second surface arranged opposite to each other, and a side surface connecting the first surface and the second surface. In the direction away from the side surface, the first interface passivation layer 20, the first doped silicon layer 12, the insulating mask layer 21, the intrinsic silicon layer 15, the second doped silicon layer 16 and the transparent conductive layer 17 are sequentially arranged on the side surface. The first doped silicon layer 12 and the second doped silicon layer 16 have opposite conductivity types. Among them, the back contact battery includes a surface passivation layer 13 arranged on the second surface, and the surface passivation layer 13 extends from the second surface to the side; the back contact battery also includes a second interface passivation layer 22 arranged on the first surface and located between the silicon substrate and the second doped silicon layer 16, and the second interface passivation layer 22 extends from the above-mentioned first surface to the side; on the side, the intrinsic silicon layer 15 includes a surface passivation layer 13 and a second interface passivation layer 22 stacked in a direction away from the side.

[0171] In the case of adopting the above technical solution, in addition to the intrinsic silicon layer, an insulating mask layer is also provided between the first doped silicon layer and the second doped silicon layer, which can reduce the thickness requirement of the intrinsic silicon layer while ensuring the reduction of forward leakage loss, reduce the tunneling resistance of the intrinsic silicon layer, and help improve the collection efficiency of the second doped silicon layer provided on the side of the first surface of the silicon substrate for carriers, and further improve the conversion efficiency of the back contact battery. In addition, the presence of the insulating mask layer can also enhance the protection of the side surface of the silicon substrate, and further improve the side structure reliability of the back contact battery.

[0172] In actual application, the first side of the silicon substrate corresponds to the backlight side of the back contact cell, and the second side of the silicon substrate corresponds to the light-facing side of the silicon substrate. Fig.11As shown, the back contact cell includes a first interface passivation layer 20, a first doped silicon layer 12, an insulating mask layer 21, an intrinsic silicon layer 15, a second doped silicon layer 16 and a transparent conductive layer 17 which are not only arranged on the side of the silicon substrate 11, but also arranged on the first surface of the silicon substrate 11. Specifically, on the first surface side of the silicon substrate 11, the transparent conductive layer 17 covers the first doped silicon layer 12 and the second doped silicon layer 16 on the side away from the silicon substrate 11, and a penetrating isolation groove is arranged in the transparent conductive layer 17 to disconnect the part of the transparent conductive layer 17 corresponding to the first doped silicon layer 12 from the part of the transparent conductive layer 17 corresponding to the second doped silicon layer 16 to prevent short circuit. As for the distribution of the above-mentioned first interface passivation layer 20, the first doped silicon layer 12, the insulating mask layer 21, the intrinsic silicon layer 15 and the second doped silicon layer 16 on the first side of the silicon substrate 11, reference can be made to the distribution of the first interface passivation layer 20, the first doped silicon layer 12, the intrinsic silicon layer 15 and the second doped silicon layer 16 on the first side of the silicon substrate 11 in the first aspect described above, and no specific limitation is made here.

[0173] In addition, in the side of the above-mentioned back contact cell, the second doped silicon layer can directly contact the transparent conductive layer. Fig.11 As shown, the above-mentioned back contact cell may also include an anti-reflection layer 14 disposed on the second surface, and the anti-reflection layer 14 extends from the second surface to the side surface. On the side surface, the anti-reflection layer 14 is disposed between the second doped silicon layer 16 and the transparent conductive layer 17 in the direction away from the side surface. In this case, an anti-reflection layer is added to the film layer disposed on the side surface of the silicon substrate, which can further improve the protection of the side surface of the silicon substrate, reduce the risk of damage to the side surface of the silicon substrate, and reduce the forward leakage loss. In addition, in this case, the anti-reflection layer is directly formed on the side of the second doped silicon layer away from the silicon substrate. Because there is a difference between the materials of the surface passivation layer and the second doped silicon layer, and the anti-reflection layer is easier to deposit on the surface passivation layer. Based on this, compared with the anti-reflection layer being directly formed on the surface passivation layer, when the anti-reflection layer is directly formed on the side of the second doped silicon layer away from the silicon substrate, the coating range of the anti-reflection layer on one side of the first surface can be reduced, thereby reducing the etching amount when removing the anti-reflection layer when coating on the first surface, and improving the manufacturing efficiency.

[0174] It should be noted that the following is only used to illustrate the difference between the back contact cell provided in the third aspect and the contact cell provided in the second aspect in the embodiment of the present invention. The similarities between the back contact cell provided in the third aspect and the contact cell provided in the second aspect, such as the conductivity type of the silicon substrate, the formation range and thickness of the first doped silicon layer on the side, and the formation range and thickness of the intrinsic silicon layer and the second doped silicon layer on the side, can refer to the corresponding description in the second aspect, and will not be repeated here.

[0175] In the back contact cell provided in the third aspect, the insulating mask layer may cover various areas of the side surfaces. Fig.11 As shown, the insulating mask layer 21 can also be arranged on a local area of ​​the side surface and close to the side of the first surface. The coverage of the insulating mask layer 21 on the side surface can refer to the corresponding description in the first aspect, and will not be repeated here.

[0176] In a fourth aspect, an embodiment of the present invention provides a photovoltaic module, comprising: a back-contact cell provided in the first aspect and various implementations thereof, or a back-contact cell provided in the second aspect and various implementations thereof.

[0177] The beneficial effects of the third aspect and its various implementations in the embodiments of the present invention may refer to the analysis of the beneficial effects in the first aspect and its various implementations, or may refer to the analysis of the beneficial effects in the second aspect and its various implementations, and will not be repeated here.

[0178] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

[0179] The embodiments of the present invention are described above. However, these embodiments are only for a clearer description and are not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims and their equivalents. Without departing from the scope of the present invention, a person skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present invention.

Claims

1. A back contact battery, characterized in that: include: A silicon substrate, the silicon substrate comprising a first surface and a second surface arranged opposite to each other, and a side surface connecting the first surface and the second surface; And a first interface passivation layer, a first doped silicon layer, an intrinsic silicon layer, a second doped silicon layer and a transparent conductive layer are sequentially arranged on the side along a direction away from the side; on the side of the silicon substrate, the first doped silicon layer and the intrinsic silicon layer are in direct contact; wherein the first doped silicon layer and the second doped silicon layer have opposite conductivity types.

2. The back contact cell according to claim 1, characterized in that: The back contact cell comprises a surface passivation layer disposed on the second surface, and the surface passivation layer extends from the second surface to the side surface; the back contact cell further comprises a second interface passivation layer disposed on the first surface and located between the silicon substrate and the second doped silicon layer, and the second interface passivation layer extends from the first surface to the side surface; On the side surface, the intrinsic silicon layer includes the surface passivation layer and the second interface passivation layer stacked in a direction away from the side surface; and / or, on the side of the silicon substrate, each part of the intrinsic silicon layer has the same thickness; And / or, on the side surface of the silicon substrate, the thickness of the intrinsic silicon layer is greater than or equal to 5 nm and less than or equal to 30 nm.

3. The back contact battery according to claim 2, characterized in that: The back contact cell also includes an anti-reflection layer; on the second surface, the anti-reflection layer is arranged on the side of the surface passivation layer away from the silicon substrate; the anti-reflection layer extends from the second surface to the side surface, and on the side surface, the anti-reflection layer is arranged between the second doped silicon layer and the transparent conductive layer.

4. The back contact cell according to claim 1, characterized in that: The back contact cell further comprises a surface passivation layer and an anti-reflection layer sequentially arranged on the second surface along the thickness direction of the silicon substrate, and the surface passivation layer and the anti-reflection layer extend from the second surface to the side surface; On the side surface and in a direction away from the side surface, the surface passivation layer and the anti-reflection layer are sequentially stacked and arranged between the second doped silicon layer and the transparent conductive layer.

5. The back contact cell according to claim 1, characterized in that: A doping layer is formed in the side surface of the silicon substrate; the dopant in the doping layer includes the dopant in the first doped silicon layer.

6. The back contact cell according to claim 1, characterized in that: The first interface passivation layer and the first doped silicon layer disposed on the side surface are only located on a local area of ​​the side surface and close to the first surface; Wherein, along the thickness direction of the silicon substrate, the ratio between the maximum extension length of the first interface passivation layer and the first doped silicon layer on the side and the thickness of the silicon substrate is greater than or equal to 70%; and / or, the surface of the area of ​​the side not covered by the first interface passivation layer and the first doped silicon layer is a velvet surface, and the ratio between the maximum extension length of the velvet surface on the side and the thickness of the silicon substrate is less than or equal to 30%; and / or, in the side surface, the surface reflectivity of the region not covered by the first interface passivation layer and the first doped silicon layer is less than the surface reflectivity of the region covered by the first interface passivation layer and the first doped silicon layer; And / or, the surface of the area of ​​the side surface not covered by the first interface passivation layer and the first doped silicon layer is a velvet surface; and / or, the surface of the area of ​​the side surface covered by the first interface passivation layer and the first doped silicon layer is a polished surface.

7. The back contact cell according to claim 1, characterized in that: The thickness of each part of the first interface passivation layer and / or the first doped silicon layer is the same; And / or, on the side surface of the silicon substrate, the thickness of at least one of the intrinsic silicon layer, the second doped silicon layer and the transparent conductive layer gradually increases along the direction from the second surface to the first surface.

8. The back contact battery according to any one of claims 2 to 4, characterized in that: On the side surfaces of the silicon substrate, the thickness of the surface passivation layer is equal, or the thickness of the surface passivation layer gradually increases along the direction from the first surface to the second surface; And / or, the surface passivation layer arranged on the side is located on a local area of ​​the side and close to the second surface; along the thickness direction of the silicon substrate, the ratio between the maximum extension length of the surface passivation layer on the side and the thickness of the silicon substrate is less than or equal to 80%.

9. The back contact cell according to claim 3 or 4, characterized in that: On the side surface of the silicon substrate, the thickness of the anti-reflection layer gradually increases along the direction from the first surface to the second surface; And / or, the surface passivation layer and the anti-reflection layer disposed on the side surface are located on a local area of ​​the side surface and close to the second surface; along the thickness direction of the silicon substrate, the ratio between the maximum extension length of the surface passivation layer and the anti-reflection layer on the side surface and the thickness of the silicon substrate is less than or equal to 80%; And / or, the anti-reflection layer arranged on the side surface is located on a local area of ​​the side surface and close to the second surface; along the thickness direction of the silicon substrate, the ratio between the maximum extension length of the anti-reflection layer on the side surface and the thickness of the silicon substrate is less than or equal to 80%.

10. The back contact cell according to any one of claims 2 to 4, characterized in that: The material of the surface passivation layer includes at least one of aluminum oxide, intrinsic amorphous silicon, and doped silicon glass.

11. The back contact cell according to claim 1, characterized in that: The thickness of the first doped silicon layer is greater than or equal to 30 nm and less than or equal to 140 nm.

12. The back contact cell according to claim 1, characterized in that: In the side surface of the silicon substrate, the region where the first interface passivation layer and the first doped silicon layer are arranged has a tower base-shaped texture structure; The thickness of the first interface passivation layer at the bottom surface of the tower-shaped texture structure is smaller than the thickness of the first interface passivation layer at the side wall of the tower-shaped texture structure.

13. The back contact cell according to claim 1, characterized in that: The side surface of the silicon substrate has a tower base-shaped texture structure; Wherein, the thickness of the first interface passivation layer located on the bottom surface of the tower base-shaped texture structure is less than the thickness of the first interface passivation layer located on the side wall of the tower base-shaped texture structure; The thickness of the intrinsic silicon layer at the bottom surface of the tower-shaped texture structure is greater than the thickness of the intrinsic silicon layer at the side wall of the tower-shaped texture structure; and / or the thickness of the second doped silicon layer at the bottom surface of the tower-shaped texture structure is greater than the thickness of the second doped silicon layer at the side wall of the tower-shaped texture structure.

14. A photovoltaic module, characterized in that: include: A back contact battery as claimed in any one of claims 1 to 13.

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