Storage device, capacity detection control method, device and apparatus of storage device

Abstract

This application relates to a storage device, a method, apparatus, and device for capacity detection and control of the storage device. The storage device includes a front-end, a back-end, and a first type of flash memory. The front-end is connected to the back-end, and the back-end is connected to the first type of flash memory via a chip select signal. During power-up of the storage device, the back-end scans the chip select signal using first-type firmware to determine the target chip select signal connected to the first type of flash memory, obtains the capacity parameters of the first type of flash memory, and determines the capacity of the storage device based on the capacity parameters and the target chip select signal. After the back-end determines the capacity of the storage device, the front-end reissues second-type firmware to the back-end. The back-end uses the second-type firmware to input and output data according to the capacity of the storage device. This application solves the memory usage problem caused by adding capacity detection functionality in conventional technologies.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a storage device, a method, apparatus and device for detecting and controlling the capacity of the storage device. Background Technology

[0002] With the development of information technology, massive amounts of data are constantly being generated across all industries, making the storage of this vast amount of data increasingly important. Meanwhile, solid-state drives (SSDs), with their faster read / write speeds, higher reliability, and lower power consumption, are increasingly replacing hard disk drives (HDDs). In the field of storage devices, capacity is a key consideration, determining not only how much data a device can store but also being closely related to its performance and cost.

[0003] Currently, the capacity of storage devices is written into the firmware, and different capacities require different firmware, making the production process quite complex. When compiling firmware packages for solid-state drives (SSDs), multiple firmware packages need to be compiled, and the compilation time is several times longer than normal, significantly impacting development efficiency. Even with script-controlled compilation and one-click compilation, the compilation time cannot be reduced.

[0004] To address this issue, the common practice is to add a capacity detection function to the storage device, enabling the same firmware to adapt to various capacities. However, this capacity detection function requires a certain amount of IRAM (Internal Random Access Memory) or DRAM (Dynamic Random Access Memory) space. Currently, solid-state drive controllers on the market have relatively little redundancy in their design, resulting in insufficient available resources for the firmware to function properly after adding this function. Summary of the Invention

[0005] Therefore, it is necessary to provide a storage device, a storage device capacity detection control method, apparatus, and device that can solve the memory occupation problem during capacity detection.

[0006] In a first aspect, a storage device is provided, comprising a front-end, a back-end, and a first type of flash memory, wherein the front-end is connected to the back-end, and the back-end is connected to the first type of flash memory via a chip select signal, wherein...

[0007] The backend is used to scan the chip select signal through the first type of firmware during the power-on process of the storage device to determine the target chip select signal for connecting the first type of flash memory, obtain the capacity parameters of the first type of flash memory, and determine the capacity of the storage device based on the capacity parameters and the target chip select signal.

[0008] The front end is used to reissue the second type of firmware to the back end after the back end determines the capacity of the storage device;

[0009] The backend is used to input and output data based on the storage device's capacity using the second type of firmware.

[0010] In one embodiment, the first type of flash memory includes logic cells, with the back end connected to the logic cells via chip select signals. Capacity parameters include the number of logic cells connected to the chip select signals and the size of the logic cells. The capacity includes physical capacity and user capacity. The storage device also includes a second type of flash memory.

[0011] The backend is used to read the page parameters of the first type of flash memory connected to the target chip select signal, extract the number of logical units connected to the chip select signal and the size of the logical units from the page parameters, and determine the physical capacity of the storage device based on the number of logical units connected to the target chip select signal and the size of the logical units.

[0012] The backend is also used to obtain the daily total disk write count pre-burned into the second type of flash memory, and to determine the user capacity based on the daily total disk write count and physical capacity.

[0013] Physical capacity is used to control data input and output, while user capacity is used for client queries.

[0014] In one embodiment, the backend is used to determine the reservation ratio based on the number of daily disk writes, and to determine the user capacity based on the reservation ratio and the physical capacity.

[0015] In one embodiment, the first type of flash memory is NAND flash memory, and the second type of flash memory is NOR flash memory.

[0016] In one embodiment, the back end is provided with at least one channel, each channel having a channel controller connected to at least one chip select signal, the chip select signal being connected to at least one type-1 flash memory, wherein...

[0017] The backend is used to run the first type of firmware through the channel controller during the power-on process of the storage device, so as to set each chip select signal in a preset order and send a reset signal to the first type of flash memory connected to each chip select signal.

[0018] The backend is also used to read the status of the first type of flash memory connected to each chip select signal after a preset time, in order to scan the chip select signals, obtain the chip select signals of the connected first type of flash memory in the reset state, and obtain the target chip select signal.

[0019] In one embodiment, the channels include multiple channels, wherein,

[0020] The front end is also used to detect the number of logical units connected to each channel. When it is detected that the number of logical units connected to more than a preset number of channels is less than the number of logical units connected to other channels, an exception log is recorded and the storage device is set to an abnormal state.

[0021] In a second aspect, a capacity detection and control method for a storage device is provided. The storage device includes a front-end, a back-end, and a first type of flash memory. The front-end and the back-end are connected, and the back-end and the first type of flash memory are connected via at least one chip select signal. The method is applied to the back-end, and the capacity detection and control method for the storage device includes:

[0022] During the power-on process of the storage device, the chip select signal is scanned by the first type of firmware to determine the target chip select signal for connecting the first type of flash memory;

[0023] Obtain the capacity parameters of the first type of flash memory, and determine the capacity of the storage device based on the capacity parameters and the target chip select signal;

[0024] Receive the second type of firmware from the front end and run the second type of firmware to input and output data according to the capacity of the storage device.

[0025] In a third aspect, a capacity detection and control device for a storage device is provided. The storage device includes a front-end, a back-end, and a first type of flash memory. The front-end is connected to the back-end, and the back-end is connected to the first type of flash memory via at least one chip select signal. The device is applied to the back-end. The capacity detection and control device for the storage device includes:

[0026] The scanning module is used to scan the chip select signal through the first type of firmware during the power-on process of the storage device to determine the target chip select signal for connecting the first type of flash memory;

[0027] The acquisition module is used to acquire the capacity parameters of the first type of flash memory and determine the capacity of the storage device based on the capacity parameters and the target chip select signal.

[0028] The running module is used to receive the second type of firmware from the front end and run the second type of firmware to input and output data according to the capacity of the storage device.

[0029] In a fourth aspect, this application provides a computer device including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the steps of the capacity detection and control method for the storage device provided in any embodiment of the first aspect of this application.

[0030] In a fifth aspect, this application provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the capacity detection and control method for a storage device provided in any embodiment of the first aspect of this application.

[0031] The aforementioned storage device, storage device capacity detection control method, apparatus, and device utilize a specially designed first-type firmware for capacity scanning. This firmware is specifically responsible for performing the capacity scanning function and can complete the scanning task with limited memory resources. After the scanning firmware completes the capacity scanning function, a second-type firmware for normal operation is then reissued to the backend. In this way, after completing the critical capacity scan, the backend can switch to normal operating mode, ensuring normal data input and output operations and preventing functional chaos or malfunction due to insufficient memory. Therefore, this application solves the memory occupation problem caused by adding capacity detection functions in traditional technologies. It enables flash memory capacity scanning and normal data input and output even with limited backend redundancy space for the storage device, ensuring stable operation of the storage device and improving the flexibility and reliability of storage device capacity identification and data processing. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of the internal structure of the storage device in some embodiments;

[0033] Figure 2 This is a schematic diagram of the internal structure of the storage device in some embodiments;

[0034] Figure 3 This is a flowchart illustrating the capacity detection and control method for a storage device in other embodiments;

[0035] Figure 4 This is a structural block diagram of the capacity detection and control device for the storage device in some embodiments;

[0036] Figure 5 This is a diagram showing the internal structure of a computer device in some embodiments. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0038] In the first aspect, a storage device is provided, such as Figure 1 As shown, the storage device includes a front-end, a back-end, and a type I flash memory. The front-end and back-end are connected, and the back-end is connected to the type I flash memory via a chip select signal.

[0039] The backend is used to scan the chip select signal through the first type of firmware during the power-on process of the storage device to determine the target chip select signal for connecting the first type of flash memory, obtain the capacity parameters of the first type of flash memory, and determine the capacity of the storage device based on the capacity parameters and the target chip select signal.

[0040] The front end is used to reissue the second type of firmware to the back end after the back end determines the capacity of the storage device;

[0041] The backend is used to input and output data based on the storage device's capacity using the second type of firmware.

[0042] Storage devices are devices used to store data. They can include hard drives (such as mechanical hard drives and solid-state drives). In computer systems, storage devices are a crucial component of data storage; for example, storage arrays in servers are a type of storage device capable of providing large-scale data storage services.

[0043] For solid-state drives (SSDs), the front end is the module that interacts with servers or PCs (Personal Computers). It is mainly responsible for receiving data and instructions from external devices (such as servers or PCs) and feeding back the information processed internally by the storage device to the external devices.

[0044] The backend refers to the module that stores the data received from the frontend on the disk. It is responsible for communicating with the flash memory, managing and storing data, including reading and writing operations to the flash memory.

[0045] Type I flash memory is a non-volatile storage technology that retains data even after power is lost. It features high storage density, enabling the storage of large amounts of data in a relatively small physical space. Therefore, it is commonly used in high-capacity data storage devices such as solid-state drives (SSDs) and USB flash drives.

[0046] Chip Enable (CE) is a signal used between the back-end and Type 1 flash memory to select a specific flash memory chip (or flash memory cell). By scanning the chip enable signal, the back-end can determine which flash memory chips are connected and their related information.

[0047] Capacity parameters are used to describe the storage capacity-related characteristics of Type I flash memory and are an important basis for determining the overall capacity of storage devices.

[0048] The first type of firmware is stored in the storage device for scanning. It is called by the backend during the power-on process of the storage device to scan the chip select signal and obtain flash memory capacity parameters in order to determine the storage device capacity.

[0049] The second type of firmware is the IO (Input / Output) firmware in storage devices, which is used to perform data input and output operations according to the capacity of the storage device.

[0050] Specifically, when the storage device powers on, the backend initializes, preparing to begin scanning for chip select signals. The backend starts the first type of firmware, which uses a preset scanning program to check the chip select signal lines connected to the first type of flash memory according to a specific order and rules. Each possible chip select signal line is checked one by one to determine which lines are in a valid connection state; these validly connected chip select signals are the target chip select signals. For example, if there are multiple chip select signal channels, the firmware will check each channel individually to determine if the signal matches the characteristics of a validly connected flash memory.

[0051] Furthermore, for each Type I flash memory connected via the target chip select signal, the backend communicates with the flash memory using Type I firmware. According to the flash memory's communication protocol, the firmware sends a command to the flash memory to retrieve its capacity parameters. Upon receiving the command, the flash memory replies its own capacity parameter information to the backend.

[0052] Furthermore, after the backend collects the capacity parameters of the first type of flash memory corresponding to all target chip select signals, it performs calculations based on this information. According to pre-set calculation rules, combined with the number of flash memory flashes associated with the target chip select signals and the capacity parameters of each flash memory flash, the total capacity of the storage device is calculated.

[0053] In this application, a dedicated scanning firmware, namely the first type of firmware, is written for the scanning process to complete the capacity scanning function. After the above scanning function is completed, a working firmware, namely the second type of firmware, is then reissued to the backend to ensure that its I / O functions correctly.

[0054] Furthermore, this application uses a first-type firmware to scan the chip select signal to determine the target chip select signal for connecting to the first-type flash memory, obtains the capacity parameters of the first-type flash memory, and determines the capacity of the storage device based on the capacity parameters and the target chip select signal, thus achieving firmware uniformity. Specifically, in conventional technology, different firmware packages need to be burned for storage devices of different capacities (e.g., 2T / 4T / 8T / 16T). In this application, when the storage device is powered on, the backend uses the first-type firmware to scan the chip select signal to determine the target chip select signal for connecting to the first-type flash memory, thereby obtaining the flash memory's capacity parameters and ultimately determining the storage device's capacity. This step does not rely on pre-burned firmware of a specific capacity.

[0055] For example, whether it is a 2TB or 4TB storage device, its actual capacity information can be obtained during this power-on scan process, rather than being identified by firmware pre-programmed for a specific capacity.

[0056] After the front-end determines the storage device capacity at the back-end, it reissues the second type of firmware to the back-end. The key point here is that the second type of firmware is issued based on the already determined capacity, and it can perform data input and output according to the actual determined capacity of the storage device.

[0057] This means that the second type of firmware can adapt to storage devices of different capacities. Unlike traditional technologies that require burning different firmware for each capacity, it first determines the capacity and then flexibly applies the same set of firmware for subsequent operations, thereby achieving firmware uniformity and solving the problem of needing to burn different firmware packages due to different capacities.

[0058] In one embodiment, the first type of flash memory has logic cells, and the back end is connected to the logic cells via chip select signals. The capacity parameters include the number of logic cells connected to the chip select signals and the size of the logic cells. The capacity includes physical capacity and user capacity. The storage device also has a second type of flash memory. The back end is used to read the page parameters of the first type of flash memory connected to the target chip select signal, extract the number of logic cells connected to the chip select signal and the size of the logic cells from the page parameters, determine the physical capacity of the storage device based on the number of logic cells connected to the target chip select signal and the size of the logic cells, obtain the number of daily disk writes pre-programmed into the second type of flash memory, and determine the user capacity based on the number of daily disk writes and the physical capacity. The physical capacity is used to control data input and output, and the user capacity is used for client queries.

[0059] In this application, the capacity-related parameters in the original firmware are divided into two parts:

[0060] 1. Information related to the first type of flash memory, specifically including the number of target chip select signals connected to the first type of flash memory, the number of logic cells connected to the chip select signals, and the size of the logic cells, is obtained by back-end scanning;

[0061] 2. DWPD (Drive Writes Per Day) information, which is unrelated to the first type of firmware, is burned separately into the second type of flash memory for the firmware to access.

[0062] A logic unit (LUN) is the smallest unit in Type I flash memory that can operate independently and acquire its status.

[0063] Physical capacity refers to the total amount of data that the Type 1 flash memory in a storage device can actually store. It is determined by reading the page parameters of the Type 1 flash memory from the backend, extracting the number and size of the logic cells connected to the chip select signal. This capacity reflects the actual storage capability of the storage device at the hardware level and is mainly used for controlling data input and output operations within the storage device. For example, for a hard drive, its physical capacity is like the maximum total space that all the storage platters inside the hard drive can hold; this capacity determines how much data can be physically stored on the hard drive.

[0064] User capacity refers to the storage capacity after considering certain limiting factors (such as the number of disk writes per day). It is determined based on the number of disk writes per day pre-burned into Type II flash memory and the calculated physical capacity. User capacity is usually less than or equal to physical capacity, and it represents the amount of storage that a user can effectively utilize when actually using the storage device. For example, because the storage device may reserve some space for system maintenance, data backup, or limit the space available to the user due to factors such as wear and tear, the capacity seen by the user (user capacity) will differ from the maximum physical capacity (physical capacity) that the device can actually store.

[0065] In storage devices, page parameters are a set of parameters associated with flash memory pages. For flash memory, data storage is organized in basic units of pages. Page parameters contain several pieces of information, such as the size of each page, which determines the amount of data stored at the page level during each write or read operation. They also include the format of the data stored within the page, error correction codes, and other related information. Error correction codes are used to detect and correct potential errors during data reading to ensure data accuracy. Additionally, page parameters may also relate to the logical location of the page within the entire flash memory storage system. This information helps the backend of the storage device accurately locate, read, and write data, serving as crucial information for the storage device's management and operation of data in the flash memory.

[0066] Specifically, when the storage device powers on, the backend starts the first type of firmware, preparing to perform subsequent operations. By running the first type of firmware, it scans the chip select signals to identify the target chip select signal connected to the first type of flash memory. The backend establishes a connection with the corresponding first type of flash memory through the target chip select signal and reads the page parameters of the flash memory. These page parameters contain information related to logical cells. From the read page parameters, it extracts the number of logical cells connected to the chip select signal and the size of each logical cell. This information is crucial for determining the physical capacity. Based on the extracted number of logical cells connected to the target chip select signal and the size of the logical cells, the backend calculates the physical capacity of the storage device according to a specific algorithm. For example, if each logical cell is x bytes in size and there are n logical cells in total, then the physical capacity is nx bytes.

[0067] Furthermore, the backend retrieves the daily total disk write count from the information pre-programmed into the second type of flash memory. Based on the retrieved daily total disk write count and the calculated physical capacity, it calculates the user capacity using a specific formula or rule. The calculated physical capacity is used to control data input and output operations, while the user capacity is used for client queries to meet different usage needs.

[0068] The beneficial effects of this embodiment are as follows:

[0069] By reading the parameters of the first type of flash memory pages to extract the number and size of logical cells, the physical capacity can be determined. This allows the storage device to accurately grasp its actual storage capacity, providing a precise basis for data input / output control and ensuring efficient and stable data storage and transmission. For example, when writing large data files, storage locations can be rationally allocated based on the accurate physical capacity, avoiding write failures caused by capacity estimation errors.

[0070] User capacity is determined by combining daily full disk write counts and physical capacity, taking into account actual device usage and lifespan. Daily full disk write counts reflect device usage intensity, and adjusting the usable capacity accordingly ensures users have reasonable storage space while reserving some physical capacity for wear leveling and other operations, thus extending the storage device's lifespan.

[0071] In one embodiment, the backend is used to determine the reservation ratio based on the number of daily disk writes, and to determine the user capacity based on the reservation ratio and the physical capacity.

[0072] The "reservation ratio" refers to the proportion of space reserved for wear leveling. Wear leveling is a technique used to extend the lifespan of SSDs. Since SSDs store data using flash memory chips, which have a limited write lifespan, some storage cells may be written to frequently, thus exhausting their write lifespan more quickly. To avoid this, a portion of space is reserved to balance the number of writes to different storage cells, ensuring data is written evenly across them. This reserved space is the proportion of the physical capacity. A higher reservation ratio means less usable space (user capacity) relative to the physical capacity, but this helps extend the overall lifespan and reliability of the SSD.

[0073] Specifically, this application can pre-set a loss coefficient k related to the number of writes, and calculate the loss balancing reserved space ratio p based on k, i.e., p = k * n, where n is the number of full disk writes per day. Further, user capacity is calculated based on P. That is, user capacity = physical capacity * (1 - ps), where p is the system occupied space ratio. The system occupied space ratio refers to the proportion of space occupied by system files, system programs, and necessary data generated during system operation in the storage device relative to the physical capacity of the storage device.

[0074] The benefits of this design are that by determining user capacity through a reservation ratio and physical capacity, it allows for flexible allocation based on the actual usage of the storage device. If the number of daily disk writes is low, the reservation ratio is reduced accordingly, allowing users to use more space and improving the space utilization of the storage device. Conversely, in scenarios with frequent writes, although the available space for users is reduced, the stability and reliability of the storage are guaranteed.

[0075] In one embodiment, the first type of flash memory is NAND flash memory, and the second type of flash memory is NOR flash memory.

[0076] NAND flash memory is a non-volatile storage technology. Its data storage is organized in units of blocks and pages. This type of flash memory features high storage density, enabling it to store large amounts of data in a relatively small physical space. Therefore, it is commonly used in high-capacity data storage devices such as solid-state drives (SSDs) and USB flash drives.

[0077] NOR flash memory is also a non-volatile storage technology. Its data access method is similar to ordinary random access memory, allowing data to be read byte by byte, which gives it the advantage of fast random access speed. NOR flash memory is mainly used to store program code; firmware for devices that require fast boot times is typically stored in NOR flash memory. This is because it can quickly provide instructions to the processor, facilitating rapid device startup and program execution.

[0078] Therefore, this application uses NOR flash memory to store critical information that requires rapid access, such as parameters like the daily disk write count pre-programmed into it. These parameters are crucial for storage device management and performance optimization (e.g., determining user capacity), and NOR flash memory ensures that this information can be read quickly and accurately, thus supporting the efficient operation of the storage device.

[0079] In one embodiment, such as Figure 2 As shown, the backend has at least one channel, and each channel has a channel controller (not shown). The channel controller is connected to at least one chip select signal, and the chip select signal is connected to at least one type of flash memory. The backend is used to run type-1 firmware through the channel controller during the power-on process of the storage device to set each chip select signal in a preset order, send a reset signal to the type-1 flash memory connected to each chip select signal, and read the status of the type-1 flash memory connected to each chip select signal after a preset time to scan the chip select signals, obtain the chip select signal of the connected type-1 flash memory in the reset state, and obtain the target chip select signal.

[0080] exist Figure 2In the process, the storage device includes a front-end, a flash conversion layer, and a back-end. The connection between the back-end and the first type of flash memory is divided into multiple channels. Each channel operates in complete parallel. Each channel is equipped with a channel controller. Each channel controller is connected to at least one chip select signal. Each chip select signal is connected to at least one type of flash memory.

[0081] The Flash Translation Layer (FTL) is primarily responsible for translating logical addresses into physical addresses. Operating systems and applications use logical addresses to access storage devices. The FTL translates these logical addresses into physical addresses within the flash memory chips. For example, when the operating system wants to read a file, it issues a logical address; the FTL acts like a translator, converting this logical address into the physical address in the flash memory where the file data is actually stored, ensuring accurate data retrieval.

[0082] Specifically, the back-end of the channel controller has a certain capability range, supporting 4-16 CE signals. These CE signals are important signals used for controlling and selecting Class I flash memory chips.

[0083] The channel controller activates (sets) one CE signal at a time in a specific sequence. After activation, it sends a reset command to the selected Type 1 flash memory. The purpose of this reset command is to return the Type 1 flash memory to an initial state, preparing it for subsequent operations.

[0084] After receiving a reset command, the Type 1 flash memory requires a certain amount of time (tRST) to complete the reset operation. After this time, the channel controller will attempt to read the status of the Type 1 flash memory from the bus. This status information includes whether the Type 1 flash memory has responded normally and whether it is ready for subsequent operations.

[0085] Furthermore, if the channel controller can obtain the correct reset information from the bus, it means that the channel corresponding to the activated CE signal is connected to a normally functioning Type I flash memory. However, if the controller polls (checks) all allowed maximum times and still cannot obtain the status information returned by the Type I flash memory, it means that the channel corresponding to the CE signal is either not connected to a Type I flash memory or the connected Type I flash memory is not functioning properly. In this case, it is treated as if there is no connection.

[0086] The beneficial effects of this embodiment are as follows:

[0087] By sequentially setting the CE signal, sending a reset command, and reading the status information, it is possible to accurately detect whether the channel corresponding to each CE signal is connected to a normally functioning Type-1 flash memory. This method provides a reliable detection mechanism, ensuring that the controller can clearly understand the actual physical connection status of the back-end storage modules.

[0088] Furthermore, the addition of specific functions to the solid-state drive (SSD) channel controller (such as the aforementioned function of scanning the chip select signal to determine capacity) requires a portion of internal random access memory (IRAM) or dynamic random access memory (DRAM). However, current SSD controllers on the market typically do not reserve much memory space for these additional functions in their back-end channel controller designs. Therefore, after adding these new functions, the IRAM / DRAM memory required for the normal operation of the back-end channel controller becomes insufficient. This application addresses this memory shortage issue by developing specialized scanning firmware, enabling scanning tasks to be completed with limited memory resources.

[0089] After the scanning firmware completes the capacity scan, it reissues the normal operating firmware to the backend channel controller. In this way, after completing the critical capacity scan, the channel controller can switch to normal operating mode, enabling input / output (I / O) operations to run normally and avoiding functional malfunctions or failures due to insufficient memory.

[0090] In one embodiment, the channels include multiple channels, wherein the front end is also used to detect the number of logical units connected to each channel. When it is detected that the number of logical units connected to more than a preset number of channels is less than the number of logical units connected to other channels, an exception log is recorded and the storage device is set to an abnormal state.

[0091] In this application, the backend scans the number of logical units in each channel and transmits the scan results to the backend. Generally, for channel controllers already in use, the number of CEs connected in each channel is the same. If there are differences, they will be recorded in the configuration file in the second type of flash memory. After the backend scans the CEs of each channel, the firmware can know the CE usage. If the number of CEs in a certain channel is inconsistent and not specially recorded in the second type of flash memory, it indicates that there is an abnormality in the soldering of the first type of flash memory in that channel. After reporting the above abnormality as an error, the subsequent initialization process is skipped, and a failure is returned.

[0092] It should be noted that when the number of CEs in a certain channel is inconsistent with the number of CEs in other channels, it is necessary to further determine whether the number of logic units in that channel is greater than the number of logic units in other channels. If so, no error is reported; otherwise, an error is reported.

[0093] The reason is that this application allows one or two channels to have one or two more logical units than other channels. The purpose of this design is to increase the performance of the storage device by adding extra physical space on the disk.

[0094] However, an error message will be displayed for a small number of cases where logic units are missing.

[0095] Specifically, the front-end initiates a detection program to obtain the number of logical units connected to each channel by interacting with the back-end. This may involve sending specific query commands to the back-end, which then returns the number of logical units for the corresponding channel based on the first type of flash memory information.

[0096] Furthermore, the number of logic units connected to each channel is compared. A preset number is set, and the number of channels with fewer connected logic units than other channels is counted. For example, assuming there are 10 channels in total and the preset number is 3, when it is found that 4 channels have significantly fewer connected logic units than other channels, the subsequent operation is triggered.

[0097] If a channel is found to have fewer logical units connected than a preset number of channels compared to other channels, the front end logs an anomaly. The log may include details such as the detection time, the channel numbers involved, and the number of logical units in each channel. Simultaneously, the front end sets the storage device to an abnormal state, which may involve modifying the device status flags so that other parts of the system can recognize that the storage device is currently in an abnormal condition.

[0098] The beneficial effects of this embodiment are as follows:

[0099] It can promptly detect potential hardware connection or configuration anomalies in storage devices. An abnormal number of logical cells may indicate problems such as loose, damaged, or misconfigured Type 1 flash connections in some channels. By logging anomalies, detailed clues are provided for subsequent troubleshooting, which helps to quickly locate and resolve issues and reduce device downtime.

[0100] Setting a storage device to an abnormal state prevents the system from continuing normal operations on potentially problematic devices, avoiding data loss or corruption due to the use of abnormal channels and ensuring data security and integrity.

[0101] Timely detection and identification of abnormal states help the system take appropriate protective measures, such as restricting read and write operations on the storage device or notifying the administrator for handling. This helps maintain the stability of the entire storage system and prevents localized problems from spreading and affecting the normal operation of other parts.

[0102] In a second aspect, a capacity detection and control method for a storage device is provided. The storage device includes a front-end, a back-end, and a first type of flash memory. The front-end and the back-end are connected, and the back-end and the first type of flash memory are connected via at least one chip select signal. The method is applied to the back-end and includes:

[0103] Step S31: During the power-on process of the storage device, the chip select signal is scanned by the first type of firmware to determine the target chip select signal for connecting the first type of flash memory.

[0104] Step S32: Obtain the capacity parameters of the first type of flash memory, and determine the capacity of the storage device based on the capacity parameters and the target chip select signal.

[0105] Step S33: Receive the second type of firmware sent by the front end and run the second type of firmware to input and output data according to the capacity of the storage device.

[0106] Specifically, after the storage device is powered on, the backend uses the first type of firmware to scan the chip select signals in a specific order and manner. By sending a reset signal and reading the status, it finds the normally functioning first type of flash memory corresponding to the target chip select signal.

[0107] Furthermore, the backend reads relevant capacity parameters from the first type of flash memory connected to the target chip select signal. These parameters may include the number of logical cells and the size of the logical cells. Then, based on these parameters and the number of flash memories corresponding to the target chip select signal, the total capacity of the storage device is determined through a certain calculation method (such as adding the capacities of each flash memory). For example, if there are two flash memories corresponding to target chip select signals, and the number and size of each flash memory are known, the total capacity of the two flash memories, which is the capacity of the storage device, can be calculated.

[0108] Furthermore, after learning the storage device capacity determined by the backend, the frontend will issue a second type of firmware. The backend receives and runs this firmware, which will rationally arrange data input and output operations based on the storage device's capacity. For example, when writing data, it will determine whether there is enough space to store the data based on the storage device's capacity, and how to allocate the data to different flash memory locations, etc.

[0109] In this application, the first type of firmware is mainly used to scan the chip select signal during the power-on process of the storage device to determine the capacity of the flash memory. Its main function is to identify the capacity, rather than to perform different data input / output operations for different capacities. This is equivalent to a universal "capacity detector," which can obtain capacity information regardless of the final capacity of the storage device.

[0110] The second type of firmware operates based on a predetermined capacity. After the backend determines the storage device's capacity, the frontend reissues the second type of firmware. This firmware can handle data input and output according to the determined storage device capacity. Because it operates based on the actual determined capacity, the second type of firmware can be applied to storage devices of different capacities.

[0111] For example, for storage devices with capacities of 2TB and 4TB, although the capacities are different, after the first type of firmware identifies the capacity, the second type of firmware can perform adaptive operations based on this identification result (2TB or 4TB), instead of requiring different firmware for data input / output to be burned separately for 2TB and 4TB, as is the case with traditional technology. This achieves firmware unification at the core function level of data input / output.

[0112] In a third aspect, this application provides a capacity detection and control device for a storage device, such as... Figure 4 As shown, the storage device includes a front-end, a back-end, and a first-class flash memory. The front-end is connected to the back-end, and the back-end is connected to the first-class flash memory via at least one chip select signal. The device is applied to the back-end and includes:

[0113] Scanning module 41 is used to scan the chip select signal through the first type of firmware during the power-on process of the storage device to determine the target chip select signal connected to the first type of flash memory;

[0114] The acquisition module 42 is used to acquire the capacity parameters of the first type of flash memory and determine the capacity of the storage device based on the capacity parameters and the target chip select signal.

[0115] The running module 43 is used to receive the second type of firmware sent from the front end and run the second type of firmware to input and output data according to the capacity of the storage device.

[0116] In a fourth aspect, this application provides a computer device including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the steps of the capacity detection and control method for the storage device provided in any embodiment of the first aspect of this application.

[0117] In one embodiment, the computer device may be a server, and its internal structure diagram may be as follows: Figure 5As shown, the computer device includes a processor, memory, network interface, and database connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The network interface is used for communication with external terminals via a network connection. When the computer program is executed by the processor, it implements a capacity detection and control method for the storage device.

[0118] In a fifth aspect, this application provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the capacity detection and control method for a storage device provided in any embodiment of the first aspect of this application.

[0119] The computer-readable storage medium may be Figure 5 The computer-readable storage medium in the computer device shown.

[0120] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0121] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0122] The above embodiments merely illustrate several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A storage device, characterized in that, The storage device includes a front-end, a back-end, and a first type of flash memory. The front-end is connected to the back-end, and the back-end is connected to the first type of flash memory via a chip select signal. The first type of flash memory has logic cells, and the back-end is connected to the logic cells via the chip select signal. The backend is used to scan the chip select signal through a first type of firmware during the power-on process of the storage device to determine the target chip select signal connected to the first type of flash memory, read the page parameters of the first type of flash memory connected to the target chip select signal, extract the number of logic units connected to the target chip select signal and the size of the logic units from the page parameters, and determine the physical capacity of the storage device based on the number of logic units connected to the target chip select signal and the size of the logic units. The front end is used to reissue the second type of firmware to the back end after the back end determines the physical capacity of the storage device; The backend is used to input and output data according to the physical capacity of the storage device through the second type of firmware.

2. The storage device according to claim 1, characterized in that, The storage device also includes a second type of flash memory, wherein... The backend is also used to obtain the daily total disk write count pre-programmed into the second type of flash memory, and to determine the user capacity based on the daily total disk write count and the physical capacity, wherein the user capacity is used for client query.

3. The storage device according to claim 2, characterized in that, The backend is used to determine the reservation ratio based on the daily disk write count, and to determine the user capacity based on the reservation ratio and the physical capacity.

4. The storage device according to claim 2, characterized in that, The first type of flash memory is NAND flash memory, and the second type of flash memory is NOR flash memory.

5. The storage device according to claim 1, characterized in that, The back end is provided with at least one channel, each channel having a channel controller. The channel controller is connected to at least one chip select signal, and each chip select signal is connected to at least one of the first type of flash memory. The backend is used to run the first type of firmware through the channel controller during the power-on process of the storage device, so as to set each chip select signal in a preset order and send a reset signal to the first type of flash memory connected to each chip select signal. The backend is also used to read the state of the first type of flash memory connected to each of the chip select signals after a preset time, so as to scan the chip select signals, obtain the chip select signals of the connected first type of flash memory in the reset state, and obtain the target chip select signal.

6. The storage device according to claim 5, characterized in that, The channels include multiple channels, among which, The front end is also used to detect the number of logical units connected to each of the channels. When it is detected that the number of logical units connected to more than a preset number of channels is less than the number of logical units connected to other channels, an exception log is recorded and the storage device is set to an abnormal state.

7. A method for capacity detection and control of a storage device, characterized in that, The storage device includes a front-end, a back-end, and a first type of flash memory. The front-end is connected to the back-end, and the back-end is connected to the first type of flash memory via at least one chip select signal. The first type of flash memory has logic cells, and the back-end is connected to the logic cells via the chip select signal. The method is applied to the back-end, and the method includes: During the power-on process of the storage device, the chip select signal is scanned by the first type of firmware to determine the target chip select signal for connecting the first type of flash memory; Read the page parameters of the first type of flash memory connected to the target chip select signal, extract the number of logic units connected to the target chip select signal and the size of the logic units from the page parameters, and determine the physical capacity of the storage device based on the number of logic units connected to the target chip select signal and the size of the logic units. The device receives the second type of firmware sent by the front end and runs the second type of firmware to input and output data according to the physical capacity of the storage device.

8. A capacity detection and control device for a storage device, characterized in that, The storage device includes a front-end, a back-end, and a first type of flash memory. The front-end is connected to the back-end, and the back-end is connected to the first type of flash memory via at least one chip select signal. The first type of flash memory has logic cells, and the back-end is connected to the logic cells via the chip select signal. The apparatus is applied to the back-end and includes: A scanning module is configured to scan the chip select signal using a first type of firmware during the power-on process of the storage device to determine the target chip select signal for connection to the first type of flash memory; The acquisition module is used to read the page parameters of the first type of flash memory connected to the target chip select signal, extract the number of logic units connected to the target chip select signal and the size of the logic units from the page parameters, and determine the physical capacity of the storage device based on the number of logic units connected to the target chip select signal and the size of the logic units. The running module is used to receive the second type of firmware issued by the front end and run the second type of firmware to input and output data according to the capacity of the storage device.

9. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 7.

Images