Manchester encoding communication verification system

Abstract

The invention discloses a Manchester encoding communication verification system, and relates to the field of encoding, the Manchester encoding communication verification system comprises a core ECU and a plurality of edge ECUs, each edge ECU is internally provided with an SPI controller and is connected with a voltage conversion circuit of an MOSI end and a current conversion circuit of an MISO end; the edge ECU translates Manchester data to be sent into an SPI byte number cache through the CPU core, performs matching verification on an external level signal, and determines a fault source according to a result; the SPI controller takes over SPI byte data according to the request, and sends and receives data according to a preset coding frequency; the DMA controller reads the cached SPI byte data during sending and sends the cached SPI byte data to the SPI controller, and the SPI controller inputs an external level signal during receiving and calls and caches the external level signal through the DMA controller. According to the scheme, the characteristic that the SPI and DMA technologies have no CPU intervention in data transmission is utilized, the processing efficiency of Manchester encoding is improved, and the flexibility and expandability of system encoding verification are enhanced.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of coding, and in particular to a Manchester coding communication verification system. Background Art

[0002] In modern communication technology, Manchester coding is an important data transmission method. It is widely used in many fields due to its unique advantages, including but not limited to Ethernet, vehicle bus systems and various industrial buses. The core feature of Manchester coding is that its transmission signal does not contain a DC component. This feature enables the signal to effectively resist DC offset problems when transmitted over long distances. At the same time, its built-in clock information simplifies the clock recovery process at the receiving end and enhances the stability and reliability of the system.

[0003] In the automotive field bus PSI5, the Manchester current encoding technology is used in the PSI5 bus. When this bus is applied between multiple ECUs or sensor networks, the edge ECU1 and ECUx are mounted on the PSI5 bus. The ECU determines the vehicle status by detecting the sensor data on the bus, such as collision detection. However, self-checking cannot determine the causes of ECU and circuit failures, and it is difficult to ensure vehicle safety when the external sensor data is abnormal. Although some Manchester encoding chips have appeared on the market to solve this problem, their data processing speed is difficult to maintain, and the external encoding chip will cause the cost to rise. If the edge ECU is used for self-checking, it is necessary to comprehensively consider the CPU response resource utilization problem. The edge ECU must not only complete the communication needs of the PSI5 bus, but also complete edge computing control, other sensor data acquisition, and communication with other chips such as the core ECU. In addition, although the timer and general input and output (GPIO) port of the ECU core have a low cost to implement Manchester encoding, the efficiency of this method is greatly reduced, and it may also introduce additional delays and uncertainties, affecting the real-time and reliability of communication. The limitations of this approach are particularly evident in application scenarios that require processing large amounts of data or high-frequency communications. Summary of the invention

[0004] The embodiment of the present application provides a Manchester coding communication verification system to solve the problems of coding efficiency and resource utilization when the ECU chip performs system verification. The system includes a core ECU and several edge ECUs, and the edge ECU is connected to the core ECU through the PSI5 bus; the edge ECU is equipped with an SPI controller, and the SPI controller is connected to the voltage conversion circuit of the peripheral output MOSI end and the current conversion circuit of the peripheral input MISO end through a hardware interface; the voltage conversion circuit and the current conversion circuit are connected to the PSI5 bus; The edge ECU responds to the encoding request, translates the acquired Manchester data to be translated into SPI byte data and caches it through the CPU core, and performs a matching check on the external input level signal and the Manchester data to be translated, and determines the fault source according to the matching result; The CPU core is connected to the DMA controller and sets the transmission task to the DMA controller according to the encoding request; the SPI controller is connected to the DMA controller and takes over the SPI byte data according to the encoding request, and sends and receives data according to the preset encoding frequency; In the sending phase, the cached SPI byte data is read through the DMA controller and sent to the SPI controller. In the receiving phase, the external level signal is input through the SPI controller and called and cached through the DMA controller.

[0005] Specifically, the operating frequency of the SPI controller is set to 8 times the Manchester encoding frequency, and during translation, each single-bit Manchester data to be translated is converted into 8-bit SPI byte data according to the order of the Manchester data.

[0006] Specifically, Manchester data includes bit idle, bit 0, and bit 1; the SPI byte data after translating bit idle, bit 0, and bit 1 are represented as 0x00, 0x0F, and 0xF0, respectively.

[0007] Specifically, the translated SPI bytes and the input data are stored in a buffer, which is divided into a first buffer area, a second buffer area and a third buffer area; the SPI data translated by the CPU core in response to the encoding request is alternately stored in the first buffer area and the second buffer area, and the buffer area read by the DMA controller and the buffer area executed by the CPU core at the same time are different; The SPI controller inputs an external level signal which is stored in the third buffer area through the DMA controller, and the CPU core reads the third buffer area and performs a matching check with the original Manchester data.

[0008] Specifically, two FIFO registers are provided between the DMA controller and the SPI controller. The first FIFO register stores the SPI byte data transferred outward by the DMA controller, and the second FIFO register stores the level data transferred inward by the SPI controller.

[0009] Specifically, the voltage conversion circuit includes an operational amplifier U1, a MOSI terminal is connected to one of the input terminals of U1, and an output terminal of U1 is connected to another input terminal of U1 through a resistor R2 for feedback; The output end of U1 is connected to the gate of the MOS tube through the resistor R1, the drain of the MOS tube is connected to the PSI5 bus, and the source of the MOS tube outputs a reference current.

[0010] Specifically, the current conversion circuit includes an amplifier circuit and a comparator. The amplifier circuit includes an operational amplifier U2 and a sampling resistor R4. The source of the MOS tube is grounded after passing through the sampling resistor R4. U2 is connected to both ends of the sampling resistor R4 for current sampling. A feedback resistor R5 is connected between one input terminal and an output terminal. The output end of U2 is connected to one input end of the comparator U3, and the other input end of U3 inputs the comparison current modulated by the edge ECU. The output of U3 is sent to the edge ECU through the MISO end.

[0011] Specifically, the CPU core obtains the periodic level signal for comparison, and when the received level signal matches the translated SPI byte data, it is determined that the verification is consistent; When the received level signal does not match the translated SPI byte data, the duty cycle of the level signal and the number of edge ECUs are obtained, the comparison current in the current conversion circuit is adjusted according to the duty cycle size and the number of sensors in the PSI5 bus, and the Manchester data is re-encoded for verification; when the verification result does not match, it is determined that the current edge ECU or peripheral bus circuit is faulty, and when the verification result matches, it is determined that the sensor on the PSI5 bus is faulty.

[0012] Specifically, when the level signal output by the current conversion circuit is higher than the comparison current, the converted Manchester code outputs a high level, and when the level signal is lower than the comparison current, the converted Manchester code outputs a low level; The reference current value output by the voltage conversion circuit is positively correlated with the number of sensors mounted on the PSI5 bus. The CPU core determines the reference current value and adjusts the comparison current according to the high and low level duty ratios of the inputs.

[0013] Specifically, the DMA controller is provided with at least two DMA channels, which are used for data output and data input respectively. When the DMA controller receives a corresponding transmission task, it determines the target DMA channel according to the usage status of the DMA channel, and reads data from the buffer or stores it in the buffer.

[0014] The beneficial effects brought by the technical solution provided by the embodiment of the present application include at least: This application integrates the verification coding process into the edge ECU. Instead of directly outputting the Manchester level signal, it first translates it into SPI byte data and combines DMA transmission technology to reduce CPU interrupt response, reduce CPU resource usage, and improve system flexibility and scalability. In order to further improve synchronization efficiency and accuracy, the encoding baud rate and the SPI transmission baud rate are kept consistent with the byte length. The Manchester encoding is converted bit by bit to achieve conversion of any bit length. Utilizing the SPI hardware full-duplex feature, the Manchester encoded current modulation signal sent to the bus by port MOSI is received back to port MISO through the current signal extraction circuit, and a closed-loop self-test function is implemented for the transmitted signal to ensure that the modulated signal sent to the bus is correct and reliable. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a structural diagram of a Manchester coding communication verification system provided in an embodiment of the present application; Figure 2 It is a structural schematic diagram of the edge ECU and peripheral circuits provided in an embodiment of the present application; Figure 3 is a schematic diagram of Manchester coded signal; Figure 4 The working timing diagram of the buffer is listed; Figure 5 It is a circuit diagram of the edge processor peripheral circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0016] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0017] Figure 1 It is a simplified schematic diagram of the Manchester coding communication verification system provided by the embodiment of the present application, which includes a core ECU and several edge ECUs, wherein at least one edge ECU manages several sensor devices, and the sensor devices are mounted on the PSI5 bus. The edge ECU is connected to the PSI5 bus through a peripheral circuit to realize data communication with the core ECU and other edge ECUs. For a certain edge ECU, the present application mainly uses the edge ECU to verify the circuit and sensor coding and evaluate the system stability.

[0018] Figure 2 This is a schematic diagram of the structure of the edge ECU and peripheral circuits provided in the embodiment of the present application. Figure 2Taking the SOC hardware architecture of the edge ECU as an example, an SPI controller is provided inside the edge ECU. The SPI controller is connected to the voltage conversion circuit of the peripheral output MOSI end and the current conversion circuit of the peripheral input MISO end through the hardware interface. The voltage conversion circuit and the current conversion circuit are connected to the PSI5 bus. The voltage conversion circuit converts the Manchester voltage signal into a current signal and sends it to the external PSI5 bus. The current conversion circuit connects the output of the voltage conversion circuit and samples the Manchester current on the external PSI5 bus, converts it into a voltage signal and sends it back to the edge ECU. Strictly speaking, the sampling of the external Manchester current includes the superposition of two parts, one is the current value of the direct encoding output, and the other is the current value on the PSI5 bus.

[0019] Request instructions such as coding verification are issued by the core ECU, or the ECU is triggered according to set conditions. When the edge ECU responds to the coding request, the obtained Manchester data to be translated will be translated into SPI byte data and cached through the CPU core (Core). In this process, the Manchester data to be translated can be sent from the core ECU to the edge ECU through the PSI5 bus, and then translated and encoded according to the rules after being sent to the Core. In the verification stage, the Core will match the external input level signal with the Manchester data to be translated, and determine the source of the fault based on the matching results.

[0020] Manchester data is different from the value of ordinary level signal. Ordinary level signal represents bit data through high and low levels, but interference factors can easily cause mutations, resulting in inaccurate data. Therefore, Manchester coding is more accurate.

[0021] Figure 3 This is a schematic diagram of the Manchester coding signal. Manchester coding is an automatic synchronization coding method, that is, the clock synchronization signal is hidden in the data waveform. In Manchester coding, there is a jump in the middle of each bit, and the jump in the middle of the bit serves as both a clock signal and a data signal. Each code element is represented by two level signals with different phases. Compared with the non-return-to-zero binary code represented by high and low levels, it is easier to extract the synchronization clock information in the case of continuous "0" or continuous "1". In addition, there is no DC component during Manchester code transmission, which can reduce the power consumption of the system and has strong anti-interference ability. When the transmitted signal is "1", Manchester coding jumps from high level to low level; if the transmitted information is "0", Manchester jumps from low level to high level. Keeping the low level without jump in a data cycle CS signal indicates idle.

[0022] The traditional solution can use an additional FPGA or corresponding chip for verification. For ECU verification, timers and GPIO ports are usually used to implement Manchester encoding, that is, the ECU directly outputs Manchester level signals. This form of encoding efficiency and CPU resource usage are serious. Because the CPU also needs to perform data interaction processing with the core ECU and other edge ECUs, such frequent interrupt responses will cause system delays. In order to avoid the use of level signals and frequent interrupts, this application instead uses internal conversion of the Manchester data to be translated into bit data (SPI byte data) and stores it in a buffer instead of direct output. The converted data is transported by the DMA controller, which can reduce the CPU interrupt response.

[0023] The CPU core is connected to the DMA controller. When executing the translation process, it can set the transmission task to the DMA controller according to the encoding request, so that the DMA controller is responsible for external data transmission and transfers the data from the buffer to the SPI controller. The SPI controller is connected to the DMA controller, which takes over the SPI byte data according to the encoding request and sends and receives data according to the preset encoding frequency.

[0024] In the sending phase, the edge ECU reads the SPI byte data in the buffer through the DMA controller and sends it to the SPI controller, which then sends the data to the voltage conversion circuit. In the receiving phase, the edge ECU inputs the level signal output by the external current conversion circuit through the SPI controller, and then calls and caches it through the DMA controller.

[0025] This solution aims to overcome the rate limitation of traditional chips, reduce system costs, reduce CPU resource usage, and simplify hardware design complexity. By cleverly utilizing the efficient data transmission capability of the SPI interface and the data transmission characteristics of DMA without CPU intervention, it can not only significantly improve the real-time processing efficiency of Manchester coding, but also greatly enhance the flexibility and scalability of the system while ensuring communication quality, opening up a new path for the application of Manchester coding technology in a wider range of fields.

[0026] The most important purpose of translating Manchester coded data in this application is to adapt to the data transfer of the DMA controller. Because the DMA controller takes over the CPU task execution is all byte data, in order to improve efficiency and be compatible with sensor data types, this application uses the most commonly used 8-bit encoding as an example.

[0027] Set the encoding order of the SPI controller to the MSB high to low mode, and configure the operating frequency of the SPI controller to 8 times the Manchester encoding baud rate to be sent, that is, if the Manchester encoding baud rate is 1Mbps, then configure the SPI hardware clock frequency to 8MHz. Then in the translation process, each single-bit Manchester data to be translated is converted into 8-bit SPI byte data in the order of Manchester data. This process transcoding is bit-by-bit, that is, Manchester data includes bit idle, bit 0 and bit 1, and the SPI byte data after translating bit idle, bit 0 and bit 1 are represented as 0x00, 0x0F and 0xF0 respectively. This process does not use 8-bit Manchester code to translate into 8-bit SPI byte data. Theoretically, it is feasible, but this parameter is determined by the specific sensor data type. When the sensor data is 8-bit or 16-bit data, it can strictly follow the 8-bit Manchester code to translate the 8-bit SPI byte data, but when the sensor data is not 8 bits (such as 12 bits), it is impossible to transfer the complete sensor data, so this application uses 8 bits as the basic translation. Implementing the encoding translation of any form of sensor, achieving verification while reducing CPU resource usage. The translation verification process can be simplified to the following steps: (1) First, the system completes initialization and configures the SPI operating frequency and DMA channel according to the Manchester encoding baud rate; (2) Then determine whether there is a Manchester code sequence that needs to be encoded and sent. If not, loop and wait. If yes, proceed to the next step. (3) The Manchester coded sequence bit data and bit length to be sent are sent to the translation encoding algorithm, and the translated SPI byte data is stored in the designated buffer area for DMA to cache and move; (4) Start DMA transfer and SPI data sending; (5) After sending, perform self-check on the bus signal to confirm the correctness of the bus signal; In order to ensure the synchronization of encoding transfer and verification matching, the present application also divides the buffer storing data into fine-grained divisions, specifically the first buffer area, the second buffer area and the third buffer area. The SPI data translated by the CPU core in response to the encoding request is alternately stored in the first buffer area and the second buffer area, and the buffer area read by the DMA controller at the same time is different from the buffer area executed by the CPU core. The SPI controller inputs an external level signal and stores it in the third buffer area through the DMA controller. The CPU core reads the third buffer area and performs a matching check with the original Manchester data.

[0028] Figure 4The working sequence diagram of the buffer is listed. After the Core performs the translation and encoding work, it will first store it in the first buffer area (step 1). When the first buffer area is full or reaches the set threshold, the SPI byte data will be further stored in the second buffer area (step 2). As a DMA controller, after receiving the instruction from the Core, it will take over the data handling task, that is, extract the SPI data from the first buffer area (step 3) and transfer it to the SPI controller. Assuming that the system input and output are all running normally, the DMA controller will also receive the level signal data stored inward (because it is operated by the DMA controller, it is stored in the form of bit data), and the data will be stored in the third buffer area (step 4). For the Core, a complete loop logic is completed, and the data in the third buffer area can be extracted to perform the matching check step (step 5). Assuming that the Manchester encoded data is translated in a loop, step 6 continues to be stored in the first buffer area, then after the DMA controller extracts the data from the first buffer area in the previous round, in step 7, it will first extract the SPI byte data from the second buffer area. In addition, the DMA controller is equipped with at least two DMA channels, one for data output and one for data input. When the DMA controller receives the corresponding transmission task, it determines the target DMA channel according to the usage status of the DMA channel, and reads data from the buffer or stores it in the buffer. In the above-mentioned process, it is always ensured that the DMA controller extraction and the Core core cache are not in the same buffer area, which can ensure that the data is extracted in strict order and avoid DMA channel busyness and data errors.

[0029] In some embodiments, two FIFO registers are further provided between the DMA controller and the SPI controller, wherein the first FIFO register stores the SPI byte data carried outward by the DMA controller, and the second FIFO register stores the level data carried inward by the SPI controller. The two FIFOs are used to transmit data outward and inward, respectively, and the bit depth of the FIFO can be determined according to the sensor data. For example, if the sensor data is 16 bits in length, the bit depth of the FIFO is set to 16 bits, so that the SPI controller can determine the complete sensor data according to the first-in-first-out principle, which is convenient for subsequent data analysis and processing and data decoding operations.

[0030] Figure 5It is a circuit diagram of the edge processor peripheral circuit provided by an embodiment of the present application, specifically including a voltage conversion circuit and a current conversion circuit. The voltage conversion circuit includes an operational amplifier U1, the MOSI terminal is connected to one of the input terminals of U1, and the output terminal of U1 is connected to the other input terminal of U1 through a resistor R2 feedback. At the output of U1, a cascade resistor R1 is connected to the gate of the MOS tube through the resistor R1, the drain of the MOS tube is connected to the PSI5 bus, and the source of the MOS tube outputs a reference current. In some embodiments, a resistor R3 can also be connected in parallel between the source of Q1 and the output terminal of U1 for feedback.

[0031] In the above structure, the operational amplifier U1 and the MOS tube Q1 realize the voltage-to-current conversion circuit. The operational amplifier feedback circuit can generate a fixed current when MOSI is at a high level. This current is the key to the self-loop and is connected to the input of the current conversion circuit.

[0032] The current conversion circuit includes an amplifier circuit and a comparator. The amplifier circuit includes an operational amplifier U2 and a sampling resistor R4. The source of the MOS tube is grounded after passing through the sampling resistor R4. U2 is connected to both ends of the sampling resistor R4 for current sampling. A feedback resistor R5 is connected between one input terminal and the output terminal. Of course, in some embodiments, a resistor R6 can be set between the ground terminal and the other input terminal of U2 to stabilize the circuit and proportionally amplify the current.

[0033] The output of U2 is connected to one input of the comparator U3, and the other input of U3 is input with the comparison current modulated by the edge ECU. Specifically, it can be realized by connecting the voltage divider resistors R7 and R8 and the voltage source modulation to generate a stable comparison current. The output of U3 is used as the comparison result (level signal) and is sent to the edge ECU through the MISO terminal. The MISO terminal sends a high level 1 or a low level 0, that is, a converted voltage signal. The comparison current modulation in this circuit can be achieved by voltage modulation output by the CPU.

[0034] In a possible implementation, when the level signal output by the current conversion circuit is higher than the comparison current, the converted Manchester code outputs a high level 1; when the output level signal is lower than the comparison current, the converted Manchester code outputs a low level 0. The comparison current is an ideal current value when the normal quantity and circuit structure are normal, and verification diagnosis can be performed when the circuit is abnormal or the PSI5 bus is abnormal.

[0035] The specific CPU core obtains the periodic level signal for comparison. When the received level signal matches the translated SPI byte data, it is determined that the verification is consistent.

[0036] When the received level signal does not match the translated SPI byte data, the fault source cannot be directly determined. It is necessary to further obtain the duty cycle of the level signal and the number of edge ECUs, adjust the comparison current in the current conversion circuit according to the duty cycle and the number of sensors in the PSI5 bus, and re-encode the Manchester data for verification. When the secondary verification result still does not match, it is determined that the current edge ECU or peripheral bus circuit is faulty, and when the secondary verification result matches, it is determined that the sensor on the PSI5 bus is faulty (i.e., the sensor is offline).

[0037] Because the reference current value output by the voltage conversion circuit also includes the current value of the PSI5 bus, which is positively correlated with the number of sensors mounted on the PSI5 bus. Therefore, the secondary adjustment and comparison current process is to adapt the PSI5 bus signal and determine whether any sensor is offline. The CPU core can determine the reference current value and adjust the comparison current according to the high and low level duty cycle of the input. Specifically, the voltage / current modulation comparison table can be generated in advance according to the number of sensors mounted on the vehicle bus and the circuit structure in the production stage, and the comparison voltage / current values ​​output by the ECU under different numbers of sensors mounted can be listed. The comparison table can be stored in the ECU, and the table can be looked up and modulated according to the difference in duty cycle during the verification stage to further diagnose and analyze possible results.

[0038] In summary, the present application integrates the verification coding process into the edge ECU, and does not directly output the Manchester level signal, but first translates it into SPI byte data, and combines DMA transmission technology to reduce CPU interrupt response, reduce CPU resource usage, and improve system flexibility and scalability. In order to further improve the synchronization efficiency and accuracy, the encoding baud rate and the SPI transmission baud rate are kept consistent with the byte length. The Manchester encoding is converted bit by bit to achieve the conversion of any bit length. Utilizing the SPI hardware full-duplex characteristics, the Manchester encoded current modulation signal sent from port MOSI to the bus is received back to port MISO through the current signal extraction circuit, and a closed-loop self-test function is implemented for the transmitted signal to ensure that the modulated signal sent to the bus is correct and reliable.

[0039] This specific embodiment is merely an explanation of the present invention and is not a limitation of the present invention. After reading this specification, those skilled in the art may make non-creative modifications to the present embodiment as needed. However, as long as they are within the scope of the claims of the present invention, they are protected by the patent law.

Claims

1. A Manchester coding communication verification system, comprising a core ECU and a plurality of edge ECUs, wherein the edge ECUs are connected to the core ECU via a PSI5 bus; characterized in that: The edge ECU is equipped with an SPI controller, which is connected to the voltage conversion circuit of the peripheral output MOSI end and the current conversion circuit of the peripheral input MISO end through a hardware interface; the voltage conversion circuit and the current conversion circuit are connected to the PSI5 bus, the voltage conversion circuit converts the Manchester voltage signal into a current signal and sends it to the external PSI5 bus, and the current conversion circuit connects the voltage conversion circuit output and samples the Manchester current on the external PSI5 bus, converts it into a voltage signal and sends it back to the edge ECU; The edge ECU responds to the encoding request, translates the acquired Manchester data to be translated into SPI byte data and caches it through the CPU core, and performs a matching check on the external input level signal and the Manchester data to be translated, and determines the fault source according to the matching result; The CPU core is connected to the DMA controller and sets the transmission task to the DMA controller according to the encoding request; the SPI controller is connected to the DMA controller and takes over the SPI byte data according to the encoding request, and sends and receives data according to the preset encoding frequency; In the sending phase, the cached SPI byte data is read through the DMA controller and sent to the SPI controller. In the receiving phase, the external level signal is input through the SPI controller and called and cached through the DMA controller.

2. The Manchester coding communication verification system according to claim 1, characterized in that: The operating frequency of the SPI controller is set to 8 times the Manchester encoding frequency. During translation, each single-bit Manchester data to be translated is converted into 8-bit SPI byte data according to the order of the Manchester data.

3. The Manchester coding communication verification system according to claim 2, characterized in that: Manchester data includes bit idle, bit 0 and bit 1; the SPI byte data after translating bit idle, bit 0 and bit 1 are expressed as 0x00, 0x0F and 0xF0 respectively.

4. The Manchester coding communication verification system according to claim 1, characterized in that: The translated SPI bytes and the input data are stored in a buffer, which is divided into a first buffer area, a second buffer area and a third buffer area; the SPI data translated by the CPU core in response to the encoding request is alternately stored in the first buffer area and the second buffer area, and the buffer area read by the DMA controller and the buffer area executed by the CPU core at the same time are different; The SPI controller inputs an external level signal which is stored in the third buffer area through the DMA controller, and the CPU core reads the third buffer area and performs a matching check with the original Manchester data.

5. The Manchester coding communication verification system according to claim 1, characterized in that: Two FIFO registers are also arranged between the DMA controller and the SPI controller. The first FIFO register stores the SPI byte data transferred outward by the DMA controller, and the second FIFO register stores the level data transferred inward by the SPI controller.

6. The Manchester coding communication verification system according to claim 1, characterized in that: The voltage conversion circuit comprises an operational amplifier U1, a MOSI terminal is connected to one of the input terminals of U1, and an output terminal of U1 is connected to another input terminal of U1 through a resistor R2 for feedback; The output end of U1 is connected to the gate of the MOS tube through the resistor R1, the drain of the MOS tube is connected to the PSI5 bus, and the source of the MOS tube outputs a reference current.

7. The Manchester coding communication verification system according to claim 6, characterized in that: The current conversion circuit includes an amplifier circuit and a comparator. The amplifier circuit includes an operational amplifier U2 and a sampling resistor R4. The source of the MOS tube is grounded after passing through the sampling resistor R4. U2 is connected to both ends of the sampling resistor R4 for current sampling. A feedback resistor R5 is connected between one input terminal and an output terminal. The output end of U2 is connected to one input end of the comparator U3, and the other input end of U3 inputs the comparison current modulated by the edge ECU. The output of U3 is sent to the edge ECU through the MISO end.

8. The Manchester coding communication verification system according to any one of claims 1 to 7, characterized in that: The CPU core obtains the periodic level signal for comparison. When the received level signal matches the translated SPI byte data, the verification is confirmed to be consistent; When the received level signal does not match the translated SPI byte data, the duty cycle of the level signal and the number of edge ECUs are obtained, the comparison current in the current conversion circuit is adjusted according to the duty cycle size and the number of sensors in the PSI5 bus, and the Manchester data is re-encoded for verification; When the verification results do not match, it is determined that the current edge ECU or peripheral bus circuit is faulty, and when the verification results match, it is determined that the sensor on the PSI5 bus is faulty.

9. The Manchester coding communication verification system according to claim 8, characterized in that: When the level signal output by the current conversion circuit is higher than the comparison current, the converted Manchester code outputs a high level, and when the level signal is lower than the comparison current, the converted Manchester code outputs a low level; The reference current value output by the voltage conversion circuit is positively correlated with the number of sensors mounted on the PSI5 bus. The CPU core determines the reference current value and adjusts the comparison current according to the high and low level duty ratios of the inputs.

10. The Manchester coding communication verification system according to claim 8, characterized in that: The DMA controller is provided with at least two DMA channels, which are used for data output and data input respectively. When the DMA controller receives a corresponding transmission task, it determines the target DMA channel according to the usage status of the DMA channel, and reads data from the buffer or stores it in the buffer.

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