Display panel, manufacturing method of display panel, and display device

Abstract

This application provides a display panel, a method for manufacturing the display panel, and a display device. The display panel includes a substrate, a buffer layer, an active layer, a gate insulating layer, and a gate layer. By having at least one of the buffer layer and the gate insulating layer have a stacked structure composed of two layers of the same material, the hydrogen content in the film layer near the active layer in the stacked structure is lower than that in the film layer far from the active layer. This can improve the uniformity of the thin-film transistors in the display area. By setting the active layer as a stacked structure formed by a first sub-active layer and a second sub-active layer, and making the mobility of the first sub-active layer greater than that of the second sub-active layer, the subthreshold swing of the thin-film transistors can be increased without affecting the initial threshold voltage of the thin-film transistors. This can improve the uniformity of the thin-film transistors in the display area while increasing the limit of the thin-film transistors in the non-display area.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel, a method for manufacturing the display panel, and a display device. Background Technology

[0002] Compared to the current mainstream display panels with amorphous silicon as the active layer, display panels with oxide semiconductor as the active layer have technical advantages such as high electron mobility, high switching current ratio, feasibility of flexible display, good uniformity and low production cost, which have been widely favored by the industry.

[0003] The pixel driving circuits in the display area and the gate driving circuits in the non-display area have different requirements for the characteristics of thin-film transistor (TFT) devices. The display area requires TFTs with high uniformity, while the non-display area requires TFTs with greater flexibility. Due to current technological limitations, the flexibility of TFTs in the non-display area is relatively low and cannot meet the requirements.

[0004] Therefore, it is necessary to provide a display panel, a method for manufacturing the display panel, and a display device to improve this deficiency. Summary of the Invention

[0005] The embodiments of this application provide a display panel, a method for manufacturing the display panel, and a display device, which can improve the uniformity of the thin-film transistor performance in the display area.

[0006] To achieve the above objectives, according to a first aspect of this application, a display panel is provided, comprising:

[0007] Substrate;

[0008] A buffer layer is disposed on one side of the substrate;

[0009] An active layer is disposed on the side of the buffer layer away from the substrate, and the material of the active layer includes an oxide semiconductor material;

[0010] A gate insulating layer is disposed on the side of the active layer away from the buffer layer;

[0011] A gate layer is disposed on the side of the gate insulating layer away from the active layer;

[0012] Wherein, at least one of the buffer layer and the gate insulating layer has a stacked structure composed of two layers of the same material, wherein the hydrogen content in the film layer near the active layer in the stacked structure is less than the hydrogen content in the film layer away from the active layer; the active layer includes a first sub-active layer and a second sub-active layer, the second sub-active layer is disposed on the side of the first sub-active layer near the gate layer, and the mobility of the first sub-active layer is greater than the mobility of the second sub-active layer.

[0013] Optionally, the thickness of the first sub-active layer is greater than the thickness of the second sub-active layer.

[0014] Optionally, the thickness of the first sub-active layer is greater than or equal to 200 angstroms and less than or equal to 1000 angstroms, and the thickness of the second sub-active layer is greater than or equal to 50 angstroms and less than or equal to 500 angstroms.

[0015] Optionally, the buffer layer includes:

[0016] A first sub-buffer layer is disposed on one side of the substrate, and the material of the first sub-buffer layer includes silicon nitride;

[0017] A second sub-buffer layer is disposed on the side of the first sub-buffer layer away from the substrate, and the material of the second sub-buffer layer includes silicon oxide;

[0018] A third sub-buffer layer is disposed on the surface of the second sub-buffer layer away from the first sub-buffer layer, and the material of the third sub-buffer layer includes silicon oxide;

[0019] The hydrogen content in the third sub-buffer layer is less than the hydrogen content in the second sub-buffer layer.

[0020] Optionally, the thickness of the second sub-buffer layer is greater than the thickness of the third sub-buffer layer.

[0021] Optionally, the thickness of the second sub-buffer layer is greater than or equal to 2000 angstroms and less than or equal to 4000 angstroms, and the thickness of the third sub-buffer layer is greater than or equal to 200 angstroms and less than or equal to 1000 angstroms.

[0022] Optionally, the buffer layer further includes a fourth sub-buffer layer, which is disposed between the first sub-buffer layer and the second sub-buffer layer;

[0023] The fourth sub-buffer layer is made of silicon nitride, and the hydrogen content in the fourth sub-buffer layer is less than that in the first sub-buffer layer.

[0024] Optionally, the thickness of the fourth sub-buffer layer is less than the thickness of the first sub-buffer layer.

[0025] Optionally, the gate insulating layer comprises:

[0026] A first sub-gate insulating layer is disposed on the side of the active layer away from the substrate;

[0027] The second sub-gate insulating layer is disposed on the surface of the first sub-gate insulating layer away from the active layer;

[0028] The hydrogen content in the first sub-gate insulating layer is less than the hydrogen content in the second sub-gate insulating layer.

[0029] Optionally, the thickness of the first sub-gate insulating layer is less than the thickness of the second sub-gate insulating layer.

[0030] Optionally, the thickness of the first sub-gate insulating layer is greater than or equal to 200 angstroms and less than or equal to 600 angstroms, and the thickness of the second sub-gate insulating layer is greater than or equal to 1000 angstroms and less than or equal to 2000 angstroms.

[0031] Optionally, the display panel further includes:

[0032] An interlayer dielectric layer is disposed on the side of the gate layer away from the gate insulating layer;

[0033] The source and drain layers are disposed on the side of the interlayer dielectric layer away from the gate layer;

[0034] A first passivation layer is disposed on the side of the source / drain layer away from the interlayer dielectric layer;

[0035] An organic insulating layer is disposed on the side of the first passivation layer away from the source and drain layers;

[0036] The second passivation layer is disposed on the side of the organic insulating layer away from the first passivation layer;

[0037] The second passivation layer includes a first sub-passivation layer and a second sub-passivation layer. The second sub-passivation layer is disposed on the surface of the first sub-passivation layer away from the organic insulating layer. The hydrogen content in the first sub-passivation layer is less than the hydrogen content in the second sub-passivation layer.

[0038] Optionally, the thickness of the first sub-passivation layer is less than the thickness of the second sub-passivation layer.

[0039] According to a second aspect of this application, a method for manufacturing a display panel is provided, the method comprising the following steps:

[0040] A buffer layer is formed on one side of the substrate;

[0041] A first sub-active layer is formed on the side of the buffer layer away from the substrate;

[0042] A second sub-active layer is formed on the first sub-active layer to obtain an active layer;

[0043] A gate insulating layer is formed on the side of the active layer away from the buffer layer;

[0044] A gate layer is formed on the side of the gate insulating layer away from the active layer;

[0045] Wherein, at least one of the buffer layer and the gate insulating layer has a stacked structure composed of two layers of the same material, wherein the film layer near the active layer in the stacked structure has a slower film formation rate than the film layer far from the active layer, the film layer near the active layer in the stacked structure has a lower hydrogen content than the film layer far from the active layer, and the mobility of the first sub-active layer is greater than the mobility of the second sub-active layer.

[0046] According to a third aspect of this application, a display device is provided, including a display panel as described above.

[0047] In the display panel of this application embodiment, by making at least one of the buffer layer and the gate insulating layer have a stacked structure made of two layers of the same material, the film layer near the active layer in the stacked structure has a lower hydrogen content than the film layer far from the active layer. In this way, the film layer with lower hydrogen content can be used to block hydrogen diffusion to the active layer during the manufacturing process, thereby improving the uniformity of the thin film transistor performance in the display area. Furthermore, by setting the active layer to a stacked structure made of a first sub-active layer and a second sub-active layer, the mobility of the first sub-active layer is greater than that of the second sub-active layer. In this way, the subthreshold swing of the thin film transistor can be increased without affecting the initial threshold voltage of the thin film transistor, thereby increasing the limit of the thin film transistor.

[0048] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0049] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0050] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0051] Figure 1 A schematic diagram of the structure of a first type of display panel provided for an embodiment of this application;

[0052] Figure 2 A schematic diagram of the structure of a second display panel provided for an embodiment of this application;

[0053] Figure 3 A schematic diagram of the structure of a third type of display panel provided for an embodiment of this application;

[0054] Figure 4 A schematic diagram of the structure of a fourth display panel provided for an embodiment of this application;

[0055] Figure 5 A schematic diagram of the structure of a fifth type of display panel provided for embodiments of this application;

[0056] Figure 6 A flowchart illustrating a method for manufacturing a display panel according to an embodiment of this application;

[0057] Figure 7 This is a schematic diagram of the structure of a display device provided in an embodiment of this application.

[0058] Explanation of reference numerals in the attached figures:

[0059] 10. Substrate; 11. Buffer layer; 111. First sub-buffer layer; 112. Second sub-buffer layer; 113. Third sub-buffer layer; 114. Fourth sub-buffer layer; 12. Active layer; 121. First sub-active layer; 122. Second sub-active layer; 13. Gate insulating layer; 131. First sub-gate insulating layer; 132. Second sub-gate insulating layer; 14. Gate layer; 15. Light-shielding layer; 16. Interlayer dielectric layer; 17. Source / drain layer; 18. First passivation layer; 19. Organic insulating layer; 20. First electrode layer; 21. Second passivation layer; 211. First sub-passivation layer; 212. Second sub-passivation layer; 22. Second electrode layer;

[0060] 100, Display panel; 200, Housing; 1000, Display device. Detailed Implementation

[0061] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0062] Embodiments of this application provide a display panel, which includes a substrate, a buffer layer, an active layer, a gate insulating layer, and a gate layer. The buffer layer is disposed on one side of the substrate, and the active layer is disposed on the side of the buffer layer away from the substrate. The active layer is made of an oxide semiconductor material. The gate insulating layer is disposed on the side of the active layer away from the buffer layer, and the gate layer is disposed on the side of the gate insulating layer away from the active layer. At least one of the buffer layer and the gate insulating layer has a stacked structure composed of two layers of the same material. In the stacked structure, the film layer closer to the active layer has a lower hydrogen content than the film layer farther from the active layer. The active layer includes a first sub-active layer and a second sub-active layer. The second sub-active layer is disposed on the side of the first sub-active layer away from the substrate, and the mobility of the first sub-active layer is greater than the mobility of the second sub-active layer.

[0063] In the display panel of this application embodiment, by having at least one of the buffer layer and the gate insulating layer have a stacked structure composed of two layers of the same material, the film layer near the active layer in the stacked structure has a lower hydrogen content than the film layer far from the active layer. In this way, the film layer with lower hydrogen content can be used to block hydrogen diffusion to the active layer during the manufacturing process, thereby improving the uniformity of the thin-film transistors in the display area. By setting the active layer as a stacked structure formed by a first sub-active layer and a second sub-active layer, and making the mobility of the first sub-active layer greater than the mobility of the second sub-active layer, the subthreshold swing of the thin-film transistor can be increased without affecting the initial threshold voltage of the thin-film transistor. This can improve the uniformity of the thin-film transistors in the display area while increasing the limit of the thin-film transistors in the non-display area.

[0064] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of a first display panel provided in an embodiment of this application. The display panel includes a substrate 10, a buffer layer 11, an active layer 12, a gate insulating layer 13, and a gate layer 14. The buffer layer 11 is disposed on one side of the substrate 10, and the active layer 12 is disposed on the side of the buffer layer 11 away from the substrate 10. The material of the active layer 12 includes an oxide semiconductor material. The gate insulating layer 13 is disposed on the side of the active layer 12 away from the buffer layer 11, and the gate layer 14 is disposed on the side of the gate insulating layer 13 away from the active layer 12. At least one of the buffer layer 11 and the gate insulating layer 13 has a stacked structure formed by stacking two layers of the same material. In the stacked structure, the film layer closer to the active layer 12 has a lower hydrogen content than the film layer farther from the active layer 12. The active layer 12 includes a first sub-active layer 121 and a second sub-active layer 122. The second sub-active layer 122 is disposed on the side of the first sub-active layer 121 close to the gate layer 14. The mobility of the first sub-active layer 121 is greater than the mobility of the second sub-active layer 122.

[0065] In the embodiments of this application, the display panel includes a display area and a non-display area disposed around the display area. The display area is provided with a pixel driving circuit, and the non-display area is provided with a gate driving circuit. Both the pixel driving circuit and the gate driving circuit include thin film transistors T. The active layer 12 has a plurality of active portions, which participate in the formation of the thin film transistors T.

[0066] In embodiments of this application, by having at least one of the buffer layer 11 and the gate insulating layer 13 have a stacked structure composed of two layers of the same material, the film layer near the active layer 12 in the stacked structure has a lower hydrogen content than the film layer far from the active layer 12. This allows the film layer with lower hydrogen content to block hydrogen diffusion from the manufacturing process to the active layer 12, thereby improving the uniformity of the thin-film transistors in the display area. By setting the active layer 12 as a stacked structure formed by a first sub-active layer 121 and a second sub-active layer 122, and making the mobility of the first sub-active layer 121 greater than the mobility of the second sub-active layer 122, the subthreshold swing of the thin-film transistor T can be increased without affecting the initial threshold voltage of the thin-film transistor T. This improves the uniformity of the thin-film transistor performance in the display area while increasing the limit of the thin-film transistors in the non-display area.

[0067] In some embodiments, the mobility of the first sub-active layer 121 is greater than or equal to 20m. 2 / Vs and less than or equal to 50m 2 / Vs; The mobility of the second sub-active layer 122 is less than or equal to 10m 2 / Vs.

[0068] In some embodiments, please refer to Figure 1 The substrate 10 is a rigid substrate, and the material of the substrate 10 is glass. In some other embodiments, the substrate 10 may also be a flexible substrate, and the material of the flexible substrate may be a transparent organic material such as polyimide.

[0069] In some embodiments, please refer to Figure 1 A first sub-active layer 121 is disposed on the surface of the buffer layer 11 away from the substrate 10, and a second sub-active layer 122 is disposed on the surface of the first sub-active layer 121 away from the buffer layer 11. The thickness of the first sub-active layer 121 is greater than the thickness of the second sub-active layer 122. The first sub-active layer 121 is the main part of the active layer 12, which ensures that the active layer 12 has a high mobility. By forming a thinner second sub-active layer 122 with a lower mobility on the first sub-active layer 121, the subthreshold swing of the thin-film transistor can be increased without affecting the initial threshold voltage of the transistor. This can improve the uniformity of the thin-film transistors in the display area while increasing the limit of the thin-film transistors in the non-display area.

[0070] In some embodiments, the thickness of the first sub-active layer 121 is greater than or equal to 200 angstroms and less than or equal to 1000 angstroms, and the thickness of the second sub-active layer is greater than or equal to 50 angstroms and less than or equal to 500 angstroms. For example, the thickness of the first sub-active layer 121 is 200 angstroms, 400 angstroms, 600 angstroms, 800 angstroms, or 1000 angstroms, etc.; the thickness of the second sub-active layer 122 is 50 angstroms, 80 angstroms, 100 angstroms, 200 angstroms, 300 angstroms, 400 angstroms, or 500 angstroms, etc. As long as it is ensured that the thickness of the first sub-active layer 121 is greater than the thickness of the second sub-active layer 122, the subthreshold swing of the thin-film transistor can be increased without affecting the initial threshold voltage of the transistor. This allows for the improvement of the uniformity of the thin-film transistors in the display area while increasing the limit of the thin-film transistors in the non-display area.

[0071] In some embodiments, the materials of the first sub-active layer 121 and the second sub-active layer 122 both include oxide semiconductor materials, which may be, but are not limited to, metal oxide semiconductor materials such as indium gallium zinc oxide.

[0072] In some embodiments, the first sub-active layer 121 and the second sub-active layer 122 are made of the same material, and the first sub-active layer 121 and the second sub-active layer 122 can be formed sequentially in the same process using a single photomask.

[0073] In some embodiments, please refer to Figure 1 The buffer layer 11 includes a first sub-buffer layer 111, a second sub-buffer layer 112, and a third sub-buffer layer 113. The first sub-buffer layer 111 is disposed on one side of the substrate 10, and the material of the first sub-buffer layer 111 includes silicon nitride. The second sub-buffer layer 112 is disposed on the side of the first sub-buffer layer 111 away from the substrate 10, and the material of the second sub-buffer layer 112 includes silicon oxide. The third sub-buffer layer 113 is disposed on the surface of the second sub-buffer layer 112 away from the first sub-buffer layer 111, and the material of the third sub-buffer layer 113 includes silicon oxide.

[0074] It should be noted that by increasing the deposition rate of the second sub-buffer layer 112, the deposition time of the buffer layer 11 is reduced, thus improving process efficiency. Conversely, by decreasing the deposition rate of the third sub-buffer layer 113, the hydrogen content in the third sub-buffer layer 113 can be made lower than that in the second sub-buffer layer 112, resulting in better film quality and improved contact between the third sub-buffer layer 113 and the active layer 12. During fabrication, the slower deposition rate and lower hydrogen content of the third sub-buffer layer 113 can prevent hydrogen from the second sub-buffer layer 112 and the first sub-buffer layer 111 from diffusing into the active layer 12, thereby improving the uniformity of the thin-film transistor.

[0075] It should be noted that the hydrogen content in this application refers to the atomic percentage of hydrogen in the material of the membrane layer. Taking the second sub-buffer layer 112 and the third sub-buffer layer 113 as examples, the fact that the hydrogen content in the third sub-buffer layer 113 is less than that in the second sub-buffer layer 112 means that the atomic percentage of hydrogen in the third sub-buffer layer 113 is less than that in the second sub-buffer layer 112. The atomic percentage of hydrogen in the second sub-buffer layer 112 and the third sub-buffer layer 113 can be detected by detection equipment such as a mass spectrometer.

[0076] In some embodiments, the thickness of the second sub-buffer layer 112 is greater than the thickness of the third sub-buffer layer 113. It should be noted that, since the second sub-buffer layer 112 has a faster film formation rate, increasing the thickness of the second sub-buffer layer 112 can further reduce the film formation time of the buffer layer 11, thereby improving process efficiency.

[0077] In some embodiments, the thickness of the second sub-buffer layer 112 is greater than or equal to 2000 angstroms and less than or equal to 4000 angstroms, and the thickness of the third sub-buffer layer 113 is greater than or equal to 200 angstroms and less than or equal to 1000 angstroms. For example, the thickness of the second sub-buffer layer 112 is 2000 angstroms, 2500 angstroms, 3000 angstroms, 3500 angstroms, or 4000 angstroms, and the thickness of the third sub-buffer layer 113 is 200 angstroms, 400 angstroms, 600 angstroms, 800 angstroms, or 1000 angstroms, etc. This ensures that while reducing the film deposition time of the buffer layer 11 and improving process efficiency, the film deposition quality of the buffer layer 11 is improved, and the uniformity of the thin-film transistor is enhanced.

[0078] In some embodiments, please refer to Figure 2 , Figure 2 This is a schematic diagram of the structure of a second type of display panel provided in an embodiment of this application. Its structure is similar to... Figure 1 The structures of the display panels shown are roughly the same, except that the buffer layer 11 also includes a fourth sub-buffer layer 114, which is disposed between the first sub-buffer layer 111 and the second sub-buffer layer 112. The hydrogen content in the fourth sub-buffer layer 114 is less than the hydrogen content in the first sub-buffer layer 111.

[0079] In this embodiment, a fourth sub-buffer layer 114 is added between the first sub-buffer layer 111 and the second sub-buffer layer 112. The film formation rate of the fourth sub-buffer layer 114 is lower than that of the first sub-buffer layer 111, so that the fourth sub-buffer layer 114 has a lower hydrogen content. In this way, the fourth sub-buffer layer 114 can be used to block the diffusion of hydrogen in the first sub-buffer layer 111 to the active layer 12, thereby further improving the uniformity of the thin film transistor.

[0080] In some embodiments, the thickness of the fourth sub-buffer layer 114 is less than the thickness of the first sub-buffer layer 111. Since the film formation rate of the fourth sub-buffer layer 114 is slower than that of the first sub-buffer layer 111, by making the thickness of the fourth sub-buffer layer 114 less than the thickness of the first sub-buffer layer 111, both the process efficiency and film formation quality of the buffer layer 11 can be balanced.

[0081] In some embodiments, please refer to Figure 1 The gate insulating layer 13 is disposed on the surface of the active layer 12 away from the buffer layer 11, and the gate insulating layer 13 is a single-layer structure formed of silicon oxide material.

[0082] In some embodiments, please refer to Figure 3 , Figure 3 This is a schematic diagram of the structure of a third type of display panel provided in an embodiment of this application. Its structure is similar to... Figure 1 The structures of the display panels shown are largely the same, with the difference being that the gate insulating layer 13 includes a first sub-gate insulating layer 131 and a second sub-gate insulating layer 132. The first sub-gate insulating layer 131 is disposed on the side of the active layer 12 away from the substrate 10, and the second sub-gate insulating layer 132 is disposed on the surface of the first sub-gate insulating layer 131 away from the active layer 12. Both the first sub-gate insulating layer 131 and the second sub-gate insulating layer 132 are made of silicon oxide. The hydrogen content in the first sub-gate insulating layer 131 is lower than that in the second sub-gate insulating layer 132. This allows the first sub-gate insulating layer 131, with its lower hydrogen content, to prevent hydrogen from the second sub-gate insulating layer 132 from diffusing into the active layer 12, thereby improving the uniformity of the thin-film transistor.

[0083] In some embodiments, please refer to Figure 3 The thickness of the first sub-gate insulating layer 131 is less than the thickness of the second sub-gate insulating layer 132. It should be noted that the deposition rate of the first sub-gate insulating layer 131 is less than the deposition rate of the second sub-gate insulating layer 132. This allows the hydrogen content in the first sub-gate insulating layer 131 to be less than the hydrogen content in the second sub-gate insulating layer 132. By making the thickness of the first sub-gate insulating layer 131 less than the thickness of the second sub-gate insulating layer 132, the process efficiency of the gate insulating layer 13 is improved.

[0084] In some embodiments, the thickness of the first sub-gate insulating layer 131 is greater than or equal to 200 angstroms and less than or equal to 600 angstroms, and the thickness of the second sub-gate insulating layer 132 is greater than or equal to 1000 angstroms and less than or equal to 2000 angstroms. For example, the thickness of the first sub-gate insulating layer 131 is 200 angstroms, 300 angstroms, 500 angstroms, or 600 angstroms, and the thickness of the second sub-gate insulating layer 132 is 1000 angstroms, 1300 angstroms, 1500 angstroms, 1700 angstroms, or 2000 angstroms.

[0085] In some embodiments, please refer to Figure 4 , Figure 4 This is a schematic diagram of the structure of a fourth display panel provided in an embodiment of this application, and its structure is similar to... Figure 3 The structures shown are roughly the same, in Figure 4 In the illustrated embodiment, the gate insulating layer 13 includes a first sub-gate insulating layer 131 and a second sub-gate insulating layer 132, and the buffer layer 11 includes a first sub-buffer layer 111, a second sub-buffer layer 112 and a third sub-buffer layer 113. The buffer layer 11 may also include a fourth sub-buffer layer. In this way, the subthreshold swing of the thin-film transistor can be increased without affecting the initial threshold voltage of the thin-film transistor. This can improve the uniformity of the thin-film transistor in the display area while increasing the limit of the thin-film transistor in the non-display area.

[0086] In some embodiments, please refer to Figures 1 to 4 The display panel also includes a light-shielding layer 15, an interlayer dielectric layer 16, a source-drain layer 17, a first passivation layer 18, an organic insulating layer 19, and a second passivation layer 21. The light-shielding layer 15 is disposed between the substrate 10 and the buffer layer 11. The interlayer dielectric layer 16 is disposed on the side of the gate layer 14 away from the gate insulating layer 13. The source-drain layer 17 is disposed on the side of the interlayer dielectric layer 16 away from the gate layer 14. The first passivation layer 18 is disposed on the side of the source-drain layer 17 away from the interlayer dielectric layer 16. The organic insulating layer 19 is disposed on the side of the first passivation layer 18 away from the source-drain layer 17. The second passivation layer 21 is disposed on the side of the organic insulating layer 19 away from the first passivation layer 18.

[0087] In some implementations, please refer to Figures 1 to 4 The interlayer dielectric layer 16 and the first passivation layer 18 are both monolayer structures formed of silicon oxide material, and the second passivation layer 21 is a monolayer structure formed of silicon nitride material.

[0088] In some embodiments, the display panel further includes a first electrode layer 20 and a second electrode layer 22. The first electrode layer 20 is disposed on the surface of the organic insulating layer 19 away from the first passivation layer 18, and the second electrode layer 22 is disposed on the side of the second passivation layer 21 away from the organic insulating layer 19. The first electrode layer 20 is one of a common electrode and a pixel electrode, and the second electrode layer 22 is the other of a common electrode and a pixel electrode.

[0089] In some embodiments, please refer to Figure 5 , Figure 5 This is a schematic diagram of the structure of a fifth type of display panel provided in an embodiment of this application. Its structure is similar to... Figure 1The structures of the display panels shown are roughly the same, except that the second passivation layer 21 includes a first sub-passivation layer 211 and a second sub-passivation layer 212. The first sub-passivation layer 211 is disposed on the surface of the organic insulating layer 19 and the first electrode layer 20 away from the first passivation layer 18, and the second sub-passivation layer 212 is disposed on the surface of the first sub-passivation layer 211 away from the organic insulating layer 19. The hydrogen content in the first sub-passivation layer 211 is less than the hydrogen content in the second sub-passivation layer 212.

[0090] In this embodiment, by making the hydrogen content in the first sub-passivation layer 211 less than the hydrogen content in the second sub-passivation layer 212, the first sub-passivation layer 211 with a lower hydrogen content can be used to block the diffusion of hydrogen from the second sub-passivation layer 212 to the active layer 12, thereby improving the uniformity of the thin film transistor.

[0091] In some embodiments, please refer to Figure 5 The thickness of the first sub-passivation layer 211 is less than the thickness of the second sub-passivation layer 212. By making the film formation rate of the first sub-passivation layer 211 less than that of the second sub-passivation layer 212, the hydrogen content in the first sub-passivation layer 211 is less than that in the second sub-passivation layer 212. By making the thickness of the first sub-passivation layer 211 less than that of the second sub-passivation layer 212, the film formation time of the second passivation layer 21 can be reduced, the process efficiency of the second passivation layer 21 can be improved, and the mass production of the second passivation layer 21 can be guaranteed.

[0092] exist Figure 5 In the illustrated embodiment, the buffer layer 11 can be a three-layer stacked structure formed by a first sub-buffer layer 111, a second sub-buffer layer 112, and a third sub-buffer layer 113, or a four-layer stacked structure formed by a first sub-buffer layer 111, a fourth sub-buffer layer 114, a second sub-buffer layer 112, and a third sub-buffer layer 113. The gate insulating layer 13 can be a single-layer structure formed by silicon oxide material, or it can be a stacked structure formed by stacking a first sub-gate insulating layer 131 and a second sub-gate insulating layer 132 as in the above embodiment.

[0093] Based on the display panel provided in the above embodiments of this application, embodiments of this application also provide a method for manufacturing the display panel. Please refer to [link to relevant documentation]. Figures 1 to 6 , Figure 6 A flowchart illustrating a method for manufacturing a display panel according to an embodiment of this application. The method includes the following steps:

[0094] Step S1: Form a buffer layer 11 on one side of the substrate 10;

[0095] Step S2: A first sub-active layer 121 is formed on the side of the buffer layer 11 away from the substrate 10, and a second sub-active layer 122 is formed on the first sub-active layer 121 to obtain the active layer 12.

[0096] Step S3: Form a gate insulating layer 13 on the side of the active layer 12 away from the buffer layer 11;

[0097] Step S4: Form a gate layer 14 on the side of the gate insulating layer 13 away from the active layer 12.

[0098] In the embodiments of this application, at least one of the buffer layer 11 and the gate insulating layer 13 has a stacked structure formed by stacking two layers of the same material. The film layer near the active layer 12 in the stacked structure has a slower film formation rate than the film layer far from the active layer 12. The film layer near the active layer 12 in the stacked structure has a lower hydrogen content than the film layer far from the active layer 12. The mobility of the first sub-active layer 121 is greater than the mobility of the second sub-active layer 122.

[0099] In some embodiments, step S1 includes: sequentially depositing a first sub-buffer layer 111 on a substrate 10, forming a second sub-buffer layer 112 on the first sub-buffer layer 111 at a first film formation rate, and forming a third sub-buffer layer 113 on the second sub-buffer layer 112 at a second film formation rate to obtain a buffer layer 11.

[0100] In this embodiment, the first film formation rate is greater than the second film formation rate, so that the hydrogen content in the third sub-buffer layer 113 is less than the hydrogen content in the second sub-buffer layer 112. The third sub-buffer layer 113 with a lower hydrogen content can prevent hydrogen in the second sub-buffer layer 112 from diffusing into the subsequently formed active layer 12, thereby improving the uniformity of the thin film transistor.

[0101] In some embodiments, after the buffer layer 11 is formed, a baking process can be performed on the buffer layer 11 to release film stress and improve the film quality of the buffer layer 11.

[0102] In some embodiments, after the buffer layer 11 is formed, the buffer layer 11 can be subjected to a nitrous oxide plasma process to repair the silicon-oxygen bonds on the surface of the third sub-buffer layer 113 in the buffer layer 11, thereby repairing the surface defects of the third sub-buffer layer 113.

[0103] In some embodiments, step S2 further includes: after forming the active layer 12, performing a nitrous oxide plasma process on the active layer 12 to repair defects on the surface of the active layer 12.

[0104] In some embodiments, step S3 includes: forming a first sub-gate insulating layer 131 on the side of the active layer 12 away from the buffer layer 11 at a third film formation rate, and forming a second sub-gate insulating layer 132 on the first sub-gate insulating layer 131 at a fourth film formation rate, thereby obtaining a gate insulating layer 13.

[0105] In this embodiment, the third film formation rate is less than the fourth film formation rate, so that the hydrogen content in the first sub-gate insulating layer 131 is less than the hydrogen content in the second sub-gate insulating layer 132. The first sub-gate insulating layer 131 with a lower hydrogen content can prevent hydrogen in the second sub-gate insulating layer 132 from diffusing into the active layer 12, thereby improving the uniformity of the thin film transistor.

[0106] In some embodiments, the method of manufacturing the display panel further includes the following steps:

[0107] Step S5: After forming the gate layer 14, the gate insulating layer 13 is dry-etched, and the active layer 12 is simultaneously conductiveized.

[0108] In some embodiments, helium and argon are selected as the gases used to conduct the active layer 12, which can improve the uniformity of the conductor formation of the active layer 12, thereby improving the uniformity of the threshold voltage of the thin film transistor.

[0109] In some embodiments, the method of manufacturing the display panel further includes the following steps:

[0110] Step S6: Sequentially form an interlayer dielectric layer 16, a source / drain layer 17, a first passivation layer 18, an organic insulating layer 19, and a first electrode layer 20 on the gate layer 14.

[0111] Step S7: Form a second passivation layer 21 on the organic insulating layer 19 and the first electrode layer 20;

[0112] Step S8: Form a second electrode layer 22 on the second passivation layer 21.

[0113] In some embodiments, a high content of nitrous oxide gas can be selected in the process of step S6, which can prevent hydrogen from diffusing into the active layer 12 in subsequent processes, thereby improving the uniformity of the thin film transistor performance.

[0114] In some implementations, step S7 includes the following steps: forming a first sub-passivation layer 211 on the organic insulating layer 19 and the first electrode layer 20 at a fifth film formation rate; and forming a second sub-passivation layer 212 on the first sub-passivation layer 211 at a sixth film formation rate.

[0115] In this embodiment, since the fifth film formation rate is less than the sixth film formation rate, the hydrogen content in the first sub-passivation layer 211 is less than the hydrogen content in the second sub-passivation layer 212. The first sub-passivation layer 211 with a lower hydrogen content can be used to block the diffusion of hydrogen from the second sub-passivation layer 212 to the active layer 12, thereby improving the uniformity of the thin film transistor.

[0116] Based on the display panel provided in the above embodiments of this application, embodiments of this application also provide a display device. Please refer to [link to relevant documentation]. Figure 7 , Figure 7 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. The display device 1000 includes a display panel 100 and a housing 200, with the display panel 100 disposed on the housing 200. The display device 1000 can be any of the display panels provided in the above embodiments. The display device provided in the embodiments of this application can achieve the same technical effects as the display panels provided in any of the above embodiments, and will not be described in detail here.

[0117] The beneficial effects of the embodiments of this application are as follows: The embodiments of this application provide a display panel, a method for manufacturing a display panel, and a display device. The display panel includes a substrate, a buffer layer, an active layer, a gate insulating layer, and a gate layer. By making at least one of the buffer layer and the gate insulating layer have a stacked structure formed by two layers of the same material, the hydrogen content in the film layer near the active layer in the stacked structure is lower than that in the film layer far from the active layer. This can improve the uniformity of the thin-film transistors in the display area. By setting the active layer as a stacked structure formed by a first sub-active layer and a second sub-active layer, and making the mobility of the first sub-active layer greater than that of the second sub-active layer, the subthreshold swing of the thin-film transistors can be increased without affecting the initial threshold voltage of the thin-film transistors. This can improve the uniformity of the thin-film transistors in the display area while increasing the limit of the thin-film transistors in the non-display area.

[0118] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0119] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0120] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0121] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel, characterized in that, include: Substrate; A buffer layer is disposed on one side of the substrate; An active layer is disposed on the side of the buffer layer away from the substrate, and the material of the active layer includes an oxide semiconductor material; A gate insulating layer is disposed on the side of the active layer away from the buffer layer; A gate layer is disposed on the side of the gate insulating layer away from the active layer; A second passivation layer is disposed on the side of the gate layer away from the gate insulating layer; Wherein, at least one of the buffer layer and the gate insulating layer has a stacked structure composed of two layers of the same material, wherein the hydrogen content in the film layer near the active layer is less than the hydrogen content in the film layer away from the active layer; the active layer includes a first sub-active layer and a second sub-active layer, the second sub-active layer being disposed on the side of the first sub-active layer near the gate layer, and the mobility of the first sub-active layer being greater than the mobility of the second sub-active layer; the second passivation layer includes a first sub-passivation layer and a second sub-passivation layer, the second sub-passivation layer being disposed on the surface of the first sub-passivation layer away from the gate layer, and the hydrogen content in the first sub-passivation layer being less than the hydrogen content in the second sub-passivation layer.

2. The display panel as described in claim 1, characterized in that, The thickness of the first sub-active layer is greater than the thickness of the second sub-active layer.

3. The display panel as described in claim 2, characterized in that, The thickness of the first sub-active layer is greater than or equal to 200 angstroms and less than or equal to 1000 angstroms, and the thickness of the second sub-active layer is greater than or equal to 50 angstroms and less than or equal to 500 angstroms.

4. The display panel as described in claim 1, characterized in that, The buffer layer includes: A first sub-buffer layer is disposed on one side of the substrate, and the material of the first sub-buffer layer includes silicon nitride; A second sub-buffer layer is disposed on the side of the first sub-buffer layer away from the substrate, and the material of the second sub-buffer layer includes silicon oxide; A third sub-buffer layer is disposed on the surface of the second sub-buffer layer away from the first sub-buffer layer, and the material of the third sub-buffer layer includes silicon oxide; The hydrogen content in the third sub-buffer layer is less than the hydrogen content in the second sub-buffer layer.

5. The display panel as described in claim 4, characterized in that, The thickness of the second sub-buffer layer is greater than the thickness of the third sub-buffer layer.

6. The display panel as described in claim 5, characterized in that, The thickness of the second sub-buffer layer is greater than or equal to 2000 angstroms and less than or equal to 4000 angstroms, and the thickness of the third sub-buffer layer is greater than or equal to 200 angstroms and less than or equal to 1000 angstroms.

7. The display panel as described in claim 4, characterized in that, The buffer layer further includes a fourth sub-buffer layer, which is disposed between the first sub-buffer layer and the second sub-buffer layer; The fourth sub-buffer layer is made of silicon nitride, and the hydrogen content in the fourth sub-buffer layer is less than that in the first sub-buffer layer.

8. The display panel as described in claim 7, characterized in that, The thickness of the fourth sub-buffer layer is less than the thickness of the first sub-buffer layer.

9. The display panel as claimed in claim 1, characterized in that, The gate insulating layer includes: A first sub-gate insulating layer is disposed on the side of the active layer away from the substrate; The second sub-gate insulating layer is disposed on the surface of the first sub-gate insulating layer away from the active layer; The hydrogen content in the first sub-gate insulating layer is less than the hydrogen content in the second sub-gate insulating layer.

10. The display panel as claimed in claim 9, characterized in that, The thickness of the first sub-gate insulating layer is less than the thickness of the second sub-gate insulating layer.

11. The display panel as claimed in claim 10, characterized in that, The thickness of the first sub-gate insulating layer is greater than or equal to 200 angstroms and less than or equal to 600 angstroms, and the thickness of the second sub-gate insulating layer is greater than or equal to 1000 angstroms and less than or equal to 2000 angstroms.

12. The display panel as claimed in claim 1, characterized in that, The display panel also includes: An interlayer dielectric layer is disposed on the side of the gate layer away from the gate insulating layer; The source and drain layers are disposed on the side of the interlayer dielectric layer away from the gate layer; A first passivation layer is disposed on the side of the source / drain layer away from the interlayer dielectric layer; An organic insulating layer is disposed on the side of the first passivation layer away from the source and drain layers; The second passivation layer is disposed on the side of the organic insulating layer away from the first passivation layer.

13. The display panel as claimed in claim 12, characterized in that, The thickness of the first sub-passivation layer is less than the thickness of the second sub-passivation layer.

14. A method for manufacturing a display panel, characterized in that, The method for manufacturing the display panel includes the following steps: A buffer layer is formed on one side of the substrate; A first sub-active layer is formed on the side of the buffer layer away from the substrate; A second sub-active layer is formed on the first sub-active layer to obtain an active layer; A gate insulating layer is formed on the side of the active layer away from the buffer layer; A gate layer is formed on the side of the gate insulating layer away from the active layer; A second passivation layer is formed on the side of the gate layer away from the gate insulating layer; In this configuration, at least one of the buffer layer and the gate insulating layer has a stacked structure composed of two layers of the same material. In the stacked structure, the film layer near the active layer has a slower film formation rate than the film layer far from the active layer. The film layer near the active layer has a lower hydrogen content than the film layer far from the active layer. The mobility of the first sub-active layer is greater than the mobility of the second sub-active layer. The second passivation layer includes a first sub-passivation layer and a second sub-passivation layer. The second sub-passivation layer is disposed on the surface of the first sub-passivation layer away from the gate layer. The hydrogen content in the first sub-passivation layer is less than the hydrogen content in the second sub-passivation layer.

15. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 13.

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