Thin film transistor, method of manufacturing the same, and display device

Abstract

This application discloses a thin-film transistor (TFT), its fabrication method, and a display device. The TFT fabrication method includes: providing a pre-fabricated TFT; and sequentially subjecting the pre-fabricated TFT to a first thermal annealing treatment and an ultraviolet radiation treatment to obtain the TFT. The TFT fabricated by the method described in this application has a steeper subthreshold swing and lower power consumption.

Description

Technical Field

[0001] This application relates to the field of thin-film transistor technology, and in particular to a thin-film transistor, its fabrication method, and a display device. Background Technology

[0002] In the context of global informatization, emerging fields such as artificial intelligence, the Internet of Things, and big data are placing higher demands on the performance of electronic devices. According to Moore's Law, to adapt to the rapid development of the electronic information field, the number of transistors on integrated circuits is constantly increasing, making high energy consumption a key issue for future sustainable development.

[0003] However, existing thin-film transistors consume relatively high power and need to be further reduced. Summary of the Invention

[0004] In view of this, this application provides a thin-film transistor, a method for fabricating the same, and a display device.

[0005] The embodiments of this application are implemented as follows: a method for fabricating a thin-film transistor includes the following steps:

[0006] Provide pre-fabricated thin-film transistors;

[0007] The pre-fabricated thin-film transistor is subjected to a first thermal annealing treatment and an ultraviolet radiation treatment in sequence to obtain the thin-film transistor.

[0008] Accordingly, this application also provides a thin-film transistor prepared by the above-described preparation method.

[0009] Accordingly, embodiments of this application also provide a display device, which includes the aforementioned thin-film transistor.

[0010] The thin-film transistor fabrication method described in this application produces thin-film transistors with a steeper subthreshold swing and lower energy consumption. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a flowchart illustrating a method for fabricating a thin-film transistor according to an embodiment of this application;

[0013] Figure 2 This is a schematic diagram of the structure of a thin-film transistor provided in an embodiment of this application;

[0014] Figure 3 This is a flowchart illustrating a method for fabricating a pre-fabricated thin-film transistor according to an embodiment of this application;

[0015] Figure 4 These are transfer characteristic curves of the thin-film transistors of Embodiment 1 and Comparative Example 1 of this application.

[0016] Figure label:

[0017] Thin-film transistor 100; substrate 10; gate 20, gate insulating layer 30, source 40, drain 50, active layer 60; first active layer 61; second active layer 62; first surface 621; passivation layer 70; channel 101. Detailed Implementation

[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. Furthermore, it should be understood that the specific embodiments described herein are only for illustration and explanation of this application and are not intended to limit this application.

[0019] In this application, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in its actual use or operating state, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device. Furthermore, in the description of this application, the term "comprising" means "including but not limited to". The terms first, second, third, etc., are used merely as illustrative purposes and do not impose numerical requirements or establish a numerical order.

[0020] In this application, "and / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. A and B can be singular or plural.

[0021] In this application, "at least one" means one or more, and "more than one" means two or more. "At least one," "at least one of the following," or similar expressions refer to any combination of these items, including any combination of single or multiple items. For example, "at least one of a, b, or c," or "at least one of a, b, and c," can both mean: a, b, c, ab (i.e., a and b), ac, bc, or abc, where a, b, and c can be single or multiple.

[0022] In this application, the term "on" forming another layer on a certain layer is a broad concept. It can mean that the formed other layer is adjacent to a certain layer, or it can mean that there are other spacer structures between the other layer and the certain layer. For example, when a second electrode is formed "on" a first charge carrier functional layer, the term "on" can mean that the formed second electrode is adjacent to the first charge carrier functional layer, or it can mean that there are other spacer structures between the second electrode and the first charge carrier functional layer, such as a light-emitting layer.

[0023] Various embodiments of this application may exist in the form of a range; it should be understood that the description in the form of a range is merely for convenience and brevity and should not be construed as a hard limitation on the scope of this application; therefore, it should be considered that the range description has specifically disclosed all possible sub-ranges and single numerical values ​​within that range. For example, it should be considered that the range description from 1 to 6 has specifically disclosed sub-ranges such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6, etc., and single numbers within the range, such as 1, 2, 3, 4, 5, and 6, whichever applies. Furthermore, whenever a numerical range is referred to herein, it means including any referenced number (fraction or integer) within the range referred to.

[0024] According to Boltzmann theory, limited by carrier distribution, the subthreshold swing (SS) of conventional metal-oxide-semiconductor thin-film transistors is limited to 60 mV decade at room temperature. -1 Currently, the structures and fabrication processes of most metal-oxide-slim (MOS) thin-film transistors (TFTs) result in a subthreshold swing that is still far from the limit, meaning there is still much room for improvement in reducing power consumption. Therefore, to further advance the information technology field and effectively reduce the power consumption of integrated circuits, a method for fabricating MOS thin-film transistors with steep subthreshold swing characteristics is needed.

[0025] The technical solution of this application is as follows:

[0026] Firstly, please refer to Figures 1-2 This application provides a method for fabricating a thin-film transistor, comprising the following steps:

[0027] Step S11: Provide a pre-fabricated thin-film transistor, the pre-fabricated thin-film transistor including a substrate 10, a gate 20, a gate insulating layer 30, a source 40, a drain 50, an active layer 60, and a passivation layer 70;

[0028] Step S12: Perform a first thermal annealing treatment and an ultraviolet radiation treatment on the pre-fabricated thin-film transistor in sequence to obtain thin-film transistor 100.

[0029] The method for fabricating thin-film transistors described in this application involves sequentially performing a first thermal annealing treatment and an ultraviolet radiation treatment on the pre-fabricated thin-film transistor. The addition of ultraviolet radiation treatment after the first thermal annealing treatment can induce the decomposition of weak dangling bonds, the transition of oxygen vacancies, and the activation of interstitial atoms in the thin-film transistor. This can improve the carrier transport capability and fast response capability of the thin-film transistor. Thus, the fabricated thin-film transistor can have a steep subthreshold swing, and it is beneficial to achieve fast response, high electron mobility, large on / off ratio, low leakage current, and high stability of the thin-film transistor.

[0030] The thin-film transistor 100 fabricated in this application has a bottom-gate bottom-contact inverted coplanar structure. Compared with a bottom-gate top-contact structure, the bottom-gate bottom-contact inverted coplanar structure has a smaller contact resistance and a shorter effective contact length, which is beneficial for carrier transport and facilitates faster response of the thin-film transistor. The shortened effective contact length also reduces the effective overlap area between the gate 20 and the source 40, significantly reducing parasitic capacitance and improving the electrical performance and power consumption of the thin-film transistor.

[0031] In some embodiments, the process of performing a first thermal annealing and an ultraviolet radiation treatment on the pre-fabricated thin-film transistor in sequence, and before obtaining the thin-film transistor, further includes a second annealing treatment.

[0032] Adding ultraviolet radiation treatment after the first thermal annealing treatment can induce the decomposition of weak dangling bonds, the transition of oxygen vacancies, and the activation of interstitial atoms in thin-film transistors. However, while the decomposition of weak dangling bonds and the transition of oxygen vacancies improve the carrier transport capacity and fast response capability, they may also increase defects. Adding a second thermal annealing treatment after ultraviolet radiation treatment helps to repair defects in the thin film and also helps to rearrange dissociated atoms. In this way, the carrier transport capacity and fast response capability of the thin-film transistor can be further effectively improved, and the subthreshold swing of the prepared thin-film transistor can be further effectively improved. This is beneficial to achieving fast response, high electron mobility, large on / off ratio, low leakage current, and high stability of the thin-film transistor.

[0033] The thin-film transistor 100 prepared in this application has a passivation layer 70 on the top layer. The passivation layer 70 has strong hydrophobicity, which makes the device surface have fewer dangling bonds. It can effectively isolate water and oxygen in the environment, inhibit the degradation of the electrical properties of each functional layer of the thin film during long-term operation in the natural environment, thereby improving the stability of the device.

[0034] In some embodiments, the electron mobility of the thin-film transistor 100 can be as high as 45.5 cm⁻¹. 2 ·V -1 ·s -1 .

[0035] In some embodiments, the subthreshold swing of the thin-film transistor 100 can be as low as 86 mV·decade. -1 It can be understood that the subthreshold swing is the voltage value required to increase the current by one order of magnitude.

[0036] In step S11:

[0037] The pre-fabricated thin-film transistor is prepared using a known method for preparing bottom-gate bottom-contact thin-film transistors.

[0038] In some embodiments, please refer to Figure 3 The method for fabricating the pre-fabricated thin-film transistor includes:

[0039] Step S01: Provide a substrate 10 and fabricate a gate 20 on the substrate 10;

[0040] Step S02: Prepare a gate insulating layer 30 on the gate 20;

[0041] Step S03: A source 40 and a drain 50 are formed on the gate insulating layer 30, and a channel 101 is formed between the source 40 and the drain 50, and a portion of the surface of the gate insulating layer 30 is exposed through the channel 101.

[0042] Step S04: Fill the channel 101 with active layer material to obtain active layer 60;

[0043] Step S05: A passivation layer 70 is prepared on the surface of the active layer 60 away from the gate insulating layer 30 to obtain a pre-fabricated thin-film transistor.

[0044] In some embodiments, before sequentially fabricating the gate 20 on the substrate 10, the method further includes cleaning the substrate 10. Specifically, the substrate 10 is treated with UV radiation to decompose organic impurities on its surface, then cleaned with deionized water and isopropanol, and finally dried.

[0045] In the thin-film transistor 100, the gate 20 is bonded to the surface of the substrate 10. The gate insulating layer 30 is located on the surface of the gate 20 away from the substrate 10. The source 40 and the drain 50 are disposed on the surface of the gate insulating layer 30 away from the gate 20. A channel 101 is formed between the source 40 and the drain 50, and a portion of the surface of the gate insulating layer 30 is exposed through the channel 101. The active layer 60 fills the channel 101. The passivation layer 70 is disposed on the surface of the active layer 60 away from the gate insulating layer 30.

[0046] In some embodiments, the active layer 60 includes a first active layer 61 and a second active layer 62, the first active layer 61 being housed within the channel 101, and the second active layer 62 being external to the channel 101. The second active layer 62 has a first surface 621, which is bonded to the surface of the first active layer 61 remote from the gate insulating layer 30.

[0047] In some embodiments, a portion of the first surface 621 is bonded to the first active layer 61, a portion is bonded to at least a portion of the surface of the source 40 remote from the gate insulating layer 30, and a portion is bonded to at least a portion of the surface of the drain 50 remote from the gate insulating layer 30. In other words, the second active layer 62 is disposed on the surface of the first active layer 61 remote from the gate insulating layer 30 and overlaps the source 40 and the drain 50.

[0048] The methods for fabricating the gate 20, the gate insulating layer 30, the source 40, the drain 50, the active layer 60, and the passivation layer 70 described in this application can be implemented using conventional techniques in the art, such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, pulsed laser deposition, thermal evaporation coating, electron beam evaporation coating, magnetron sputtering, and multi-arc ion plating. The magnetron sputtering method can be DC magnetron sputtering, pulsed DC magnetron sputtering, etc.

[0049] Understandably, the gate 20 has a patterned structure; in other words, the gate 20 is a patterned gate 20. The gate insulating layer 30 has a patterned structure; in other words, the gate insulating layer 30 is a patterned gate insulating layer 30. The source 40 has a patterned structure; in other words, the source 40 is a patterned source 40. The drain 50 has a patterned structure; in other words, the drain 50 is a patterned drain 50. The active layer 60 has a patterned structure; in other words, the active layer 60 is a patterned active layer 60. The passivation layer 70 has a patterned structure; in other words, the passivation layer 70 is a patterned passivation layer 70.

[0050] The substrate 10 is a known substrate used for thin-film transistors, such as a glass substrate, a quartz substrate, a single-crystal silicon substrate, a sapphire substrate, etc.

[0051] The gate 20 is made of a known gate material used in thin-film transistors, and may include, but is not limited to, one or more of gold, silver, copper, aluminum, neodymium, and molybdenum. The gate material has low resistivity and high conductivity.

[0052] Understandably, in some embodiments, the gate 20 may also include a doped material, such as Nd, that is used in the gate of a thin-film transistor.

[0053] The material of the gate insulating layer 30 is a known gate insulating layer material used in thin-film transistors, for example, including but not limited to Al2O3, ZrO2, and SiN. x It contains one or more of SiO2 and HfO2. Squirrel gate insulating material has a high dielectric constant and good insulation properties.

[0054] The source electrode 40 is made of a known source electrode material used in thin-film transistors, and may include, but is not limited to, one or more of gold, silver, copper, aluminum, and molybdenum. The source electrode material has low resistivity and high conductivity.

[0055] The drain electrode 50 is made of a known drain material used in thin-film transistors, and may include, but is not limited to, one or more of gold, silver, copper, aluminum, and molybdenum. The drain material has low resistivity and high conductivity.

[0056] The active layer 60 is made of a known active layer material for thin-film transistors, and may include, but is not limited to, doped oxide semiconductor materials. In some embodiments, the doped oxide semiconductor material includes, but is not limited to, one or more of IGZO, Pr-IZO, Nd-IZO, and NdAl-IZO.

[0057] The passivation layer 70 is made of a known passivation layer material used in thin-film transistors, for example, including but not limited to Al2O3, SiO2, AlGaAlO3, etc. x One or more of the following. The passivation layer material has good hydrophobicity, good insulation, and high chemical stability.

[0058] In step S12:

[0059] In some embodiments, the temperature of the first thermal annealing treatment is 200–350°C, for example, 200°C, 220°C, 230°C, 250°C, 260°C, 280°C, 300°C, 310°C, 320°C, 330°C, 350°C, etc.; the time of the first thermal annealing treatment is 0.5–2 hours, for example, 0.5 hours, 0.8 hours, 1 hour, 1.2 hours, 1.3 hours, 1.5 hours, 1.6 hours, 1.8 hours, 2 hours, etc. Within the temperature and time range, the concentration of defects and impurities in the thin film can be effectively reduced, the carrier concentration and mobility can be increased, and the electrical properties can be improved.

[0060] In some embodiments, the peak wavelength of the ultraviolet light used in the ultraviolet radiation treatment is 315–400 nm, for example, 315 nm, 320 nm, 330 nm, 340 nm, 350 nm, 360 nm, 370 nm, 380 nm, 390 nm, or 400 nm; the duration of the ultraviolet radiation treatment is 1000–2400 s, for example, 1000 s, 1100 s, 1200 s, 1300 s, 1400 s, 1500 s, 1600 s, 1700 s, 1800 s, 1900 s, 2000 s, 2100 s, 2200 s, 2300 s, or 2400 s; and the power density of the ultraviolet radiation treatment is 150–200 mW·cm². -2 For example, 150mW·cm -2 160mW·cm -2 170mW·cm -2 180mW·cm -2 190mW·cm -2 200mW·cm -2 Within the stated range, the decomposition of weak dangling bonds, the transition of oxygen vacancies, and the activation of interstitial atoms in the thin film can be induced.

[0061] In some embodiments, the instrument used for the ultraviolet radiation treatment is a UV curing lamp.

[0062] In some embodiments, the temperature of the second thermal annealing treatment is 150–250°C, for example, 150°C, 160°C, 170°C, 180°C, 190°C, 200°C, 210°C, 220°C, 230°C, 240°C, or 250°C; the time of the second thermal annealing treatment is 0.5–1.5 h, for example, 0.5 h, 0.6 h, 0.7 h, 0.8 h, 0.9 h, 1 h, 1.1 h, 1.2 h, 1.3 h, 1.4 h, or 1.5 h. Within the temperature and time range, it helps to repair defects in the thin film and rearrange dissociated atoms, thereby improving the carrier transport capacity and the device's rapid response capability.

[0063] Secondly, please refer to Figure 2 This application also provides a thin-film transistor 100, which is prepared by the thin-film transistor preparation method described above.

[0064] In some embodiments, the thin-film transistor 100 is a bottom-gate bottom-contact inverted coplanar thin-film transistor.

[0065] In some embodiments, the thin-film transistor 100 includes a substrate 10 and a gate 20, a gate insulating layer 30, a source 40, a drain 50, an active layer 60, and a passivation layer 70 disposed on the substrate 10.

[0066] The gate 20 is bonded to the surface of the substrate 10.

[0067] The gate insulating layer 30 is located on the surface of the gate 20 away from the substrate 10.

[0068] The source electrode 40 and the drain electrode 50 are disposed on the surface of the gate insulating layer 30 away from the gate electrode 20. A channel 101 is formed between the source electrode 40 and the drain electrode 50, and a portion of the surface of the gate insulating layer 30 is exposed through the channel 101.

[0069] In some embodiments, the active layer 60 fills the channel 101.

[0070] In other embodiments, the active layer 60 includes a first active layer 61 and a second active layer 62, the first active layer 61 being housed within the channel 101 and the second active layer 62 being external to the channel 101. The second active layer 62 has a first surface 621, which is bonded to the surface of the first active layer 61 remote from the gate insulating layer 30.

[0071] Furthermore, in some embodiments, a portion of the first surface 621 is bonded to the first active layer 61, a portion is bonded to at least a portion of the surface of the source 40 remote from the gate insulating layer 30, and a portion is bonded to at least a portion of the surface of the drain 50 remote from the gate insulating layer 30. In other words, the second active layer 62 is disposed on the surface of the first active layer 61 remote from the gate insulating layer 30 and overlaps the source 40 and the drain 50.

[0072] The passivation layer 70 is disposed on the surface of the active layer 60 away from the gate insulating layer 30.

[0073] The materials of the substrate 10, the gate 20, the gate insulating layer 30, the source 40, the drain 50, the active layer 60, and the passivation layer 70 are as described above and will not be repeated here.

[0074] The thin-film transistor has high electron mobility and a steep subthreshold swing.

[0075] In some embodiments, the electron mobility of the thin-film transistor 100 can be as high as 45.5 cm⁻¹. 2 ·V -1 ·s -1 .

[0076] In some embodiments, the subthreshold swing of the thin-film transistor 100 can be as low as 86 mV·decade. -1 .

[0077] Thirdly, this application also relates to a display device, which includes the thin-film transistor 100.

[0078] The display device can be any electronic product with display function, including but not limited to smartphones, tablets, laptops, digital cameras, digital camcorders, smart wearable devices, smart weighing scales, in-vehicle displays, televisions, or e-book readers. Among them, smart wearable devices can be, for example, smart bracelets, smartwatches, virtual reality (VR) headsets, etc.

[0079] The present application will be specifically described below through specific embodiments. The following embodiments are only some embodiments of the present application and are not intended to limit the present application.

[0080] Example 1

[0081] The specific fabrication steps of the thin-film transistor in this embodiment are as follows:

[0082] (1) Cleaning of the substrate: Select a glass substrate, treat it with UV radiation for 1 minute to decompose organic contaminants on the surface, then clean it with deionized water and isopropanol respectively, and finally dry it.

[0083] (2) Gate fabrication: Nd:Al (mass ratio 3:97) thin film was prepared on the dry substrate obtained in step (1) by DC magnetron sputtering, and a patterned gate 20 was formed by wet etching.

[0084] (3) Preparation of insulating layer film: On the substrate obtained in step (2), the Nd:Al film of the top part of the gate 20 is oxidized to Nd:Al2O3 by anodic oxidation to form a patterned gate insulating layer 30.

[0085] (4) Fabrication of source and drain: Patterned source 40 and drain 50 are fabricated on the substrate obtained in step (3) using DC magnetron sputtering and a metal mask. The material of source 40 and drain 50 is Al.

[0086] (5) Preparation of active layer: A patterned active layer 60 is prepared on the substrate obtained in step (4) using pulsed DC magnetron sputtering and a metal mask. The material of the active layer 60 is NdAl-IZO.

[0087] (6) Preparation of passivation layer film: A patterned passivation layer 70 is prepared on the substrate obtained in step (5) using magnetron sputtering and a metal mask. The material of the passivation layer 70 is GaAlO. x Thus, a pre-fabricated thin-film transistor is obtained;

[0088] (7) Post-processing of the device: The pre-fabricated thin-film transistor obtained in step (6) is subjected to a first thermal annealing treatment at 300°C for 0.5 hours in an atmospheric environment, and then a power density of 170 mW·cm⁻¹ is used. -2 The device is subjected to ultraviolet radiation treatment using a UV curing lamp. The peak wavelength of the ultraviolet light used in the ultraviolet radiation treatment is 365nm. Next, a second thermal annealing treatment at 200℃ is performed for 1 hour in an atmospheric environment to obtain a thin film transistor.

[0089] Comparative Example 1

[0090] This comparative example is basically the same as Example 1, except that step (7) in this comparative example does not include ultraviolet radiation treatment and second thermal annealing treatment.

[0091] Thin-film transistor performance testing:

[0092] The transfer characteristics of the thin-film transistors of Example 1 and Comparative Example 1 were tested, and the results were obtained. Figure 4 The transfer characteristic curves of the thin-film transistors of Example 1 and Comparative Example 1 are shown, where (a) is the transfer characteristic curve of the thin-film transistor of Comparative Example 1 and (b) is the transfer characteristic curve of the thin-film transistor of Example 1.

[0093] The method for testing transfer characteristics is as follows: applying a voltage (V) to the source / drain electrodes of the thin-film transistor. ds 20V, and the gate voltage (V) g The voltage is scanned from -20V to +20V in 0.2V steps, and then I is read using a semiconductor tester. ds The current is used to obtain the transfer characteristic curve.

[0094] Depend on Figure 4 It can be seen that in the fabrication process of thin-film transistors, adding ultraviolet radiation treatment and a second thermal annealing treatment after the first thermal annealing treatment successfully eliminated the hump phenomenon.

[0095] The electron mobility and subthreshold swing of the thin-film transistors of Example 1 and Comparative Example 1 were tested, and the test results are shown in Table 1.

[0096] The electron mobility test method is as follows: based on the transfer characteristics, in the saturation region (V0) of the thin-film transistor device... ds >V g -V th ),I dsExpressed by the following equation:

[0097]

[0098] Where W and L represent the width and length of the channel, respectively, and C ox It is the capacitance per unit area of ​​the gate insulating layer, V th It is the threshold voltage, μ sat It is the carrier mobility in the saturation region;

[0099] From the above equation, we can obtain the carrier mobility μ in the saturation region. sat and With V g The slope of the curve is proportional to the slope of the curve, and can be calculated from the slope k:

[0100]

[0101] The formula for calculating electron mobility is:

[0102]

[0103] The subthreshold swing is calculated based on the transfer characteristic curve and the following formula:

[0104]

[0105] Where SS is the subthreshold swing, V GS It is the gate voltage, I D It is the source-drain current, dV GS It is the change in gate-source voltage, dlg(I D ) is the logarithmic change in current.

[0106] Table 1:

[0107]

[0108] As shown in Table 1:

[0109] Compared to the thin-film transistor of Comparative Example 1, the thin-film crystal of Example 1 exhibits higher electron mobility and a steeper subthreshold swing. This demonstrates that, during the fabrication of thin-film transistors, adding ultraviolet radiation treatment and thermal annealing after conventional thermal annealing can effectively improve the electron mobility of the thin-film transistor and give it a steeper subthreshold swing. This may be because ultraviolet radiation treatment can induce the decomposition of weak dangling bonds, the transition of oxygen vacancies, and the activation of interstitial atoms in the thin film, while the second thermal annealing treatment helps to repair defects and rearrange dissociated atoms in the thin film, improving the carrier transport capacity and the device's fast response capability, thus enabling the fabricated thin-film transistor to have a steeper subthreshold swing.

[0110] The technical solution of this application has been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A method for fabricating a thin-film transistor, characterized in that, Includes the following steps: Provide pre-fabricated thin-film transistors; The pre-fabricated thin-film transistor is subjected to a first thermal annealing treatment and an ultraviolet radiation treatment in sequence to obtain the thin-film transistor.

2. The preparation method according to claim 1, characterized in that, The temperature of the first heat annealing treatment is 200–350°C; and / or The first heat annealing treatment takes 0.5 to 2 hours; and / or The peak wavelength of the ultraviolet light used in the ultraviolet radiation treatment is 315–400 nm; and / or The ultraviolet radiation treatment time is 1000–2400 s; and / or The power density of the ultraviolet radiation treatment is 150–200 mW·cm⁻¹. -2 .

3. The preparation method according to claim 1, characterized in that, After the pre-fabricated thin-film transistor undergoes a first thermal annealing process and an ultraviolet radiation process, and before obtaining the thin-film transistor, a second annealing process is further included, wherein... The temperature of the second heat annealing treatment is 150–250°C; and / or The second heat annealing treatment takes 0.5 to 1.5 hours.

4. The preparation method according to claim 1, characterized in that, The method for fabricating the pre-fabricated thin-film transistor includes: A substrate is provided, on which a gate is fabricated; A gate insulating layer is prepared on the gate; A source and a drain are fabricated on the gate insulating layer, and a channel is formed between the source and the drain, with a portion of the surface of the gate insulating layer exposed through the channel; An active layer material is filled into the channel to obtain an active layer; A passivation layer is prepared on the surface of the active layer away from the gate insulating layer to obtain a pre-fabricated thin-film transistor.

5. The preparation method according to claim 4, characterized in that, The active layer includes a first active layer and a second active layer, the first active layer being housed in the channel, the second active layer being outside the channel, the second active layer having a first surface, and the second active layer being bonded to the surface of the first active layer away from the gate insulating layer by at least a portion of the first surface.

6. The preparation method according to claim 5, characterized in that, A portion of the first surface is bonded to the first active layer, a portion of the first surface is bonded to at least a portion of the surface of the source electrode remote from the gate insulating layer, and a portion of the first surface is bonded to at least a portion of the surface of the drain electrode remote from the gate insulating layer.

7. The preparation method according to claim 4, characterized in that, The substrate is a glass substrate, a quartz substrate, a monocrystalline silicon substrate, or a sapphire substrate; and / or The gate material includes one or more of gold, silver, copper, aluminum, neodymium, and molybdenum; and / or The gate insulating layer is made of Al2O3, ZrO2, and SiN. x One or more of SiO2 and HfO2; and / or The source electrode material and the drain electrode material each independently include one or more of gold, silver, copper, aluminum, and molybdenum; and / or The active layer is made of a doped oxide semiconductor material, which includes one or more of IGZO, Pr-IZO, Nd-IZO, and NdAl-IZO; and / or The passivation layer is made of materials including Al2O3, SiO2, AlGaAlO3, etc. x One or more of them.

8. A thin-film transistor prepared by the preparation method according to any one of claims 1 to 7.

9. The thin-film transistor as claimed in claim 8, characterized in that, The thin-film transistor includes a substrate and a gate, a gate insulating layer, a source, a drain, an active layer, and a passivation layer disposed on the substrate, wherein... The gate is bonded to the surface of the substrate; The gate insulating layer is located on the surface of the gate away from the substrate; The source and the drain are disposed on the surface of the gate insulating layer away from the gate, and a channel is formed between the source and the drain, with a portion of the surface of the gate insulating layer exposed through the channel; The active layer fills the channel; The passivation layer is disposed on the surface of the active layer away from the gate insulating layer.

10. The thin-film transistor as claimed in claim 9, characterized in that, The active layer includes a first active layer and a second active layer, the first active layer being housed in the channel, the second active layer being outside the channel, the second active layer having a first surface, and the second active layer being bonded to the surface of the first active layer away from the gate insulating layer by at least a portion of the first surface.

11. The thin-film transistor as claimed in claim 10, characterized in that, A portion of the first surface is bonded to the first active layer, a portion of the first surface is bonded to at least a portion of the surface of the source electrode remote from the gate insulating layer, and a portion of the first surface is bonded to at least a portion of the surface of the drain electrode remote from the gate insulating layer.

12. The thin-film transistor as claimed in claim 9, characterized in that, The electron mobility of the thin-film transistor is 45.5 cm⁻¹. 2 ·V -1 ·s -1 ; and / or The subthreshold swing of the thin-film transistor is 86 mV·decade. -1 .

13. A display device, characterized in that, The thin-film transistor includes the thin-film transistor prepared by the preparation method according to any one of claims 1 to 7, or the thin-film transistor according to any one of claims 8 to 12.

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